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TARGET_NRF51_MICROBIT/core_caFunc.h@115:87f2f5183dfb, 2016-03-02 (annotated)

Committer:
Kojto
Date:
Wed Mar 02 09:58:28 2016 +0100
Revision:
115:87f2f5183dfb
Parent:
108:34e6b704fe68
Child:
121:6c34061e7c34
Release 115 of the mbed library



Changes:

- new targets - NUCLEO_F746ZG

- Bugfix - STM32F7 + STM32L4 - RTC init fix

- Bugfix - STM32L4 Set NVIC_RAM_VECTOR_ADDRESS to 0x10000000

- B96B_F446VE - CAN addition

- Changed target name from NZ32SC151 to NZ32_SC151

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 104:b9ad9a133dc7 1 /**************************************************************************//**
Kojto 104:b9ad9a133dc7 2 * @file core_caFunc.h
Kojto 104:b9ad9a133dc7 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 104:b9ad9a133dc7 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 104:b9ad9a133dc7 6 *
Kojto 104:b9ad9a133dc7 7 * @note
Kojto 104:b9ad9a133dc7 8 *
Kojto 104:b9ad9a133dc7 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 104:b9ad9a133dc7 11
Kojto 104:b9ad9a133dc7 12 All rights reserved.
Kojto 104:b9ad9a133dc7 13 Redistribution and use in source and binary forms, with or without
Kojto 104:b9ad9a133dc7 14 modification, are permitted provided that the following conditions are met:
Kojto 104:b9ad9a133dc7 15 - Redistributions of source code must retain the above copyright
Kojto 104:b9ad9a133dc7 16 notice, this list of conditions and the following disclaimer.
Kojto 104:b9ad9a133dc7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 104:b9ad9a133dc7 18 notice, this list of conditions and the following disclaimer in the
Kojto 104:b9ad9a133dc7 19 documentation and/or other materials provided with the distribution.
Kojto 104:b9ad9a133dc7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 104:b9ad9a133dc7 21 to endorse or promote products derived from this software without
Kojto 104:b9ad9a133dc7 22 specific prior written permission.
Kojto 104:b9ad9a133dc7 23 *
Kojto 104:b9ad9a133dc7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 104:b9ad9a133dc7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 104:b9ad9a133dc7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 104:b9ad9a133dc7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 104:b9ad9a133dc7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 104:b9ad9a133dc7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 104:b9ad9a133dc7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 104:b9ad9a133dc7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 104:b9ad9a133dc7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 104:b9ad9a133dc7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 104:b9ad9a133dc7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 104:b9ad9a133dc7 35 ---------------------------------------------------------------------------*/
Kojto 104:b9ad9a133dc7 36
Kojto 104:b9ad9a133dc7 37
Kojto 104:b9ad9a133dc7 38 #ifndef __CORE_CAFUNC_H__
Kojto 104:b9ad9a133dc7 39 #define __CORE_CAFUNC_H__
Kojto 104:b9ad9a133dc7 40
Kojto 104:b9ad9a133dc7 41
Kojto 104:b9ad9a133dc7 42 /* ########################### Core Function Access ########################### */
Kojto 104:b9ad9a133dc7 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 104:b9ad9a133dc7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 104:b9ad9a133dc7 45 @{
Kojto 104:b9ad9a133dc7 46 */
Kojto 104:b9ad9a133dc7 47
Kojto 104:b9ad9a133dc7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 104:b9ad9a133dc7 49 /* ARM armcc specific functions */
Kojto 104:b9ad9a133dc7 50
Kojto 104:b9ad9a133dc7 51 #if (__ARMCC_VERSION < 400677)
Kojto 104:b9ad9a133dc7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 104:b9ad9a133dc7 53 #endif
Kojto 104:b9ad9a133dc7 54
Kojto 104:b9ad9a133dc7 55 #define MODE_USR 0x10
Kojto 104:b9ad9a133dc7 56 #define MODE_FIQ 0x11
Kojto 104:b9ad9a133dc7 57 #define MODE_IRQ 0x12
Kojto 104:b9ad9a133dc7 58 #define MODE_SVC 0x13
Kojto 104:b9ad9a133dc7 59 #define MODE_MON 0x16
Kojto 104:b9ad9a133dc7 60 #define MODE_ABT 0x17
Kojto 104:b9ad9a133dc7 61 #define MODE_HYP 0x1A
Kojto 104:b9ad9a133dc7 62 #define MODE_UND 0x1B
Kojto 104:b9ad9a133dc7 63 #define MODE_SYS 0x1F
Kojto 104:b9ad9a133dc7 64
Kojto 104:b9ad9a133dc7 65 /** \brief Get APSR Register
Kojto 104:b9ad9a133dc7 66
Kojto 104:b9ad9a133dc7 67 This function returns the content of the APSR Register.
Kojto 104:b9ad9a133dc7 68
Kojto 104:b9ad9a133dc7 69 \return APSR Register value
Kojto 104:b9ad9a133dc7 70 */
Kojto 104:b9ad9a133dc7 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 104:b9ad9a133dc7 72 {
Kojto 104:b9ad9a133dc7 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 104:b9ad9a133dc7 74 return(__regAPSR);
Kojto 104:b9ad9a133dc7 75 }
Kojto 104:b9ad9a133dc7 76
Kojto 104:b9ad9a133dc7 77
Kojto 104:b9ad9a133dc7 78 /** \brief Get CPSR Register
Kojto 104:b9ad9a133dc7 79
Kojto 104:b9ad9a133dc7 80 This function returns the content of the CPSR Register.
Kojto 104:b9ad9a133dc7 81
Kojto 104:b9ad9a133dc7 82 \return CPSR Register value
Kojto 104:b9ad9a133dc7 83 */
Kojto 104:b9ad9a133dc7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 104:b9ad9a133dc7 85 {
Kojto 104:b9ad9a133dc7 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 104:b9ad9a133dc7 87 return(__regCPSR);
Kojto 104:b9ad9a133dc7 88 }
Kojto 104:b9ad9a133dc7 89
Kojto 104:b9ad9a133dc7 90 /** \brief Set Stack Pointer
Kojto 104:b9ad9a133dc7 91
Kojto 104:b9ad9a133dc7 92 This function assigns the given value to the current stack pointer.
Kojto 104:b9ad9a133dc7 93
Kojto 104:b9ad9a133dc7 94 \param [in] topOfStack Stack Pointer value to set
Kojto 104:b9ad9a133dc7 95 */
Kojto 104:b9ad9a133dc7 96 register uint32_t __regSP __ASM("sp");
Kojto 104:b9ad9a133dc7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 104:b9ad9a133dc7 98 {
Kojto 104:b9ad9a133dc7 99 __regSP = topOfStack;
Kojto 104:b9ad9a133dc7 100 }
Kojto 104:b9ad9a133dc7 101
Kojto 104:b9ad9a133dc7 102
Kojto 104:b9ad9a133dc7 103 /** \brief Get link register
Kojto 104:b9ad9a133dc7 104
Kojto 104:b9ad9a133dc7 105 This function returns the value of the link register
Kojto 104:b9ad9a133dc7 106
Kojto 104:b9ad9a133dc7 107 \return Value of link register
Kojto 104:b9ad9a133dc7 108 */
Kojto 104:b9ad9a133dc7 109 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 104:b9ad9a133dc7 111 {
Kojto 104:b9ad9a133dc7 112 return(__reglr);
Kojto 104:b9ad9a133dc7 113 }
Kojto 104:b9ad9a133dc7 114
Kojto 104:b9ad9a133dc7 115 /** \brief Set link register
Kojto 104:b9ad9a133dc7 116
Kojto 104:b9ad9a133dc7 117 This function sets the value of the link register
Kojto 104:b9ad9a133dc7 118
Kojto 104:b9ad9a133dc7 119 \param [in] lr LR value to set
Kojto 104:b9ad9a133dc7 120 */
Kojto 104:b9ad9a133dc7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 104:b9ad9a133dc7 122 {
Kojto 104:b9ad9a133dc7 123 __reglr = lr;
Kojto 104:b9ad9a133dc7 124 }
Kojto 104:b9ad9a133dc7 125
Kojto 104:b9ad9a133dc7 126 /** \brief Set Process Stack Pointer
Kojto 104:b9ad9a133dc7 127
Kojto 104:b9ad9a133dc7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 104:b9ad9a133dc7 129
Kojto 104:b9ad9a133dc7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 104:b9ad9a133dc7 131 */
Kojto 104:b9ad9a133dc7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 104:b9ad9a133dc7 133 {
Kojto 104:b9ad9a133dc7 134 ARM
Kojto 104:b9ad9a133dc7 135 PRESERVE8
Kojto 104:b9ad9a133dc7 136
Kojto 104:b9ad9a133dc7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 104:b9ad9a133dc7 138 MRS R1, CPSR
Kojto 104:b9ad9a133dc7 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 104:b9ad9a133dc7 140 MOV SP, R0
Kojto 104:b9ad9a133dc7 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 104:b9ad9a133dc7 142 ISB
Kojto 104:b9ad9a133dc7 143 BX LR
Kojto 104:b9ad9a133dc7 144
Kojto 104:b9ad9a133dc7 145 }
Kojto 104:b9ad9a133dc7 146
Kojto 104:b9ad9a133dc7 147 /** \brief Set User Mode
Kojto 104:b9ad9a133dc7 148
Kojto 104:b9ad9a133dc7 149 This function changes the processor state to User Mode
Kojto 104:b9ad9a133dc7 150 */
Kojto 104:b9ad9a133dc7 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 104:b9ad9a133dc7 152 {
Kojto 104:b9ad9a133dc7 153 ARM
Kojto 104:b9ad9a133dc7 154
Kojto 104:b9ad9a133dc7 155 CPS #MODE_USR
Kojto 104:b9ad9a133dc7 156 BX LR
Kojto 104:b9ad9a133dc7 157 }
Kojto 104:b9ad9a133dc7 158
Kojto 104:b9ad9a133dc7 159
Kojto 104:b9ad9a133dc7 160 /** \brief Enable FIQ
Kojto 104:b9ad9a133dc7 161
Kojto 104:b9ad9a133dc7 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 163 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 164 */
Kojto 104:b9ad9a133dc7 165 #define __enable_fault_irq __enable_fiq
Kojto 104:b9ad9a133dc7 166
Kojto 104:b9ad9a133dc7 167
Kojto 104:b9ad9a133dc7 168 /** \brief Disable FIQ
Kojto 104:b9ad9a133dc7 169
Kojto 104:b9ad9a133dc7 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 171 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 172 */
Kojto 104:b9ad9a133dc7 173 #define __disable_fault_irq __disable_fiq
Kojto 104:b9ad9a133dc7 174
Kojto 104:b9ad9a133dc7 175
Kojto 104:b9ad9a133dc7 176 /** \brief Get FPSCR
Kojto 104:b9ad9a133dc7 177
Kojto 104:b9ad9a133dc7 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 179
Kojto 104:b9ad9a133dc7 180 \return Floating Point Status/Control register value
Kojto 104:b9ad9a133dc7 181 */
Kojto 104:b9ad9a133dc7 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 104:b9ad9a133dc7 183 {
Kojto 104:b9ad9a133dc7 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 186 return(__regfpscr);
Kojto 104:b9ad9a133dc7 187 #else
Kojto 104:b9ad9a133dc7 188 return(0);
Kojto 104:b9ad9a133dc7 189 #endif
Kojto 104:b9ad9a133dc7 190 }
Kojto 104:b9ad9a133dc7 191
Kojto 104:b9ad9a133dc7 192
Kojto 104:b9ad9a133dc7 193 /** \brief Set FPSCR
Kojto 104:b9ad9a133dc7 194
Kojto 104:b9ad9a133dc7 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 196
Kojto 104:b9ad9a133dc7 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 104:b9ad9a133dc7 198 */
Kojto 104:b9ad9a133dc7 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 104:b9ad9a133dc7 200 {
Kojto 104:b9ad9a133dc7 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 203 __regfpscr = (fpscr);
Kojto 104:b9ad9a133dc7 204 #endif
Kojto 104:b9ad9a133dc7 205 }
Kojto 104:b9ad9a133dc7 206
Kojto 104:b9ad9a133dc7 207 /** \brief Get FPEXC
Kojto 104:b9ad9a133dc7 208
Kojto 104:b9ad9a133dc7 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 210
Kojto 104:b9ad9a133dc7 211 \return Floating Point Exception Control register value
Kojto 104:b9ad9a133dc7 212 */
Kojto 104:b9ad9a133dc7 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 104:b9ad9a133dc7 214 {
Kojto 104:b9ad9a133dc7 215 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 217 return(__regfpexc);
Kojto 104:b9ad9a133dc7 218 #else
Kojto 104:b9ad9a133dc7 219 return(0);
Kojto 104:b9ad9a133dc7 220 #endif
Kojto 104:b9ad9a133dc7 221 }
Kojto 104:b9ad9a133dc7 222
Kojto 104:b9ad9a133dc7 223
Kojto 104:b9ad9a133dc7 224 /** \brief Set FPEXC
Kojto 104:b9ad9a133dc7 225
Kojto 104:b9ad9a133dc7 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 227
Kojto 104:b9ad9a133dc7 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 104:b9ad9a133dc7 229 */
Kojto 104:b9ad9a133dc7 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 104:b9ad9a133dc7 231 {
Kojto 104:b9ad9a133dc7 232 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 234 __regfpexc = (fpexc);
Kojto 104:b9ad9a133dc7 235 #endif
Kojto 104:b9ad9a133dc7 236 }
Kojto 104:b9ad9a133dc7 237
Kojto 104:b9ad9a133dc7 238 /** \brief Get CPACR
Kojto 104:b9ad9a133dc7 239
Kojto 104:b9ad9a133dc7 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 241
Kojto 104:b9ad9a133dc7 242 \return Coprocessor Access Control register value
Kojto 104:b9ad9a133dc7 243 */
Kojto 104:b9ad9a133dc7 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 104:b9ad9a133dc7 245 {
Kojto 104:b9ad9a133dc7 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 247 return __regCPACR;
Kojto 104:b9ad9a133dc7 248 }
Kojto 104:b9ad9a133dc7 249
Kojto 104:b9ad9a133dc7 250 /** \brief Set CPACR
Kojto 104:b9ad9a133dc7 251
Kojto 104:b9ad9a133dc7 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 104:b9ad9a133dc7 255 */
Kojto 104:b9ad9a133dc7 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 104:b9ad9a133dc7 257 {
Kojto 104:b9ad9a133dc7 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 259 __regCPACR = cpacr;
Kojto 104:b9ad9a133dc7 260 __ISB();
Kojto 104:b9ad9a133dc7 261 }
Kojto 104:b9ad9a133dc7 262
Kojto 104:b9ad9a133dc7 263 /** \brief Get CBAR
Kojto 104:b9ad9a133dc7 264
Kojto 104:b9ad9a133dc7 265 This function returns the value of the Configuration Base Address register.
Kojto 104:b9ad9a133dc7 266
Kojto 104:b9ad9a133dc7 267 \return Configuration Base Address register value
Kojto 104:b9ad9a133dc7 268 */
Kojto 104:b9ad9a133dc7 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 104:b9ad9a133dc7 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 104:b9ad9a133dc7 271 return(__regCBAR);
Kojto 104:b9ad9a133dc7 272 }
Kojto 104:b9ad9a133dc7 273
Kojto 104:b9ad9a133dc7 274 /** \brief Get TTBR0
Kojto 104:b9ad9a133dc7 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 104:b9ad9a133dc7 277
Kojto 104:b9ad9a133dc7 278 \return Translation Table Base Register 0 value
Kojto 104:b9ad9a133dc7 279 */
Kojto 104:b9ad9a133dc7 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 104:b9ad9a133dc7 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 282 return(__regTTBR0);
Kojto 104:b9ad9a133dc7 283 }
Kojto 104:b9ad9a133dc7 284
Kojto 104:b9ad9a133dc7 285 /** \brief Set TTBR0
Kojto 104:b9ad9a133dc7 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 104:b9ad9a133dc7 288
Kojto 104:b9ad9a133dc7 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 104:b9ad9a133dc7 290 */
Kojto 104:b9ad9a133dc7 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 104:b9ad9a133dc7 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 293 __regTTBR0 = ttbr0;
Kojto 104:b9ad9a133dc7 294 __ISB();
Kojto 104:b9ad9a133dc7 295 }
Kojto 104:b9ad9a133dc7 296
Kojto 104:b9ad9a133dc7 297 /** \brief Get DACR
Kojto 104:b9ad9a133dc7 298
Kojto 104:b9ad9a133dc7 299 This function returns the value of the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 300
Kojto 104:b9ad9a133dc7 301 \return Domain Access Control Register value
Kojto 104:b9ad9a133dc7 302 */
Kojto 104:b9ad9a133dc7 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 104:b9ad9a133dc7 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 305 return(__regDACR);
Kojto 104:b9ad9a133dc7 306 }
Kojto 104:b9ad9a133dc7 307
Kojto 104:b9ad9a133dc7 308 /** \brief Set DACR
Kojto 104:b9ad9a133dc7 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 311
Kojto 104:b9ad9a133dc7 312 \param [in] dacr Domain Access Control Register value to set
Kojto 104:b9ad9a133dc7 313 */
Kojto 104:b9ad9a133dc7 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 104:b9ad9a133dc7 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 316 __regDACR = dacr;
Kojto 104:b9ad9a133dc7 317 __ISB();
Kojto 104:b9ad9a133dc7 318 }
Kojto 104:b9ad9a133dc7 319
Kojto 104:b9ad9a133dc7 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 104:b9ad9a133dc7 321
Kojto 104:b9ad9a133dc7 322 /** \brief Set SCTLR
Kojto 104:b9ad9a133dc7 323
Kojto 104:b9ad9a133dc7 324 This function assigns the given value to the System Control Register.
Kojto 104:b9ad9a133dc7 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 104:b9ad9a133dc7 327 */
Kojto 104:b9ad9a133dc7 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 104:b9ad9a133dc7 329 {
Kojto 104:b9ad9a133dc7 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 331 __regSCTLR = sctlr;
Kojto 104:b9ad9a133dc7 332 }
Kojto 104:b9ad9a133dc7 333
Kojto 104:b9ad9a133dc7 334 /** \brief Get SCTLR
Kojto 104:b9ad9a133dc7 335
Kojto 104:b9ad9a133dc7 336 This function returns the value of the System Control Register.
Kojto 104:b9ad9a133dc7 337
Kojto 104:b9ad9a133dc7 338 \return System Control Register value
Kojto 104:b9ad9a133dc7 339 */
Kojto 104:b9ad9a133dc7 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 104:b9ad9a133dc7 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 342 return(__regSCTLR);
Kojto 104:b9ad9a133dc7 343 }
Kojto 104:b9ad9a133dc7 344
Kojto 104:b9ad9a133dc7 345 /** \brief Enable Caches
Kojto 104:b9ad9a133dc7 346
Kojto 104:b9ad9a133dc7 347 Enable Caches
Kojto 104:b9ad9a133dc7 348 */
Kojto 104:b9ad9a133dc7 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 104:b9ad9a133dc7 350 // Set I bit 12 to enable I Cache
Kojto 104:b9ad9a133dc7 351 // Set C bit 2 to enable D Cache
Kojto 104:b9ad9a133dc7 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 104:b9ad9a133dc7 353 }
Kojto 104:b9ad9a133dc7 354
Kojto 104:b9ad9a133dc7 355 /** \brief Disable Caches
Kojto 104:b9ad9a133dc7 356
Kojto 104:b9ad9a133dc7 357 Disable Caches
Kojto 104:b9ad9a133dc7 358 */
Kojto 104:b9ad9a133dc7 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 104:b9ad9a133dc7 360 // Clear I bit 12 to disable I Cache
Kojto 104:b9ad9a133dc7 361 // Clear C bit 2 to disable D Cache
Kojto 104:b9ad9a133dc7 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 104:b9ad9a133dc7 363 __ISB();
Kojto 104:b9ad9a133dc7 364 }
Kojto 104:b9ad9a133dc7 365
Kojto 104:b9ad9a133dc7 366 /** \brief Enable BTAC
Kojto 104:b9ad9a133dc7 367
Kojto 104:b9ad9a133dc7 368 Enable BTAC
Kojto 104:b9ad9a133dc7 369 */
Kojto 104:b9ad9a133dc7 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 104:b9ad9a133dc7 371 // Set Z bit 11 to enable branch prediction
Kojto 104:b9ad9a133dc7 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 104:b9ad9a133dc7 373 __ISB();
Kojto 104:b9ad9a133dc7 374 }
Kojto 104:b9ad9a133dc7 375
Kojto 104:b9ad9a133dc7 376 /** \brief Disable BTAC
Kojto 104:b9ad9a133dc7 377
Kojto 104:b9ad9a133dc7 378 Disable BTAC
Kojto 104:b9ad9a133dc7 379 */
Kojto 104:b9ad9a133dc7 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 104:b9ad9a133dc7 381 // Clear Z bit 11 to disable branch prediction
Kojto 104:b9ad9a133dc7 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 104:b9ad9a133dc7 383 }
Kojto 104:b9ad9a133dc7 384
Kojto 104:b9ad9a133dc7 385
Kojto 104:b9ad9a133dc7 386 /** \brief Enable MMU
Kojto 104:b9ad9a133dc7 387
Kojto 104:b9ad9a133dc7 388 Enable MMU
Kojto 104:b9ad9a133dc7 389 */
Kojto 104:b9ad9a133dc7 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 104:b9ad9a133dc7 391 // Set M bit 0 to enable the MMU
Kojto 104:b9ad9a133dc7 392 // Set AFE bit to enable simplified access permissions model
Kojto 104:b9ad9a133dc7 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 104:b9ad9a133dc7 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 104:b9ad9a133dc7 395 __ISB();
Kojto 104:b9ad9a133dc7 396 }
Kojto 104:b9ad9a133dc7 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 104:b9ad9a133dc7 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 104:b9ad9a133dc7 401 */
Kojto 104:b9ad9a133dc7 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 104:b9ad9a133dc7 403 // Clear M bit 0 to disable the MMU
Kojto 104:b9ad9a133dc7 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 104:b9ad9a133dc7 405 __ISB();
Kojto 104:b9ad9a133dc7 406 }
Kojto 104:b9ad9a133dc7 407
Kojto 104:b9ad9a133dc7 408 /******************************** TLB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 409 /** \brief Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 410
Kojto 104:b9ad9a133dc7 411 TLBIALL. Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 412 */
Kojto 104:b9ad9a133dc7 413
Kojto 104:b9ad9a133dc7 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 104:b9ad9a133dc7 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 104:b9ad9a133dc7 416 __TLBIALL = 0;
Kojto 104:b9ad9a133dc7 417 __DSB();
Kojto 104:b9ad9a133dc7 418 __ISB();
Kojto 104:b9ad9a133dc7 419 }
Kojto 104:b9ad9a133dc7 420
Kojto 104:b9ad9a133dc7 421 /******************************** BTB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 422 /** \brief Invalidate entire branch predictor array
Kojto 104:b9ad9a133dc7 423
Kojto 104:b9ad9a133dc7 424 BPIALL. Branch Predictor Invalidate All.
Kojto 104:b9ad9a133dc7 425 */
Kojto 104:b9ad9a133dc7 426
Kojto 104:b9ad9a133dc7 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 104:b9ad9a133dc7 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 104:b9ad9a133dc7 429 __BPIALL = 0;
Kojto 104:b9ad9a133dc7 430 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 104:b9ad9a133dc7 432 }
Kojto 104:b9ad9a133dc7 433
Kojto 104:b9ad9a133dc7 434
Kojto 104:b9ad9a133dc7 435 /******************************** L1 cache operations ******************************************************/
Kojto 104:b9ad9a133dc7 436
Kojto 104:b9ad9a133dc7 437 /** \brief Invalidate the whole I$
Kojto 104:b9ad9a133dc7 438
Kojto 104:b9ad9a133dc7 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 104:b9ad9a133dc7 440 */
Kojto 104:b9ad9a133dc7 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 104:b9ad9a133dc7 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 104:b9ad9a133dc7 443 __ICIALLU = 0;
Kojto 104:b9ad9a133dc7 444 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 104:b9ad9a133dc7 446 }
Kojto 104:b9ad9a133dc7 447
Kojto 104:b9ad9a133dc7 448 /** \brief Clean D$ by MVA
Kojto 104:b9ad9a133dc7 449
Kojto 104:b9ad9a133dc7 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 104:b9ad9a133dc7 451 */
Kojto 104:b9ad9a133dc7 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 104:b9ad9a133dc7 454 __DCCMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 456 }
Kojto 104:b9ad9a133dc7 457
Kojto 104:b9ad9a133dc7 458 /** \brief Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 459
Kojto 104:b9ad9a133dc7 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 461 */
Kojto 104:b9ad9a133dc7 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 104:b9ad9a133dc7 464 __DCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 466 }
Kojto 104:b9ad9a133dc7 467
Kojto 104:b9ad9a133dc7 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 469
Kojto 104:b9ad9a133dc7 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 471 */
Kojto 104:b9ad9a133dc7 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 104:b9ad9a133dc7 474 __DCCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 476 }
Kojto 104:b9ad9a133dc7 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 104:b9ad9a133dc7 481 */
Kojto 104:b9ad9a133dc7 482 #pragma push
Kojto 104:b9ad9a133dc7 483 #pragma arm
Kojto 104:b9ad9a133dc7 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 104:b9ad9a133dc7 485 ARM
Kojto 104:b9ad9a133dc7 486
Kojto 104:b9ad9a133dc7 487 PUSH {R4-R11}
Kojto 104:b9ad9a133dc7 488
Kojto 104:b9ad9a133dc7 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 104:b9ad9a133dc7 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 104:b9ad9a133dc7 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 104:b9ad9a133dc7 492 BEQ Finished // If 0, no need to clean
Kojto 104:b9ad9a133dc7 493
Kojto 104:b9ad9a133dc7 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 104:b9ad9a133dc7 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 104:b9ad9a133dc7 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 104:b9ad9a133dc7 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 104:b9ad9a133dc7 498 CMP R1, #2
Kojto 104:b9ad9a133dc7 499 BLT Skip // No cache or only instruction cache at this level
Kojto 104:b9ad9a133dc7 500
Kojto 104:b9ad9a133dc7 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 104:b9ad9a133dc7 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 104:b9ad9a133dc7 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 104:b9ad9a133dc7 504 AND R2, R1, #7 // Extract the line length field
Kojto 104:b9ad9a133dc7 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 104:b9ad9a133dc7 506 LDR R4, =0x3FF
Kojto 104:b9ad9a133dc7 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 104:b9ad9a133dc7 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 104:b9ad9a133dc7 509 LDR R7, =0x7FFF
Kojto 104:b9ad9a133dc7 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 104:b9ad9a133dc7 511
Kojto 104:b9ad9a133dc7 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 104:b9ad9a133dc7 513
Kojto 104:b9ad9a133dc7 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 104:b9ad9a133dc7 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 104:b9ad9a133dc7 516 CMP R0, #0
Kojto 104:b9ad9a133dc7 517 BNE Dccsw
Kojto 104:b9ad9a133dc7 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 519 B cont
Kojto 104:b9ad9a133dc7 520 Dccsw CMP R0, #1
Kojto 104:b9ad9a133dc7 521 BNE Dccisw
Kojto 104:b9ad9a133dc7 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 104:b9ad9a133dc7 526 BGE Loop3
Kojto 104:b9ad9a133dc7 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 104:b9ad9a133dc7 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 104:b9ad9a133dc7 530 CMP R3, R10
Kojto 104:b9ad9a133dc7 531 BGT Loop1
Kojto 104:b9ad9a133dc7 532
Kojto 104:b9ad9a133dc7 533 Finished
Kojto 104:b9ad9a133dc7 534 DSB
Kojto 104:b9ad9a133dc7 535 POP {R4-R11}
Kojto 104:b9ad9a133dc7 536 BX lr
Kojto 104:b9ad9a133dc7 537
Kojto 104:b9ad9a133dc7 538 }
Kojto 104:b9ad9a133dc7 539 #pragma pop
Kojto 104:b9ad9a133dc7 540
Kojto 104:b9ad9a133dc7 541
Kojto 104:b9ad9a133dc7 542 /** \brief Invalidate the whole D$
Kojto 104:b9ad9a133dc7 543
Kojto 104:b9ad9a133dc7 544 DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 545 */
Kojto 104:b9ad9a133dc7 546
Kojto 104:b9ad9a133dc7 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 548 __v7_all_cache(0);
Kojto 104:b9ad9a133dc7 549 }
Kojto 104:b9ad9a133dc7 550
Kojto 104:b9ad9a133dc7 551 /** \brief Clean the whole D$
Kojto 104:b9ad9a133dc7 552
Kojto 104:b9ad9a133dc7 553 DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 554 */
Kojto 104:b9ad9a133dc7 555
Kojto 104:b9ad9a133dc7 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 104:b9ad9a133dc7 557 __v7_all_cache(1);
Kojto 104:b9ad9a133dc7 558 }
Kojto 104:b9ad9a133dc7 559
Kojto 104:b9ad9a133dc7 560 /** \brief Clean and invalidate the whole D$
Kojto 104:b9ad9a133dc7 561
Kojto 104:b9ad9a133dc7 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 563 */
Kojto 104:b9ad9a133dc7 564
Kojto 104:b9ad9a133dc7 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 566 __v7_all_cache(2);
Kojto 104:b9ad9a133dc7 567 }
Kojto 104:b9ad9a133dc7 568
Kojto 104:b9ad9a133dc7 569 #include "core_ca_mmu.h"
Kojto 104:b9ad9a133dc7 570
Kojto 104:b9ad9a133dc7 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 104:b9ad9a133dc7 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
Kojto 115:87f2f5183dfb 814 #include "core_ca_mmu.h"
Kojto 104:b9ad9a133dc7 815
Kojto 104:b9ad9a133dc7 816 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 104:b9ad9a133dc7 817 /* GNU gcc specific functions */
Kojto 104:b9ad9a133dc7 818
Kojto 104:b9ad9a133dc7 819 #define MODE_USR 0x10
Kojto 104:b9ad9a133dc7 820 #define MODE_FIQ 0x11
Kojto 104:b9ad9a133dc7 821 #define MODE_IRQ 0x12
Kojto 104:b9ad9a133dc7 822 #define MODE_SVC 0x13
Kojto 104:b9ad9a133dc7 823 #define MODE_MON 0x16
Kojto 104:b9ad9a133dc7 824 #define MODE_ABT 0x17
Kojto 104:b9ad9a133dc7 825 #define MODE_HYP 0x1A
Kojto 104:b9ad9a133dc7 826 #define MODE_UND 0x1B
Kojto 104:b9ad9a133dc7 827 #define MODE_SYS 0x1F
Kojto 104:b9ad9a133dc7 828
Kojto 104:b9ad9a133dc7 829
Kojto 104:b9ad9a133dc7 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 104:b9ad9a133dc7 831 {
Kojto 104:b9ad9a133dc7 832 __ASM volatile ("cpsie i");
Kojto 104:b9ad9a133dc7 833 }
Kojto 104:b9ad9a133dc7 834
Kojto 104:b9ad9a133dc7 835 /** \brief Disable IRQ Interrupts
Kojto 104:b9ad9a133dc7 836
Kojto 104:b9ad9a133dc7 837 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 104:b9ad9a133dc7 838 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 839 */
Kojto 104:b9ad9a133dc7 840 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 104:b9ad9a133dc7 841 {
Kojto 104:b9ad9a133dc7 842 uint32_t result;
Kojto 104:b9ad9a133dc7 843
Kojto 104:b9ad9a133dc7 844 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 104:b9ad9a133dc7 845 __ASM volatile ("cpsid i");
Kojto 104:b9ad9a133dc7 846 return(result & 0x80);
Kojto 104:b9ad9a133dc7 847 }
Kojto 104:b9ad9a133dc7 848
Kojto 104:b9ad9a133dc7 849
Kojto 104:b9ad9a133dc7 850 /** \brief Get APSR Register
Kojto 104:b9ad9a133dc7 851
Kojto 104:b9ad9a133dc7 852 This function returns the content of the APSR Register.
Kojto 104:b9ad9a133dc7 853
Kojto 104:b9ad9a133dc7 854 \return APSR Register value
Kojto 104:b9ad9a133dc7 855 */
Kojto 104:b9ad9a133dc7 856 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 104:b9ad9a133dc7 857 {
Kojto 104:b9ad9a133dc7 858 #if 1
Kojto 108:34e6b704fe68 859 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 860 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 104:b9ad9a133dc7 861 #else
Kojto 104:b9ad9a133dc7 862 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 863 #endif
Kojto 104:b9ad9a133dc7 864 return(__regAPSR);
Kojto 104:b9ad9a133dc7 865 }
Kojto 104:b9ad9a133dc7 866
Kojto 104:b9ad9a133dc7 867
Kojto 104:b9ad9a133dc7 868 /** \brief Get CPSR Register
Kojto 104:b9ad9a133dc7 869
Kojto 104:b9ad9a133dc7 870 This function returns the content of the CPSR Register.
Kojto 104:b9ad9a133dc7 871
Kojto 104:b9ad9a133dc7 872 \return CPSR Register value
Kojto 104:b9ad9a133dc7 873 */
Kojto 104:b9ad9a133dc7 874 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 104:b9ad9a133dc7 875 {
Kojto 104:b9ad9a133dc7 876 #if 1
Kojto 104:b9ad9a133dc7 877 register uint32_t __regCPSR;
Kojto 104:b9ad9a133dc7 878 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 104:b9ad9a133dc7 879 #else
Kojto 104:b9ad9a133dc7 880 register uint32_t __regCPSR __ASM("cpsr");
Kojto 104:b9ad9a133dc7 881 #endif
Kojto 104:b9ad9a133dc7 882 return(__regCPSR);
Kojto 104:b9ad9a133dc7 883 }
Kojto 104:b9ad9a133dc7 884
Kojto 104:b9ad9a133dc7 885 #if 0
Kojto 104:b9ad9a133dc7 886 /** \brief Set Stack Pointer
Kojto 104:b9ad9a133dc7 887
Kojto 104:b9ad9a133dc7 888 This function assigns the given value to the current stack pointer.
Kojto 104:b9ad9a133dc7 889
Kojto 104:b9ad9a133dc7 890 \param [in] topOfStack Stack Pointer value to set
Kojto 104:b9ad9a133dc7 891 */
Kojto 104:b9ad9a133dc7 892 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 104:b9ad9a133dc7 893 {
Kojto 104:b9ad9a133dc7 894 register uint32_t __regSP __ASM("sp");
Kojto 104:b9ad9a133dc7 895 __regSP = topOfStack;
Kojto 104:b9ad9a133dc7 896 }
Kojto 104:b9ad9a133dc7 897 #endif
Kojto 104:b9ad9a133dc7 898
Kojto 104:b9ad9a133dc7 899 /** \brief Get link register
Kojto 104:b9ad9a133dc7 900
Kojto 104:b9ad9a133dc7 901 This function returns the value of the link register
Kojto 104:b9ad9a133dc7 902
Kojto 104:b9ad9a133dc7 903 \return Value of link register
Kojto 104:b9ad9a133dc7 904 */
Kojto 104:b9ad9a133dc7 905 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 104:b9ad9a133dc7 906 {
Kojto 104:b9ad9a133dc7 907 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 908 return(__reglr);
Kojto 104:b9ad9a133dc7 909 }
Kojto 104:b9ad9a133dc7 910
Kojto 104:b9ad9a133dc7 911 #if 0
Kojto 104:b9ad9a133dc7 912 /** \brief Set link register
Kojto 104:b9ad9a133dc7 913
Kojto 104:b9ad9a133dc7 914 This function sets the value of the link register
Kojto 104:b9ad9a133dc7 915
Kojto 104:b9ad9a133dc7 916 \param [in] lr LR value to set
Kojto 104:b9ad9a133dc7 917 */
Kojto 104:b9ad9a133dc7 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 104:b9ad9a133dc7 919 {
Kojto 104:b9ad9a133dc7 920 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 921 __reglr = lr;
Kojto 104:b9ad9a133dc7 922 }
Kojto 104:b9ad9a133dc7 923 #endif
Kojto 104:b9ad9a133dc7 924
Kojto 104:b9ad9a133dc7 925 /** \brief Set Process Stack Pointer
Kojto 104:b9ad9a133dc7 926
Kojto 104:b9ad9a133dc7 927 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 104:b9ad9a133dc7 928
Kojto 104:b9ad9a133dc7 929 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 104:b9ad9a133dc7 930 */
Kojto 108:34e6b704fe68 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 932 {
Kojto 108:34e6b704fe68 933 __asm__ volatile (
Kojto 108:34e6b704fe68 934 ".ARM;"
Kojto 108:34e6b704fe68 935 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 936
Kojto 108:34e6b704fe68 937 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 938 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 939 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 940 "MOV SP, R0;"
Kojto 108:34e6b704fe68 941 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 942 "ISB;"
Kojto 108:34e6b704fe68 943 //"BX LR;"
Kojto 108:34e6b704fe68 944 :
Kojto 108:34e6b704fe68 945 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 946 : "r0", "r1");
Kojto 108:34e6b704fe68 947 return;
Kojto 108:34e6b704fe68 948 }
Kojto 104:b9ad9a133dc7 949
Kojto 104:b9ad9a133dc7 950 /** \brief Set User Mode
Kojto 104:b9ad9a133dc7 951
Kojto 104:b9ad9a133dc7 952 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 953 */
Kojto 108:34e6b704fe68 954 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 955 {
Kojto 108:34e6b704fe68 956 __asm__ volatile (
Kojto 108:34e6b704fe68 957 ".ARM;"
Kojto 104:b9ad9a133dc7 958
Kojto 108:34e6b704fe68 959 "CPS %0;"
Kojto 108:34e6b704fe68 960 //"BX LR;"
Kojto 108:34e6b704fe68 961 :
Kojto 108:34e6b704fe68 962 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 963 : );
Kojto 108:34e6b704fe68 964 return;
Kojto 108:34e6b704fe68 965 }
Kojto 108:34e6b704fe68 966
Kojto 104:b9ad9a133dc7 967
Kojto 104:b9ad9a133dc7 968 /** \brief Enable FIQ
Kojto 104:b9ad9a133dc7 969
Kojto 104:b9ad9a133dc7 970 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 971 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 972 */
Kojto 108:34e6b704fe68 973 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 104:b9ad9a133dc7 974
Kojto 104:b9ad9a133dc7 975
Kojto 104:b9ad9a133dc7 976 /** \brief Disable FIQ
Kojto 104:b9ad9a133dc7 977
Kojto 104:b9ad9a133dc7 978 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 979 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 980 */
Kojto 108:34e6b704fe68 981 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 104:b9ad9a133dc7 982
Kojto 104:b9ad9a133dc7 983
Kojto 104:b9ad9a133dc7 984 /** \brief Get FPSCR
Kojto 104:b9ad9a133dc7 985
Kojto 104:b9ad9a133dc7 986 This function returns the current value of the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 987
Kojto 104:b9ad9a133dc7 988 \return Floating Point Status/Control register value
Kojto 104:b9ad9a133dc7 989 */
Kojto 104:b9ad9a133dc7 990 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 104:b9ad9a133dc7 991 {
Kojto 104:b9ad9a133dc7 992 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 993 #if 1
Kojto 104:b9ad9a133dc7 994 uint32_t result;
Kojto 104:b9ad9a133dc7 995
Kojto 104:b9ad9a133dc7 996 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 104:b9ad9a133dc7 997 return (result);
Kojto 104:b9ad9a133dc7 998 #else
Kojto 104:b9ad9a133dc7 999 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 1000 return(__regfpscr);
Kojto 104:b9ad9a133dc7 1001 #endif
Kojto 104:b9ad9a133dc7 1002 #else
Kojto 104:b9ad9a133dc7 1003 return(0);
Kojto 104:b9ad9a133dc7 1004 #endif
Kojto 104:b9ad9a133dc7 1005 }
Kojto 104:b9ad9a133dc7 1006
Kojto 104:b9ad9a133dc7 1007
Kojto 104:b9ad9a133dc7 1008 /** \brief Set FPSCR
Kojto 104:b9ad9a133dc7 1009
Kojto 104:b9ad9a133dc7 1010 This function assigns the given value to the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 1011
Kojto 104:b9ad9a133dc7 1012 \param [in] fpscr Floating Point Status/Control value to set
Kojto 104:b9ad9a133dc7 1013 */
Kojto 104:b9ad9a133dc7 1014 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 104:b9ad9a133dc7 1015 {
Kojto 104:b9ad9a133dc7 1016 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 1017 #if 1
Kojto 104:b9ad9a133dc7 1018 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 104:b9ad9a133dc7 1019 #else
Kojto 104:b9ad9a133dc7 1020 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 1021 __regfpscr = (fpscr);
Kojto 104:b9ad9a133dc7 1022 #endif
Kojto 104:b9ad9a133dc7 1023 #endif
Kojto 104:b9ad9a133dc7 1024 }
Kojto 104:b9ad9a133dc7 1025
Kojto 104:b9ad9a133dc7 1026 /** \brief Get FPEXC
Kojto 104:b9ad9a133dc7 1027
Kojto 104:b9ad9a133dc7 1028 This function returns the current value of the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 1029
Kojto 104:b9ad9a133dc7 1030 \return Floating Point Exception Control register value
Kojto 104:b9ad9a133dc7 1031 */
Kojto 104:b9ad9a133dc7 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 104:b9ad9a133dc7 1033 {
Kojto 104:b9ad9a133dc7 1034 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 1035 #if 1
Kojto 104:b9ad9a133dc7 1036 uint32_t result;
Kojto 104:b9ad9a133dc7 1037
Kojto 104:b9ad9a133dc7 1038 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 104:b9ad9a133dc7 1039 return (result);
Kojto 104:b9ad9a133dc7 1040 #else
Kojto 104:b9ad9a133dc7 1041 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 1042 return(__regfpexc);
Kojto 104:b9ad9a133dc7 1043 #endif
Kojto 104:b9ad9a133dc7 1044 #else
Kojto 104:b9ad9a133dc7 1045 return(0);
Kojto 104:b9ad9a133dc7 1046 #endif
Kojto 104:b9ad9a133dc7 1047 }
Kojto 104:b9ad9a133dc7 1048
Kojto 104:b9ad9a133dc7 1049
Kojto 104:b9ad9a133dc7 1050 /** \brief Set FPEXC
Kojto 104:b9ad9a133dc7 1051
Kojto 104:b9ad9a133dc7 1052 This function assigns the given value to the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 1053
Kojto 104:b9ad9a133dc7 1054 \param [in] fpscr Floating Point Exception Control value to set
Kojto 104:b9ad9a133dc7 1055 */
Kojto 104:b9ad9a133dc7 1056 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 104:b9ad9a133dc7 1057 {
Kojto 104:b9ad9a133dc7 1058 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 1059 #if 1
Kojto 104:b9ad9a133dc7 1060 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 104:b9ad9a133dc7 1061 #else
Kojto 104:b9ad9a133dc7 1062 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 1063 __regfpexc = (fpexc);
Kojto 104:b9ad9a133dc7 1064 #endif
Kojto 104:b9ad9a133dc7 1065 #endif
Kojto 104:b9ad9a133dc7 1066 }
Kojto 104:b9ad9a133dc7 1067
Kojto 104:b9ad9a133dc7 1068 /** \brief Get CPACR
Kojto 104:b9ad9a133dc7 1069
Kojto 104:b9ad9a133dc7 1070 This function returns the current value of the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 1071
Kojto 104:b9ad9a133dc7 1072 \return Coprocessor Access Control register value
Kojto 104:b9ad9a133dc7 1073 */
Kojto 104:b9ad9a133dc7 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 104:b9ad9a133dc7 1075 {
Kojto 104:b9ad9a133dc7 1076 #if 1
Kojto 104:b9ad9a133dc7 1077 register uint32_t __regCPACR;
Kojto 104:b9ad9a133dc7 1078 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 104:b9ad9a133dc7 1079 #else
Kojto 104:b9ad9a133dc7 1080 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 1081 #endif
Kojto 104:b9ad9a133dc7 1082 return __regCPACR;
Kojto 104:b9ad9a133dc7 1083 }
Kojto 104:b9ad9a133dc7 1084
Kojto 104:b9ad9a133dc7 1085 /** \brief Set CPACR
Kojto 104:b9ad9a133dc7 1086
Kojto 104:b9ad9a133dc7 1087 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 1088
Kojto 108:34e6b704fe68 1089 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 104:b9ad9a133dc7 1090 */
Kojto 104:b9ad9a133dc7 1091 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 104:b9ad9a133dc7 1092 {
Kojto 104:b9ad9a133dc7 1093 #if 1
Kojto 104:b9ad9a133dc7 1094 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 104:b9ad9a133dc7 1095 #else
Kojto 104:b9ad9a133dc7 1096 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 1097 __regCPACR = cpacr;
Kojto 104:b9ad9a133dc7 1098 #endif
Kojto 104:b9ad9a133dc7 1099 __ISB();
Kojto 104:b9ad9a133dc7 1100 }
Kojto 104:b9ad9a133dc7 1101
Kojto 104:b9ad9a133dc7 1102 /** \brief Get CBAR
Kojto 104:b9ad9a133dc7 1103
Kojto 104:b9ad9a133dc7 1104 This function returns the value of the Configuration Base Address register.
Kojto 104:b9ad9a133dc7 1105
Kojto 104:b9ad9a133dc7 1106 \return Configuration Base Address register value
Kojto 104:b9ad9a133dc7 1107 */
Kojto 104:b9ad9a133dc7 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 104:b9ad9a133dc7 1109 #if 1
Kojto 104:b9ad9a133dc7 1110 register uint32_t __regCBAR;
Kojto 104:b9ad9a133dc7 1111 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 104:b9ad9a133dc7 1112 #else
Kojto 104:b9ad9a133dc7 1113 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 104:b9ad9a133dc7 1114 #endif
Kojto 104:b9ad9a133dc7 1115 return(__regCBAR);
Kojto 104:b9ad9a133dc7 1116 }
Kojto 104:b9ad9a133dc7 1117
Kojto 104:b9ad9a133dc7 1118 /** \brief Get TTBR0
Kojto 104:b9ad9a133dc7 1119
Kojto 108:34e6b704fe68 1120 This function returns the value of the Translation Table Base Register 0.
Kojto 104:b9ad9a133dc7 1121
Kojto 104:b9ad9a133dc7 1122 \return Translation Table Base Register 0 value
Kojto 104:b9ad9a133dc7 1123 */
Kojto 104:b9ad9a133dc7 1124 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 104:b9ad9a133dc7 1125 #if 1
Kojto 104:b9ad9a133dc7 1126 register uint32_t __regTTBR0;
Kojto 104:b9ad9a133dc7 1127 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 104:b9ad9a133dc7 1128 #else
Kojto 104:b9ad9a133dc7 1129 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 1130 #endif
Kojto 104:b9ad9a133dc7 1131 return(__regTTBR0);
Kojto 104:b9ad9a133dc7 1132 }
Kojto 104:b9ad9a133dc7 1133
Kojto 104:b9ad9a133dc7 1134 /** \brief Set TTBR0
Kojto 104:b9ad9a133dc7 1135
Kojto 108:34e6b704fe68 1136 This function assigns the given value to the Translation Table Base Register 0.
Kojto 104:b9ad9a133dc7 1137
Kojto 104:b9ad9a133dc7 1138 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 104:b9ad9a133dc7 1139 */
Kojto 104:b9ad9a133dc7 1140 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 104:b9ad9a133dc7 1141 #if 1
Kojto 104:b9ad9a133dc7 1142 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 104:b9ad9a133dc7 1143 #else
Kojto 104:b9ad9a133dc7 1144 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 1145 __regTTBR0 = ttbr0;
Kojto 104:b9ad9a133dc7 1146 #endif
Kojto 104:b9ad9a133dc7 1147 __ISB();
Kojto 104:b9ad9a133dc7 1148 }
Kojto 104:b9ad9a133dc7 1149
Kojto 104:b9ad9a133dc7 1150 /** \brief Get DACR
Kojto 104:b9ad9a133dc7 1151
Kojto 104:b9ad9a133dc7 1152 This function returns the value of the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 1153
Kojto 104:b9ad9a133dc7 1154 \return Domain Access Control Register value
Kojto 104:b9ad9a133dc7 1155 */
Kojto 104:b9ad9a133dc7 1156 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 104:b9ad9a133dc7 1157 #if 1
Kojto 104:b9ad9a133dc7 1158 register uint32_t __regDACR;
Kojto 104:b9ad9a133dc7 1159 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 104:b9ad9a133dc7 1160 #else
Kojto 104:b9ad9a133dc7 1161 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 1162 #endif
Kojto 104:b9ad9a133dc7 1163 return(__regDACR);
Kojto 104:b9ad9a133dc7 1164 }
Kojto 104:b9ad9a133dc7 1165
Kojto 104:b9ad9a133dc7 1166 /** \brief Set DACR
Kojto 104:b9ad9a133dc7 1167
Kojto 108:34e6b704fe68 1168 This function assigns the given value to the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 1169
Kojto 104:b9ad9a133dc7 1170 \param [in] dacr Domain Access Control Register value to set
Kojto 104:b9ad9a133dc7 1171 */
Kojto 104:b9ad9a133dc7 1172 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 104:b9ad9a133dc7 1173 #if 1
Kojto 104:b9ad9a133dc7 1174 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 104:b9ad9a133dc7 1175 #else
Kojto 104:b9ad9a133dc7 1176 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 1177 __regDACR = dacr;
Kojto 104:b9ad9a133dc7 1178 #endif
Kojto 104:b9ad9a133dc7 1179 __ISB();
Kojto 104:b9ad9a133dc7 1180 }
Kojto 104:b9ad9a133dc7 1181
Kojto 104:b9ad9a133dc7 1182 /******************************** Cache and BTAC enable ****************************************************/
Kojto 104:b9ad9a133dc7 1183
Kojto 104:b9ad9a133dc7 1184 /** \brief Set SCTLR
Kojto 104:b9ad9a133dc7 1185
Kojto 104:b9ad9a133dc7 1186 This function assigns the given value to the System Control Register.
Kojto 104:b9ad9a133dc7 1187
Kojto 108:34e6b704fe68 1188 \param [in] sctlr System Control Register value to set
Kojto 104:b9ad9a133dc7 1189 */
Kojto 104:b9ad9a133dc7 1190 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 104:b9ad9a133dc7 1191 {
Kojto 104:b9ad9a133dc7 1192 #if 1
Kojto 104:b9ad9a133dc7 1193 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 104:b9ad9a133dc7 1194 #else
Kojto 104:b9ad9a133dc7 1195 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 1196 __regSCTLR = sctlr;
Kojto 104:b9ad9a133dc7 1197 #endif
Kojto 104:b9ad9a133dc7 1198 }
Kojto 104:b9ad9a133dc7 1199
Kojto 104:b9ad9a133dc7 1200 /** \brief Get SCTLR
Kojto 104:b9ad9a133dc7 1201
Kojto 104:b9ad9a133dc7 1202 This function returns the value of the System Control Register.
Kojto 104:b9ad9a133dc7 1203
Kojto 104:b9ad9a133dc7 1204 \return System Control Register value
Kojto 104:b9ad9a133dc7 1205 */
Kojto 104:b9ad9a133dc7 1206 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 104:b9ad9a133dc7 1207 #if 1
Kojto 104:b9ad9a133dc7 1208 register uint32_t __regSCTLR;
Kojto 104:b9ad9a133dc7 1209 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 104:b9ad9a133dc7 1210 #else
Kojto 104:b9ad9a133dc7 1211 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 1212 #endif
Kojto 104:b9ad9a133dc7 1213 return(__regSCTLR);
Kojto 104:b9ad9a133dc7 1214 }
Kojto 104:b9ad9a133dc7 1215
Kojto 104:b9ad9a133dc7 1216 /** \brief Enable Caches
Kojto 104:b9ad9a133dc7 1217
Kojto 104:b9ad9a133dc7 1218 Enable Caches
Kojto 104:b9ad9a133dc7 1219 */
Kojto 104:b9ad9a133dc7 1220 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 104:b9ad9a133dc7 1221 // Set I bit 12 to enable I Cache
Kojto 104:b9ad9a133dc7 1222 // Set C bit 2 to enable D Cache
Kojto 104:b9ad9a133dc7 1223 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 104:b9ad9a133dc7 1224 }
Kojto 104:b9ad9a133dc7 1225
Kojto 104:b9ad9a133dc7 1226 /** \brief Disable Caches
Kojto 104:b9ad9a133dc7 1227
Kojto 104:b9ad9a133dc7 1228 Disable Caches
Kojto 104:b9ad9a133dc7 1229 */
Kojto 104:b9ad9a133dc7 1230 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 104:b9ad9a133dc7 1231 // Clear I bit 12 to disable I Cache
Kojto 104:b9ad9a133dc7 1232 // Clear C bit 2 to disable D Cache
Kojto 104:b9ad9a133dc7 1233 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 104:b9ad9a133dc7 1234 __ISB();
Kojto 104:b9ad9a133dc7 1235 }
Kojto 104:b9ad9a133dc7 1236
Kojto 104:b9ad9a133dc7 1237 /** \brief Enable BTAC
Kojto 104:b9ad9a133dc7 1238
Kojto 104:b9ad9a133dc7 1239 Enable BTAC
Kojto 104:b9ad9a133dc7 1240 */
Kojto 104:b9ad9a133dc7 1241 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 104:b9ad9a133dc7 1242 // Set Z bit 11 to enable branch prediction
Kojto 104:b9ad9a133dc7 1243 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 104:b9ad9a133dc7 1244 __ISB();
Kojto 104:b9ad9a133dc7 1245 }
Kojto 104:b9ad9a133dc7 1246
Kojto 104:b9ad9a133dc7 1247 /** \brief Disable BTAC
Kojto 104:b9ad9a133dc7 1248
Kojto 104:b9ad9a133dc7 1249 Disable BTAC
Kojto 104:b9ad9a133dc7 1250 */
Kojto 104:b9ad9a133dc7 1251 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 104:b9ad9a133dc7 1252 // Clear Z bit 11 to disable branch prediction
Kojto 104:b9ad9a133dc7 1253 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 104:b9ad9a133dc7 1254 }
Kojto 104:b9ad9a133dc7 1255
Kojto 104:b9ad9a133dc7 1256
Kojto 104:b9ad9a133dc7 1257 /** \brief Enable MMU
Kojto 104:b9ad9a133dc7 1258
Kojto 104:b9ad9a133dc7 1259 Enable MMU
Kojto 104:b9ad9a133dc7 1260 */
Kojto 104:b9ad9a133dc7 1261 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 104:b9ad9a133dc7 1262 // Set M bit 0 to enable the MMU
Kojto 104:b9ad9a133dc7 1263 // Set AFE bit to enable simplified access permissions model
Kojto 104:b9ad9a133dc7 1264 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 104:b9ad9a133dc7 1265 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 104:b9ad9a133dc7 1266 __ISB();
Kojto 104:b9ad9a133dc7 1267 }
Kojto 104:b9ad9a133dc7 1268
Kojto 108:34e6b704fe68 1269 /** \brief Disable MMU
Kojto 104:b9ad9a133dc7 1270
Kojto 108:34e6b704fe68 1271 Disable MMU
Kojto 104:b9ad9a133dc7 1272 */
Kojto 104:b9ad9a133dc7 1273 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 104:b9ad9a133dc7 1274 // Clear M bit 0 to disable the MMU
Kojto 104:b9ad9a133dc7 1275 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 104:b9ad9a133dc7 1276 __ISB();
Kojto 104:b9ad9a133dc7 1277 }
Kojto 104:b9ad9a133dc7 1278
Kojto 104:b9ad9a133dc7 1279 /******************************** TLB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 1280 /** \brief Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 1281
Kojto 104:b9ad9a133dc7 1282 TLBIALL. Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 1283 */
Kojto 104:b9ad9a133dc7 1284
Kojto 104:b9ad9a133dc7 1285 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 104:b9ad9a133dc7 1286 #if 1
Kojto 104:b9ad9a133dc7 1287 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 104:b9ad9a133dc7 1288 #else
Kojto 104:b9ad9a133dc7 1289 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 104:b9ad9a133dc7 1290 __TLBIALL = 0;
Kojto 104:b9ad9a133dc7 1291 #endif
Kojto 104:b9ad9a133dc7 1292 __DSB();
Kojto 104:b9ad9a133dc7 1293 __ISB();
Kojto 104:b9ad9a133dc7 1294 }
Kojto 104:b9ad9a133dc7 1295
Kojto 104:b9ad9a133dc7 1296 /******************************** BTB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 1297 /** \brief Invalidate entire branch predictor array
Kojto 104:b9ad9a133dc7 1298
Kojto 104:b9ad9a133dc7 1299 BPIALL. Branch Predictor Invalidate All.
Kojto 104:b9ad9a133dc7 1300 */
Kojto 104:b9ad9a133dc7 1301
Kojto 104:b9ad9a133dc7 1302 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 104:b9ad9a133dc7 1303 #if 1
Kojto 104:b9ad9a133dc7 1304 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 104:b9ad9a133dc7 1305 #else
Kojto 104:b9ad9a133dc7 1306 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 104:b9ad9a133dc7 1307 __BPIALL = 0;
Kojto 104:b9ad9a133dc7 1308 #endif
Kojto 104:b9ad9a133dc7 1309 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 1310 __ISB(); //ensure instruction fetch path sees new state
Kojto 104:b9ad9a133dc7 1311 }
Kojto 104:b9ad9a133dc7 1312
Kojto 104:b9ad9a133dc7 1313
Kojto 104:b9ad9a133dc7 1314 /******************************** L1 cache operations ******************************************************/
Kojto 104:b9ad9a133dc7 1315
Kojto 104:b9ad9a133dc7 1316 /** \brief Invalidate the whole I$
Kojto 104:b9ad9a133dc7 1317
Kojto 104:b9ad9a133dc7 1318 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 104:b9ad9a133dc7 1319 */
Kojto 104:b9ad9a133dc7 1320 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 104:b9ad9a133dc7 1321 #if 1
Kojto 104:b9ad9a133dc7 1322 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 104:b9ad9a133dc7 1323 #else
Kojto 104:b9ad9a133dc7 1324 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 104:b9ad9a133dc7 1325 __ICIALLU = 0;
Kojto 104:b9ad9a133dc7 1326 #endif
Kojto 104:b9ad9a133dc7 1327 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 1328 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 104:b9ad9a133dc7 1329 }
Kojto 104:b9ad9a133dc7 1330
Kojto 104:b9ad9a133dc7 1331 /** \brief Clean D$ by MVA
Kojto 104:b9ad9a133dc7 1332
Kojto 104:b9ad9a133dc7 1333 DCCMVAC. Data cache clean by MVA to PoC
Kojto 104:b9ad9a133dc7 1334 */
Kojto 104:b9ad9a133dc7 1335 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1336 #if 1
Kojto 104:b9ad9a133dc7 1337 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1338 #else
Kojto 104:b9ad9a133dc7 1339 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 104:b9ad9a133dc7 1340 __DCCMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1341 #endif
Kojto 104:b9ad9a133dc7 1342 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1343 }
Kojto 104:b9ad9a133dc7 1344
Kojto 104:b9ad9a133dc7 1345 /** \brief Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 1346
Kojto 104:b9ad9a133dc7 1347 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 1348 */
Kojto 104:b9ad9a133dc7 1349 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1350 #if 1
Kojto 104:b9ad9a133dc7 1351 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1352 #else
Kojto 104:b9ad9a133dc7 1353 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 104:b9ad9a133dc7 1354 __DCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1355 #endif
Kojto 104:b9ad9a133dc7 1356 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1357 }
Kojto 104:b9ad9a133dc7 1358
Kojto 104:b9ad9a133dc7 1359 /** \brief Clean and Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 1360
Kojto 104:b9ad9a133dc7 1361 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 1362 */
Kojto 104:b9ad9a133dc7 1363 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1364 #if 1
Kojto 104:b9ad9a133dc7 1365 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1366 #else
Kojto 104:b9ad9a133dc7 1367 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 104:b9ad9a133dc7 1368 __DCCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1369 #endif
Kojto 104:b9ad9a133dc7 1370 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1371 }
Kojto 104:b9ad9a133dc7 1372
Kojto 108:34e6b704fe68 1373 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 104:b9ad9a133dc7 1374
Kojto 108:34e6b704fe68 1375 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 104:b9ad9a133dc7 1376 */
Kojto 104:b9ad9a133dc7 1377 extern void __v7_all_cache(uint32_t op);
Kojto 104:b9ad9a133dc7 1378
Kojto 104:b9ad9a133dc7 1379
Kojto 104:b9ad9a133dc7 1380 /** \brief Invalidate the whole D$
Kojto 104:b9ad9a133dc7 1381
Kojto 104:b9ad9a133dc7 1382 DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 1383 */
Kojto 104:b9ad9a133dc7 1384
Kojto 104:b9ad9a133dc7 1385 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1386 __v7_all_cache(0);
Kojto 104:b9ad9a133dc7 1387 }
Kojto 104:b9ad9a133dc7 1388
Kojto 104:b9ad9a133dc7 1389 /** \brief Clean the whole D$
Kojto 104:b9ad9a133dc7 1390
Kojto 104:b9ad9a133dc7 1391 DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 1392 */
Kojto 104:b9ad9a133dc7 1393
Kojto 104:b9ad9a133dc7 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1395 __v7_all_cache(1);
Kojto 104:b9ad9a133dc7 1396 }
Kojto 104:b9ad9a133dc7 1397
Kojto 104:b9ad9a133dc7 1398 /** \brief Clean and invalidate the whole D$
Kojto 104:b9ad9a133dc7 1399
Kojto 104:b9ad9a133dc7 1400 DCCISW. Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 1401 */
Kojto 104:b9ad9a133dc7 1402
Kojto 104:b9ad9a133dc7 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1404 __v7_all_cache(2);
Kojto 104:b9ad9a133dc7 1405 }
Kojto 104:b9ad9a133dc7 1406
Kojto 104:b9ad9a133dc7 1407 #include "core_ca_mmu.h"
Kojto 104:b9ad9a133dc7 1408
Kojto 104:b9ad9a133dc7 1409 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 104:b9ad9a133dc7 1410
Kojto 104:b9ad9a133dc7 1411 #error TASKING Compiler support not implemented for Cortex-A
Kojto 104:b9ad9a133dc7 1412
Kojto 104:b9ad9a133dc7 1413 #endif
Kojto 104:b9ad9a133dc7 1414
Kojto 104:b9ad9a133dc7 1415 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 104:b9ad9a133dc7 1416
Kojto 104:b9ad9a133dc7 1417
Kojto 104:b9ad9a133dc7 1418 #endif /* __CORE_CAFUNC_H__ */