mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF51_MICROBIT/core_caFunc.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Parent:
104:b9ad9a133dc7
Child:
115:87f2f5183dfb
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 104:b9ad9a133dc7 1 /**************************************************************************//**
Kojto 104:b9ad9a133dc7 2 * @file core_caFunc.h
Kojto 104:b9ad9a133dc7 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 104:b9ad9a133dc7 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 104:b9ad9a133dc7 6 *
Kojto 104:b9ad9a133dc7 7 * @note
Kojto 104:b9ad9a133dc7 8 *
Kojto 104:b9ad9a133dc7 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 104:b9ad9a133dc7 11
Kojto 104:b9ad9a133dc7 12 All rights reserved.
Kojto 104:b9ad9a133dc7 13 Redistribution and use in source and binary forms, with or without
Kojto 104:b9ad9a133dc7 14 modification, are permitted provided that the following conditions are met:
Kojto 104:b9ad9a133dc7 15 - Redistributions of source code must retain the above copyright
Kojto 104:b9ad9a133dc7 16 notice, this list of conditions and the following disclaimer.
Kojto 104:b9ad9a133dc7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 104:b9ad9a133dc7 18 notice, this list of conditions and the following disclaimer in the
Kojto 104:b9ad9a133dc7 19 documentation and/or other materials provided with the distribution.
Kojto 104:b9ad9a133dc7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 104:b9ad9a133dc7 21 to endorse or promote products derived from this software without
Kojto 104:b9ad9a133dc7 22 specific prior written permission.
Kojto 104:b9ad9a133dc7 23 *
Kojto 104:b9ad9a133dc7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 104:b9ad9a133dc7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 104:b9ad9a133dc7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 104:b9ad9a133dc7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 104:b9ad9a133dc7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 104:b9ad9a133dc7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 104:b9ad9a133dc7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 104:b9ad9a133dc7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 104:b9ad9a133dc7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 104:b9ad9a133dc7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 104:b9ad9a133dc7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 104:b9ad9a133dc7 35 ---------------------------------------------------------------------------*/
Kojto 104:b9ad9a133dc7 36
Kojto 104:b9ad9a133dc7 37
Kojto 104:b9ad9a133dc7 38 #ifndef __CORE_CAFUNC_H__
Kojto 104:b9ad9a133dc7 39 #define __CORE_CAFUNC_H__
Kojto 104:b9ad9a133dc7 40
Kojto 104:b9ad9a133dc7 41
Kojto 104:b9ad9a133dc7 42 /* ########################### Core Function Access ########################### */
Kojto 104:b9ad9a133dc7 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 104:b9ad9a133dc7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 104:b9ad9a133dc7 45 @{
Kojto 104:b9ad9a133dc7 46 */
Kojto 104:b9ad9a133dc7 47
Kojto 104:b9ad9a133dc7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 104:b9ad9a133dc7 49 /* ARM armcc specific functions */
Kojto 104:b9ad9a133dc7 50
Kojto 104:b9ad9a133dc7 51 #if (__ARMCC_VERSION < 400677)
Kojto 104:b9ad9a133dc7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 104:b9ad9a133dc7 53 #endif
Kojto 104:b9ad9a133dc7 54
Kojto 104:b9ad9a133dc7 55 #define MODE_USR 0x10
Kojto 104:b9ad9a133dc7 56 #define MODE_FIQ 0x11
Kojto 104:b9ad9a133dc7 57 #define MODE_IRQ 0x12
Kojto 104:b9ad9a133dc7 58 #define MODE_SVC 0x13
Kojto 104:b9ad9a133dc7 59 #define MODE_MON 0x16
Kojto 104:b9ad9a133dc7 60 #define MODE_ABT 0x17
Kojto 104:b9ad9a133dc7 61 #define MODE_HYP 0x1A
Kojto 104:b9ad9a133dc7 62 #define MODE_UND 0x1B
Kojto 104:b9ad9a133dc7 63 #define MODE_SYS 0x1F
Kojto 104:b9ad9a133dc7 64
Kojto 104:b9ad9a133dc7 65 /** \brief Get APSR Register
Kojto 104:b9ad9a133dc7 66
Kojto 104:b9ad9a133dc7 67 This function returns the content of the APSR Register.
Kojto 104:b9ad9a133dc7 68
Kojto 104:b9ad9a133dc7 69 \return APSR Register value
Kojto 104:b9ad9a133dc7 70 */
Kojto 104:b9ad9a133dc7 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 104:b9ad9a133dc7 72 {
Kojto 104:b9ad9a133dc7 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 104:b9ad9a133dc7 74 return(__regAPSR);
Kojto 104:b9ad9a133dc7 75 }
Kojto 104:b9ad9a133dc7 76
Kojto 104:b9ad9a133dc7 77
Kojto 104:b9ad9a133dc7 78 /** \brief Get CPSR Register
Kojto 104:b9ad9a133dc7 79
Kojto 104:b9ad9a133dc7 80 This function returns the content of the CPSR Register.
Kojto 104:b9ad9a133dc7 81
Kojto 104:b9ad9a133dc7 82 \return CPSR Register value
Kojto 104:b9ad9a133dc7 83 */
Kojto 104:b9ad9a133dc7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 104:b9ad9a133dc7 85 {
Kojto 104:b9ad9a133dc7 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 104:b9ad9a133dc7 87 return(__regCPSR);
Kojto 104:b9ad9a133dc7 88 }
Kojto 104:b9ad9a133dc7 89
Kojto 104:b9ad9a133dc7 90 /** \brief Set Stack Pointer
Kojto 104:b9ad9a133dc7 91
Kojto 104:b9ad9a133dc7 92 This function assigns the given value to the current stack pointer.
Kojto 104:b9ad9a133dc7 93
Kojto 104:b9ad9a133dc7 94 \param [in] topOfStack Stack Pointer value to set
Kojto 104:b9ad9a133dc7 95 */
Kojto 104:b9ad9a133dc7 96 register uint32_t __regSP __ASM("sp");
Kojto 104:b9ad9a133dc7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 104:b9ad9a133dc7 98 {
Kojto 104:b9ad9a133dc7 99 __regSP = topOfStack;
Kojto 104:b9ad9a133dc7 100 }
Kojto 104:b9ad9a133dc7 101
Kojto 104:b9ad9a133dc7 102
Kojto 104:b9ad9a133dc7 103 /** \brief Get link register
Kojto 104:b9ad9a133dc7 104
Kojto 104:b9ad9a133dc7 105 This function returns the value of the link register
Kojto 104:b9ad9a133dc7 106
Kojto 104:b9ad9a133dc7 107 \return Value of link register
Kojto 104:b9ad9a133dc7 108 */
Kojto 104:b9ad9a133dc7 109 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 104:b9ad9a133dc7 111 {
Kojto 104:b9ad9a133dc7 112 return(__reglr);
Kojto 104:b9ad9a133dc7 113 }
Kojto 104:b9ad9a133dc7 114
Kojto 104:b9ad9a133dc7 115 /** \brief Set link register
Kojto 104:b9ad9a133dc7 116
Kojto 104:b9ad9a133dc7 117 This function sets the value of the link register
Kojto 104:b9ad9a133dc7 118
Kojto 104:b9ad9a133dc7 119 \param [in] lr LR value to set
Kojto 104:b9ad9a133dc7 120 */
Kojto 104:b9ad9a133dc7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 104:b9ad9a133dc7 122 {
Kojto 104:b9ad9a133dc7 123 __reglr = lr;
Kojto 104:b9ad9a133dc7 124 }
Kojto 104:b9ad9a133dc7 125
Kojto 104:b9ad9a133dc7 126 /** \brief Set Process Stack Pointer
Kojto 104:b9ad9a133dc7 127
Kojto 104:b9ad9a133dc7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 104:b9ad9a133dc7 129
Kojto 104:b9ad9a133dc7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 104:b9ad9a133dc7 131 */
Kojto 104:b9ad9a133dc7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 104:b9ad9a133dc7 133 {
Kojto 104:b9ad9a133dc7 134 ARM
Kojto 104:b9ad9a133dc7 135 PRESERVE8
Kojto 104:b9ad9a133dc7 136
Kojto 104:b9ad9a133dc7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 104:b9ad9a133dc7 138 MRS R1, CPSR
Kojto 104:b9ad9a133dc7 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 104:b9ad9a133dc7 140 MOV SP, R0
Kojto 104:b9ad9a133dc7 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 104:b9ad9a133dc7 142 ISB
Kojto 104:b9ad9a133dc7 143 BX LR
Kojto 104:b9ad9a133dc7 144
Kojto 104:b9ad9a133dc7 145 }
Kojto 104:b9ad9a133dc7 146
Kojto 104:b9ad9a133dc7 147 /** \brief Set User Mode
Kojto 104:b9ad9a133dc7 148
Kojto 104:b9ad9a133dc7 149 This function changes the processor state to User Mode
Kojto 104:b9ad9a133dc7 150 */
Kojto 104:b9ad9a133dc7 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 104:b9ad9a133dc7 152 {
Kojto 104:b9ad9a133dc7 153 ARM
Kojto 104:b9ad9a133dc7 154
Kojto 104:b9ad9a133dc7 155 CPS #MODE_USR
Kojto 104:b9ad9a133dc7 156 BX LR
Kojto 104:b9ad9a133dc7 157 }
Kojto 104:b9ad9a133dc7 158
Kojto 104:b9ad9a133dc7 159
Kojto 104:b9ad9a133dc7 160 /** \brief Enable FIQ
Kojto 104:b9ad9a133dc7 161
Kojto 104:b9ad9a133dc7 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 163 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 164 */
Kojto 104:b9ad9a133dc7 165 #define __enable_fault_irq __enable_fiq
Kojto 104:b9ad9a133dc7 166
Kojto 104:b9ad9a133dc7 167
Kojto 104:b9ad9a133dc7 168 /** \brief Disable FIQ
Kojto 104:b9ad9a133dc7 169
Kojto 104:b9ad9a133dc7 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 171 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 172 */
Kojto 104:b9ad9a133dc7 173 #define __disable_fault_irq __disable_fiq
Kojto 104:b9ad9a133dc7 174
Kojto 104:b9ad9a133dc7 175
Kojto 104:b9ad9a133dc7 176 /** \brief Get FPSCR
Kojto 104:b9ad9a133dc7 177
Kojto 104:b9ad9a133dc7 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 179
Kojto 104:b9ad9a133dc7 180 \return Floating Point Status/Control register value
Kojto 104:b9ad9a133dc7 181 */
Kojto 104:b9ad9a133dc7 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 104:b9ad9a133dc7 183 {
Kojto 104:b9ad9a133dc7 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 186 return(__regfpscr);
Kojto 104:b9ad9a133dc7 187 #else
Kojto 104:b9ad9a133dc7 188 return(0);
Kojto 104:b9ad9a133dc7 189 #endif
Kojto 104:b9ad9a133dc7 190 }
Kojto 104:b9ad9a133dc7 191
Kojto 104:b9ad9a133dc7 192
Kojto 104:b9ad9a133dc7 193 /** \brief Set FPSCR
Kojto 104:b9ad9a133dc7 194
Kojto 104:b9ad9a133dc7 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 196
Kojto 104:b9ad9a133dc7 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 104:b9ad9a133dc7 198 */
Kojto 104:b9ad9a133dc7 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 104:b9ad9a133dc7 200 {
Kojto 104:b9ad9a133dc7 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 203 __regfpscr = (fpscr);
Kojto 104:b9ad9a133dc7 204 #endif
Kojto 104:b9ad9a133dc7 205 }
Kojto 104:b9ad9a133dc7 206
Kojto 104:b9ad9a133dc7 207 /** \brief Get FPEXC
Kojto 104:b9ad9a133dc7 208
Kojto 104:b9ad9a133dc7 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 210
Kojto 104:b9ad9a133dc7 211 \return Floating Point Exception Control register value
Kojto 104:b9ad9a133dc7 212 */
Kojto 104:b9ad9a133dc7 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 104:b9ad9a133dc7 214 {
Kojto 104:b9ad9a133dc7 215 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 217 return(__regfpexc);
Kojto 104:b9ad9a133dc7 218 #else
Kojto 104:b9ad9a133dc7 219 return(0);
Kojto 104:b9ad9a133dc7 220 #endif
Kojto 104:b9ad9a133dc7 221 }
Kojto 104:b9ad9a133dc7 222
Kojto 104:b9ad9a133dc7 223
Kojto 104:b9ad9a133dc7 224 /** \brief Set FPEXC
Kojto 104:b9ad9a133dc7 225
Kojto 104:b9ad9a133dc7 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 227
Kojto 104:b9ad9a133dc7 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 104:b9ad9a133dc7 229 */
Kojto 104:b9ad9a133dc7 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 104:b9ad9a133dc7 231 {
Kojto 104:b9ad9a133dc7 232 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 234 __regfpexc = (fpexc);
Kojto 104:b9ad9a133dc7 235 #endif
Kojto 104:b9ad9a133dc7 236 }
Kojto 104:b9ad9a133dc7 237
Kojto 104:b9ad9a133dc7 238 /** \brief Get CPACR
Kojto 104:b9ad9a133dc7 239
Kojto 104:b9ad9a133dc7 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 241
Kojto 104:b9ad9a133dc7 242 \return Coprocessor Access Control register value
Kojto 104:b9ad9a133dc7 243 */
Kojto 104:b9ad9a133dc7 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 104:b9ad9a133dc7 245 {
Kojto 104:b9ad9a133dc7 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 247 return __regCPACR;
Kojto 104:b9ad9a133dc7 248 }
Kojto 104:b9ad9a133dc7 249
Kojto 104:b9ad9a133dc7 250 /** \brief Set CPACR
Kojto 104:b9ad9a133dc7 251
Kojto 104:b9ad9a133dc7 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 104:b9ad9a133dc7 255 */
Kojto 104:b9ad9a133dc7 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 104:b9ad9a133dc7 257 {
Kojto 104:b9ad9a133dc7 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 259 __regCPACR = cpacr;
Kojto 104:b9ad9a133dc7 260 __ISB();
Kojto 104:b9ad9a133dc7 261 }
Kojto 104:b9ad9a133dc7 262
Kojto 104:b9ad9a133dc7 263 /** \brief Get CBAR
Kojto 104:b9ad9a133dc7 264
Kojto 104:b9ad9a133dc7 265 This function returns the value of the Configuration Base Address register.
Kojto 104:b9ad9a133dc7 266
Kojto 104:b9ad9a133dc7 267 \return Configuration Base Address register value
Kojto 104:b9ad9a133dc7 268 */
Kojto 104:b9ad9a133dc7 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 104:b9ad9a133dc7 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 104:b9ad9a133dc7 271 return(__regCBAR);
Kojto 104:b9ad9a133dc7 272 }
Kojto 104:b9ad9a133dc7 273
Kojto 104:b9ad9a133dc7 274 /** \brief Get TTBR0
Kojto 104:b9ad9a133dc7 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 104:b9ad9a133dc7 277
Kojto 104:b9ad9a133dc7 278 \return Translation Table Base Register 0 value
Kojto 104:b9ad9a133dc7 279 */
Kojto 104:b9ad9a133dc7 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 104:b9ad9a133dc7 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 282 return(__regTTBR0);
Kojto 104:b9ad9a133dc7 283 }
Kojto 104:b9ad9a133dc7 284
Kojto 104:b9ad9a133dc7 285 /** \brief Set TTBR0
Kojto 104:b9ad9a133dc7 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 104:b9ad9a133dc7 288
Kojto 104:b9ad9a133dc7 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 104:b9ad9a133dc7 290 */
Kojto 104:b9ad9a133dc7 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 104:b9ad9a133dc7 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 293 __regTTBR0 = ttbr0;
Kojto 104:b9ad9a133dc7 294 __ISB();
Kojto 104:b9ad9a133dc7 295 }
Kojto 104:b9ad9a133dc7 296
Kojto 104:b9ad9a133dc7 297 /** \brief Get DACR
Kojto 104:b9ad9a133dc7 298
Kojto 104:b9ad9a133dc7 299 This function returns the value of the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 300
Kojto 104:b9ad9a133dc7 301 \return Domain Access Control Register value
Kojto 104:b9ad9a133dc7 302 */
Kojto 104:b9ad9a133dc7 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 104:b9ad9a133dc7 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 305 return(__regDACR);
Kojto 104:b9ad9a133dc7 306 }
Kojto 104:b9ad9a133dc7 307
Kojto 104:b9ad9a133dc7 308 /** \brief Set DACR
Kojto 104:b9ad9a133dc7 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 311
Kojto 104:b9ad9a133dc7 312 \param [in] dacr Domain Access Control Register value to set
Kojto 104:b9ad9a133dc7 313 */
Kojto 104:b9ad9a133dc7 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 104:b9ad9a133dc7 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 316 __regDACR = dacr;
Kojto 104:b9ad9a133dc7 317 __ISB();
Kojto 104:b9ad9a133dc7 318 }
Kojto 104:b9ad9a133dc7 319
Kojto 104:b9ad9a133dc7 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 104:b9ad9a133dc7 321
Kojto 104:b9ad9a133dc7 322 /** \brief Set SCTLR
Kojto 104:b9ad9a133dc7 323
Kojto 104:b9ad9a133dc7 324 This function assigns the given value to the System Control Register.
Kojto 104:b9ad9a133dc7 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 104:b9ad9a133dc7 327 */
Kojto 104:b9ad9a133dc7 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 104:b9ad9a133dc7 329 {
Kojto 104:b9ad9a133dc7 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 331 __regSCTLR = sctlr;
Kojto 104:b9ad9a133dc7 332 }
Kojto 104:b9ad9a133dc7 333
Kojto 104:b9ad9a133dc7 334 /** \brief Get SCTLR
Kojto 104:b9ad9a133dc7 335
Kojto 104:b9ad9a133dc7 336 This function returns the value of the System Control Register.
Kojto 104:b9ad9a133dc7 337
Kojto 104:b9ad9a133dc7 338 \return System Control Register value
Kojto 104:b9ad9a133dc7 339 */
Kojto 104:b9ad9a133dc7 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 104:b9ad9a133dc7 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 342 return(__regSCTLR);
Kojto 104:b9ad9a133dc7 343 }
Kojto 104:b9ad9a133dc7 344
Kojto 104:b9ad9a133dc7 345 /** \brief Enable Caches
Kojto 104:b9ad9a133dc7 346
Kojto 104:b9ad9a133dc7 347 Enable Caches
Kojto 104:b9ad9a133dc7 348 */
Kojto 104:b9ad9a133dc7 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 104:b9ad9a133dc7 350 // Set I bit 12 to enable I Cache
Kojto 104:b9ad9a133dc7 351 // Set C bit 2 to enable D Cache
Kojto 104:b9ad9a133dc7 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 104:b9ad9a133dc7 353 }
Kojto 104:b9ad9a133dc7 354
Kojto 104:b9ad9a133dc7 355 /** \brief Disable Caches
Kojto 104:b9ad9a133dc7 356
Kojto 104:b9ad9a133dc7 357 Disable Caches
Kojto 104:b9ad9a133dc7 358 */
Kojto 104:b9ad9a133dc7 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 104:b9ad9a133dc7 360 // Clear I bit 12 to disable I Cache
Kojto 104:b9ad9a133dc7 361 // Clear C bit 2 to disable D Cache
Kojto 104:b9ad9a133dc7 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 104:b9ad9a133dc7 363 __ISB();
Kojto 104:b9ad9a133dc7 364 }
Kojto 104:b9ad9a133dc7 365
Kojto 104:b9ad9a133dc7 366 /** \brief Enable BTAC
Kojto 104:b9ad9a133dc7 367
Kojto 104:b9ad9a133dc7 368 Enable BTAC
Kojto 104:b9ad9a133dc7 369 */
Kojto 104:b9ad9a133dc7 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 104:b9ad9a133dc7 371 // Set Z bit 11 to enable branch prediction
Kojto 104:b9ad9a133dc7 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 104:b9ad9a133dc7 373 __ISB();
Kojto 104:b9ad9a133dc7 374 }
Kojto 104:b9ad9a133dc7 375
Kojto 104:b9ad9a133dc7 376 /** \brief Disable BTAC
Kojto 104:b9ad9a133dc7 377
Kojto 104:b9ad9a133dc7 378 Disable BTAC
Kojto 104:b9ad9a133dc7 379 */
Kojto 104:b9ad9a133dc7 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 104:b9ad9a133dc7 381 // Clear Z bit 11 to disable branch prediction
Kojto 104:b9ad9a133dc7 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 104:b9ad9a133dc7 383 }
Kojto 104:b9ad9a133dc7 384
Kojto 104:b9ad9a133dc7 385
Kojto 104:b9ad9a133dc7 386 /** \brief Enable MMU
Kojto 104:b9ad9a133dc7 387
Kojto 104:b9ad9a133dc7 388 Enable MMU
Kojto 104:b9ad9a133dc7 389 */
Kojto 104:b9ad9a133dc7 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 104:b9ad9a133dc7 391 // Set M bit 0 to enable the MMU
Kojto 104:b9ad9a133dc7 392 // Set AFE bit to enable simplified access permissions model
Kojto 104:b9ad9a133dc7 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 104:b9ad9a133dc7 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 104:b9ad9a133dc7 395 __ISB();
Kojto 104:b9ad9a133dc7 396 }
Kojto 104:b9ad9a133dc7 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 104:b9ad9a133dc7 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 104:b9ad9a133dc7 401 */
Kojto 104:b9ad9a133dc7 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 104:b9ad9a133dc7 403 // Clear M bit 0 to disable the MMU
Kojto 104:b9ad9a133dc7 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 104:b9ad9a133dc7 405 __ISB();
Kojto 104:b9ad9a133dc7 406 }
Kojto 104:b9ad9a133dc7 407
Kojto 104:b9ad9a133dc7 408 /******************************** TLB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 409 /** \brief Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 410
Kojto 104:b9ad9a133dc7 411 TLBIALL. Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 412 */
Kojto 104:b9ad9a133dc7 413
Kojto 104:b9ad9a133dc7 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 104:b9ad9a133dc7 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 104:b9ad9a133dc7 416 __TLBIALL = 0;
Kojto 104:b9ad9a133dc7 417 __DSB();
Kojto 104:b9ad9a133dc7 418 __ISB();
Kojto 104:b9ad9a133dc7 419 }
Kojto 104:b9ad9a133dc7 420
Kojto 104:b9ad9a133dc7 421 /******************************** BTB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 422 /** \brief Invalidate entire branch predictor array
Kojto 104:b9ad9a133dc7 423
Kojto 104:b9ad9a133dc7 424 BPIALL. Branch Predictor Invalidate All.
Kojto 104:b9ad9a133dc7 425 */
Kojto 104:b9ad9a133dc7 426
Kojto 104:b9ad9a133dc7 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 104:b9ad9a133dc7 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 104:b9ad9a133dc7 429 __BPIALL = 0;
Kojto 104:b9ad9a133dc7 430 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 104:b9ad9a133dc7 432 }
Kojto 104:b9ad9a133dc7 433
Kojto 104:b9ad9a133dc7 434
Kojto 104:b9ad9a133dc7 435 /******************************** L1 cache operations ******************************************************/
Kojto 104:b9ad9a133dc7 436
Kojto 104:b9ad9a133dc7 437 /** \brief Invalidate the whole I$
Kojto 104:b9ad9a133dc7 438
Kojto 104:b9ad9a133dc7 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 104:b9ad9a133dc7 440 */
Kojto 104:b9ad9a133dc7 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 104:b9ad9a133dc7 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 104:b9ad9a133dc7 443 __ICIALLU = 0;
Kojto 104:b9ad9a133dc7 444 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 104:b9ad9a133dc7 446 }
Kojto 104:b9ad9a133dc7 447
Kojto 104:b9ad9a133dc7 448 /** \brief Clean D$ by MVA
Kojto 104:b9ad9a133dc7 449
Kojto 104:b9ad9a133dc7 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 104:b9ad9a133dc7 451 */
Kojto 104:b9ad9a133dc7 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 104:b9ad9a133dc7 454 __DCCMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 456 }
Kojto 104:b9ad9a133dc7 457
Kojto 104:b9ad9a133dc7 458 /** \brief Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 459
Kojto 104:b9ad9a133dc7 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 461 */
Kojto 104:b9ad9a133dc7 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 104:b9ad9a133dc7 464 __DCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 466 }
Kojto 104:b9ad9a133dc7 467
Kojto 104:b9ad9a133dc7 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 469
Kojto 104:b9ad9a133dc7 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 471 */
Kojto 104:b9ad9a133dc7 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 104:b9ad9a133dc7 474 __DCCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 476 }
Kojto 104:b9ad9a133dc7 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 104:b9ad9a133dc7 481 */
Kojto 104:b9ad9a133dc7 482 #pragma push
Kojto 104:b9ad9a133dc7 483 #pragma arm
Kojto 104:b9ad9a133dc7 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 104:b9ad9a133dc7 485 ARM
Kojto 104:b9ad9a133dc7 486
Kojto 104:b9ad9a133dc7 487 PUSH {R4-R11}
Kojto 104:b9ad9a133dc7 488
Kojto 104:b9ad9a133dc7 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 104:b9ad9a133dc7 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 104:b9ad9a133dc7 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 104:b9ad9a133dc7 492 BEQ Finished // If 0, no need to clean
Kojto 104:b9ad9a133dc7 493
Kojto 104:b9ad9a133dc7 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 104:b9ad9a133dc7 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 104:b9ad9a133dc7 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 104:b9ad9a133dc7 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 104:b9ad9a133dc7 498 CMP R1, #2
Kojto 104:b9ad9a133dc7 499 BLT Skip // No cache or only instruction cache at this level
Kojto 104:b9ad9a133dc7 500
Kojto 104:b9ad9a133dc7 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 104:b9ad9a133dc7 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 104:b9ad9a133dc7 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 104:b9ad9a133dc7 504 AND R2, R1, #7 // Extract the line length field
Kojto 104:b9ad9a133dc7 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 104:b9ad9a133dc7 506 LDR R4, =0x3FF
Kojto 104:b9ad9a133dc7 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 104:b9ad9a133dc7 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 104:b9ad9a133dc7 509 LDR R7, =0x7FFF
Kojto 104:b9ad9a133dc7 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 104:b9ad9a133dc7 511
Kojto 104:b9ad9a133dc7 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 104:b9ad9a133dc7 513
Kojto 104:b9ad9a133dc7 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 104:b9ad9a133dc7 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 104:b9ad9a133dc7 516 CMP R0, #0
Kojto 104:b9ad9a133dc7 517 BNE Dccsw
Kojto 104:b9ad9a133dc7 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 519 B cont
Kojto 104:b9ad9a133dc7 520 Dccsw CMP R0, #1
Kojto 104:b9ad9a133dc7 521 BNE Dccisw
Kojto 104:b9ad9a133dc7 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 104:b9ad9a133dc7 526 BGE Loop3
Kojto 104:b9ad9a133dc7 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 104:b9ad9a133dc7 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 104:b9ad9a133dc7 530 CMP R3, R10
Kojto 104:b9ad9a133dc7 531 BGT Loop1
Kojto 104:b9ad9a133dc7 532
Kojto 104:b9ad9a133dc7 533 Finished
Kojto 104:b9ad9a133dc7 534 DSB
Kojto 104:b9ad9a133dc7 535 POP {R4-R11}
Kojto 104:b9ad9a133dc7 536 BX lr
Kojto 104:b9ad9a133dc7 537
Kojto 104:b9ad9a133dc7 538 }
Kojto 104:b9ad9a133dc7 539 #pragma pop
Kojto 104:b9ad9a133dc7 540
Kojto 104:b9ad9a133dc7 541
Kojto 104:b9ad9a133dc7 542 /** \brief Invalidate the whole D$
Kojto 104:b9ad9a133dc7 543
Kojto 104:b9ad9a133dc7 544 DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 545 */
Kojto 104:b9ad9a133dc7 546
Kojto 104:b9ad9a133dc7 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 548 __v7_all_cache(0);
Kojto 104:b9ad9a133dc7 549 }
Kojto 104:b9ad9a133dc7 550
Kojto 104:b9ad9a133dc7 551 /** \brief Clean the whole D$
Kojto 104:b9ad9a133dc7 552
Kojto 104:b9ad9a133dc7 553 DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 554 */
Kojto 104:b9ad9a133dc7 555
Kojto 104:b9ad9a133dc7 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 104:b9ad9a133dc7 557 __v7_all_cache(1);
Kojto 104:b9ad9a133dc7 558 }
Kojto 104:b9ad9a133dc7 559
Kojto 104:b9ad9a133dc7 560 /** \brief Clean and invalidate the whole D$
Kojto 104:b9ad9a133dc7 561
Kojto 104:b9ad9a133dc7 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 563 */
Kojto 104:b9ad9a133dc7 564
Kojto 104:b9ad9a133dc7 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 566 __v7_all_cache(2);
Kojto 104:b9ad9a133dc7 567 }
Kojto 104:b9ad9a133dc7 568
Kojto 104:b9ad9a133dc7 569 #include "core_ca_mmu.h"
Kojto 104:b9ad9a133dc7 570
Kojto 104:b9ad9a133dc7 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 104:b9ad9a133dc7 572
Kojto 104:b9ad9a133dc7 573 #error IAR Compiler support not implemented for Cortex-A
Kojto 104:b9ad9a133dc7 574
Kojto 104:b9ad9a133dc7 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 104:b9ad9a133dc7 576 /* GNU gcc specific functions */
Kojto 104:b9ad9a133dc7 577
Kojto 104:b9ad9a133dc7 578 #define MODE_USR 0x10
Kojto 104:b9ad9a133dc7 579 #define MODE_FIQ 0x11
Kojto 104:b9ad9a133dc7 580 #define MODE_IRQ 0x12
Kojto 104:b9ad9a133dc7 581 #define MODE_SVC 0x13
Kojto 104:b9ad9a133dc7 582 #define MODE_MON 0x16
Kojto 104:b9ad9a133dc7 583 #define MODE_ABT 0x17
Kojto 104:b9ad9a133dc7 584 #define MODE_HYP 0x1A
Kojto 104:b9ad9a133dc7 585 #define MODE_UND 0x1B
Kojto 104:b9ad9a133dc7 586 #define MODE_SYS 0x1F
Kojto 104:b9ad9a133dc7 587
Kojto 104:b9ad9a133dc7 588
Kojto 104:b9ad9a133dc7 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 104:b9ad9a133dc7 590 {
Kojto 104:b9ad9a133dc7 591 __ASM volatile ("cpsie i");
Kojto 104:b9ad9a133dc7 592 }
Kojto 104:b9ad9a133dc7 593
Kojto 104:b9ad9a133dc7 594 /** \brief Disable IRQ Interrupts
Kojto 104:b9ad9a133dc7 595
Kojto 104:b9ad9a133dc7 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 104:b9ad9a133dc7 597 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 598 */
Kojto 104:b9ad9a133dc7 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 104:b9ad9a133dc7 600 {
Kojto 104:b9ad9a133dc7 601 uint32_t result;
Kojto 104:b9ad9a133dc7 602
Kojto 104:b9ad9a133dc7 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 104:b9ad9a133dc7 604 __ASM volatile ("cpsid i");
Kojto 104:b9ad9a133dc7 605 return(result & 0x80);
Kojto 104:b9ad9a133dc7 606 }
Kojto 104:b9ad9a133dc7 607
Kojto 104:b9ad9a133dc7 608
Kojto 104:b9ad9a133dc7 609 /** \brief Get APSR Register
Kojto 104:b9ad9a133dc7 610
Kojto 104:b9ad9a133dc7 611 This function returns the content of the APSR Register.
Kojto 104:b9ad9a133dc7 612
Kojto 104:b9ad9a133dc7 613 \return APSR Register value
Kojto 104:b9ad9a133dc7 614 */
Kojto 104:b9ad9a133dc7 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 104:b9ad9a133dc7 616 {
Kojto 104:b9ad9a133dc7 617 #if 1
Kojto 108:34e6b704fe68 618 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 104:b9ad9a133dc7 620 #else
Kojto 104:b9ad9a133dc7 621 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 622 #endif
Kojto 104:b9ad9a133dc7 623 return(__regAPSR);
Kojto 104:b9ad9a133dc7 624 }
Kojto 104:b9ad9a133dc7 625
Kojto 104:b9ad9a133dc7 626
Kojto 104:b9ad9a133dc7 627 /** \brief Get CPSR Register
Kojto 104:b9ad9a133dc7 628
Kojto 104:b9ad9a133dc7 629 This function returns the content of the CPSR Register.
Kojto 104:b9ad9a133dc7 630
Kojto 104:b9ad9a133dc7 631 \return CPSR Register value
Kojto 104:b9ad9a133dc7 632 */
Kojto 104:b9ad9a133dc7 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 104:b9ad9a133dc7 634 {
Kojto 104:b9ad9a133dc7 635 #if 1
Kojto 104:b9ad9a133dc7 636 register uint32_t __regCPSR;
Kojto 104:b9ad9a133dc7 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 104:b9ad9a133dc7 638 #else
Kojto 104:b9ad9a133dc7 639 register uint32_t __regCPSR __ASM("cpsr");
Kojto 104:b9ad9a133dc7 640 #endif
Kojto 104:b9ad9a133dc7 641 return(__regCPSR);
Kojto 104:b9ad9a133dc7 642 }
Kojto 104:b9ad9a133dc7 643
Kojto 104:b9ad9a133dc7 644 #if 0
Kojto 104:b9ad9a133dc7 645 /** \brief Set Stack Pointer
Kojto 104:b9ad9a133dc7 646
Kojto 104:b9ad9a133dc7 647 This function assigns the given value to the current stack pointer.
Kojto 104:b9ad9a133dc7 648
Kojto 104:b9ad9a133dc7 649 \param [in] topOfStack Stack Pointer value to set
Kojto 104:b9ad9a133dc7 650 */
Kojto 104:b9ad9a133dc7 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 104:b9ad9a133dc7 652 {
Kojto 104:b9ad9a133dc7 653 register uint32_t __regSP __ASM("sp");
Kojto 104:b9ad9a133dc7 654 __regSP = topOfStack;
Kojto 104:b9ad9a133dc7 655 }
Kojto 104:b9ad9a133dc7 656 #endif
Kojto 104:b9ad9a133dc7 657
Kojto 104:b9ad9a133dc7 658 /** \brief Get link register
Kojto 104:b9ad9a133dc7 659
Kojto 104:b9ad9a133dc7 660 This function returns the value of the link register
Kojto 104:b9ad9a133dc7 661
Kojto 104:b9ad9a133dc7 662 \return Value of link register
Kojto 104:b9ad9a133dc7 663 */
Kojto 104:b9ad9a133dc7 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 104:b9ad9a133dc7 665 {
Kojto 104:b9ad9a133dc7 666 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 667 return(__reglr);
Kojto 104:b9ad9a133dc7 668 }
Kojto 104:b9ad9a133dc7 669
Kojto 104:b9ad9a133dc7 670 #if 0
Kojto 104:b9ad9a133dc7 671 /** \brief Set link register
Kojto 104:b9ad9a133dc7 672
Kojto 104:b9ad9a133dc7 673 This function sets the value of the link register
Kojto 104:b9ad9a133dc7 674
Kojto 104:b9ad9a133dc7 675 \param [in] lr LR value to set
Kojto 104:b9ad9a133dc7 676 */
Kojto 104:b9ad9a133dc7 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 104:b9ad9a133dc7 678 {
Kojto 104:b9ad9a133dc7 679 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 680 __reglr = lr;
Kojto 104:b9ad9a133dc7 681 }
Kojto 104:b9ad9a133dc7 682 #endif
Kojto 104:b9ad9a133dc7 683
Kojto 104:b9ad9a133dc7 684 /** \brief Set Process Stack Pointer
Kojto 104:b9ad9a133dc7 685
Kojto 104:b9ad9a133dc7 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 104:b9ad9a133dc7 687
Kojto 104:b9ad9a133dc7 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 104:b9ad9a133dc7 689 */
Kojto 108:34e6b704fe68 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 691 {
Kojto 108:34e6b704fe68 692 __asm__ volatile (
Kojto 108:34e6b704fe68 693 ".ARM;"
Kojto 108:34e6b704fe68 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 695
Kojto 108:34e6b704fe68 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 697 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 698 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 699 "MOV SP, R0;"
Kojto 108:34e6b704fe68 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 701 "ISB;"
Kojto 108:34e6b704fe68 702 //"BX LR;"
Kojto 108:34e6b704fe68 703 :
Kojto 108:34e6b704fe68 704 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 705 : "r0", "r1");
Kojto 108:34e6b704fe68 706 return;
Kojto 108:34e6b704fe68 707 }
Kojto 104:b9ad9a133dc7 708
Kojto 104:b9ad9a133dc7 709 /** \brief Set User Mode
Kojto 104:b9ad9a133dc7 710
Kojto 104:b9ad9a133dc7 711 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 712 */
Kojto 108:34e6b704fe68 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 714 {
Kojto 108:34e6b704fe68 715 __asm__ volatile (
Kojto 108:34e6b704fe68 716 ".ARM;"
Kojto 104:b9ad9a133dc7 717
Kojto 108:34e6b704fe68 718 "CPS %0;"
Kojto 108:34e6b704fe68 719 //"BX LR;"
Kojto 108:34e6b704fe68 720 :
Kojto 108:34e6b704fe68 721 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 722 : );
Kojto 108:34e6b704fe68 723 return;
Kojto 108:34e6b704fe68 724 }
Kojto 108:34e6b704fe68 725
Kojto 104:b9ad9a133dc7 726
Kojto 104:b9ad9a133dc7 727 /** \brief Enable FIQ
Kojto 104:b9ad9a133dc7 728
Kojto 104:b9ad9a133dc7 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 730 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 731 */
Kojto 108:34e6b704fe68 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 104:b9ad9a133dc7 733
Kojto 104:b9ad9a133dc7 734
Kojto 104:b9ad9a133dc7 735 /** \brief Disable FIQ
Kojto 104:b9ad9a133dc7 736
Kojto 104:b9ad9a133dc7 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 738 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 739 */
Kojto 108:34e6b704fe68 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 104:b9ad9a133dc7 741
Kojto 104:b9ad9a133dc7 742
Kojto 104:b9ad9a133dc7 743 /** \brief Get FPSCR
Kojto 104:b9ad9a133dc7 744
Kojto 104:b9ad9a133dc7 745 This function returns the current value of the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 746
Kojto 104:b9ad9a133dc7 747 \return Floating Point Status/Control register value
Kojto 104:b9ad9a133dc7 748 */
Kojto 104:b9ad9a133dc7 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 104:b9ad9a133dc7 750 {
Kojto 104:b9ad9a133dc7 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 752 #if 1
Kojto 104:b9ad9a133dc7 753 uint32_t result;
Kojto 104:b9ad9a133dc7 754
Kojto 104:b9ad9a133dc7 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 104:b9ad9a133dc7 756 return (result);
Kojto 104:b9ad9a133dc7 757 #else
Kojto 104:b9ad9a133dc7 758 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 759 return(__regfpscr);
Kojto 104:b9ad9a133dc7 760 #endif
Kojto 104:b9ad9a133dc7 761 #else
Kojto 104:b9ad9a133dc7 762 return(0);
Kojto 104:b9ad9a133dc7 763 #endif
Kojto 104:b9ad9a133dc7 764 }
Kojto 104:b9ad9a133dc7 765
Kojto 104:b9ad9a133dc7 766
Kojto 104:b9ad9a133dc7 767 /** \brief Set FPSCR
Kojto 104:b9ad9a133dc7 768
Kojto 104:b9ad9a133dc7 769 This function assigns the given value to the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 770
Kojto 104:b9ad9a133dc7 771 \param [in] fpscr Floating Point Status/Control value to set
Kojto 104:b9ad9a133dc7 772 */
Kojto 104:b9ad9a133dc7 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 104:b9ad9a133dc7 774 {
Kojto 104:b9ad9a133dc7 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 776 #if 1
Kojto 104:b9ad9a133dc7 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 104:b9ad9a133dc7 778 #else
Kojto 104:b9ad9a133dc7 779 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 780 __regfpscr = (fpscr);
Kojto 104:b9ad9a133dc7 781 #endif
Kojto 104:b9ad9a133dc7 782 #endif
Kojto 104:b9ad9a133dc7 783 }
Kojto 104:b9ad9a133dc7 784
Kojto 104:b9ad9a133dc7 785 /** \brief Get FPEXC
Kojto 104:b9ad9a133dc7 786
Kojto 104:b9ad9a133dc7 787 This function returns the current value of the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 788
Kojto 104:b9ad9a133dc7 789 \return Floating Point Exception Control register value
Kojto 104:b9ad9a133dc7 790 */
Kojto 104:b9ad9a133dc7 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 104:b9ad9a133dc7 792 {
Kojto 104:b9ad9a133dc7 793 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 794 #if 1
Kojto 104:b9ad9a133dc7 795 uint32_t result;
Kojto 104:b9ad9a133dc7 796
Kojto 104:b9ad9a133dc7 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 104:b9ad9a133dc7 798 return (result);
Kojto 104:b9ad9a133dc7 799 #else
Kojto 104:b9ad9a133dc7 800 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 801 return(__regfpexc);
Kojto 104:b9ad9a133dc7 802 #endif
Kojto 104:b9ad9a133dc7 803 #else
Kojto 104:b9ad9a133dc7 804 return(0);
Kojto 104:b9ad9a133dc7 805 #endif
Kojto 104:b9ad9a133dc7 806 }
Kojto 104:b9ad9a133dc7 807
Kojto 104:b9ad9a133dc7 808
Kojto 104:b9ad9a133dc7 809 /** \brief Set FPEXC
Kojto 104:b9ad9a133dc7 810
Kojto 104:b9ad9a133dc7 811 This function assigns the given value to the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 812
Kojto 104:b9ad9a133dc7 813 \param [in] fpscr Floating Point Exception Control value to set
Kojto 104:b9ad9a133dc7 814 */
Kojto 104:b9ad9a133dc7 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 104:b9ad9a133dc7 816 {
Kojto 104:b9ad9a133dc7 817 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 818 #if 1
Kojto 104:b9ad9a133dc7 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 104:b9ad9a133dc7 820 #else
Kojto 104:b9ad9a133dc7 821 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 822 __regfpexc = (fpexc);
Kojto 104:b9ad9a133dc7 823 #endif
Kojto 104:b9ad9a133dc7 824 #endif
Kojto 104:b9ad9a133dc7 825 }
Kojto 104:b9ad9a133dc7 826
Kojto 104:b9ad9a133dc7 827 /** \brief Get CPACR
Kojto 104:b9ad9a133dc7 828
Kojto 104:b9ad9a133dc7 829 This function returns the current value of the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 830
Kojto 104:b9ad9a133dc7 831 \return Coprocessor Access Control register value
Kojto 104:b9ad9a133dc7 832 */
Kojto 104:b9ad9a133dc7 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 104:b9ad9a133dc7 834 {
Kojto 104:b9ad9a133dc7 835 #if 1
Kojto 104:b9ad9a133dc7 836 register uint32_t __regCPACR;
Kojto 104:b9ad9a133dc7 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 104:b9ad9a133dc7 838 #else
Kojto 104:b9ad9a133dc7 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 840 #endif
Kojto 104:b9ad9a133dc7 841 return __regCPACR;
Kojto 104:b9ad9a133dc7 842 }
Kojto 104:b9ad9a133dc7 843
Kojto 104:b9ad9a133dc7 844 /** \brief Set CPACR
Kojto 104:b9ad9a133dc7 845
Kojto 104:b9ad9a133dc7 846 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 847
Kojto 108:34e6b704fe68 848 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 104:b9ad9a133dc7 849 */
Kojto 104:b9ad9a133dc7 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 104:b9ad9a133dc7 851 {
Kojto 104:b9ad9a133dc7 852 #if 1
Kojto 104:b9ad9a133dc7 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 104:b9ad9a133dc7 854 #else
Kojto 104:b9ad9a133dc7 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 856 __regCPACR = cpacr;
Kojto 104:b9ad9a133dc7 857 #endif
Kojto 104:b9ad9a133dc7 858 __ISB();
Kojto 104:b9ad9a133dc7 859 }
Kojto 104:b9ad9a133dc7 860
Kojto 104:b9ad9a133dc7 861 /** \brief Get CBAR
Kojto 104:b9ad9a133dc7 862
Kojto 104:b9ad9a133dc7 863 This function returns the value of the Configuration Base Address register.
Kojto 104:b9ad9a133dc7 864
Kojto 104:b9ad9a133dc7 865 \return Configuration Base Address register value
Kojto 104:b9ad9a133dc7 866 */
Kojto 104:b9ad9a133dc7 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 104:b9ad9a133dc7 868 #if 1
Kojto 104:b9ad9a133dc7 869 register uint32_t __regCBAR;
Kojto 104:b9ad9a133dc7 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 104:b9ad9a133dc7 871 #else
Kojto 104:b9ad9a133dc7 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 104:b9ad9a133dc7 873 #endif
Kojto 104:b9ad9a133dc7 874 return(__regCBAR);
Kojto 104:b9ad9a133dc7 875 }
Kojto 104:b9ad9a133dc7 876
Kojto 104:b9ad9a133dc7 877 /** \brief Get TTBR0
Kojto 104:b9ad9a133dc7 878
Kojto 108:34e6b704fe68 879 This function returns the value of the Translation Table Base Register 0.
Kojto 104:b9ad9a133dc7 880
Kojto 104:b9ad9a133dc7 881 \return Translation Table Base Register 0 value
Kojto 104:b9ad9a133dc7 882 */
Kojto 104:b9ad9a133dc7 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 104:b9ad9a133dc7 884 #if 1
Kojto 104:b9ad9a133dc7 885 register uint32_t __regTTBR0;
Kojto 104:b9ad9a133dc7 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 104:b9ad9a133dc7 887 #else
Kojto 104:b9ad9a133dc7 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 889 #endif
Kojto 104:b9ad9a133dc7 890 return(__regTTBR0);
Kojto 104:b9ad9a133dc7 891 }
Kojto 104:b9ad9a133dc7 892
Kojto 104:b9ad9a133dc7 893 /** \brief Set TTBR0
Kojto 104:b9ad9a133dc7 894
Kojto 108:34e6b704fe68 895 This function assigns the given value to the Translation Table Base Register 0.
Kojto 104:b9ad9a133dc7 896
Kojto 104:b9ad9a133dc7 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 104:b9ad9a133dc7 898 */
Kojto 104:b9ad9a133dc7 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 104:b9ad9a133dc7 900 #if 1
Kojto 104:b9ad9a133dc7 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 104:b9ad9a133dc7 902 #else
Kojto 104:b9ad9a133dc7 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 904 __regTTBR0 = ttbr0;
Kojto 104:b9ad9a133dc7 905 #endif
Kojto 104:b9ad9a133dc7 906 __ISB();
Kojto 104:b9ad9a133dc7 907 }
Kojto 104:b9ad9a133dc7 908
Kojto 104:b9ad9a133dc7 909 /** \brief Get DACR
Kojto 104:b9ad9a133dc7 910
Kojto 104:b9ad9a133dc7 911 This function returns the value of the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 912
Kojto 104:b9ad9a133dc7 913 \return Domain Access Control Register value
Kojto 104:b9ad9a133dc7 914 */
Kojto 104:b9ad9a133dc7 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 104:b9ad9a133dc7 916 #if 1
Kojto 104:b9ad9a133dc7 917 register uint32_t __regDACR;
Kojto 104:b9ad9a133dc7 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 104:b9ad9a133dc7 919 #else
Kojto 104:b9ad9a133dc7 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 921 #endif
Kojto 104:b9ad9a133dc7 922 return(__regDACR);
Kojto 104:b9ad9a133dc7 923 }
Kojto 104:b9ad9a133dc7 924
Kojto 104:b9ad9a133dc7 925 /** \brief Set DACR
Kojto 104:b9ad9a133dc7 926
Kojto 108:34e6b704fe68 927 This function assigns the given value to the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 928
Kojto 104:b9ad9a133dc7 929 \param [in] dacr Domain Access Control Register value to set
Kojto 104:b9ad9a133dc7 930 */
Kojto 104:b9ad9a133dc7 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 104:b9ad9a133dc7 932 #if 1
Kojto 104:b9ad9a133dc7 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 104:b9ad9a133dc7 934 #else
Kojto 104:b9ad9a133dc7 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 936 __regDACR = dacr;
Kojto 104:b9ad9a133dc7 937 #endif
Kojto 104:b9ad9a133dc7 938 __ISB();
Kojto 104:b9ad9a133dc7 939 }
Kojto 104:b9ad9a133dc7 940
Kojto 104:b9ad9a133dc7 941 /******************************** Cache and BTAC enable ****************************************************/
Kojto 104:b9ad9a133dc7 942
Kojto 104:b9ad9a133dc7 943 /** \brief Set SCTLR
Kojto 104:b9ad9a133dc7 944
Kojto 104:b9ad9a133dc7 945 This function assigns the given value to the System Control Register.
Kojto 104:b9ad9a133dc7 946
Kojto 108:34e6b704fe68 947 \param [in] sctlr System Control Register value to set
Kojto 104:b9ad9a133dc7 948 */
Kojto 104:b9ad9a133dc7 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 104:b9ad9a133dc7 950 {
Kojto 104:b9ad9a133dc7 951 #if 1
Kojto 104:b9ad9a133dc7 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 104:b9ad9a133dc7 953 #else
Kojto 104:b9ad9a133dc7 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 955 __regSCTLR = sctlr;
Kojto 104:b9ad9a133dc7 956 #endif
Kojto 104:b9ad9a133dc7 957 }
Kojto 104:b9ad9a133dc7 958
Kojto 104:b9ad9a133dc7 959 /** \brief Get SCTLR
Kojto 104:b9ad9a133dc7 960
Kojto 104:b9ad9a133dc7 961 This function returns the value of the System Control Register.
Kojto 104:b9ad9a133dc7 962
Kojto 104:b9ad9a133dc7 963 \return System Control Register value
Kojto 104:b9ad9a133dc7 964 */
Kojto 104:b9ad9a133dc7 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 104:b9ad9a133dc7 966 #if 1
Kojto 104:b9ad9a133dc7 967 register uint32_t __regSCTLR;
Kojto 104:b9ad9a133dc7 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 104:b9ad9a133dc7 969 #else
Kojto 104:b9ad9a133dc7 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 971 #endif
Kojto 104:b9ad9a133dc7 972 return(__regSCTLR);
Kojto 104:b9ad9a133dc7 973 }
Kojto 104:b9ad9a133dc7 974
Kojto 104:b9ad9a133dc7 975 /** \brief Enable Caches
Kojto 104:b9ad9a133dc7 976
Kojto 104:b9ad9a133dc7 977 Enable Caches
Kojto 104:b9ad9a133dc7 978 */
Kojto 104:b9ad9a133dc7 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 104:b9ad9a133dc7 980 // Set I bit 12 to enable I Cache
Kojto 104:b9ad9a133dc7 981 // Set C bit 2 to enable D Cache
Kojto 104:b9ad9a133dc7 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 104:b9ad9a133dc7 983 }
Kojto 104:b9ad9a133dc7 984
Kojto 104:b9ad9a133dc7 985 /** \brief Disable Caches
Kojto 104:b9ad9a133dc7 986
Kojto 104:b9ad9a133dc7 987 Disable Caches
Kojto 104:b9ad9a133dc7 988 */
Kojto 104:b9ad9a133dc7 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 104:b9ad9a133dc7 990 // Clear I bit 12 to disable I Cache
Kojto 104:b9ad9a133dc7 991 // Clear C bit 2 to disable D Cache
Kojto 104:b9ad9a133dc7 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 104:b9ad9a133dc7 993 __ISB();
Kojto 104:b9ad9a133dc7 994 }
Kojto 104:b9ad9a133dc7 995
Kojto 104:b9ad9a133dc7 996 /** \brief Enable BTAC
Kojto 104:b9ad9a133dc7 997
Kojto 104:b9ad9a133dc7 998 Enable BTAC
Kojto 104:b9ad9a133dc7 999 */
Kojto 104:b9ad9a133dc7 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 104:b9ad9a133dc7 1001 // Set Z bit 11 to enable branch prediction
Kojto 104:b9ad9a133dc7 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 104:b9ad9a133dc7 1003 __ISB();
Kojto 104:b9ad9a133dc7 1004 }
Kojto 104:b9ad9a133dc7 1005
Kojto 104:b9ad9a133dc7 1006 /** \brief Disable BTAC
Kojto 104:b9ad9a133dc7 1007
Kojto 104:b9ad9a133dc7 1008 Disable BTAC
Kojto 104:b9ad9a133dc7 1009 */
Kojto 104:b9ad9a133dc7 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 104:b9ad9a133dc7 1011 // Clear Z bit 11 to disable branch prediction
Kojto 104:b9ad9a133dc7 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 104:b9ad9a133dc7 1013 }
Kojto 104:b9ad9a133dc7 1014
Kojto 104:b9ad9a133dc7 1015
Kojto 104:b9ad9a133dc7 1016 /** \brief Enable MMU
Kojto 104:b9ad9a133dc7 1017
Kojto 104:b9ad9a133dc7 1018 Enable MMU
Kojto 104:b9ad9a133dc7 1019 */
Kojto 104:b9ad9a133dc7 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 104:b9ad9a133dc7 1021 // Set M bit 0 to enable the MMU
Kojto 104:b9ad9a133dc7 1022 // Set AFE bit to enable simplified access permissions model
Kojto 104:b9ad9a133dc7 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 104:b9ad9a133dc7 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 104:b9ad9a133dc7 1025 __ISB();
Kojto 104:b9ad9a133dc7 1026 }
Kojto 104:b9ad9a133dc7 1027
Kojto 108:34e6b704fe68 1028 /** \brief Disable MMU
Kojto 104:b9ad9a133dc7 1029
Kojto 108:34e6b704fe68 1030 Disable MMU
Kojto 104:b9ad9a133dc7 1031 */
Kojto 104:b9ad9a133dc7 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 104:b9ad9a133dc7 1033 // Clear M bit 0 to disable the MMU
Kojto 104:b9ad9a133dc7 1034 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 104:b9ad9a133dc7 1035 __ISB();
Kojto 104:b9ad9a133dc7 1036 }
Kojto 104:b9ad9a133dc7 1037
Kojto 104:b9ad9a133dc7 1038 /******************************** TLB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 1039 /** \brief Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 1040
Kojto 104:b9ad9a133dc7 1041 TLBIALL. Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 1042 */
Kojto 104:b9ad9a133dc7 1043
Kojto 104:b9ad9a133dc7 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 104:b9ad9a133dc7 1045 #if 1
Kojto 104:b9ad9a133dc7 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 104:b9ad9a133dc7 1047 #else
Kojto 104:b9ad9a133dc7 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 104:b9ad9a133dc7 1049 __TLBIALL = 0;
Kojto 104:b9ad9a133dc7 1050 #endif
Kojto 104:b9ad9a133dc7 1051 __DSB();
Kojto 104:b9ad9a133dc7 1052 __ISB();
Kojto 104:b9ad9a133dc7 1053 }
Kojto 104:b9ad9a133dc7 1054
Kojto 104:b9ad9a133dc7 1055 /******************************** BTB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 1056 /** \brief Invalidate entire branch predictor array
Kojto 104:b9ad9a133dc7 1057
Kojto 104:b9ad9a133dc7 1058 BPIALL. Branch Predictor Invalidate All.
Kojto 104:b9ad9a133dc7 1059 */
Kojto 104:b9ad9a133dc7 1060
Kojto 104:b9ad9a133dc7 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 104:b9ad9a133dc7 1062 #if 1
Kojto 104:b9ad9a133dc7 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 104:b9ad9a133dc7 1064 #else
Kojto 104:b9ad9a133dc7 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 104:b9ad9a133dc7 1066 __BPIALL = 0;
Kojto 104:b9ad9a133dc7 1067 #endif
Kojto 104:b9ad9a133dc7 1068 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 1069 __ISB(); //ensure instruction fetch path sees new state
Kojto 104:b9ad9a133dc7 1070 }
Kojto 104:b9ad9a133dc7 1071
Kojto 104:b9ad9a133dc7 1072
Kojto 104:b9ad9a133dc7 1073 /******************************** L1 cache operations ******************************************************/
Kojto 104:b9ad9a133dc7 1074
Kojto 104:b9ad9a133dc7 1075 /** \brief Invalidate the whole I$
Kojto 104:b9ad9a133dc7 1076
Kojto 104:b9ad9a133dc7 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 104:b9ad9a133dc7 1078 */
Kojto 104:b9ad9a133dc7 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 104:b9ad9a133dc7 1080 #if 1
Kojto 104:b9ad9a133dc7 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 104:b9ad9a133dc7 1082 #else
Kojto 104:b9ad9a133dc7 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 104:b9ad9a133dc7 1084 __ICIALLU = 0;
Kojto 104:b9ad9a133dc7 1085 #endif
Kojto 104:b9ad9a133dc7 1086 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 104:b9ad9a133dc7 1088 }
Kojto 104:b9ad9a133dc7 1089
Kojto 104:b9ad9a133dc7 1090 /** \brief Clean D$ by MVA
Kojto 104:b9ad9a133dc7 1091
Kojto 104:b9ad9a133dc7 1092 DCCMVAC. Data cache clean by MVA to PoC
Kojto 104:b9ad9a133dc7 1093 */
Kojto 104:b9ad9a133dc7 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1095 #if 1
Kojto 104:b9ad9a133dc7 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1097 #else
Kojto 104:b9ad9a133dc7 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 104:b9ad9a133dc7 1099 __DCCMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1100 #endif
Kojto 104:b9ad9a133dc7 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1102 }
Kojto 104:b9ad9a133dc7 1103
Kojto 104:b9ad9a133dc7 1104 /** \brief Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 1105
Kojto 104:b9ad9a133dc7 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 1107 */
Kojto 104:b9ad9a133dc7 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1109 #if 1
Kojto 104:b9ad9a133dc7 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1111 #else
Kojto 104:b9ad9a133dc7 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 104:b9ad9a133dc7 1113 __DCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1114 #endif
Kojto 104:b9ad9a133dc7 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1116 }
Kojto 104:b9ad9a133dc7 1117
Kojto 104:b9ad9a133dc7 1118 /** \brief Clean and Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 1119
Kojto 104:b9ad9a133dc7 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 1121 */
Kojto 104:b9ad9a133dc7 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1123 #if 1
Kojto 104:b9ad9a133dc7 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1125 #else
Kojto 104:b9ad9a133dc7 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 104:b9ad9a133dc7 1127 __DCCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1128 #endif
Kojto 104:b9ad9a133dc7 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1130 }
Kojto 104:b9ad9a133dc7 1131
Kojto 108:34e6b704fe68 1132 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 104:b9ad9a133dc7 1133
Kojto 108:34e6b704fe68 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 104:b9ad9a133dc7 1135 */
Kojto 104:b9ad9a133dc7 1136 extern void __v7_all_cache(uint32_t op);
Kojto 104:b9ad9a133dc7 1137
Kojto 104:b9ad9a133dc7 1138
Kojto 104:b9ad9a133dc7 1139 /** \brief Invalidate the whole D$
Kojto 104:b9ad9a133dc7 1140
Kojto 104:b9ad9a133dc7 1141 DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 1142 */
Kojto 104:b9ad9a133dc7 1143
Kojto 104:b9ad9a133dc7 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1145 __v7_all_cache(0);
Kojto 104:b9ad9a133dc7 1146 }
Kojto 104:b9ad9a133dc7 1147
Kojto 104:b9ad9a133dc7 1148 /** \brief Clean the whole D$
Kojto 104:b9ad9a133dc7 1149
Kojto 104:b9ad9a133dc7 1150 DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 1151 */
Kojto 104:b9ad9a133dc7 1152
Kojto 104:b9ad9a133dc7 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1154 __v7_all_cache(1);
Kojto 104:b9ad9a133dc7 1155 }
Kojto 104:b9ad9a133dc7 1156
Kojto 104:b9ad9a133dc7 1157 /** \brief Clean and invalidate the whole D$
Kojto 104:b9ad9a133dc7 1158
Kojto 104:b9ad9a133dc7 1159 DCCISW. Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 1160 */
Kojto 104:b9ad9a133dc7 1161
Kojto 104:b9ad9a133dc7 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1163 __v7_all_cache(2);
Kojto 104:b9ad9a133dc7 1164 }
Kojto 104:b9ad9a133dc7 1165
Kojto 104:b9ad9a133dc7 1166 #include "core_ca_mmu.h"
Kojto 104:b9ad9a133dc7 1167
Kojto 104:b9ad9a133dc7 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 104:b9ad9a133dc7 1169
Kojto 104:b9ad9a133dc7 1170 #error TASKING Compiler support not implemented for Cortex-A
Kojto 104:b9ad9a133dc7 1171
Kojto 104:b9ad9a133dc7 1172 #endif
Kojto 104:b9ad9a133dc7 1173
Kojto 104:b9ad9a133dc7 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 104:b9ad9a133dc7 1175
Kojto 104:b9ad9a133dc7 1176
Kojto 104:b9ad9a133dc7 1177 #endif /* __CORE_CAFUNC_H__ */