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TARGET_NRF51_MICROBIT/core_caFunc.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Child:
108:34e6b704fe68
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 104:b9ad9a133dc7 1 /**************************************************************************//**
Kojto 104:b9ad9a133dc7 2 * @file core_caFunc.h
Kojto 104:b9ad9a133dc7 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 104:b9ad9a133dc7 4 * @version V3.10
Kojto 104:b9ad9a133dc7 5 * @date 9 May 2013
Kojto 104:b9ad9a133dc7 6 *
Kojto 104:b9ad9a133dc7 7 * @note
Kojto 104:b9ad9a133dc7 8 *
Kojto 104:b9ad9a133dc7 9 ******************************************************************************/
Kojto 104:b9ad9a133dc7 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
Kojto 104:b9ad9a133dc7 11
Kojto 104:b9ad9a133dc7 12 All rights reserved.
Kojto 104:b9ad9a133dc7 13 Redistribution and use in source and binary forms, with or without
Kojto 104:b9ad9a133dc7 14 modification, are permitted provided that the following conditions are met:
Kojto 104:b9ad9a133dc7 15 - Redistributions of source code must retain the above copyright
Kojto 104:b9ad9a133dc7 16 notice, this list of conditions and the following disclaimer.
Kojto 104:b9ad9a133dc7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 104:b9ad9a133dc7 18 notice, this list of conditions and the following disclaimer in the
Kojto 104:b9ad9a133dc7 19 documentation and/or other materials provided with the distribution.
Kojto 104:b9ad9a133dc7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 104:b9ad9a133dc7 21 to endorse or promote products derived from this software without
Kojto 104:b9ad9a133dc7 22 specific prior written permission.
Kojto 104:b9ad9a133dc7 23 *
Kojto 104:b9ad9a133dc7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 104:b9ad9a133dc7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 104:b9ad9a133dc7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 104:b9ad9a133dc7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 104:b9ad9a133dc7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 104:b9ad9a133dc7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 104:b9ad9a133dc7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 104:b9ad9a133dc7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 104:b9ad9a133dc7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 104:b9ad9a133dc7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 104:b9ad9a133dc7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 104:b9ad9a133dc7 35 ---------------------------------------------------------------------------*/
Kojto 104:b9ad9a133dc7 36
Kojto 104:b9ad9a133dc7 37
Kojto 104:b9ad9a133dc7 38 #ifndef __CORE_CAFUNC_H__
Kojto 104:b9ad9a133dc7 39 #define __CORE_CAFUNC_H__
Kojto 104:b9ad9a133dc7 40
Kojto 104:b9ad9a133dc7 41
Kojto 104:b9ad9a133dc7 42 /* ########################### Core Function Access ########################### */
Kojto 104:b9ad9a133dc7 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 104:b9ad9a133dc7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 104:b9ad9a133dc7 45 @{
Kojto 104:b9ad9a133dc7 46 */
Kojto 104:b9ad9a133dc7 47
Kojto 104:b9ad9a133dc7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 104:b9ad9a133dc7 49 /* ARM armcc specific functions */
Kojto 104:b9ad9a133dc7 50
Kojto 104:b9ad9a133dc7 51 #if (__ARMCC_VERSION < 400677)
Kojto 104:b9ad9a133dc7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 104:b9ad9a133dc7 53 #endif
Kojto 104:b9ad9a133dc7 54
Kojto 104:b9ad9a133dc7 55 #define MODE_USR 0x10
Kojto 104:b9ad9a133dc7 56 #define MODE_FIQ 0x11
Kojto 104:b9ad9a133dc7 57 #define MODE_IRQ 0x12
Kojto 104:b9ad9a133dc7 58 #define MODE_SVC 0x13
Kojto 104:b9ad9a133dc7 59 #define MODE_MON 0x16
Kojto 104:b9ad9a133dc7 60 #define MODE_ABT 0x17
Kojto 104:b9ad9a133dc7 61 #define MODE_HYP 0x1A
Kojto 104:b9ad9a133dc7 62 #define MODE_UND 0x1B
Kojto 104:b9ad9a133dc7 63 #define MODE_SYS 0x1F
Kojto 104:b9ad9a133dc7 64
Kojto 104:b9ad9a133dc7 65 /** \brief Get APSR Register
Kojto 104:b9ad9a133dc7 66
Kojto 104:b9ad9a133dc7 67 This function returns the content of the APSR Register.
Kojto 104:b9ad9a133dc7 68
Kojto 104:b9ad9a133dc7 69 \return APSR Register value
Kojto 104:b9ad9a133dc7 70 */
Kojto 104:b9ad9a133dc7 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 104:b9ad9a133dc7 72 {
Kojto 104:b9ad9a133dc7 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 104:b9ad9a133dc7 74 return(__regAPSR);
Kojto 104:b9ad9a133dc7 75 }
Kojto 104:b9ad9a133dc7 76
Kojto 104:b9ad9a133dc7 77
Kojto 104:b9ad9a133dc7 78 /** \brief Get CPSR Register
Kojto 104:b9ad9a133dc7 79
Kojto 104:b9ad9a133dc7 80 This function returns the content of the CPSR Register.
Kojto 104:b9ad9a133dc7 81
Kojto 104:b9ad9a133dc7 82 \return CPSR Register value
Kojto 104:b9ad9a133dc7 83 */
Kojto 104:b9ad9a133dc7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 104:b9ad9a133dc7 85 {
Kojto 104:b9ad9a133dc7 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 104:b9ad9a133dc7 87 return(__regCPSR);
Kojto 104:b9ad9a133dc7 88 }
Kojto 104:b9ad9a133dc7 89
Kojto 104:b9ad9a133dc7 90 /** \brief Set Stack Pointer
Kojto 104:b9ad9a133dc7 91
Kojto 104:b9ad9a133dc7 92 This function assigns the given value to the current stack pointer.
Kojto 104:b9ad9a133dc7 93
Kojto 104:b9ad9a133dc7 94 \param [in] topOfStack Stack Pointer value to set
Kojto 104:b9ad9a133dc7 95 */
Kojto 104:b9ad9a133dc7 96 register uint32_t __regSP __ASM("sp");
Kojto 104:b9ad9a133dc7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 104:b9ad9a133dc7 98 {
Kojto 104:b9ad9a133dc7 99 __regSP = topOfStack;
Kojto 104:b9ad9a133dc7 100 }
Kojto 104:b9ad9a133dc7 101
Kojto 104:b9ad9a133dc7 102
Kojto 104:b9ad9a133dc7 103 /** \brief Get link register
Kojto 104:b9ad9a133dc7 104
Kojto 104:b9ad9a133dc7 105 This function returns the value of the link register
Kojto 104:b9ad9a133dc7 106
Kojto 104:b9ad9a133dc7 107 \return Value of link register
Kojto 104:b9ad9a133dc7 108 */
Kojto 104:b9ad9a133dc7 109 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 104:b9ad9a133dc7 111 {
Kojto 104:b9ad9a133dc7 112 return(__reglr);
Kojto 104:b9ad9a133dc7 113 }
Kojto 104:b9ad9a133dc7 114
Kojto 104:b9ad9a133dc7 115 /** \brief Set link register
Kojto 104:b9ad9a133dc7 116
Kojto 104:b9ad9a133dc7 117 This function sets the value of the link register
Kojto 104:b9ad9a133dc7 118
Kojto 104:b9ad9a133dc7 119 \param [in] lr LR value to set
Kojto 104:b9ad9a133dc7 120 */
Kojto 104:b9ad9a133dc7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 104:b9ad9a133dc7 122 {
Kojto 104:b9ad9a133dc7 123 __reglr = lr;
Kojto 104:b9ad9a133dc7 124 }
Kojto 104:b9ad9a133dc7 125
Kojto 104:b9ad9a133dc7 126 /** \brief Set Process Stack Pointer
Kojto 104:b9ad9a133dc7 127
Kojto 104:b9ad9a133dc7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 104:b9ad9a133dc7 129
Kojto 104:b9ad9a133dc7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 104:b9ad9a133dc7 131 */
Kojto 104:b9ad9a133dc7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 104:b9ad9a133dc7 133 {
Kojto 104:b9ad9a133dc7 134 ARM
Kojto 104:b9ad9a133dc7 135 PRESERVE8
Kojto 104:b9ad9a133dc7 136
Kojto 104:b9ad9a133dc7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 104:b9ad9a133dc7 138 MRS R1, CPSR
Kojto 104:b9ad9a133dc7 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 104:b9ad9a133dc7 140 MOV SP, R0
Kojto 104:b9ad9a133dc7 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 104:b9ad9a133dc7 142 ISB
Kojto 104:b9ad9a133dc7 143 BX LR
Kojto 104:b9ad9a133dc7 144
Kojto 104:b9ad9a133dc7 145 }
Kojto 104:b9ad9a133dc7 146
Kojto 104:b9ad9a133dc7 147 /** \brief Set User Mode
Kojto 104:b9ad9a133dc7 148
Kojto 104:b9ad9a133dc7 149 This function changes the processor state to User Mode
Kojto 104:b9ad9a133dc7 150
Kojto 104:b9ad9a133dc7 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 104:b9ad9a133dc7 152 */
Kojto 104:b9ad9a133dc7 153 __STATIC_ASM void __set_CPS_USR(void)
Kojto 104:b9ad9a133dc7 154 {
Kojto 104:b9ad9a133dc7 155 ARM
Kojto 104:b9ad9a133dc7 156
Kojto 104:b9ad9a133dc7 157 CPS #MODE_USR
Kojto 104:b9ad9a133dc7 158 BX LR
Kojto 104:b9ad9a133dc7 159 }
Kojto 104:b9ad9a133dc7 160
Kojto 104:b9ad9a133dc7 161
Kojto 104:b9ad9a133dc7 162 /** \brief Enable FIQ
Kojto 104:b9ad9a133dc7 163
Kojto 104:b9ad9a133dc7 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 165 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 166 */
Kojto 104:b9ad9a133dc7 167 #define __enable_fault_irq __enable_fiq
Kojto 104:b9ad9a133dc7 168
Kojto 104:b9ad9a133dc7 169
Kojto 104:b9ad9a133dc7 170 /** \brief Disable FIQ
Kojto 104:b9ad9a133dc7 171
Kojto 104:b9ad9a133dc7 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 173 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 174 */
Kojto 104:b9ad9a133dc7 175 #define __disable_fault_irq __disable_fiq
Kojto 104:b9ad9a133dc7 176
Kojto 104:b9ad9a133dc7 177
Kojto 104:b9ad9a133dc7 178 /** \brief Get FPSCR
Kojto 104:b9ad9a133dc7 179
Kojto 104:b9ad9a133dc7 180 This function returns the current value of the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 181
Kojto 104:b9ad9a133dc7 182 \return Floating Point Status/Control register value
Kojto 104:b9ad9a133dc7 183 */
Kojto 104:b9ad9a133dc7 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 104:b9ad9a133dc7 185 {
Kojto 104:b9ad9a133dc7 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 187 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 188 return(__regfpscr);
Kojto 104:b9ad9a133dc7 189 #else
Kojto 104:b9ad9a133dc7 190 return(0);
Kojto 104:b9ad9a133dc7 191 #endif
Kojto 104:b9ad9a133dc7 192 }
Kojto 104:b9ad9a133dc7 193
Kojto 104:b9ad9a133dc7 194
Kojto 104:b9ad9a133dc7 195 /** \brief Set FPSCR
Kojto 104:b9ad9a133dc7 196
Kojto 104:b9ad9a133dc7 197 This function assigns the given value to the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 198
Kojto 104:b9ad9a133dc7 199 \param [in] fpscr Floating Point Status/Control value to set
Kojto 104:b9ad9a133dc7 200 */
Kojto 104:b9ad9a133dc7 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 104:b9ad9a133dc7 202 {
Kojto 104:b9ad9a133dc7 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 204 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 205 __regfpscr = (fpscr);
Kojto 104:b9ad9a133dc7 206 #endif
Kojto 104:b9ad9a133dc7 207 }
Kojto 104:b9ad9a133dc7 208
Kojto 104:b9ad9a133dc7 209 /** \brief Get FPEXC
Kojto 104:b9ad9a133dc7 210
Kojto 104:b9ad9a133dc7 211 This function returns the current value of the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 212
Kojto 104:b9ad9a133dc7 213 \return Floating Point Exception Control register value
Kojto 104:b9ad9a133dc7 214 */
Kojto 104:b9ad9a133dc7 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 104:b9ad9a133dc7 216 {
Kojto 104:b9ad9a133dc7 217 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 218 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 219 return(__regfpexc);
Kojto 104:b9ad9a133dc7 220 #else
Kojto 104:b9ad9a133dc7 221 return(0);
Kojto 104:b9ad9a133dc7 222 #endif
Kojto 104:b9ad9a133dc7 223 }
Kojto 104:b9ad9a133dc7 224
Kojto 104:b9ad9a133dc7 225
Kojto 104:b9ad9a133dc7 226 /** \brief Set FPEXC
Kojto 104:b9ad9a133dc7 227
Kojto 104:b9ad9a133dc7 228 This function assigns the given value to the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 229
Kojto 104:b9ad9a133dc7 230 \param [in] fpscr Floating Point Exception Control value to set
Kojto 104:b9ad9a133dc7 231 */
Kojto 104:b9ad9a133dc7 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 104:b9ad9a133dc7 233 {
Kojto 104:b9ad9a133dc7 234 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 235 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 236 __regfpexc = (fpexc);
Kojto 104:b9ad9a133dc7 237 #endif
Kojto 104:b9ad9a133dc7 238 }
Kojto 104:b9ad9a133dc7 239
Kojto 104:b9ad9a133dc7 240 /** \brief Get CPACR
Kojto 104:b9ad9a133dc7 241
Kojto 104:b9ad9a133dc7 242 This function returns the current value of the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 243
Kojto 104:b9ad9a133dc7 244 \return Coprocessor Access Control register value
Kojto 104:b9ad9a133dc7 245 */
Kojto 104:b9ad9a133dc7 246 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 104:b9ad9a133dc7 247 {
Kojto 104:b9ad9a133dc7 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 249 return __regCPACR;
Kojto 104:b9ad9a133dc7 250 }
Kojto 104:b9ad9a133dc7 251
Kojto 104:b9ad9a133dc7 252 /** \brief Set CPACR
Kojto 104:b9ad9a133dc7 253
Kojto 104:b9ad9a133dc7 254 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 255
Kojto 104:b9ad9a133dc7 256 \param [in] cpacr Coporcessor Acccess Control value to set
Kojto 104:b9ad9a133dc7 257 */
Kojto 104:b9ad9a133dc7 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 104:b9ad9a133dc7 259 {
Kojto 104:b9ad9a133dc7 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 261 __regCPACR = cpacr;
Kojto 104:b9ad9a133dc7 262 __ISB();
Kojto 104:b9ad9a133dc7 263 }
Kojto 104:b9ad9a133dc7 264
Kojto 104:b9ad9a133dc7 265 /** \brief Get CBAR
Kojto 104:b9ad9a133dc7 266
Kojto 104:b9ad9a133dc7 267 This function returns the value of the Configuration Base Address register.
Kojto 104:b9ad9a133dc7 268
Kojto 104:b9ad9a133dc7 269 \return Configuration Base Address register value
Kojto 104:b9ad9a133dc7 270 */
Kojto 104:b9ad9a133dc7 271 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 104:b9ad9a133dc7 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 104:b9ad9a133dc7 273 return(__regCBAR);
Kojto 104:b9ad9a133dc7 274 }
Kojto 104:b9ad9a133dc7 275
Kojto 104:b9ad9a133dc7 276 /** \brief Get TTBR0
Kojto 104:b9ad9a133dc7 277
Kojto 104:b9ad9a133dc7 278 This function returns the value of the Configuration Base Address register.
Kojto 104:b9ad9a133dc7 279
Kojto 104:b9ad9a133dc7 280 \return Translation Table Base Register 0 value
Kojto 104:b9ad9a133dc7 281 */
Kojto 104:b9ad9a133dc7 282 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 104:b9ad9a133dc7 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 284 return(__regTTBR0);
Kojto 104:b9ad9a133dc7 285 }
Kojto 104:b9ad9a133dc7 286
Kojto 104:b9ad9a133dc7 287 /** \brief Set TTBR0
Kojto 104:b9ad9a133dc7 288
Kojto 104:b9ad9a133dc7 289 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 290
Kojto 104:b9ad9a133dc7 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 104:b9ad9a133dc7 292 */
Kojto 104:b9ad9a133dc7 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 104:b9ad9a133dc7 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 295 __regTTBR0 = ttbr0;
Kojto 104:b9ad9a133dc7 296 __ISB();
Kojto 104:b9ad9a133dc7 297 }
Kojto 104:b9ad9a133dc7 298
Kojto 104:b9ad9a133dc7 299 /** \brief Get DACR
Kojto 104:b9ad9a133dc7 300
Kojto 104:b9ad9a133dc7 301 This function returns the value of the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 302
Kojto 104:b9ad9a133dc7 303 \return Domain Access Control Register value
Kojto 104:b9ad9a133dc7 304 */
Kojto 104:b9ad9a133dc7 305 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 104:b9ad9a133dc7 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 307 return(__regDACR);
Kojto 104:b9ad9a133dc7 308 }
Kojto 104:b9ad9a133dc7 309
Kojto 104:b9ad9a133dc7 310 /** \brief Set DACR
Kojto 104:b9ad9a133dc7 311
Kojto 104:b9ad9a133dc7 312 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 313
Kojto 104:b9ad9a133dc7 314 \param [in] dacr Domain Access Control Register value to set
Kojto 104:b9ad9a133dc7 315 */
Kojto 104:b9ad9a133dc7 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 104:b9ad9a133dc7 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 318 __regDACR = dacr;
Kojto 104:b9ad9a133dc7 319 __ISB();
Kojto 104:b9ad9a133dc7 320 }
Kojto 104:b9ad9a133dc7 321
Kojto 104:b9ad9a133dc7 322 /******************************** Cache and BTAC enable ****************************************************/
Kojto 104:b9ad9a133dc7 323
Kojto 104:b9ad9a133dc7 324 /** \brief Set SCTLR
Kojto 104:b9ad9a133dc7 325
Kojto 104:b9ad9a133dc7 326 This function assigns the given value to the System Control Register.
Kojto 104:b9ad9a133dc7 327
Kojto 104:b9ad9a133dc7 328 \param [in] sctlr System Control Register, value to set
Kojto 104:b9ad9a133dc7 329 */
Kojto 104:b9ad9a133dc7 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 104:b9ad9a133dc7 331 {
Kojto 104:b9ad9a133dc7 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 333 __regSCTLR = sctlr;
Kojto 104:b9ad9a133dc7 334 }
Kojto 104:b9ad9a133dc7 335
Kojto 104:b9ad9a133dc7 336 /** \brief Get SCTLR
Kojto 104:b9ad9a133dc7 337
Kojto 104:b9ad9a133dc7 338 This function returns the value of the System Control Register.
Kojto 104:b9ad9a133dc7 339
Kojto 104:b9ad9a133dc7 340 \return System Control Register value
Kojto 104:b9ad9a133dc7 341 */
Kojto 104:b9ad9a133dc7 342 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 104:b9ad9a133dc7 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 344 return(__regSCTLR);
Kojto 104:b9ad9a133dc7 345 }
Kojto 104:b9ad9a133dc7 346
Kojto 104:b9ad9a133dc7 347 /** \brief Enable Caches
Kojto 104:b9ad9a133dc7 348
Kojto 104:b9ad9a133dc7 349 Enable Caches
Kojto 104:b9ad9a133dc7 350 */
Kojto 104:b9ad9a133dc7 351 __STATIC_INLINE void __enable_caches(void) {
Kojto 104:b9ad9a133dc7 352 // Set I bit 12 to enable I Cache
Kojto 104:b9ad9a133dc7 353 // Set C bit 2 to enable D Cache
Kojto 104:b9ad9a133dc7 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 104:b9ad9a133dc7 355 }
Kojto 104:b9ad9a133dc7 356
Kojto 104:b9ad9a133dc7 357 /** \brief Disable Caches
Kojto 104:b9ad9a133dc7 358
Kojto 104:b9ad9a133dc7 359 Disable Caches
Kojto 104:b9ad9a133dc7 360 */
Kojto 104:b9ad9a133dc7 361 __STATIC_INLINE void __disable_caches(void) {
Kojto 104:b9ad9a133dc7 362 // Clear I bit 12 to disable I Cache
Kojto 104:b9ad9a133dc7 363 // Clear C bit 2 to disable D Cache
Kojto 104:b9ad9a133dc7 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 104:b9ad9a133dc7 365 __ISB();
Kojto 104:b9ad9a133dc7 366 }
Kojto 104:b9ad9a133dc7 367
Kojto 104:b9ad9a133dc7 368 /** \brief Enable BTAC
Kojto 104:b9ad9a133dc7 369
Kojto 104:b9ad9a133dc7 370 Enable BTAC
Kojto 104:b9ad9a133dc7 371 */
Kojto 104:b9ad9a133dc7 372 __STATIC_INLINE void __enable_btac(void) {
Kojto 104:b9ad9a133dc7 373 // Set Z bit 11 to enable branch prediction
Kojto 104:b9ad9a133dc7 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 104:b9ad9a133dc7 375 __ISB();
Kojto 104:b9ad9a133dc7 376 }
Kojto 104:b9ad9a133dc7 377
Kojto 104:b9ad9a133dc7 378 /** \brief Disable BTAC
Kojto 104:b9ad9a133dc7 379
Kojto 104:b9ad9a133dc7 380 Disable BTAC
Kojto 104:b9ad9a133dc7 381 */
Kojto 104:b9ad9a133dc7 382 __STATIC_INLINE void __disable_btac(void) {
Kojto 104:b9ad9a133dc7 383 // Clear Z bit 11 to disable branch prediction
Kojto 104:b9ad9a133dc7 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 104:b9ad9a133dc7 385 }
Kojto 104:b9ad9a133dc7 386
Kojto 104:b9ad9a133dc7 387
Kojto 104:b9ad9a133dc7 388 /** \brief Enable MMU
Kojto 104:b9ad9a133dc7 389
Kojto 104:b9ad9a133dc7 390 Enable MMU
Kojto 104:b9ad9a133dc7 391 */
Kojto 104:b9ad9a133dc7 392 __STATIC_INLINE void __enable_mmu(void) {
Kojto 104:b9ad9a133dc7 393 // Set M bit 0 to enable the MMU
Kojto 104:b9ad9a133dc7 394 // Set AFE bit to enable simplified access permissions model
Kojto 104:b9ad9a133dc7 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 104:b9ad9a133dc7 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 104:b9ad9a133dc7 397 __ISB();
Kojto 104:b9ad9a133dc7 398 }
Kojto 104:b9ad9a133dc7 399
Kojto 104:b9ad9a133dc7 400 /** \brief Enable MMU
Kojto 104:b9ad9a133dc7 401
Kojto 104:b9ad9a133dc7 402 Enable MMU
Kojto 104:b9ad9a133dc7 403 */
Kojto 104:b9ad9a133dc7 404 __STATIC_INLINE void __disable_mmu(void) {
Kojto 104:b9ad9a133dc7 405 // Clear M bit 0 to disable the MMU
Kojto 104:b9ad9a133dc7 406 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 104:b9ad9a133dc7 407 __ISB();
Kojto 104:b9ad9a133dc7 408 }
Kojto 104:b9ad9a133dc7 409
Kojto 104:b9ad9a133dc7 410 /******************************** TLB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 411 /** \brief Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 412
Kojto 104:b9ad9a133dc7 413 TLBIALL. Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 414 */
Kojto 104:b9ad9a133dc7 415
Kojto 104:b9ad9a133dc7 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 104:b9ad9a133dc7 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 104:b9ad9a133dc7 418 __TLBIALL = 0;
Kojto 104:b9ad9a133dc7 419 __DSB();
Kojto 104:b9ad9a133dc7 420 __ISB();
Kojto 104:b9ad9a133dc7 421 }
Kojto 104:b9ad9a133dc7 422
Kojto 104:b9ad9a133dc7 423 /******************************** BTB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 424 /** \brief Invalidate entire branch predictor array
Kojto 104:b9ad9a133dc7 425
Kojto 104:b9ad9a133dc7 426 BPIALL. Branch Predictor Invalidate All.
Kojto 104:b9ad9a133dc7 427 */
Kojto 104:b9ad9a133dc7 428
Kojto 104:b9ad9a133dc7 429 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 104:b9ad9a133dc7 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 104:b9ad9a133dc7 431 __BPIALL = 0;
Kojto 104:b9ad9a133dc7 432 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 433 __ISB(); //ensure instruction fetch path sees new state
Kojto 104:b9ad9a133dc7 434 }
Kojto 104:b9ad9a133dc7 435
Kojto 104:b9ad9a133dc7 436
Kojto 104:b9ad9a133dc7 437 /******************************** L1 cache operations ******************************************************/
Kojto 104:b9ad9a133dc7 438
Kojto 104:b9ad9a133dc7 439 /** \brief Invalidate the whole I$
Kojto 104:b9ad9a133dc7 440
Kojto 104:b9ad9a133dc7 441 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 104:b9ad9a133dc7 442 */
Kojto 104:b9ad9a133dc7 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 104:b9ad9a133dc7 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 104:b9ad9a133dc7 445 __ICIALLU = 0;
Kojto 104:b9ad9a133dc7 446 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 447 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 104:b9ad9a133dc7 448 }
Kojto 104:b9ad9a133dc7 449
Kojto 104:b9ad9a133dc7 450 /** \brief Clean D$ by MVA
Kojto 104:b9ad9a133dc7 451
Kojto 104:b9ad9a133dc7 452 DCCMVAC. Data cache clean by MVA to PoC
Kojto 104:b9ad9a133dc7 453 */
Kojto 104:b9ad9a133dc7 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 104:b9ad9a133dc7 456 __DCCMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 458 }
Kojto 104:b9ad9a133dc7 459
Kojto 104:b9ad9a133dc7 460 /** \brief Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 461
Kojto 104:b9ad9a133dc7 462 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 463 */
Kojto 104:b9ad9a133dc7 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 104:b9ad9a133dc7 466 __DCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 468 }
Kojto 104:b9ad9a133dc7 469
Kojto 104:b9ad9a133dc7 470 /** \brief Clean and Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 471
Kojto 104:b9ad9a133dc7 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 473 */
Kojto 104:b9ad9a133dc7 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 104:b9ad9a133dc7 476 __DCCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 478 }
Kojto 104:b9ad9a133dc7 479
Kojto 104:b9ad9a133dc7 480 /** \brief
Kojto 104:b9ad9a133dc7 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 104:b9ad9a133dc7 482 */
Kojto 104:b9ad9a133dc7 483 #pragma push
Kojto 104:b9ad9a133dc7 484 #pragma arm
Kojto 104:b9ad9a133dc7 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 104:b9ad9a133dc7 486 ARM
Kojto 104:b9ad9a133dc7 487
Kojto 104:b9ad9a133dc7 488 PUSH {R4-R11}
Kojto 104:b9ad9a133dc7 489
Kojto 104:b9ad9a133dc7 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 104:b9ad9a133dc7 491 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 104:b9ad9a133dc7 492 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 104:b9ad9a133dc7 493 BEQ Finished // If 0, no need to clean
Kojto 104:b9ad9a133dc7 494
Kojto 104:b9ad9a133dc7 495 MOV R10, #0 // R10 holds current cache level << 1
Kojto 104:b9ad9a133dc7 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 104:b9ad9a133dc7 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 104:b9ad9a133dc7 498 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 104:b9ad9a133dc7 499 CMP R1, #2
Kojto 104:b9ad9a133dc7 500 BLT Skip // No cache or only instruction cache at this level
Kojto 104:b9ad9a133dc7 501
Kojto 104:b9ad9a133dc7 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 104:b9ad9a133dc7 503 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 104:b9ad9a133dc7 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 104:b9ad9a133dc7 505 AND R2, R1, #7 // Extract the line length field
Kojto 104:b9ad9a133dc7 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 104:b9ad9a133dc7 507 LDR R4, =0x3FF
Kojto 104:b9ad9a133dc7 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 104:b9ad9a133dc7 509 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 104:b9ad9a133dc7 510 LDR R7, =0x7FFF
Kojto 104:b9ad9a133dc7 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 104:b9ad9a133dc7 512
Kojto 104:b9ad9a133dc7 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 104:b9ad9a133dc7 514
Kojto 104:b9ad9a133dc7 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 104:b9ad9a133dc7 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 104:b9ad9a133dc7 517 CMP R0, #0
Kojto 104:b9ad9a133dc7 518 BNE Dccsw
Kojto 104:b9ad9a133dc7 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 520 B cont
Kojto 104:b9ad9a133dc7 521 Dccsw CMP R0, #1
Kojto 104:b9ad9a133dc7 522 BNE Dccisw
Kojto 104:b9ad9a133dc7 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 524 B cont
Kojto 104:b9ad9a133dc7 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 526 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 104:b9ad9a133dc7 527 BGE Loop3
Kojto 104:b9ad9a133dc7 528 SUBS R7, R7, #1 // Decrement the Set number
Kojto 104:b9ad9a133dc7 529 BGE Loop2
Kojto 104:b9ad9a133dc7 530 Skip ADD R10, R10, #2 // increment the cache number
Kojto 104:b9ad9a133dc7 531 CMP R3, R10
Kojto 104:b9ad9a133dc7 532 BGT Loop1
Kojto 104:b9ad9a133dc7 533
Kojto 104:b9ad9a133dc7 534 Finished
Kojto 104:b9ad9a133dc7 535 DSB
Kojto 104:b9ad9a133dc7 536 POP {R4-R11}
Kojto 104:b9ad9a133dc7 537 BX lr
Kojto 104:b9ad9a133dc7 538
Kojto 104:b9ad9a133dc7 539 }
Kojto 104:b9ad9a133dc7 540 #pragma pop
Kojto 104:b9ad9a133dc7 541
Kojto 104:b9ad9a133dc7 542 /** \brief __v7_all_cache - helper function
Kojto 104:b9ad9a133dc7 543
Kojto 104:b9ad9a133dc7 544 */
Kojto 104:b9ad9a133dc7 545
Kojto 104:b9ad9a133dc7 546 /** \brief Invalidate the whole D$
Kojto 104:b9ad9a133dc7 547
Kojto 104:b9ad9a133dc7 548 DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 549 */
Kojto 104:b9ad9a133dc7 550
Kojto 104:b9ad9a133dc7 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 552 __v7_all_cache(0);
Kojto 104:b9ad9a133dc7 553 }
Kojto 104:b9ad9a133dc7 554
Kojto 104:b9ad9a133dc7 555 /** \brief Clean the whole D$
Kojto 104:b9ad9a133dc7 556
Kojto 104:b9ad9a133dc7 557 DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 558 */
Kojto 104:b9ad9a133dc7 559
Kojto 104:b9ad9a133dc7 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 104:b9ad9a133dc7 561 __v7_all_cache(1);
Kojto 104:b9ad9a133dc7 562 }
Kojto 104:b9ad9a133dc7 563
Kojto 104:b9ad9a133dc7 564 /** \brief Clean and invalidate the whole D$
Kojto 104:b9ad9a133dc7 565
Kojto 104:b9ad9a133dc7 566 DCCISW. Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 567 */
Kojto 104:b9ad9a133dc7 568
Kojto 104:b9ad9a133dc7 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 570 __v7_all_cache(2);
Kojto 104:b9ad9a133dc7 571 }
Kojto 104:b9ad9a133dc7 572
Kojto 104:b9ad9a133dc7 573 #include "core_ca_mmu.h"
Kojto 104:b9ad9a133dc7 574
Kojto 104:b9ad9a133dc7 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 104:b9ad9a133dc7 576
Kojto 104:b9ad9a133dc7 577 #error IAR Compiler support not implemented for Cortex-A
Kojto 104:b9ad9a133dc7 578
Kojto 104:b9ad9a133dc7 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 104:b9ad9a133dc7 580
Kojto 104:b9ad9a133dc7 581 /* GNU gcc specific functions */
Kojto 104:b9ad9a133dc7 582
Kojto 104:b9ad9a133dc7 583 #define MODE_USR 0x10
Kojto 104:b9ad9a133dc7 584 #define MODE_FIQ 0x11
Kojto 104:b9ad9a133dc7 585 #define MODE_IRQ 0x12
Kojto 104:b9ad9a133dc7 586 #define MODE_SVC 0x13
Kojto 104:b9ad9a133dc7 587 #define MODE_MON 0x16
Kojto 104:b9ad9a133dc7 588 #define MODE_ABT 0x17
Kojto 104:b9ad9a133dc7 589 #define MODE_HYP 0x1A
Kojto 104:b9ad9a133dc7 590 #define MODE_UND 0x1B
Kojto 104:b9ad9a133dc7 591 #define MODE_SYS 0x1F
Kojto 104:b9ad9a133dc7 592
Kojto 104:b9ad9a133dc7 593
Kojto 104:b9ad9a133dc7 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 104:b9ad9a133dc7 595 {
Kojto 104:b9ad9a133dc7 596 __ASM volatile ("cpsie i");
Kojto 104:b9ad9a133dc7 597 }
Kojto 104:b9ad9a133dc7 598
Kojto 104:b9ad9a133dc7 599 /** \brief Disable IRQ Interrupts
Kojto 104:b9ad9a133dc7 600
Kojto 104:b9ad9a133dc7 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 104:b9ad9a133dc7 602 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 603 */
Kojto 104:b9ad9a133dc7 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 104:b9ad9a133dc7 605 {
Kojto 104:b9ad9a133dc7 606 uint32_t result;
Kojto 104:b9ad9a133dc7 607
Kojto 104:b9ad9a133dc7 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 104:b9ad9a133dc7 609 __ASM volatile ("cpsid i");
Kojto 104:b9ad9a133dc7 610 return(result & 0x80);
Kojto 104:b9ad9a133dc7 611 }
Kojto 104:b9ad9a133dc7 612
Kojto 104:b9ad9a133dc7 613
Kojto 104:b9ad9a133dc7 614 /** \brief Get APSR Register
Kojto 104:b9ad9a133dc7 615
Kojto 104:b9ad9a133dc7 616 This function returns the content of the APSR Register.
Kojto 104:b9ad9a133dc7 617
Kojto 104:b9ad9a133dc7 618 \return APSR Register value
Kojto 104:b9ad9a133dc7 619 */
Kojto 104:b9ad9a133dc7 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 104:b9ad9a133dc7 621 {
Kojto 104:b9ad9a133dc7 622 #if 1
Kojto 104:b9ad9a133dc7 623 uint32_t result;
Kojto 104:b9ad9a133dc7 624
Kojto 104:b9ad9a133dc7 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
Kojto 104:b9ad9a133dc7 626 return (result);
Kojto 104:b9ad9a133dc7 627 #else
Kojto 104:b9ad9a133dc7 628 register uint32_t __regAPSR __ASM("apsr");
Kojto 104:b9ad9a133dc7 629 return(__regAPSR);
Kojto 104:b9ad9a133dc7 630 #endif
Kojto 104:b9ad9a133dc7 631 }
Kojto 104:b9ad9a133dc7 632
Kojto 104:b9ad9a133dc7 633
Kojto 104:b9ad9a133dc7 634 /** \brief Get CPSR Register
Kojto 104:b9ad9a133dc7 635
Kojto 104:b9ad9a133dc7 636 This function returns the content of the CPSR Register.
Kojto 104:b9ad9a133dc7 637
Kojto 104:b9ad9a133dc7 638 \return CPSR Register value
Kojto 104:b9ad9a133dc7 639 */
Kojto 104:b9ad9a133dc7 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 104:b9ad9a133dc7 641 {
Kojto 104:b9ad9a133dc7 642 #if 1
Kojto 104:b9ad9a133dc7 643 register uint32_t __regCPSR;
Kojto 104:b9ad9a133dc7 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 104:b9ad9a133dc7 645 #else
Kojto 104:b9ad9a133dc7 646 register uint32_t __regCPSR __ASM("cpsr");
Kojto 104:b9ad9a133dc7 647 #endif
Kojto 104:b9ad9a133dc7 648 return(__regCPSR);
Kojto 104:b9ad9a133dc7 649 }
Kojto 104:b9ad9a133dc7 650
Kojto 104:b9ad9a133dc7 651 #if 0
Kojto 104:b9ad9a133dc7 652 /** \brief Set Stack Pointer
Kojto 104:b9ad9a133dc7 653
Kojto 104:b9ad9a133dc7 654 This function assigns the given value to the current stack pointer.
Kojto 104:b9ad9a133dc7 655
Kojto 104:b9ad9a133dc7 656 \param [in] topOfStack Stack Pointer value to set
Kojto 104:b9ad9a133dc7 657 */
Kojto 104:b9ad9a133dc7 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 104:b9ad9a133dc7 659 {
Kojto 104:b9ad9a133dc7 660 register uint32_t __regSP __ASM("sp");
Kojto 104:b9ad9a133dc7 661 __regSP = topOfStack;
Kojto 104:b9ad9a133dc7 662 }
Kojto 104:b9ad9a133dc7 663 #endif
Kojto 104:b9ad9a133dc7 664
Kojto 104:b9ad9a133dc7 665 /** \brief Get link register
Kojto 104:b9ad9a133dc7 666
Kojto 104:b9ad9a133dc7 667 This function returns the value of the link register
Kojto 104:b9ad9a133dc7 668
Kojto 104:b9ad9a133dc7 669 \return Value of link register
Kojto 104:b9ad9a133dc7 670 */
Kojto 104:b9ad9a133dc7 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 104:b9ad9a133dc7 672 {
Kojto 104:b9ad9a133dc7 673 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 674 return(__reglr);
Kojto 104:b9ad9a133dc7 675 }
Kojto 104:b9ad9a133dc7 676
Kojto 104:b9ad9a133dc7 677 #if 0
Kojto 104:b9ad9a133dc7 678 /** \brief Set link register
Kojto 104:b9ad9a133dc7 679
Kojto 104:b9ad9a133dc7 680 This function sets the value of the link register
Kojto 104:b9ad9a133dc7 681
Kojto 104:b9ad9a133dc7 682 \param [in] lr LR value to set
Kojto 104:b9ad9a133dc7 683 */
Kojto 104:b9ad9a133dc7 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 104:b9ad9a133dc7 685 {
Kojto 104:b9ad9a133dc7 686 register uint32_t __reglr __ASM("lr");
Kojto 104:b9ad9a133dc7 687 __reglr = lr;
Kojto 104:b9ad9a133dc7 688 }
Kojto 104:b9ad9a133dc7 689 #endif
Kojto 104:b9ad9a133dc7 690
Kojto 104:b9ad9a133dc7 691 /** \brief Set Process Stack Pointer
Kojto 104:b9ad9a133dc7 692
Kojto 104:b9ad9a133dc7 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 104:b9ad9a133dc7 694
Kojto 104:b9ad9a133dc7 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 104:b9ad9a133dc7 696 */
Kojto 104:b9ad9a133dc7 697 extern void __set_PSP(uint32_t topOfProcStack);
Kojto 104:b9ad9a133dc7 698
Kojto 104:b9ad9a133dc7 699 /** \brief Set User Mode
Kojto 104:b9ad9a133dc7 700
Kojto 104:b9ad9a133dc7 701 This function changes the processor state to User Mode
Kojto 104:b9ad9a133dc7 702
Kojto 104:b9ad9a133dc7 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 104:b9ad9a133dc7 704 */
Kojto 104:b9ad9a133dc7 705 extern void __set_CPS_USR(void);
Kojto 104:b9ad9a133dc7 706
Kojto 104:b9ad9a133dc7 707 /** \brief Enable FIQ
Kojto 104:b9ad9a133dc7 708
Kojto 104:b9ad9a133dc7 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 710 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 711 */
Kojto 104:b9ad9a133dc7 712 #define __enable_fault_irq __enable_fiq
Kojto 104:b9ad9a133dc7 713
Kojto 104:b9ad9a133dc7 714
Kojto 104:b9ad9a133dc7 715 /** \brief Disable FIQ
Kojto 104:b9ad9a133dc7 716
Kojto 104:b9ad9a133dc7 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 104:b9ad9a133dc7 718 Can only be executed in Privileged modes.
Kojto 104:b9ad9a133dc7 719 */
Kojto 104:b9ad9a133dc7 720 #define __disable_fault_irq __disable_fiq
Kojto 104:b9ad9a133dc7 721
Kojto 104:b9ad9a133dc7 722
Kojto 104:b9ad9a133dc7 723 /** \brief Get FPSCR
Kojto 104:b9ad9a133dc7 724
Kojto 104:b9ad9a133dc7 725 This function returns the current value of the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 726
Kojto 104:b9ad9a133dc7 727 \return Floating Point Status/Control register value
Kojto 104:b9ad9a133dc7 728 */
Kojto 104:b9ad9a133dc7 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 104:b9ad9a133dc7 730 {
Kojto 104:b9ad9a133dc7 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 732 #if 1
Kojto 104:b9ad9a133dc7 733 uint32_t result;
Kojto 104:b9ad9a133dc7 734
Kojto 104:b9ad9a133dc7 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 104:b9ad9a133dc7 736 return (result);
Kojto 104:b9ad9a133dc7 737 #else
Kojto 104:b9ad9a133dc7 738 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 739 return(__regfpscr);
Kojto 104:b9ad9a133dc7 740 #endif
Kojto 104:b9ad9a133dc7 741 #else
Kojto 104:b9ad9a133dc7 742 return(0);
Kojto 104:b9ad9a133dc7 743 #endif
Kojto 104:b9ad9a133dc7 744 }
Kojto 104:b9ad9a133dc7 745
Kojto 104:b9ad9a133dc7 746
Kojto 104:b9ad9a133dc7 747 /** \brief Set FPSCR
Kojto 104:b9ad9a133dc7 748
Kojto 104:b9ad9a133dc7 749 This function assigns the given value to the Floating Point Status/Control register.
Kojto 104:b9ad9a133dc7 750
Kojto 104:b9ad9a133dc7 751 \param [in] fpscr Floating Point Status/Control value to set
Kojto 104:b9ad9a133dc7 752 */
Kojto 104:b9ad9a133dc7 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 104:b9ad9a133dc7 754 {
Kojto 104:b9ad9a133dc7 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 104:b9ad9a133dc7 756 #if 1
Kojto 104:b9ad9a133dc7 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 104:b9ad9a133dc7 758 #else
Kojto 104:b9ad9a133dc7 759 register uint32_t __regfpscr __ASM("fpscr");
Kojto 104:b9ad9a133dc7 760 __regfpscr = (fpscr);
Kojto 104:b9ad9a133dc7 761 #endif
Kojto 104:b9ad9a133dc7 762 #endif
Kojto 104:b9ad9a133dc7 763 }
Kojto 104:b9ad9a133dc7 764
Kojto 104:b9ad9a133dc7 765 /** \brief Get FPEXC
Kojto 104:b9ad9a133dc7 766
Kojto 104:b9ad9a133dc7 767 This function returns the current value of the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 768
Kojto 104:b9ad9a133dc7 769 \return Floating Point Exception Control register value
Kojto 104:b9ad9a133dc7 770 */
Kojto 104:b9ad9a133dc7 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 104:b9ad9a133dc7 772 {
Kojto 104:b9ad9a133dc7 773 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 774 #if 1
Kojto 104:b9ad9a133dc7 775 uint32_t result;
Kojto 104:b9ad9a133dc7 776
Kojto 104:b9ad9a133dc7 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 104:b9ad9a133dc7 778 return (result);
Kojto 104:b9ad9a133dc7 779 #else
Kojto 104:b9ad9a133dc7 780 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 781 return(__regfpexc);
Kojto 104:b9ad9a133dc7 782 #endif
Kojto 104:b9ad9a133dc7 783 #else
Kojto 104:b9ad9a133dc7 784 return(0);
Kojto 104:b9ad9a133dc7 785 #endif
Kojto 104:b9ad9a133dc7 786 }
Kojto 104:b9ad9a133dc7 787
Kojto 104:b9ad9a133dc7 788
Kojto 104:b9ad9a133dc7 789 /** \brief Set FPEXC
Kojto 104:b9ad9a133dc7 790
Kojto 104:b9ad9a133dc7 791 This function assigns the given value to the Floating Point Exception Control register.
Kojto 104:b9ad9a133dc7 792
Kojto 104:b9ad9a133dc7 793 \param [in] fpscr Floating Point Exception Control value to set
Kojto 104:b9ad9a133dc7 794 */
Kojto 104:b9ad9a133dc7 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 104:b9ad9a133dc7 796 {
Kojto 104:b9ad9a133dc7 797 #if (__FPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 798 #if 1
Kojto 104:b9ad9a133dc7 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 104:b9ad9a133dc7 800 #else
Kojto 104:b9ad9a133dc7 801 register uint32_t __regfpexc __ASM("fpexc");
Kojto 104:b9ad9a133dc7 802 __regfpexc = (fpexc);
Kojto 104:b9ad9a133dc7 803 #endif
Kojto 104:b9ad9a133dc7 804 #endif
Kojto 104:b9ad9a133dc7 805 }
Kojto 104:b9ad9a133dc7 806
Kojto 104:b9ad9a133dc7 807 /** \brief Get CPACR
Kojto 104:b9ad9a133dc7 808
Kojto 104:b9ad9a133dc7 809 This function returns the current value of the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 810
Kojto 104:b9ad9a133dc7 811 \return Coprocessor Access Control register value
Kojto 104:b9ad9a133dc7 812 */
Kojto 104:b9ad9a133dc7 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 104:b9ad9a133dc7 814 {
Kojto 104:b9ad9a133dc7 815 #if 1
Kojto 104:b9ad9a133dc7 816 register uint32_t __regCPACR;
Kojto 104:b9ad9a133dc7 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 104:b9ad9a133dc7 818 #else
Kojto 104:b9ad9a133dc7 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 820 #endif
Kojto 104:b9ad9a133dc7 821 return __regCPACR;
Kojto 104:b9ad9a133dc7 822 }
Kojto 104:b9ad9a133dc7 823
Kojto 104:b9ad9a133dc7 824 /** \brief Set CPACR
Kojto 104:b9ad9a133dc7 825
Kojto 104:b9ad9a133dc7 826 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 827
Kojto 104:b9ad9a133dc7 828 \param [in] cpacr Coporcessor Acccess Control value to set
Kojto 104:b9ad9a133dc7 829 */
Kojto 104:b9ad9a133dc7 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 104:b9ad9a133dc7 831 {
Kojto 104:b9ad9a133dc7 832 #if 1
Kojto 104:b9ad9a133dc7 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 104:b9ad9a133dc7 834 #else
Kojto 104:b9ad9a133dc7 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 104:b9ad9a133dc7 836 __regCPACR = cpacr;
Kojto 104:b9ad9a133dc7 837 #endif
Kojto 104:b9ad9a133dc7 838 __ISB();
Kojto 104:b9ad9a133dc7 839 }
Kojto 104:b9ad9a133dc7 840
Kojto 104:b9ad9a133dc7 841 /** \brief Get CBAR
Kojto 104:b9ad9a133dc7 842
Kojto 104:b9ad9a133dc7 843 This function returns the value of the Configuration Base Address register.
Kojto 104:b9ad9a133dc7 844
Kojto 104:b9ad9a133dc7 845 \return Configuration Base Address register value
Kojto 104:b9ad9a133dc7 846 */
Kojto 104:b9ad9a133dc7 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 104:b9ad9a133dc7 848 #if 1
Kojto 104:b9ad9a133dc7 849 register uint32_t __regCBAR;
Kojto 104:b9ad9a133dc7 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 104:b9ad9a133dc7 851 #else
Kojto 104:b9ad9a133dc7 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 104:b9ad9a133dc7 853 #endif
Kojto 104:b9ad9a133dc7 854 return(__regCBAR);
Kojto 104:b9ad9a133dc7 855 }
Kojto 104:b9ad9a133dc7 856
Kojto 104:b9ad9a133dc7 857 /** \brief Get TTBR0
Kojto 104:b9ad9a133dc7 858
Kojto 104:b9ad9a133dc7 859 This function returns the value of the Configuration Base Address register.
Kojto 104:b9ad9a133dc7 860
Kojto 104:b9ad9a133dc7 861 \return Translation Table Base Register 0 value
Kojto 104:b9ad9a133dc7 862 */
Kojto 104:b9ad9a133dc7 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 104:b9ad9a133dc7 864 #if 1
Kojto 104:b9ad9a133dc7 865 register uint32_t __regTTBR0;
Kojto 104:b9ad9a133dc7 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 104:b9ad9a133dc7 867 #else
Kojto 104:b9ad9a133dc7 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 869 #endif
Kojto 104:b9ad9a133dc7 870 return(__regTTBR0);
Kojto 104:b9ad9a133dc7 871 }
Kojto 104:b9ad9a133dc7 872
Kojto 104:b9ad9a133dc7 873 /** \brief Set TTBR0
Kojto 104:b9ad9a133dc7 874
Kojto 104:b9ad9a133dc7 875 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 876
Kojto 104:b9ad9a133dc7 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 104:b9ad9a133dc7 878 */
Kojto 104:b9ad9a133dc7 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 104:b9ad9a133dc7 880 #if 1
Kojto 104:b9ad9a133dc7 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 104:b9ad9a133dc7 882 #else
Kojto 104:b9ad9a133dc7 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 104:b9ad9a133dc7 884 __regTTBR0 = ttbr0;
Kojto 104:b9ad9a133dc7 885 #endif
Kojto 104:b9ad9a133dc7 886 __ISB();
Kojto 104:b9ad9a133dc7 887 }
Kojto 104:b9ad9a133dc7 888
Kojto 104:b9ad9a133dc7 889 /** \brief Get DACR
Kojto 104:b9ad9a133dc7 890
Kojto 104:b9ad9a133dc7 891 This function returns the value of the Domain Access Control Register.
Kojto 104:b9ad9a133dc7 892
Kojto 104:b9ad9a133dc7 893 \return Domain Access Control Register value
Kojto 104:b9ad9a133dc7 894 */
Kojto 104:b9ad9a133dc7 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 104:b9ad9a133dc7 896 #if 1
Kojto 104:b9ad9a133dc7 897 register uint32_t __regDACR;
Kojto 104:b9ad9a133dc7 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 104:b9ad9a133dc7 899 #else
Kojto 104:b9ad9a133dc7 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 901 #endif
Kojto 104:b9ad9a133dc7 902 return(__regDACR);
Kojto 104:b9ad9a133dc7 903 }
Kojto 104:b9ad9a133dc7 904
Kojto 104:b9ad9a133dc7 905 /** \brief Set DACR
Kojto 104:b9ad9a133dc7 906
Kojto 104:b9ad9a133dc7 907 This function assigns the given value to the Coprocessor Access Control register.
Kojto 104:b9ad9a133dc7 908
Kojto 104:b9ad9a133dc7 909 \param [in] dacr Domain Access Control Register value to set
Kojto 104:b9ad9a133dc7 910 */
Kojto 104:b9ad9a133dc7 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 104:b9ad9a133dc7 912 #if 1
Kojto 104:b9ad9a133dc7 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 104:b9ad9a133dc7 914 #else
Kojto 104:b9ad9a133dc7 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 104:b9ad9a133dc7 916 __regDACR = dacr;
Kojto 104:b9ad9a133dc7 917 #endif
Kojto 104:b9ad9a133dc7 918 __ISB();
Kojto 104:b9ad9a133dc7 919 }
Kojto 104:b9ad9a133dc7 920
Kojto 104:b9ad9a133dc7 921 /******************************** Cache and BTAC enable ****************************************************/
Kojto 104:b9ad9a133dc7 922
Kojto 104:b9ad9a133dc7 923 /** \brief Set SCTLR
Kojto 104:b9ad9a133dc7 924
Kojto 104:b9ad9a133dc7 925 This function assigns the given value to the System Control Register.
Kojto 104:b9ad9a133dc7 926
Kojto 104:b9ad9a133dc7 927 \param [in] sctlr System Control Register, value to set
Kojto 104:b9ad9a133dc7 928 */
Kojto 104:b9ad9a133dc7 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 104:b9ad9a133dc7 930 {
Kojto 104:b9ad9a133dc7 931 #if 1
Kojto 104:b9ad9a133dc7 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 104:b9ad9a133dc7 933 #else
Kojto 104:b9ad9a133dc7 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 935 __regSCTLR = sctlr;
Kojto 104:b9ad9a133dc7 936 #endif
Kojto 104:b9ad9a133dc7 937 }
Kojto 104:b9ad9a133dc7 938
Kojto 104:b9ad9a133dc7 939 /** \brief Get SCTLR
Kojto 104:b9ad9a133dc7 940
Kojto 104:b9ad9a133dc7 941 This function returns the value of the System Control Register.
Kojto 104:b9ad9a133dc7 942
Kojto 104:b9ad9a133dc7 943 \return System Control Register value
Kojto 104:b9ad9a133dc7 944 */
Kojto 104:b9ad9a133dc7 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 104:b9ad9a133dc7 946 #if 1
Kojto 104:b9ad9a133dc7 947 register uint32_t __regSCTLR;
Kojto 104:b9ad9a133dc7 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 104:b9ad9a133dc7 949 #else
Kojto 104:b9ad9a133dc7 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 104:b9ad9a133dc7 951 #endif
Kojto 104:b9ad9a133dc7 952 return(__regSCTLR);
Kojto 104:b9ad9a133dc7 953 }
Kojto 104:b9ad9a133dc7 954
Kojto 104:b9ad9a133dc7 955 /** \brief Enable Caches
Kojto 104:b9ad9a133dc7 956
Kojto 104:b9ad9a133dc7 957 Enable Caches
Kojto 104:b9ad9a133dc7 958 */
Kojto 104:b9ad9a133dc7 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 104:b9ad9a133dc7 960 // Set I bit 12 to enable I Cache
Kojto 104:b9ad9a133dc7 961 // Set C bit 2 to enable D Cache
Kojto 104:b9ad9a133dc7 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 104:b9ad9a133dc7 963 }
Kojto 104:b9ad9a133dc7 964
Kojto 104:b9ad9a133dc7 965 /** \brief Disable Caches
Kojto 104:b9ad9a133dc7 966
Kojto 104:b9ad9a133dc7 967 Disable Caches
Kojto 104:b9ad9a133dc7 968 */
Kojto 104:b9ad9a133dc7 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 104:b9ad9a133dc7 970 // Clear I bit 12 to disable I Cache
Kojto 104:b9ad9a133dc7 971 // Clear C bit 2 to disable D Cache
Kojto 104:b9ad9a133dc7 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 104:b9ad9a133dc7 973 __ISB();
Kojto 104:b9ad9a133dc7 974 }
Kojto 104:b9ad9a133dc7 975
Kojto 104:b9ad9a133dc7 976 /** \brief Enable BTAC
Kojto 104:b9ad9a133dc7 977
Kojto 104:b9ad9a133dc7 978 Enable BTAC
Kojto 104:b9ad9a133dc7 979 */
Kojto 104:b9ad9a133dc7 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 104:b9ad9a133dc7 981 // Set Z bit 11 to enable branch prediction
Kojto 104:b9ad9a133dc7 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 104:b9ad9a133dc7 983 __ISB();
Kojto 104:b9ad9a133dc7 984 }
Kojto 104:b9ad9a133dc7 985
Kojto 104:b9ad9a133dc7 986 /** \brief Disable BTAC
Kojto 104:b9ad9a133dc7 987
Kojto 104:b9ad9a133dc7 988 Disable BTAC
Kojto 104:b9ad9a133dc7 989 */
Kojto 104:b9ad9a133dc7 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 104:b9ad9a133dc7 991 // Clear Z bit 11 to disable branch prediction
Kojto 104:b9ad9a133dc7 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 104:b9ad9a133dc7 993 }
Kojto 104:b9ad9a133dc7 994
Kojto 104:b9ad9a133dc7 995
Kojto 104:b9ad9a133dc7 996 /** \brief Enable MMU
Kojto 104:b9ad9a133dc7 997
Kojto 104:b9ad9a133dc7 998 Enable MMU
Kojto 104:b9ad9a133dc7 999 */
Kojto 104:b9ad9a133dc7 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 104:b9ad9a133dc7 1001 // Set M bit 0 to enable the MMU
Kojto 104:b9ad9a133dc7 1002 // Set AFE bit to enable simplified access permissions model
Kojto 104:b9ad9a133dc7 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 104:b9ad9a133dc7 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 104:b9ad9a133dc7 1005 __ISB();
Kojto 104:b9ad9a133dc7 1006 }
Kojto 104:b9ad9a133dc7 1007
Kojto 104:b9ad9a133dc7 1008 /** \brief Enable MMU
Kojto 104:b9ad9a133dc7 1009
Kojto 104:b9ad9a133dc7 1010 Enable MMU
Kojto 104:b9ad9a133dc7 1011 */
Kojto 104:b9ad9a133dc7 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 104:b9ad9a133dc7 1013 // Clear M bit 0 to disable the MMU
Kojto 104:b9ad9a133dc7 1014 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 104:b9ad9a133dc7 1015 __ISB();
Kojto 104:b9ad9a133dc7 1016 }
Kojto 104:b9ad9a133dc7 1017
Kojto 104:b9ad9a133dc7 1018 /******************************** TLB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 1019 /** \brief Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 1020
Kojto 104:b9ad9a133dc7 1021 TLBIALL. Invalidate the whole tlb
Kojto 104:b9ad9a133dc7 1022 */
Kojto 104:b9ad9a133dc7 1023
Kojto 104:b9ad9a133dc7 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 104:b9ad9a133dc7 1025 #if 1
Kojto 104:b9ad9a133dc7 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 104:b9ad9a133dc7 1027 #else
Kojto 104:b9ad9a133dc7 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 104:b9ad9a133dc7 1029 __TLBIALL = 0;
Kojto 104:b9ad9a133dc7 1030 #endif
Kojto 104:b9ad9a133dc7 1031 __DSB();
Kojto 104:b9ad9a133dc7 1032 __ISB();
Kojto 104:b9ad9a133dc7 1033 }
Kojto 104:b9ad9a133dc7 1034
Kojto 104:b9ad9a133dc7 1035 /******************************** BTB maintenance operations ************************************************/
Kojto 104:b9ad9a133dc7 1036 /** \brief Invalidate entire branch predictor array
Kojto 104:b9ad9a133dc7 1037
Kojto 104:b9ad9a133dc7 1038 BPIALL. Branch Predictor Invalidate All.
Kojto 104:b9ad9a133dc7 1039 */
Kojto 104:b9ad9a133dc7 1040
Kojto 104:b9ad9a133dc7 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 104:b9ad9a133dc7 1042 #if 1
Kojto 104:b9ad9a133dc7 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 104:b9ad9a133dc7 1044 #else
Kojto 104:b9ad9a133dc7 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 104:b9ad9a133dc7 1046 __BPIALL = 0;
Kojto 104:b9ad9a133dc7 1047 #endif
Kojto 104:b9ad9a133dc7 1048 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 1049 __ISB(); //ensure instruction fetch path sees new state
Kojto 104:b9ad9a133dc7 1050 }
Kojto 104:b9ad9a133dc7 1051
Kojto 104:b9ad9a133dc7 1052
Kojto 104:b9ad9a133dc7 1053 /******************************** L1 cache operations ******************************************************/
Kojto 104:b9ad9a133dc7 1054
Kojto 104:b9ad9a133dc7 1055 /** \brief Invalidate the whole I$
Kojto 104:b9ad9a133dc7 1056
Kojto 104:b9ad9a133dc7 1057 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 104:b9ad9a133dc7 1058 */
Kojto 104:b9ad9a133dc7 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 104:b9ad9a133dc7 1060 #if 1
Kojto 104:b9ad9a133dc7 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 104:b9ad9a133dc7 1062 #else
Kojto 104:b9ad9a133dc7 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 104:b9ad9a133dc7 1064 __ICIALLU = 0;
Kojto 104:b9ad9a133dc7 1065 #endif
Kojto 104:b9ad9a133dc7 1066 __DSB(); //ensure completion of the invalidation
Kojto 104:b9ad9a133dc7 1067 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 104:b9ad9a133dc7 1068 }
Kojto 104:b9ad9a133dc7 1069
Kojto 104:b9ad9a133dc7 1070 /** \brief Clean D$ by MVA
Kojto 104:b9ad9a133dc7 1071
Kojto 104:b9ad9a133dc7 1072 DCCMVAC. Data cache clean by MVA to PoC
Kojto 104:b9ad9a133dc7 1073 */
Kojto 104:b9ad9a133dc7 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1075 #if 1
Kojto 104:b9ad9a133dc7 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1077 #else
Kojto 104:b9ad9a133dc7 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 104:b9ad9a133dc7 1079 __DCCMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1080 #endif
Kojto 104:b9ad9a133dc7 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1082 }
Kojto 104:b9ad9a133dc7 1083
Kojto 104:b9ad9a133dc7 1084 /** \brief Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 1085
Kojto 104:b9ad9a133dc7 1086 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 1087 */
Kojto 104:b9ad9a133dc7 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1089 #if 1
Kojto 104:b9ad9a133dc7 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1091 #else
Kojto 104:b9ad9a133dc7 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 104:b9ad9a133dc7 1093 __DCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1094 #endif
Kojto 104:b9ad9a133dc7 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1096 }
Kojto 104:b9ad9a133dc7 1097
Kojto 104:b9ad9a133dc7 1098 /** \brief Clean and Invalidate D$ by MVA
Kojto 104:b9ad9a133dc7 1099
Kojto 104:b9ad9a133dc7 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 104:b9ad9a133dc7 1101 */
Kojto 104:b9ad9a133dc7 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 104:b9ad9a133dc7 1103 #if 1
Kojto 104:b9ad9a133dc7 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 104:b9ad9a133dc7 1105 #else
Kojto 104:b9ad9a133dc7 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 104:b9ad9a133dc7 1107 __DCCIMVAC = (uint32_t)va;
Kojto 104:b9ad9a133dc7 1108 #endif
Kojto 104:b9ad9a133dc7 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 104:b9ad9a133dc7 1110 }
Kojto 104:b9ad9a133dc7 1111
Kojto 104:b9ad9a133dc7 1112 /** \brief
Kojto 104:b9ad9a133dc7 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 104:b9ad9a133dc7 1114 */
Kojto 104:b9ad9a133dc7 1115
Kojto 104:b9ad9a133dc7 1116 /** \brief __v7_all_cache - helper function
Kojto 104:b9ad9a133dc7 1117
Kojto 104:b9ad9a133dc7 1118 */
Kojto 104:b9ad9a133dc7 1119
Kojto 104:b9ad9a133dc7 1120 extern void __v7_all_cache(uint32_t op);
Kojto 104:b9ad9a133dc7 1121
Kojto 104:b9ad9a133dc7 1122
Kojto 104:b9ad9a133dc7 1123 /** \brief Invalidate the whole D$
Kojto 104:b9ad9a133dc7 1124
Kojto 104:b9ad9a133dc7 1125 DCISW. Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 1126 */
Kojto 104:b9ad9a133dc7 1127
Kojto 104:b9ad9a133dc7 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1129 __v7_all_cache(0);
Kojto 104:b9ad9a133dc7 1130 }
Kojto 104:b9ad9a133dc7 1131
Kojto 104:b9ad9a133dc7 1132 /** \brief Clean the whole D$
Kojto 104:b9ad9a133dc7 1133
Kojto 104:b9ad9a133dc7 1134 DCCSW. Clean by Set/Way
Kojto 104:b9ad9a133dc7 1135 */
Kojto 104:b9ad9a133dc7 1136
Kojto 104:b9ad9a133dc7 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1138 __v7_all_cache(1);
Kojto 104:b9ad9a133dc7 1139 }
Kojto 104:b9ad9a133dc7 1140
Kojto 104:b9ad9a133dc7 1141 /** \brief Clean and invalidate the whole D$
Kojto 104:b9ad9a133dc7 1142
Kojto 104:b9ad9a133dc7 1143 DCCISW. Clean and Invalidate by Set/Way
Kojto 104:b9ad9a133dc7 1144 */
Kojto 104:b9ad9a133dc7 1145
Kojto 104:b9ad9a133dc7 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 104:b9ad9a133dc7 1147 __v7_all_cache(2);
Kojto 104:b9ad9a133dc7 1148 }
Kojto 104:b9ad9a133dc7 1149
Kojto 104:b9ad9a133dc7 1150 #include "core_ca_mmu.h"
Kojto 104:b9ad9a133dc7 1151
Kojto 104:b9ad9a133dc7 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 104:b9ad9a133dc7 1153
Kojto 104:b9ad9a133dc7 1154 #error TASKING Compiler support not implemented for Cortex-A
Kojto 104:b9ad9a133dc7 1155
Kojto 104:b9ad9a133dc7 1156 #endif
Kojto 104:b9ad9a133dc7 1157
Kojto 104:b9ad9a133dc7 1158 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 104:b9ad9a133dc7 1159
Kojto 104:b9ad9a133dc7 1160
Kojto 104:b9ad9a133dc7 1161 #endif /* __CORE_CAFUNC_H__ */