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TARGET_NUCLEO_F031K6/core_caFunc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
130:d75b3fe1f5cb 
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**************************************************************************//**
Kojto 109:9296ab0bfc11 2 * @file core_caFunc.h
Kojto 109:9296ab0bfc11 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 109:9296ab0bfc11 4 * @version V3.10
Kojto 109:9296ab0bfc11 5 * @date 30 Oct 2013
Kojto 109:9296ab0bfc11 6 *
Kojto 109:9296ab0bfc11 7 * @note
Kojto 109:9296ab0bfc11 8 *
Kojto 109:9296ab0bfc11 9 ******************************************************************************/
Kojto 109:9296ab0bfc11 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 109:9296ab0bfc11 11
Kojto 109:9296ab0bfc11 12 All rights reserved.
Kojto 109:9296ab0bfc11 13 Redistribution and use in source and binary forms, with or without
Kojto 109:9296ab0bfc11 14 modification, are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 - Redistributions of source code must retain the above copyright
Kojto 109:9296ab0bfc11 16 notice, this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 - Redistributions in binary form must reproduce the above copyright
Kojto 109:9296ab0bfc11 18 notice, this list of conditions and the following disclaimer in the
Kojto 109:9296ab0bfc11 19 documentation and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 109:9296ab0bfc11 21 to endorse or promote products derived from this software without
Kojto 109:9296ab0bfc11 22 specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 109:9296ab0bfc11 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 109:9296ab0bfc11 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 109:9296ab0bfc11 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 109:9296ab0bfc11 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 109:9296ab0bfc11 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 109:9296ab0bfc11 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 109:9296ab0bfc11 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 109:9296ab0bfc11 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 35 ---------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 36
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 #ifndef __CORE_CAFUNC_H__
Kojto 109:9296ab0bfc11 39 #define __CORE_CAFUNC_H__
Kojto 109:9296ab0bfc11 40
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 /* ########################### Core Function Access ########################### */
Kojto 109:9296ab0bfc11 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 109:9296ab0bfc11 45 @{
Kojto 109:9296ab0bfc11 46 */
Kojto 109:9296ab0bfc11 47
Kojto 109:9296ab0bfc11 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 109:9296ab0bfc11 49 /* ARM armcc specific functions */
Kojto 109:9296ab0bfc11 50
Kojto 109:9296ab0bfc11 51 #if (__ARMCC_VERSION < 400677)
Kojto 109:9296ab0bfc11 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 109:9296ab0bfc11 53 #endif
Kojto 109:9296ab0bfc11 54
Kojto 109:9296ab0bfc11 55 #define MODE_USR 0x10
Kojto 109:9296ab0bfc11 56 #define MODE_FIQ 0x11
Kojto 109:9296ab0bfc11 57 #define MODE_IRQ 0x12
Kojto 109:9296ab0bfc11 58 #define MODE_SVC 0x13
Kojto 109:9296ab0bfc11 59 #define MODE_MON 0x16
Kojto 109:9296ab0bfc11 60 #define MODE_ABT 0x17
Kojto 109:9296ab0bfc11 61 #define MODE_HYP 0x1A
Kojto 109:9296ab0bfc11 62 #define MODE_UND 0x1B
Kojto 109:9296ab0bfc11 63 #define MODE_SYS 0x1F
Kojto 109:9296ab0bfc11 64
Kojto 109:9296ab0bfc11 65 /** \brief Get APSR Register
Kojto 109:9296ab0bfc11 66
Kojto 109:9296ab0bfc11 67 This function returns the content of the APSR Register.
Kojto 109:9296ab0bfc11 68
Kojto 109:9296ab0bfc11 69 \return APSR Register value
Kojto 109:9296ab0bfc11 70 */
Kojto 109:9296ab0bfc11 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 109:9296ab0bfc11 72 {
Kojto 109:9296ab0bfc11 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 109:9296ab0bfc11 74 return(__regAPSR);
Kojto 109:9296ab0bfc11 75 }
Kojto 109:9296ab0bfc11 76
Kojto 109:9296ab0bfc11 77
Kojto 109:9296ab0bfc11 78 /** \brief Get CPSR Register
Kojto 109:9296ab0bfc11 79
Kojto 109:9296ab0bfc11 80 This function returns the content of the CPSR Register.
Kojto 109:9296ab0bfc11 81
Kojto 109:9296ab0bfc11 82 \return CPSR Register value
Kojto 109:9296ab0bfc11 83 */
Kojto 109:9296ab0bfc11 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 109:9296ab0bfc11 85 {
Kojto 109:9296ab0bfc11 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 109:9296ab0bfc11 87 return(__regCPSR);
Kojto 109:9296ab0bfc11 88 }
Kojto 109:9296ab0bfc11 89
Kojto 109:9296ab0bfc11 90 /** \brief Set Stack Pointer
Kojto 109:9296ab0bfc11 91
Kojto 109:9296ab0bfc11 92 This function assigns the given value to the current stack pointer.
Kojto 109:9296ab0bfc11 93
Kojto 109:9296ab0bfc11 94 \param [in] topOfStack Stack Pointer value to set
Kojto 109:9296ab0bfc11 95 */
Kojto 109:9296ab0bfc11 96 register uint32_t __regSP __ASM("sp");
Kojto 109:9296ab0bfc11 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 109:9296ab0bfc11 98 {
Kojto 109:9296ab0bfc11 99 __regSP = topOfStack;
Kojto 109:9296ab0bfc11 100 }
Kojto 109:9296ab0bfc11 101
Kojto 109:9296ab0bfc11 102
Kojto 109:9296ab0bfc11 103 /** \brief Get link register
Kojto 109:9296ab0bfc11 104
Kojto 109:9296ab0bfc11 105 This function returns the value of the link register
Kojto 109:9296ab0bfc11 106
Kojto 109:9296ab0bfc11 107 \return Value of link register
Kojto 109:9296ab0bfc11 108 */
Kojto 109:9296ab0bfc11 109 register uint32_t __reglr __ASM("lr");
Kojto 109:9296ab0bfc11 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 109:9296ab0bfc11 111 {
Kojto 109:9296ab0bfc11 112 return(__reglr);
Kojto 109:9296ab0bfc11 113 }
Kojto 109:9296ab0bfc11 114
Kojto 109:9296ab0bfc11 115 /** \brief Set link register
Kojto 109:9296ab0bfc11 116
Kojto 109:9296ab0bfc11 117 This function sets the value of the link register
Kojto 109:9296ab0bfc11 118
Kojto 109:9296ab0bfc11 119 \param [in] lr LR value to set
Kojto 109:9296ab0bfc11 120 */
Kojto 109:9296ab0bfc11 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 109:9296ab0bfc11 122 {
Kojto 109:9296ab0bfc11 123 __reglr = lr;
Kojto 109:9296ab0bfc11 124 }
Kojto 109:9296ab0bfc11 125
Kojto 109:9296ab0bfc11 126 /** \brief Set Process Stack Pointer
Kojto 109:9296ab0bfc11 127
Kojto 109:9296ab0bfc11 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 109:9296ab0bfc11 129
Kojto 109:9296ab0bfc11 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 109:9296ab0bfc11 131 */
Kojto 109:9296ab0bfc11 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 109:9296ab0bfc11 133 {
Kojto 109:9296ab0bfc11 134 ARM
Kojto 109:9296ab0bfc11 135 PRESERVE8
Kojto 109:9296ab0bfc11 136
Kojto 109:9296ab0bfc11 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 109:9296ab0bfc11 138 MRS R1, CPSR
Kojto 109:9296ab0bfc11 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 109:9296ab0bfc11 140 MOV SP, R0
Kojto 109:9296ab0bfc11 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 109:9296ab0bfc11 142 ISB
Kojto 109:9296ab0bfc11 143 BX LR
Kojto 109:9296ab0bfc11 144
Kojto 109:9296ab0bfc11 145 }
Kojto 109:9296ab0bfc11 146
Kojto 109:9296ab0bfc11 147 /** \brief Set User Mode
Kojto 109:9296ab0bfc11 148
Kojto 109:9296ab0bfc11 149 This function changes the processor state to User Mode
Kojto 109:9296ab0bfc11 150 */
Kojto 109:9296ab0bfc11 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 109:9296ab0bfc11 152 {
Kojto 109:9296ab0bfc11 153 ARM
Kojto 109:9296ab0bfc11 154
Kojto 109:9296ab0bfc11 155 CPS #MODE_USR
Kojto 109:9296ab0bfc11 156 BX LR
Kojto 109:9296ab0bfc11 157 }
Kojto 109:9296ab0bfc11 158
Kojto 109:9296ab0bfc11 159
Kojto 109:9296ab0bfc11 160 /** \brief Enable FIQ
Kojto 109:9296ab0bfc11 161
Kojto 109:9296ab0bfc11 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 109:9296ab0bfc11 163 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 164 */
Kojto 109:9296ab0bfc11 165 #define __enable_fault_irq __enable_fiq
Kojto 109:9296ab0bfc11 166
Kojto 109:9296ab0bfc11 167
Kojto 109:9296ab0bfc11 168 /** \brief Disable FIQ
Kojto 109:9296ab0bfc11 169
Kojto 109:9296ab0bfc11 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 109:9296ab0bfc11 171 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 172 */
Kojto 109:9296ab0bfc11 173 #define __disable_fault_irq __disable_fiq
Kojto 109:9296ab0bfc11 174
Kojto 109:9296ab0bfc11 175
Kojto 109:9296ab0bfc11 176 /** \brief Get FPSCR
Kojto 109:9296ab0bfc11 177
Kojto 109:9296ab0bfc11 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 109:9296ab0bfc11 179
Kojto 109:9296ab0bfc11 180 \return Floating Point Status/Control register value
Kojto 109:9296ab0bfc11 181 */
Kojto 109:9296ab0bfc11 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 109:9296ab0bfc11 183 {
Kojto 109:9296ab0bfc11 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 109:9296ab0bfc11 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 109:9296ab0bfc11 186 return(__regfpscr);
Kojto 109:9296ab0bfc11 187 #else
Kojto 109:9296ab0bfc11 188 return(0);
Kojto 109:9296ab0bfc11 189 #endif
Kojto 109:9296ab0bfc11 190 }
Kojto 109:9296ab0bfc11 191
Kojto 109:9296ab0bfc11 192
Kojto 109:9296ab0bfc11 193 /** \brief Set FPSCR
Kojto 109:9296ab0bfc11 194
Kojto 109:9296ab0bfc11 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 109:9296ab0bfc11 196
Kojto 109:9296ab0bfc11 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 109:9296ab0bfc11 198 */
Kojto 109:9296ab0bfc11 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 109:9296ab0bfc11 200 {
Kojto 109:9296ab0bfc11 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 109:9296ab0bfc11 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 109:9296ab0bfc11 203 __regfpscr = (fpscr);
Kojto 109:9296ab0bfc11 204 #endif
Kojto 109:9296ab0bfc11 205 }
Kojto 109:9296ab0bfc11 206
Kojto 109:9296ab0bfc11 207 /** \brief Get FPEXC
Kojto 109:9296ab0bfc11 208
Kojto 109:9296ab0bfc11 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 109:9296ab0bfc11 210
Kojto 109:9296ab0bfc11 211 \return Floating Point Exception Control register value
Kojto 109:9296ab0bfc11 212 */
Kojto 109:9296ab0bfc11 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 109:9296ab0bfc11 214 {
Kojto 109:9296ab0bfc11 215 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 109:9296ab0bfc11 217 return(__regfpexc);
Kojto 109:9296ab0bfc11 218 #else
Kojto 109:9296ab0bfc11 219 return(0);
Kojto 109:9296ab0bfc11 220 #endif
Kojto 109:9296ab0bfc11 221 }
Kojto 109:9296ab0bfc11 222
Kojto 109:9296ab0bfc11 223
Kojto 109:9296ab0bfc11 224 /** \brief Set FPEXC
Kojto 109:9296ab0bfc11 225
Kojto 109:9296ab0bfc11 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 109:9296ab0bfc11 227
Kojto 109:9296ab0bfc11 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 109:9296ab0bfc11 229 */
Kojto 109:9296ab0bfc11 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 109:9296ab0bfc11 231 {
Kojto 109:9296ab0bfc11 232 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 109:9296ab0bfc11 234 __regfpexc = (fpexc);
Kojto 109:9296ab0bfc11 235 #endif
Kojto 109:9296ab0bfc11 236 }
Kojto 109:9296ab0bfc11 237
Kojto 109:9296ab0bfc11 238 /** \brief Get CPACR
Kojto 109:9296ab0bfc11 239
Kojto 109:9296ab0bfc11 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 109:9296ab0bfc11 241
Kojto 109:9296ab0bfc11 242 \return Coprocessor Access Control register value
Kojto 109:9296ab0bfc11 243 */
Kojto 109:9296ab0bfc11 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 109:9296ab0bfc11 245 {
Kojto 109:9296ab0bfc11 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 109:9296ab0bfc11 247 return __regCPACR;
Kojto 109:9296ab0bfc11 248 }
Kojto 109:9296ab0bfc11 249
Kojto 109:9296ab0bfc11 250 /** \brief Set CPACR
Kojto 109:9296ab0bfc11 251
Kojto 109:9296ab0bfc11 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 109:9296ab0bfc11 253
Kojto 109:9296ab0bfc11 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 109:9296ab0bfc11 255 */
Kojto 109:9296ab0bfc11 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 109:9296ab0bfc11 257 {
Kojto 109:9296ab0bfc11 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 109:9296ab0bfc11 259 __regCPACR = cpacr;
Kojto 109:9296ab0bfc11 260 __ISB();
Kojto 109:9296ab0bfc11 261 }
Kojto 109:9296ab0bfc11 262
Kojto 109:9296ab0bfc11 263 /** \brief Get CBAR
Kojto 109:9296ab0bfc11 264
Kojto 109:9296ab0bfc11 265 This function returns the value of the Configuration Base Address register.
Kojto 109:9296ab0bfc11 266
Kojto 109:9296ab0bfc11 267 \return Configuration Base Address register value
Kojto 109:9296ab0bfc11 268 */
Kojto 109:9296ab0bfc11 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 109:9296ab0bfc11 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 109:9296ab0bfc11 271 return(__regCBAR);
Kojto 109:9296ab0bfc11 272 }
Kojto 109:9296ab0bfc11 273
Kojto 109:9296ab0bfc11 274 /** \brief Get TTBR0
Kojto 109:9296ab0bfc11 275
Kojto 109:9296ab0bfc11 276 This function returns the value of the Translation Table Base Register 0.
Kojto 109:9296ab0bfc11 277
Kojto 109:9296ab0bfc11 278 \return Translation Table Base Register 0 value
Kojto 109:9296ab0bfc11 279 */
Kojto 109:9296ab0bfc11 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 109:9296ab0bfc11 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 109:9296ab0bfc11 282 return(__regTTBR0);
Kojto 109:9296ab0bfc11 283 }
Kojto 109:9296ab0bfc11 284
Kojto 109:9296ab0bfc11 285 /** \brief Set TTBR0
Kojto 109:9296ab0bfc11 286
Kojto 109:9296ab0bfc11 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 109:9296ab0bfc11 288
Kojto 109:9296ab0bfc11 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 109:9296ab0bfc11 290 */
Kojto 109:9296ab0bfc11 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 109:9296ab0bfc11 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 109:9296ab0bfc11 293 __regTTBR0 = ttbr0;
Kojto 109:9296ab0bfc11 294 __ISB();
Kojto 109:9296ab0bfc11 295 }
Kojto 109:9296ab0bfc11 296
Kojto 109:9296ab0bfc11 297 /** \brief Get DACR
Kojto 109:9296ab0bfc11 298
Kojto 109:9296ab0bfc11 299 This function returns the value of the Domain Access Control Register.
Kojto 109:9296ab0bfc11 300
Kojto 109:9296ab0bfc11 301 \return Domain Access Control Register value
Kojto 109:9296ab0bfc11 302 */
Kojto 109:9296ab0bfc11 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 109:9296ab0bfc11 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 109:9296ab0bfc11 305 return(__regDACR);
Kojto 109:9296ab0bfc11 306 }
Kojto 109:9296ab0bfc11 307
Kojto 109:9296ab0bfc11 308 /** \brief Set DACR
Kojto 109:9296ab0bfc11 309
Kojto 109:9296ab0bfc11 310 This function assigns the given value to the Domain Access Control Register.
Kojto 109:9296ab0bfc11 311
Kojto 109:9296ab0bfc11 312 \param [in] dacr Domain Access Control Register value to set
Kojto 109:9296ab0bfc11 313 */
Kojto 109:9296ab0bfc11 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 109:9296ab0bfc11 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 109:9296ab0bfc11 316 __regDACR = dacr;
Kojto 109:9296ab0bfc11 317 __ISB();
Kojto 109:9296ab0bfc11 318 }
Kojto 109:9296ab0bfc11 319
Kojto 109:9296ab0bfc11 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 109:9296ab0bfc11 321
Kojto 109:9296ab0bfc11 322 /** \brief Set SCTLR
Kojto 109:9296ab0bfc11 323
Kojto 109:9296ab0bfc11 324 This function assigns the given value to the System Control Register.
Kojto 109:9296ab0bfc11 325
Kojto 109:9296ab0bfc11 326 \param [in] sctlr System Control Register value to set
Kojto 109:9296ab0bfc11 327 */
Kojto 109:9296ab0bfc11 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 109:9296ab0bfc11 329 {
Kojto 109:9296ab0bfc11 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 109:9296ab0bfc11 331 __regSCTLR = sctlr;
Kojto 109:9296ab0bfc11 332 }
Kojto 109:9296ab0bfc11 333
Kojto 109:9296ab0bfc11 334 /** \brief Get SCTLR
Kojto 109:9296ab0bfc11 335
Kojto 109:9296ab0bfc11 336 This function returns the value of the System Control Register.
Kojto 109:9296ab0bfc11 337
Kojto 109:9296ab0bfc11 338 \return System Control Register value
Kojto 109:9296ab0bfc11 339 */
Kojto 109:9296ab0bfc11 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 109:9296ab0bfc11 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 109:9296ab0bfc11 342 return(__regSCTLR);
Kojto 109:9296ab0bfc11 343 }
Kojto 109:9296ab0bfc11 344
Kojto 109:9296ab0bfc11 345 /** \brief Enable Caches
Kojto 109:9296ab0bfc11 346
Kojto 109:9296ab0bfc11 347 Enable Caches
Kojto 109:9296ab0bfc11 348 */
Kojto 109:9296ab0bfc11 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 109:9296ab0bfc11 350 // Set I bit 12 to enable I Cache
Kojto 109:9296ab0bfc11 351 // Set C bit 2 to enable D Cache
Kojto 109:9296ab0bfc11 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 109:9296ab0bfc11 353 }
Kojto 109:9296ab0bfc11 354
Kojto 109:9296ab0bfc11 355 /** \brief Disable Caches
Kojto 109:9296ab0bfc11 356
Kojto 109:9296ab0bfc11 357 Disable Caches
Kojto 109:9296ab0bfc11 358 */
Kojto 109:9296ab0bfc11 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 109:9296ab0bfc11 360 // Clear I bit 12 to disable I Cache
Kojto 109:9296ab0bfc11 361 // Clear C bit 2 to disable D Cache
Kojto 109:9296ab0bfc11 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 109:9296ab0bfc11 363 __ISB();
Kojto 109:9296ab0bfc11 364 }
Kojto 109:9296ab0bfc11 365
Kojto 109:9296ab0bfc11 366 /** \brief Enable BTAC
Kojto 109:9296ab0bfc11 367
Kojto 109:9296ab0bfc11 368 Enable BTAC
Kojto 109:9296ab0bfc11 369 */
Kojto 109:9296ab0bfc11 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 109:9296ab0bfc11 371 // Set Z bit 11 to enable branch prediction
Kojto 109:9296ab0bfc11 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 109:9296ab0bfc11 373 __ISB();
Kojto 109:9296ab0bfc11 374 }
Kojto 109:9296ab0bfc11 375
Kojto 109:9296ab0bfc11 376 /** \brief Disable BTAC
Kojto 109:9296ab0bfc11 377
Kojto 109:9296ab0bfc11 378 Disable BTAC
Kojto 109:9296ab0bfc11 379 */
Kojto 109:9296ab0bfc11 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 109:9296ab0bfc11 381 // Clear Z bit 11 to disable branch prediction
Kojto 109:9296ab0bfc11 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 109:9296ab0bfc11 383 }
Kojto 109:9296ab0bfc11 384
Kojto 109:9296ab0bfc11 385
Kojto 109:9296ab0bfc11 386 /** \brief Enable MMU
Kojto 109:9296ab0bfc11 387
Kojto 109:9296ab0bfc11 388 Enable MMU
Kojto 109:9296ab0bfc11 389 */
Kojto 109:9296ab0bfc11 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 109:9296ab0bfc11 391 // Set M bit 0 to enable the MMU
Kojto 109:9296ab0bfc11 392 // Set AFE bit to enable simplified access permissions model
Kojto 109:9296ab0bfc11 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 109:9296ab0bfc11 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 109:9296ab0bfc11 395 __ISB();
Kojto 109:9296ab0bfc11 396 }
Kojto 109:9296ab0bfc11 397
Kojto 109:9296ab0bfc11 398 /** \brief Disable MMU
Kojto 109:9296ab0bfc11 399
Kojto 109:9296ab0bfc11 400 Disable MMU
Kojto 109:9296ab0bfc11 401 */
Kojto 109:9296ab0bfc11 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 109:9296ab0bfc11 403 // Clear M bit 0 to disable the MMU
Kojto 109:9296ab0bfc11 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 109:9296ab0bfc11 405 __ISB();
Kojto 109:9296ab0bfc11 406 }
Kojto 109:9296ab0bfc11 407
Kojto 109:9296ab0bfc11 408 /******************************** TLB maintenance operations ************************************************/
Kojto 109:9296ab0bfc11 409 /** \brief Invalidate the whole tlb
Kojto 109:9296ab0bfc11 410
Kojto 109:9296ab0bfc11 411 TLBIALL. Invalidate the whole tlb
Kojto 109:9296ab0bfc11 412 */
Kojto 109:9296ab0bfc11 413
Kojto 109:9296ab0bfc11 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 109:9296ab0bfc11 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 109:9296ab0bfc11 416 __TLBIALL = 0;
Kojto 109:9296ab0bfc11 417 __DSB();
Kojto 109:9296ab0bfc11 418 __ISB();
Kojto 109:9296ab0bfc11 419 }
Kojto 109:9296ab0bfc11 420
Kojto 109:9296ab0bfc11 421 /******************************** BTB maintenance operations ************************************************/
Kojto 109:9296ab0bfc11 422 /** \brief Invalidate entire branch predictor array
Kojto 109:9296ab0bfc11 423
Kojto 109:9296ab0bfc11 424 BPIALL. Branch Predictor Invalidate All.
Kojto 109:9296ab0bfc11 425 */
Kojto 109:9296ab0bfc11 426
Kojto 109:9296ab0bfc11 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 109:9296ab0bfc11 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 109:9296ab0bfc11 429 __BPIALL = 0;
Kojto 109:9296ab0bfc11 430 __DSB(); //ensure completion of the invalidation
Kojto 109:9296ab0bfc11 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 109:9296ab0bfc11 432 }
Kojto 109:9296ab0bfc11 433
Kojto 109:9296ab0bfc11 434
Kojto 109:9296ab0bfc11 435 /******************************** L1 cache operations ******************************************************/
Kojto 109:9296ab0bfc11 436
Kojto 109:9296ab0bfc11 437 /** \brief Invalidate the whole I$
Kojto 109:9296ab0bfc11 438
Kojto 109:9296ab0bfc11 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 109:9296ab0bfc11 440 */
Kojto 109:9296ab0bfc11 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 109:9296ab0bfc11 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 109:9296ab0bfc11 443 __ICIALLU = 0;
Kojto 109:9296ab0bfc11 444 __DSB(); //ensure completion of the invalidation
Kojto 109:9296ab0bfc11 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 109:9296ab0bfc11 446 }
Kojto 109:9296ab0bfc11 447
Kojto 109:9296ab0bfc11 448 /** \brief Clean D$ by MVA
Kojto 109:9296ab0bfc11 449
Kojto 109:9296ab0bfc11 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 109:9296ab0bfc11 451 */
Kojto 109:9296ab0bfc11 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 109:9296ab0bfc11 454 __DCCMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 456 }
Kojto 109:9296ab0bfc11 457
Kojto 109:9296ab0bfc11 458 /** \brief Invalidate D$ by MVA
Kojto 109:9296ab0bfc11 459
Kojto 109:9296ab0bfc11 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 109:9296ab0bfc11 461 */
Kojto 109:9296ab0bfc11 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 109:9296ab0bfc11 464 __DCIMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 466 }
Kojto 109:9296ab0bfc11 467
Kojto 109:9296ab0bfc11 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 109:9296ab0bfc11 469
Kojto 109:9296ab0bfc11 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 109:9296ab0bfc11 471 */
Kojto 109:9296ab0bfc11 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 109:9296ab0bfc11 474 __DCCIMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 476 }
Kojto 109:9296ab0bfc11 477
Kojto 109:9296ab0bfc11 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 109:9296ab0bfc11 479
Kojto 109:9296ab0bfc11 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 109:9296ab0bfc11 481 */
Kojto 109:9296ab0bfc11 482 #pragma push
Kojto 109:9296ab0bfc11 483 #pragma arm
Kojto 109:9296ab0bfc11 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 109:9296ab0bfc11 485 ARM
Kojto 109:9296ab0bfc11 486
Kojto 109:9296ab0bfc11 487 PUSH {R4-R11}
Kojto 109:9296ab0bfc11 488
Kojto 109:9296ab0bfc11 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 109:9296ab0bfc11 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 109:9296ab0bfc11 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 109:9296ab0bfc11 492 BEQ Finished // If 0, no need to clean
Kojto 109:9296ab0bfc11 493
Kojto 109:9296ab0bfc11 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 109:9296ab0bfc11 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 109:9296ab0bfc11 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 109:9296ab0bfc11 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 109:9296ab0bfc11 498 CMP R1, #2
Kojto 109:9296ab0bfc11 499 BLT Skip // No cache or only instruction cache at this level
Kojto 109:9296ab0bfc11 500
Kojto 109:9296ab0bfc11 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 109:9296ab0bfc11 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 109:9296ab0bfc11 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 109:9296ab0bfc11 504 AND R2, R1, #7 // Extract the line length field
Kojto 109:9296ab0bfc11 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 109:9296ab0bfc11 506 LDR R4, =0x3FF
Kojto 109:9296ab0bfc11 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 109:9296ab0bfc11 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 109:9296ab0bfc11 509 LDR R7, =0x7FFF
Kojto 109:9296ab0bfc11 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 109:9296ab0bfc11 511
Kojto 109:9296ab0bfc11 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 109:9296ab0bfc11 513
Kojto 109:9296ab0bfc11 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 109:9296ab0bfc11 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 109:9296ab0bfc11 516 CMP R0, #0
Kojto 109:9296ab0bfc11 517 BNE Dccsw
Kojto 109:9296ab0bfc11 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 109:9296ab0bfc11 519 B cont
Kojto 109:9296ab0bfc11 520 Dccsw CMP R0, #1
Kojto 109:9296ab0bfc11 521 BNE Dccisw
Kojto 109:9296ab0bfc11 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 109:9296ab0bfc11 523 B cont
Kojto 109:9296ab0bfc11 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 109:9296ab0bfc11 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 109:9296ab0bfc11 526 BGE Loop3
Kojto 109:9296ab0bfc11 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 109:9296ab0bfc11 528 BGE Loop2
Kojto 109:9296ab0bfc11 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 109:9296ab0bfc11 530 CMP R3, R10
Kojto 109:9296ab0bfc11 531 BGT Loop1
Kojto 109:9296ab0bfc11 532
Kojto 109:9296ab0bfc11 533 Finished
Kojto 109:9296ab0bfc11 534 DSB
Kojto 109:9296ab0bfc11 535 POP {R4-R11}
Kojto 109:9296ab0bfc11 536 BX lr
Kojto 109:9296ab0bfc11 537
Kojto 109:9296ab0bfc11 538 }
Kojto 109:9296ab0bfc11 539 #pragma pop
Kojto 109:9296ab0bfc11 540
Kojto 109:9296ab0bfc11 541
Kojto 109:9296ab0bfc11 542 /** \brief Invalidate the whole D$
Kojto 109:9296ab0bfc11 543
Kojto 109:9296ab0bfc11 544 DCISW. Invalidate by Set/Way
Kojto 109:9296ab0bfc11 545 */
Kojto 109:9296ab0bfc11 546
Kojto 109:9296ab0bfc11 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 109:9296ab0bfc11 548 __v7_all_cache(0);
Kojto 109:9296ab0bfc11 549 }
Kojto 109:9296ab0bfc11 550
Kojto 109:9296ab0bfc11 551 /** \brief Clean the whole D$
Kojto 109:9296ab0bfc11 552
Kojto 109:9296ab0bfc11 553 DCCSW. Clean by Set/Way
Kojto 109:9296ab0bfc11 554 */
Kojto 109:9296ab0bfc11 555
Kojto 109:9296ab0bfc11 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 109:9296ab0bfc11 557 __v7_all_cache(1);
Kojto 109:9296ab0bfc11 558 }
Kojto 109:9296ab0bfc11 559
Kojto 109:9296ab0bfc11 560 /** \brief Clean and invalidate the whole D$
Kojto 109:9296ab0bfc11 561
Kojto 109:9296ab0bfc11 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 109:9296ab0bfc11 563 */
Kojto 109:9296ab0bfc11 564
Kojto 109:9296ab0bfc11 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 109:9296ab0bfc11 566 __v7_all_cache(2);
Kojto 109:9296ab0bfc11 567 }
Kojto 109:9296ab0bfc11 568
Kojto 109:9296ab0bfc11 569 #include "core_ca_mmu.h"
Kojto 109:9296ab0bfc11 570
Kojto 109:9296ab0bfc11 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 109:9296ab0bfc11 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
<> 130:d75b3fe1f5cb 814 /** \brief Clean the whole D$
<> 130:d75b3fe1f5cb 815
<> 130:d75b3fe1f5cb 816 DCCSW. Clean by Set/Way
<> 130:d75b3fe1f5cb 817 */
<> 130:d75b3fe1f5cb 818
<> 130:d75b3fe1f5cb 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 130:d75b3fe1f5cb 820 __v7_all_cache(1);
<> 130:d75b3fe1f5cb 821 }
<> 130:d75b3fe1f5cb 822
<> 130:d75b3fe1f5cb 823 /** \brief Clean and invalidate the whole D$
<> 130:d75b3fe1f5cb 824
<> 130:d75b3fe1f5cb 825 DCCISW. Clean and Invalidate by Set/Way
<> 130:d75b3fe1f5cb 826 */
<> 130:d75b3fe1f5cb 827
<> 130:d75b3fe1f5cb 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 130:d75b3fe1f5cb 829 __v7_all_cache(2);
<> 130:d75b3fe1f5cb 830 }
Kojto 121:6c34061e7c34 831 /** \brief Clean and Invalidate D$ by MVA
Kojto 121:6c34061e7c34 832
Kojto 121:6c34061e7c34 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 121:6c34061e7c34 834 */
Kojto 121:6c34061e7c34 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 121:6c34061e7c34 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 121:6c34061e7c34 837 __DMB();
Kojto 121:6c34061e7c34 838 }
Kojto 121:6c34061e7c34 839
Kojto 115:87f2f5183dfb 840 #include "core_ca_mmu.h"
Kojto 109:9296ab0bfc11 841
Kojto 109:9296ab0bfc11 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 109:9296ab0bfc11 843 /* GNU gcc specific functions */
Kojto 109:9296ab0bfc11 844
Kojto 109:9296ab0bfc11 845 #define MODE_USR 0x10
Kojto 109:9296ab0bfc11 846 #define MODE_FIQ 0x11
Kojto 109:9296ab0bfc11 847 #define MODE_IRQ 0x12
Kojto 109:9296ab0bfc11 848 #define MODE_SVC 0x13
Kojto 109:9296ab0bfc11 849 #define MODE_MON 0x16
Kojto 109:9296ab0bfc11 850 #define MODE_ABT 0x17
Kojto 109:9296ab0bfc11 851 #define MODE_HYP 0x1A
Kojto 109:9296ab0bfc11 852 #define MODE_UND 0x1B
Kojto 109:9296ab0bfc11 853 #define MODE_SYS 0x1F
Kojto 109:9296ab0bfc11 854
Kojto 109:9296ab0bfc11 855
Kojto 109:9296ab0bfc11 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 109:9296ab0bfc11 857 {
Kojto 109:9296ab0bfc11 858 __ASM volatile ("cpsie i");
Kojto 109:9296ab0bfc11 859 }
Kojto 109:9296ab0bfc11 860
Kojto 109:9296ab0bfc11 861 /** \brief Disable IRQ Interrupts
Kojto 109:9296ab0bfc11 862
Kojto 109:9296ab0bfc11 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 109:9296ab0bfc11 864 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 865 */
Kojto 109:9296ab0bfc11 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 109:9296ab0bfc11 867 {
Kojto 109:9296ab0bfc11 868 uint32_t result;
Kojto 109:9296ab0bfc11 869
Kojto 109:9296ab0bfc11 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 109:9296ab0bfc11 871 __ASM volatile ("cpsid i");
Kojto 109:9296ab0bfc11 872 return(result & 0x80);
Kojto 109:9296ab0bfc11 873 }
Kojto 109:9296ab0bfc11 874
Kojto 109:9296ab0bfc11 875
Kojto 109:9296ab0bfc11 876 /** \brief Get APSR Register
Kojto 109:9296ab0bfc11 877
Kojto 109:9296ab0bfc11 878 This function returns the content of the APSR Register.
Kojto 109:9296ab0bfc11 879
Kojto 109:9296ab0bfc11 880 \return APSR Register value
Kojto 109:9296ab0bfc11 881 */
Kojto 109:9296ab0bfc11 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 109:9296ab0bfc11 883 {
Kojto 109:9296ab0bfc11 884 #if 1
Kojto 109:9296ab0bfc11 885 register uint32_t __regAPSR;
Kojto 109:9296ab0bfc11 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 109:9296ab0bfc11 887 #else
Kojto 109:9296ab0bfc11 888 register uint32_t __regAPSR __ASM("apsr");
Kojto 109:9296ab0bfc11 889 #endif
Kojto 109:9296ab0bfc11 890 return(__regAPSR);
Kojto 109:9296ab0bfc11 891 }
Kojto 109:9296ab0bfc11 892
Kojto 109:9296ab0bfc11 893
Kojto 109:9296ab0bfc11 894 /** \brief Get CPSR Register
Kojto 109:9296ab0bfc11 895
Kojto 109:9296ab0bfc11 896 This function returns the content of the CPSR Register.
Kojto 109:9296ab0bfc11 897
Kojto 109:9296ab0bfc11 898 \return CPSR Register value
Kojto 109:9296ab0bfc11 899 */
Kojto 109:9296ab0bfc11 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 109:9296ab0bfc11 901 {
Kojto 109:9296ab0bfc11 902 #if 1
Kojto 109:9296ab0bfc11 903 register uint32_t __regCPSR;
Kojto 109:9296ab0bfc11 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 109:9296ab0bfc11 905 #else
Kojto 109:9296ab0bfc11 906 register uint32_t __regCPSR __ASM("cpsr");
Kojto 109:9296ab0bfc11 907 #endif
Kojto 109:9296ab0bfc11 908 return(__regCPSR);
Kojto 109:9296ab0bfc11 909 }
Kojto 109:9296ab0bfc11 910
Kojto 109:9296ab0bfc11 911 #if 0
Kojto 109:9296ab0bfc11 912 /** \brief Set Stack Pointer
Kojto 109:9296ab0bfc11 913
Kojto 109:9296ab0bfc11 914 This function assigns the given value to the current stack pointer.
Kojto 109:9296ab0bfc11 915
Kojto 109:9296ab0bfc11 916 \param [in] topOfStack Stack Pointer value to set
Kojto 109:9296ab0bfc11 917 */
Kojto 109:9296ab0bfc11 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 109:9296ab0bfc11 919 {
Kojto 109:9296ab0bfc11 920 register uint32_t __regSP __ASM("sp");
Kojto 109:9296ab0bfc11 921 __regSP = topOfStack;
Kojto 109:9296ab0bfc11 922 }
Kojto 109:9296ab0bfc11 923 #endif
Kojto 109:9296ab0bfc11 924
Kojto 109:9296ab0bfc11 925 /** \brief Get link register
Kojto 109:9296ab0bfc11 926
Kojto 109:9296ab0bfc11 927 This function returns the value of the link register
Kojto 109:9296ab0bfc11 928
Kojto 109:9296ab0bfc11 929 \return Value of link register
Kojto 109:9296ab0bfc11 930 */
Kojto 109:9296ab0bfc11 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 109:9296ab0bfc11 932 {
Kojto 109:9296ab0bfc11 933 register uint32_t __reglr __ASM("lr");
Kojto 109:9296ab0bfc11 934 return(__reglr);
Kojto 109:9296ab0bfc11 935 }
Kojto 109:9296ab0bfc11 936
Kojto 109:9296ab0bfc11 937 #if 0
Kojto 109:9296ab0bfc11 938 /** \brief Set link register
Kojto 109:9296ab0bfc11 939
Kojto 109:9296ab0bfc11 940 This function sets the value of the link register
Kojto 109:9296ab0bfc11 941
Kojto 109:9296ab0bfc11 942 \param [in] lr LR value to set
Kojto 109:9296ab0bfc11 943 */
Kojto 109:9296ab0bfc11 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 109:9296ab0bfc11 945 {
Kojto 109:9296ab0bfc11 946 register uint32_t __reglr __ASM("lr");
Kojto 109:9296ab0bfc11 947 __reglr = lr;
Kojto 109:9296ab0bfc11 948 }
Kojto 109:9296ab0bfc11 949 #endif
Kojto 109:9296ab0bfc11 950
Kojto 109:9296ab0bfc11 951 /** \brief Set Process Stack Pointer
Kojto 109:9296ab0bfc11 952
Kojto 109:9296ab0bfc11 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 109:9296ab0bfc11 954
Kojto 109:9296ab0bfc11 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 109:9296ab0bfc11 956 */
Kojto 109:9296ab0bfc11 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 109:9296ab0bfc11 958 {
Kojto 109:9296ab0bfc11 959 __asm__ volatile (
Kojto 109:9296ab0bfc11 960 ".ARM;"
Kojto 109:9296ab0bfc11 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 109:9296ab0bfc11 962
Kojto 109:9296ab0bfc11 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 109:9296ab0bfc11 964 "MRS R1, CPSR;"
Kojto 109:9296ab0bfc11 965 "CPS %0;" /* ;no effect in USR mode */
Kojto 109:9296ab0bfc11 966 "MOV SP, R0;"
Kojto 109:9296ab0bfc11 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 109:9296ab0bfc11 968 "ISB;"
Kojto 109:9296ab0bfc11 969 //"BX LR;"
Kojto 109:9296ab0bfc11 970 :
Kojto 109:9296ab0bfc11 971 : "i"(MODE_SYS)
Kojto 109:9296ab0bfc11 972 : "r0", "r1");
Kojto 109:9296ab0bfc11 973 return;
Kojto 109:9296ab0bfc11 974 }
Kojto 109:9296ab0bfc11 975
Kojto 109:9296ab0bfc11 976 /** \brief Set User Mode
Kojto 109:9296ab0bfc11 977
Kojto 109:9296ab0bfc11 978 This function changes the processor state to User Mode
Kojto 109:9296ab0bfc11 979 */
Kojto 109:9296ab0bfc11 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 109:9296ab0bfc11 981 {
Kojto 109:9296ab0bfc11 982 __asm__ volatile (
Kojto 109:9296ab0bfc11 983 ".ARM;"
Kojto 109:9296ab0bfc11 984
Kojto 109:9296ab0bfc11 985 "CPS %0;"
Kojto 109:9296ab0bfc11 986 //"BX LR;"
Kojto 109:9296ab0bfc11 987 :
Kojto 109:9296ab0bfc11 988 : "i"(MODE_USR)
Kojto 109:9296ab0bfc11 989 : );
Kojto 109:9296ab0bfc11 990 return;
Kojto 109:9296ab0bfc11 991 }
Kojto 109:9296ab0bfc11 992
Kojto 109:9296ab0bfc11 993
Kojto 109:9296ab0bfc11 994 /** \brief Enable FIQ
Kojto 109:9296ab0bfc11 995
Kojto 109:9296ab0bfc11 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 109:9296ab0bfc11 997 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 998 */
Kojto 109:9296ab0bfc11 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 109:9296ab0bfc11 1000
Kojto 109:9296ab0bfc11 1001
Kojto 109:9296ab0bfc11 1002 /** \brief Disable FIQ
Kojto 109:9296ab0bfc11 1003
Kojto 109:9296ab0bfc11 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 109:9296ab0bfc11 1005 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 1006 */
Kojto 109:9296ab0bfc11 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 109:9296ab0bfc11 1008
Kojto 109:9296ab0bfc11 1009
Kojto 109:9296ab0bfc11 1010 /** \brief Get FPSCR
Kojto 109:9296ab0bfc11 1011
Kojto 109:9296ab0bfc11 1012 This function returns the current value of the Floating Point Status/Control register.
Kojto 109:9296ab0bfc11 1013
Kojto 109:9296ab0bfc11 1014 \return Floating Point Status/Control register value
Kojto 109:9296ab0bfc11 1015 */
Kojto 109:9296ab0bfc11 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 109:9296ab0bfc11 1017 {
Kojto 109:9296ab0bfc11 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 109:9296ab0bfc11 1019 #if 1
Kojto 109:9296ab0bfc11 1020 uint32_t result;
Kojto 109:9296ab0bfc11 1021
Kojto 109:9296ab0bfc11 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 109:9296ab0bfc11 1023 return (result);
Kojto 109:9296ab0bfc11 1024 #else
Kojto 109:9296ab0bfc11 1025 register uint32_t __regfpscr __ASM("fpscr");
Kojto 109:9296ab0bfc11 1026 return(__regfpscr);
Kojto 109:9296ab0bfc11 1027 #endif
Kojto 109:9296ab0bfc11 1028 #else
Kojto 109:9296ab0bfc11 1029 return(0);
Kojto 109:9296ab0bfc11 1030 #endif
Kojto 109:9296ab0bfc11 1031 }
Kojto 109:9296ab0bfc11 1032
Kojto 109:9296ab0bfc11 1033
Kojto 109:9296ab0bfc11 1034 /** \brief Set FPSCR
Kojto 109:9296ab0bfc11 1035
Kojto 109:9296ab0bfc11 1036 This function assigns the given value to the Floating Point Status/Control register.
Kojto 109:9296ab0bfc11 1037
Kojto 109:9296ab0bfc11 1038 \param [in] fpscr Floating Point Status/Control value to set
Kojto 109:9296ab0bfc11 1039 */
Kojto 109:9296ab0bfc11 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 109:9296ab0bfc11 1041 {
Kojto 109:9296ab0bfc11 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 109:9296ab0bfc11 1043 #if 1
Kojto 109:9296ab0bfc11 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 109:9296ab0bfc11 1045 #else
Kojto 109:9296ab0bfc11 1046 register uint32_t __regfpscr __ASM("fpscr");
Kojto 109:9296ab0bfc11 1047 __regfpscr = (fpscr);
Kojto 109:9296ab0bfc11 1048 #endif
Kojto 109:9296ab0bfc11 1049 #endif
Kojto 109:9296ab0bfc11 1050 }
Kojto 109:9296ab0bfc11 1051
Kojto 109:9296ab0bfc11 1052 /** \brief Get FPEXC
Kojto 109:9296ab0bfc11 1053
Kojto 109:9296ab0bfc11 1054 This function returns the current value of the Floating Point Exception Control register.
Kojto 109:9296ab0bfc11 1055
Kojto 109:9296ab0bfc11 1056 \return Floating Point Exception Control register value
Kojto 109:9296ab0bfc11 1057 */
Kojto 109:9296ab0bfc11 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 109:9296ab0bfc11 1059 {
Kojto 109:9296ab0bfc11 1060 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 1061 #if 1
Kojto 109:9296ab0bfc11 1062 uint32_t result;
Kojto 109:9296ab0bfc11 1063
Kojto 109:9296ab0bfc11 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 109:9296ab0bfc11 1065 return (result);
Kojto 109:9296ab0bfc11 1066 #else
Kojto 109:9296ab0bfc11 1067 register uint32_t __regfpexc __ASM("fpexc");
Kojto 109:9296ab0bfc11 1068 return(__regfpexc);
Kojto 109:9296ab0bfc11 1069 #endif
Kojto 109:9296ab0bfc11 1070 #else
Kojto 109:9296ab0bfc11 1071 return(0);
Kojto 109:9296ab0bfc11 1072 #endif
Kojto 109:9296ab0bfc11 1073 }
Kojto 109:9296ab0bfc11 1074
Kojto 109:9296ab0bfc11 1075
Kojto 109:9296ab0bfc11 1076 /** \brief Set FPEXC
Kojto 109:9296ab0bfc11 1077
Kojto 109:9296ab0bfc11 1078 This function assigns the given value to the Floating Point Exception Control register.
Kojto 109:9296ab0bfc11 1079
Kojto 109:9296ab0bfc11 1080 \param [in] fpscr Floating Point Exception Control value to set
Kojto 109:9296ab0bfc11 1081 */
Kojto 109:9296ab0bfc11 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 109:9296ab0bfc11 1083 {
Kojto 109:9296ab0bfc11 1084 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 1085 #if 1
Kojto 109:9296ab0bfc11 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 109:9296ab0bfc11 1087 #else
Kojto 109:9296ab0bfc11 1088 register uint32_t __regfpexc __ASM("fpexc");
Kojto 109:9296ab0bfc11 1089 __regfpexc = (fpexc);
Kojto 109:9296ab0bfc11 1090 #endif
Kojto 109:9296ab0bfc11 1091 #endif
Kojto 109:9296ab0bfc11 1092 }
Kojto 109:9296ab0bfc11 1093
Kojto 109:9296ab0bfc11 1094 /** \brief Get CPACR
Kojto 109:9296ab0bfc11 1095
Kojto 109:9296ab0bfc11 1096 This function returns the current value of the Coprocessor Access Control register.
Kojto 109:9296ab0bfc11 1097
Kojto 109:9296ab0bfc11 1098 \return Coprocessor Access Control register value
Kojto 109:9296ab0bfc11 1099 */
Kojto 109:9296ab0bfc11 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 109:9296ab0bfc11 1101 {
Kojto 109:9296ab0bfc11 1102 #if 1
Kojto 109:9296ab0bfc11 1103 register uint32_t __regCPACR;
Kojto 109:9296ab0bfc11 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 109:9296ab0bfc11 1105 #else
Kojto 109:9296ab0bfc11 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 109:9296ab0bfc11 1107 #endif
Kojto 109:9296ab0bfc11 1108 return __regCPACR;
Kojto 109:9296ab0bfc11 1109 }
Kojto 109:9296ab0bfc11 1110
Kojto 109:9296ab0bfc11 1111 /** \brief Set CPACR
Kojto 109:9296ab0bfc11 1112
Kojto 109:9296ab0bfc11 1113 This function assigns the given value to the Coprocessor Access Control register.
Kojto 109:9296ab0bfc11 1114
Kojto 109:9296ab0bfc11 1115 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 109:9296ab0bfc11 1116 */
Kojto 109:9296ab0bfc11 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 109:9296ab0bfc11 1118 {
Kojto 109:9296ab0bfc11 1119 #if 1
Kojto 109:9296ab0bfc11 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 109:9296ab0bfc11 1121 #else
Kojto 109:9296ab0bfc11 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 109:9296ab0bfc11 1123 __regCPACR = cpacr;
Kojto 109:9296ab0bfc11 1124 #endif
Kojto 109:9296ab0bfc11 1125 __ISB();
Kojto 109:9296ab0bfc11 1126 }
Kojto 109:9296ab0bfc11 1127
Kojto 109:9296ab0bfc11 1128 /** \brief Get CBAR
Kojto 109:9296ab0bfc11 1129
Kojto 109:9296ab0bfc11 1130 This function returns the value of the Configuration Base Address register.
Kojto 109:9296ab0bfc11 1131
Kojto 109:9296ab0bfc11 1132 \return Configuration Base Address register value
Kojto 109:9296ab0bfc11 1133 */
Kojto 109:9296ab0bfc11 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 109:9296ab0bfc11 1135 #if 1
Kojto 109:9296ab0bfc11 1136 register uint32_t __regCBAR;
Kojto 109:9296ab0bfc11 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 109:9296ab0bfc11 1138 #else
Kojto 109:9296ab0bfc11 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 109:9296ab0bfc11 1140 #endif
Kojto 109:9296ab0bfc11 1141 return(__regCBAR);
Kojto 109:9296ab0bfc11 1142 }
Kojto 109:9296ab0bfc11 1143
Kojto 109:9296ab0bfc11 1144 /** \brief Get TTBR0
Kojto 109:9296ab0bfc11 1145
Kojto 109:9296ab0bfc11 1146 This function returns the value of the Translation Table Base Register 0.
Kojto 109:9296ab0bfc11 1147
Kojto 109:9296ab0bfc11 1148 \return Translation Table Base Register 0 value
Kojto 109:9296ab0bfc11 1149 */
Kojto 109:9296ab0bfc11 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 109:9296ab0bfc11 1151 #if 1
Kojto 109:9296ab0bfc11 1152 register uint32_t __regTTBR0;
Kojto 109:9296ab0bfc11 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 109:9296ab0bfc11 1154 #else
Kojto 109:9296ab0bfc11 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 109:9296ab0bfc11 1156 #endif
Kojto 109:9296ab0bfc11 1157 return(__regTTBR0);
Kojto 109:9296ab0bfc11 1158 }
Kojto 109:9296ab0bfc11 1159
Kojto 109:9296ab0bfc11 1160 /** \brief Set TTBR0
Kojto 109:9296ab0bfc11 1161
Kojto 109:9296ab0bfc11 1162 This function assigns the given value to the Translation Table Base Register 0.
Kojto 109:9296ab0bfc11 1163
Kojto 109:9296ab0bfc11 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 109:9296ab0bfc11 1165 */
Kojto 109:9296ab0bfc11 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 109:9296ab0bfc11 1167 #if 1
Kojto 109:9296ab0bfc11 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 109:9296ab0bfc11 1169 #else
Kojto 109:9296ab0bfc11 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 109:9296ab0bfc11 1171 __regTTBR0 = ttbr0;
Kojto 109:9296ab0bfc11 1172 #endif
Kojto 109:9296ab0bfc11 1173 __ISB();
Kojto 109:9296ab0bfc11 1174 }
Kojto 109:9296ab0bfc11 1175
Kojto 109:9296ab0bfc11 1176 /** \brief Get DACR
Kojto 109:9296ab0bfc11 1177
Kojto 109:9296ab0bfc11 1178 This function returns the value of the Domain Access Control Register.
Kojto 109:9296ab0bfc11 1179
Kojto 109:9296ab0bfc11 1180 \return Domain Access Control Register value
Kojto 109:9296ab0bfc11 1181 */
Kojto 109:9296ab0bfc11 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 109:9296ab0bfc11 1183 #if 1
Kojto 109:9296ab0bfc11 1184 register uint32_t __regDACR;
Kojto 109:9296ab0bfc11 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 109:9296ab0bfc11 1186 #else
Kojto 109:9296ab0bfc11 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 109:9296ab0bfc11 1188 #endif
Kojto 109:9296ab0bfc11 1189 return(__regDACR);
Kojto 109:9296ab0bfc11 1190 }
Kojto 109:9296ab0bfc11 1191
Kojto 109:9296ab0bfc11 1192 /** \brief Set DACR
Kojto 109:9296ab0bfc11 1193
Kojto 109:9296ab0bfc11 1194 This function assigns the given value to the Domain Access Control Register.
Kojto 109:9296ab0bfc11 1195
Kojto 109:9296ab0bfc11 1196 \param [in] dacr Domain Access Control Register value to set
Kojto 109:9296ab0bfc11 1197 */
Kojto 109:9296ab0bfc11 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 109:9296ab0bfc11 1199 #if 1
Kojto 109:9296ab0bfc11 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 109:9296ab0bfc11 1201 #else
Kojto 109:9296ab0bfc11 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 109:9296ab0bfc11 1203 __regDACR = dacr;
Kojto 109:9296ab0bfc11 1204 #endif
Kojto 109:9296ab0bfc11 1205 __ISB();
Kojto 109:9296ab0bfc11 1206 }
Kojto 109:9296ab0bfc11 1207
Kojto 109:9296ab0bfc11 1208 /******************************** Cache and BTAC enable ****************************************************/
Kojto 109:9296ab0bfc11 1209
Kojto 109:9296ab0bfc11 1210 /** \brief Set SCTLR
Kojto 109:9296ab0bfc11 1211
Kojto 109:9296ab0bfc11 1212 This function assigns the given value to the System Control Register.
Kojto 109:9296ab0bfc11 1213
Kojto 109:9296ab0bfc11 1214 \param [in] sctlr System Control Register value to set
Kojto 109:9296ab0bfc11 1215 */
Kojto 109:9296ab0bfc11 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 109:9296ab0bfc11 1217 {
Kojto 109:9296ab0bfc11 1218 #if 1
Kojto 109:9296ab0bfc11 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 109:9296ab0bfc11 1220 #else
Kojto 109:9296ab0bfc11 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 109:9296ab0bfc11 1222 __regSCTLR = sctlr;
Kojto 109:9296ab0bfc11 1223 #endif
Kojto 109:9296ab0bfc11 1224 }
Kojto 109:9296ab0bfc11 1225
Kojto 109:9296ab0bfc11 1226 /** \brief Get SCTLR
Kojto 109:9296ab0bfc11 1227
Kojto 109:9296ab0bfc11 1228 This function returns the value of the System Control Register.
Kojto 109:9296ab0bfc11 1229
Kojto 109:9296ab0bfc11 1230 \return System Control Register value
Kojto 109:9296ab0bfc11 1231 */
Kojto 109:9296ab0bfc11 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 109:9296ab0bfc11 1233 #if 1
Kojto 109:9296ab0bfc11 1234 register uint32_t __regSCTLR;
Kojto 109:9296ab0bfc11 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 109:9296ab0bfc11 1236 #else
Kojto 109:9296ab0bfc11 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 109:9296ab0bfc11 1238 #endif
Kojto 109:9296ab0bfc11 1239 return(__regSCTLR);
Kojto 109:9296ab0bfc11 1240 }
Kojto 109:9296ab0bfc11 1241
Kojto 109:9296ab0bfc11 1242 /** \brief Enable Caches
Kojto 109:9296ab0bfc11 1243
Kojto 109:9296ab0bfc11 1244 Enable Caches
Kojto 109:9296ab0bfc11 1245 */
Kojto 109:9296ab0bfc11 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 109:9296ab0bfc11 1247 // Set I bit 12 to enable I Cache
Kojto 109:9296ab0bfc11 1248 // Set C bit 2 to enable D Cache
Kojto 109:9296ab0bfc11 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 109:9296ab0bfc11 1250 }
Kojto 109:9296ab0bfc11 1251
Kojto 109:9296ab0bfc11 1252 /** \brief Disable Caches
Kojto 109:9296ab0bfc11 1253
Kojto 109:9296ab0bfc11 1254 Disable Caches
Kojto 109:9296ab0bfc11 1255 */
Kojto 109:9296ab0bfc11 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 109:9296ab0bfc11 1257 // Clear I bit 12 to disable I Cache
Kojto 109:9296ab0bfc11 1258 // Clear C bit 2 to disable D Cache
Kojto 109:9296ab0bfc11 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 109:9296ab0bfc11 1260 __ISB();
Kojto 109:9296ab0bfc11 1261 }
Kojto 109:9296ab0bfc11 1262
Kojto 109:9296ab0bfc11 1263 /** \brief Enable BTAC
Kojto 109:9296ab0bfc11 1264
Kojto 109:9296ab0bfc11 1265 Enable BTAC
Kojto 109:9296ab0bfc11 1266 */
Kojto 109:9296ab0bfc11 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 109:9296ab0bfc11 1268 // Set Z bit 11 to enable branch prediction
Kojto 109:9296ab0bfc11 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 109:9296ab0bfc11 1270 __ISB();
Kojto 109:9296ab0bfc11 1271 }
Kojto 109:9296ab0bfc11 1272
Kojto 109:9296ab0bfc11 1273 /** \brief Disable BTAC
Kojto 109:9296ab0bfc11 1274
Kojto 109:9296ab0bfc11 1275 Disable BTAC
Kojto 109:9296ab0bfc11 1276 */
Kojto 109:9296ab0bfc11 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 109:9296ab0bfc11 1278 // Clear Z bit 11 to disable branch prediction
Kojto 109:9296ab0bfc11 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 109:9296ab0bfc11 1280 }
Kojto 109:9296ab0bfc11 1281
Kojto 109:9296ab0bfc11 1282
Kojto 109:9296ab0bfc11 1283 /** \brief Enable MMU
Kojto 109:9296ab0bfc11 1284
Kojto 109:9296ab0bfc11 1285 Enable MMU
Kojto 109:9296ab0bfc11 1286 */
Kojto 109:9296ab0bfc11 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 109:9296ab0bfc11 1288 // Set M bit 0 to enable the MMU
Kojto 109:9296ab0bfc11 1289 // Set AFE bit to enable simplified access permissions model
Kojto 109:9296ab0bfc11 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 109:9296ab0bfc11 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 109:9296ab0bfc11 1292 __ISB();
Kojto 109:9296ab0bfc11 1293 }
Kojto 109:9296ab0bfc11 1294
Kojto 109:9296ab0bfc11 1295 /** \brief Disable MMU
Kojto 109:9296ab0bfc11 1296
Kojto 109:9296ab0bfc11 1297 Disable MMU
Kojto 109:9296ab0bfc11 1298 */
Kojto 109:9296ab0bfc11 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 109:9296ab0bfc11 1300 // Clear M bit 0 to disable the MMU
Kojto 109:9296ab0bfc11 1301 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 109:9296ab0bfc11 1302 __ISB();
Kojto 109:9296ab0bfc11 1303 }
Kojto 109:9296ab0bfc11 1304
Kojto 109:9296ab0bfc11 1305 /******************************** TLB maintenance operations ************************************************/
Kojto 109:9296ab0bfc11 1306 /** \brief Invalidate the whole tlb
Kojto 109:9296ab0bfc11 1307
Kojto 109:9296ab0bfc11 1308 TLBIALL. Invalidate the whole tlb
Kojto 109:9296ab0bfc11 1309 */
Kojto 109:9296ab0bfc11 1310
Kojto 109:9296ab0bfc11 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 109:9296ab0bfc11 1312 #if 1
Kojto 109:9296ab0bfc11 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 109:9296ab0bfc11 1314 #else
Kojto 109:9296ab0bfc11 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 109:9296ab0bfc11 1316 __TLBIALL = 0;
Kojto 109:9296ab0bfc11 1317 #endif
Kojto 109:9296ab0bfc11 1318 __DSB();
Kojto 109:9296ab0bfc11 1319 __ISB();
Kojto 109:9296ab0bfc11 1320 }
Kojto 109:9296ab0bfc11 1321
Kojto 109:9296ab0bfc11 1322 /******************************** BTB maintenance operations ************************************************/
Kojto 109:9296ab0bfc11 1323 /** \brief Invalidate entire branch predictor array
Kojto 109:9296ab0bfc11 1324
Kojto 109:9296ab0bfc11 1325 BPIALL. Branch Predictor Invalidate All.
Kojto 109:9296ab0bfc11 1326 */
Kojto 109:9296ab0bfc11 1327
Kojto 109:9296ab0bfc11 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 109:9296ab0bfc11 1329 #if 1
Kojto 109:9296ab0bfc11 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 109:9296ab0bfc11 1331 #else
Kojto 109:9296ab0bfc11 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 109:9296ab0bfc11 1333 __BPIALL = 0;
Kojto 109:9296ab0bfc11 1334 #endif
Kojto 109:9296ab0bfc11 1335 __DSB(); //ensure completion of the invalidation
Kojto 109:9296ab0bfc11 1336 __ISB(); //ensure instruction fetch path sees new state
Kojto 109:9296ab0bfc11 1337 }
Kojto 109:9296ab0bfc11 1338
Kojto 109:9296ab0bfc11 1339
Kojto 109:9296ab0bfc11 1340 /******************************** L1 cache operations ******************************************************/
Kojto 109:9296ab0bfc11 1341
Kojto 109:9296ab0bfc11 1342 /** \brief Invalidate the whole I$
Kojto 109:9296ab0bfc11 1343
Kojto 109:9296ab0bfc11 1344 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 109:9296ab0bfc11 1345 */
Kojto 109:9296ab0bfc11 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 109:9296ab0bfc11 1347 #if 1
Kojto 109:9296ab0bfc11 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 109:9296ab0bfc11 1349 #else
Kojto 109:9296ab0bfc11 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 109:9296ab0bfc11 1351 __ICIALLU = 0;
Kojto 109:9296ab0bfc11 1352 #endif
Kojto 109:9296ab0bfc11 1353 __DSB(); //ensure completion of the invalidation
Kojto 109:9296ab0bfc11 1354 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 109:9296ab0bfc11 1355 }
Kojto 109:9296ab0bfc11 1356
Kojto 109:9296ab0bfc11 1357 /** \brief Clean D$ by MVA
Kojto 109:9296ab0bfc11 1358
Kojto 109:9296ab0bfc11 1359 DCCMVAC. Data cache clean by MVA to PoC
Kojto 109:9296ab0bfc11 1360 */
Kojto 109:9296ab0bfc11 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 1362 #if 1
Kojto 109:9296ab0bfc11 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 109:9296ab0bfc11 1364 #else
Kojto 109:9296ab0bfc11 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 109:9296ab0bfc11 1366 __DCCMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 1367 #endif
Kojto 109:9296ab0bfc11 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 1369 }
Kojto 109:9296ab0bfc11 1370
Kojto 109:9296ab0bfc11 1371 /** \brief Invalidate D$ by MVA
Kojto 109:9296ab0bfc11 1372
Kojto 109:9296ab0bfc11 1373 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 109:9296ab0bfc11 1374 */
Kojto 109:9296ab0bfc11 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 1376 #if 1
Kojto 109:9296ab0bfc11 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 109:9296ab0bfc11 1378 #else
Kojto 109:9296ab0bfc11 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 109:9296ab0bfc11 1380 __DCIMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 1381 #endif
Kojto 109:9296ab0bfc11 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 1383 }
Kojto 109:9296ab0bfc11 1384
Kojto 109:9296ab0bfc11 1385 /** \brief Clean and Invalidate D$ by MVA
Kojto 109:9296ab0bfc11 1386
Kojto 109:9296ab0bfc11 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 109:9296ab0bfc11 1388 */
Kojto 109:9296ab0bfc11 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 1390 #if 1
Kojto 109:9296ab0bfc11 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 109:9296ab0bfc11 1392 #else
Kojto 109:9296ab0bfc11 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 109:9296ab0bfc11 1394 __DCCIMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 1395 #endif
Kojto 109:9296ab0bfc11 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 1397 }
Kojto 109:9296ab0bfc11 1398
Kojto 109:9296ab0bfc11 1399 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 109:9296ab0bfc11 1400
Kojto 109:9296ab0bfc11 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 109:9296ab0bfc11 1402 */
Kojto 109:9296ab0bfc11 1403 extern void __v7_all_cache(uint32_t op);
Kojto 109:9296ab0bfc11 1404
Kojto 109:9296ab0bfc11 1405
Kojto 109:9296ab0bfc11 1406 /** \brief Invalidate the whole D$
Kojto 109:9296ab0bfc11 1407
Kojto 109:9296ab0bfc11 1408 DCISW. Invalidate by Set/Way
Kojto 109:9296ab0bfc11 1409 */
Kojto 109:9296ab0bfc11 1410
Kojto 109:9296ab0bfc11 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 109:9296ab0bfc11 1412 __v7_all_cache(0);
Kojto 109:9296ab0bfc11 1413 }
Kojto 109:9296ab0bfc11 1414
Kojto 109:9296ab0bfc11 1415 /** \brief Clean the whole D$
Kojto 109:9296ab0bfc11 1416
Kojto 109:9296ab0bfc11 1417 DCCSW. Clean by Set/Way
Kojto 109:9296ab0bfc11 1418 */
Kojto 109:9296ab0bfc11 1419
Kojto 109:9296ab0bfc11 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 109:9296ab0bfc11 1421 __v7_all_cache(1);
Kojto 109:9296ab0bfc11 1422 }
Kojto 109:9296ab0bfc11 1423
Kojto 109:9296ab0bfc11 1424 /** \brief Clean and invalidate the whole D$
Kojto 109:9296ab0bfc11 1425
Kojto 109:9296ab0bfc11 1426 DCCISW. Clean and Invalidate by Set/Way
Kojto 109:9296ab0bfc11 1427 */
Kojto 109:9296ab0bfc11 1428
Kojto 109:9296ab0bfc11 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 109:9296ab0bfc11 1430 __v7_all_cache(2);
Kojto 109:9296ab0bfc11 1431 }
Kojto 109:9296ab0bfc11 1432
Kojto 109:9296ab0bfc11 1433 #include "core_ca_mmu.h"
Kojto 109:9296ab0bfc11 1434
Kojto 109:9296ab0bfc11 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 109:9296ab0bfc11 1436
Kojto 109:9296ab0bfc11 1437 #error TASKING Compiler support not implemented for Cortex-A
Kojto 109:9296ab0bfc11 1438
Kojto 109:9296ab0bfc11 1439 #endif
Kojto 109:9296ab0bfc11 1440
Kojto 109:9296ab0bfc11 1441 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 109:9296ab0bfc11 1442
Kojto 109:9296ab0bfc11 1443
Kojto 109:9296ab0bfc11 1444 #endif /* __CORE_CAFUNC_H__ */