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TARGET_NUCLEO_F031K6/core_caFunc.h@109:9296ab0bfc11, 2015-10-29 (annotated)

Committer:
Kojto
Date:
Thu Oct 29 08:40:18 2015 +0000
Revision:
109:9296ab0bfc11
Child:
115:87f2f5183dfb
Release 109  of the mbed library



Changes:

- new platforms - NUCLEO_F042K6, WIZNWIKI_W7500ECO

- MTS targets - bootloaders update to 0.1.1

- STM F7 - RTC enable fixes

- STM F4 - i2c pending stop before start fix

- STM all targets - analogout normalization fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**************************************************************************//**
Kojto 109:9296ab0bfc11 2 * @file core_caFunc.h
Kojto 109:9296ab0bfc11 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 109:9296ab0bfc11 4 * @version V3.10
Kojto 109:9296ab0bfc11 5 * @date 30 Oct 2013
Kojto 109:9296ab0bfc11 6 *
Kojto 109:9296ab0bfc11 7 * @note
Kojto 109:9296ab0bfc11 8 *
Kojto 109:9296ab0bfc11 9 ******************************************************************************/
Kojto 109:9296ab0bfc11 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 109:9296ab0bfc11 11
Kojto 109:9296ab0bfc11 12 All rights reserved.
Kojto 109:9296ab0bfc11 13 Redistribution and use in source and binary forms, with or without
Kojto 109:9296ab0bfc11 14 modification, are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 - Redistributions of source code must retain the above copyright
Kojto 109:9296ab0bfc11 16 notice, this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 - Redistributions in binary form must reproduce the above copyright
Kojto 109:9296ab0bfc11 18 notice, this list of conditions and the following disclaimer in the
Kojto 109:9296ab0bfc11 19 documentation and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 109:9296ab0bfc11 21 to endorse or promote products derived from this software without
Kojto 109:9296ab0bfc11 22 specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 109:9296ab0bfc11 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 109:9296ab0bfc11 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 109:9296ab0bfc11 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 109:9296ab0bfc11 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 109:9296ab0bfc11 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 109:9296ab0bfc11 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 109:9296ab0bfc11 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 109:9296ab0bfc11 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 35 ---------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 36
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 #ifndef __CORE_CAFUNC_H__
Kojto 109:9296ab0bfc11 39 #define __CORE_CAFUNC_H__
Kojto 109:9296ab0bfc11 40
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 /* ########################### Core Function Access ########################### */
Kojto 109:9296ab0bfc11 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 109:9296ab0bfc11 45 @{
Kojto 109:9296ab0bfc11 46 */
Kojto 109:9296ab0bfc11 47
Kojto 109:9296ab0bfc11 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 109:9296ab0bfc11 49 /* ARM armcc specific functions */
Kojto 109:9296ab0bfc11 50
Kojto 109:9296ab0bfc11 51 #if (__ARMCC_VERSION < 400677)
Kojto 109:9296ab0bfc11 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 109:9296ab0bfc11 53 #endif
Kojto 109:9296ab0bfc11 54
Kojto 109:9296ab0bfc11 55 #define MODE_USR 0x10
Kojto 109:9296ab0bfc11 56 #define MODE_FIQ 0x11
Kojto 109:9296ab0bfc11 57 #define MODE_IRQ 0x12
Kojto 109:9296ab0bfc11 58 #define MODE_SVC 0x13
Kojto 109:9296ab0bfc11 59 #define MODE_MON 0x16
Kojto 109:9296ab0bfc11 60 #define MODE_ABT 0x17
Kojto 109:9296ab0bfc11 61 #define MODE_HYP 0x1A
Kojto 109:9296ab0bfc11 62 #define MODE_UND 0x1B
Kojto 109:9296ab0bfc11 63 #define MODE_SYS 0x1F
Kojto 109:9296ab0bfc11 64
Kojto 109:9296ab0bfc11 65 /** \brief Get APSR Register
Kojto 109:9296ab0bfc11 66
Kojto 109:9296ab0bfc11 67 This function returns the content of the APSR Register.
Kojto 109:9296ab0bfc11 68
Kojto 109:9296ab0bfc11 69 \return APSR Register value
Kojto 109:9296ab0bfc11 70 */
Kojto 109:9296ab0bfc11 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 109:9296ab0bfc11 72 {
Kojto 109:9296ab0bfc11 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 109:9296ab0bfc11 74 return(__regAPSR);
Kojto 109:9296ab0bfc11 75 }
Kojto 109:9296ab0bfc11 76
Kojto 109:9296ab0bfc11 77
Kojto 109:9296ab0bfc11 78 /** \brief Get CPSR Register
Kojto 109:9296ab0bfc11 79
Kojto 109:9296ab0bfc11 80 This function returns the content of the CPSR Register.
Kojto 109:9296ab0bfc11 81
Kojto 109:9296ab0bfc11 82 \return CPSR Register value
Kojto 109:9296ab0bfc11 83 */
Kojto 109:9296ab0bfc11 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 109:9296ab0bfc11 85 {
Kojto 109:9296ab0bfc11 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 109:9296ab0bfc11 87 return(__regCPSR);
Kojto 109:9296ab0bfc11 88 }
Kojto 109:9296ab0bfc11 89
Kojto 109:9296ab0bfc11 90 /** \brief Set Stack Pointer
Kojto 109:9296ab0bfc11 91
Kojto 109:9296ab0bfc11 92 This function assigns the given value to the current stack pointer.
Kojto 109:9296ab0bfc11 93
Kojto 109:9296ab0bfc11 94 \param [in] topOfStack Stack Pointer value to set
Kojto 109:9296ab0bfc11 95 */
Kojto 109:9296ab0bfc11 96 register uint32_t __regSP __ASM("sp");
Kojto 109:9296ab0bfc11 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 109:9296ab0bfc11 98 {
Kojto 109:9296ab0bfc11 99 __regSP = topOfStack;
Kojto 109:9296ab0bfc11 100 }
Kojto 109:9296ab0bfc11 101
Kojto 109:9296ab0bfc11 102
Kojto 109:9296ab0bfc11 103 /** \brief Get link register
Kojto 109:9296ab0bfc11 104
Kojto 109:9296ab0bfc11 105 This function returns the value of the link register
Kojto 109:9296ab0bfc11 106
Kojto 109:9296ab0bfc11 107 \return Value of link register
Kojto 109:9296ab0bfc11 108 */
Kojto 109:9296ab0bfc11 109 register uint32_t __reglr __ASM("lr");
Kojto 109:9296ab0bfc11 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 109:9296ab0bfc11 111 {
Kojto 109:9296ab0bfc11 112 return(__reglr);
Kojto 109:9296ab0bfc11 113 }
Kojto 109:9296ab0bfc11 114
Kojto 109:9296ab0bfc11 115 /** \brief Set link register
Kojto 109:9296ab0bfc11 116
Kojto 109:9296ab0bfc11 117 This function sets the value of the link register
Kojto 109:9296ab0bfc11 118
Kojto 109:9296ab0bfc11 119 \param [in] lr LR value to set
Kojto 109:9296ab0bfc11 120 */
Kojto 109:9296ab0bfc11 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 109:9296ab0bfc11 122 {
Kojto 109:9296ab0bfc11 123 __reglr = lr;
Kojto 109:9296ab0bfc11 124 }
Kojto 109:9296ab0bfc11 125
Kojto 109:9296ab0bfc11 126 /** \brief Set Process Stack Pointer
Kojto 109:9296ab0bfc11 127
Kojto 109:9296ab0bfc11 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 109:9296ab0bfc11 129
Kojto 109:9296ab0bfc11 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 109:9296ab0bfc11 131 */
Kojto 109:9296ab0bfc11 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 109:9296ab0bfc11 133 {
Kojto 109:9296ab0bfc11 134 ARM
Kojto 109:9296ab0bfc11 135 PRESERVE8
Kojto 109:9296ab0bfc11 136
Kojto 109:9296ab0bfc11 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 109:9296ab0bfc11 138 MRS R1, CPSR
Kojto 109:9296ab0bfc11 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 109:9296ab0bfc11 140 MOV SP, R0
Kojto 109:9296ab0bfc11 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 109:9296ab0bfc11 142 ISB
Kojto 109:9296ab0bfc11 143 BX LR
Kojto 109:9296ab0bfc11 144
Kojto 109:9296ab0bfc11 145 }
Kojto 109:9296ab0bfc11 146
Kojto 109:9296ab0bfc11 147 /** \brief Set User Mode
Kojto 109:9296ab0bfc11 148
Kojto 109:9296ab0bfc11 149 This function changes the processor state to User Mode
Kojto 109:9296ab0bfc11 150 */
Kojto 109:9296ab0bfc11 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 109:9296ab0bfc11 152 {
Kojto 109:9296ab0bfc11 153 ARM
Kojto 109:9296ab0bfc11 154
Kojto 109:9296ab0bfc11 155 CPS #MODE_USR
Kojto 109:9296ab0bfc11 156 BX LR
Kojto 109:9296ab0bfc11 157 }
Kojto 109:9296ab0bfc11 158
Kojto 109:9296ab0bfc11 159
Kojto 109:9296ab0bfc11 160 /** \brief Enable FIQ
Kojto 109:9296ab0bfc11 161
Kojto 109:9296ab0bfc11 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 109:9296ab0bfc11 163 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 164 */
Kojto 109:9296ab0bfc11 165 #define __enable_fault_irq __enable_fiq
Kojto 109:9296ab0bfc11 166
Kojto 109:9296ab0bfc11 167
Kojto 109:9296ab0bfc11 168 /** \brief Disable FIQ
Kojto 109:9296ab0bfc11 169
Kojto 109:9296ab0bfc11 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 109:9296ab0bfc11 171 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 172 */
Kojto 109:9296ab0bfc11 173 #define __disable_fault_irq __disable_fiq
Kojto 109:9296ab0bfc11 174
Kojto 109:9296ab0bfc11 175
Kojto 109:9296ab0bfc11 176 /** \brief Get FPSCR
Kojto 109:9296ab0bfc11 177
Kojto 109:9296ab0bfc11 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 109:9296ab0bfc11 179
Kojto 109:9296ab0bfc11 180 \return Floating Point Status/Control register value
Kojto 109:9296ab0bfc11 181 */
Kojto 109:9296ab0bfc11 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 109:9296ab0bfc11 183 {
Kojto 109:9296ab0bfc11 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 109:9296ab0bfc11 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 109:9296ab0bfc11 186 return(__regfpscr);
Kojto 109:9296ab0bfc11 187 #else
Kojto 109:9296ab0bfc11 188 return(0);
Kojto 109:9296ab0bfc11 189 #endif
Kojto 109:9296ab0bfc11 190 }
Kojto 109:9296ab0bfc11 191
Kojto 109:9296ab0bfc11 192
Kojto 109:9296ab0bfc11 193 /** \brief Set FPSCR
Kojto 109:9296ab0bfc11 194
Kojto 109:9296ab0bfc11 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 109:9296ab0bfc11 196
Kojto 109:9296ab0bfc11 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 109:9296ab0bfc11 198 */
Kojto 109:9296ab0bfc11 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 109:9296ab0bfc11 200 {
Kojto 109:9296ab0bfc11 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 109:9296ab0bfc11 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 109:9296ab0bfc11 203 __regfpscr = (fpscr);
Kojto 109:9296ab0bfc11 204 #endif
Kojto 109:9296ab0bfc11 205 }
Kojto 109:9296ab0bfc11 206
Kojto 109:9296ab0bfc11 207 /** \brief Get FPEXC
Kojto 109:9296ab0bfc11 208
Kojto 109:9296ab0bfc11 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 109:9296ab0bfc11 210
Kojto 109:9296ab0bfc11 211 \return Floating Point Exception Control register value
Kojto 109:9296ab0bfc11 212 */
Kojto 109:9296ab0bfc11 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 109:9296ab0bfc11 214 {
Kojto 109:9296ab0bfc11 215 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 109:9296ab0bfc11 217 return(__regfpexc);
Kojto 109:9296ab0bfc11 218 #else
Kojto 109:9296ab0bfc11 219 return(0);
Kojto 109:9296ab0bfc11 220 #endif
Kojto 109:9296ab0bfc11 221 }
Kojto 109:9296ab0bfc11 222
Kojto 109:9296ab0bfc11 223
Kojto 109:9296ab0bfc11 224 /** \brief Set FPEXC
Kojto 109:9296ab0bfc11 225
Kojto 109:9296ab0bfc11 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 109:9296ab0bfc11 227
Kojto 109:9296ab0bfc11 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 109:9296ab0bfc11 229 */
Kojto 109:9296ab0bfc11 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 109:9296ab0bfc11 231 {
Kojto 109:9296ab0bfc11 232 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 109:9296ab0bfc11 234 __regfpexc = (fpexc);
Kojto 109:9296ab0bfc11 235 #endif
Kojto 109:9296ab0bfc11 236 }
Kojto 109:9296ab0bfc11 237
Kojto 109:9296ab0bfc11 238 /** \brief Get CPACR
Kojto 109:9296ab0bfc11 239
Kojto 109:9296ab0bfc11 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 109:9296ab0bfc11 241
Kojto 109:9296ab0bfc11 242 \return Coprocessor Access Control register value
Kojto 109:9296ab0bfc11 243 */
Kojto 109:9296ab0bfc11 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 109:9296ab0bfc11 245 {
Kojto 109:9296ab0bfc11 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 109:9296ab0bfc11 247 return __regCPACR;
Kojto 109:9296ab0bfc11 248 }
Kojto 109:9296ab0bfc11 249
Kojto 109:9296ab0bfc11 250 /** \brief Set CPACR
Kojto 109:9296ab0bfc11 251
Kojto 109:9296ab0bfc11 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 109:9296ab0bfc11 253
Kojto 109:9296ab0bfc11 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 109:9296ab0bfc11 255 */
Kojto 109:9296ab0bfc11 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 109:9296ab0bfc11 257 {
Kojto 109:9296ab0bfc11 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 109:9296ab0bfc11 259 __regCPACR = cpacr;
Kojto 109:9296ab0bfc11 260 __ISB();
Kojto 109:9296ab0bfc11 261 }
Kojto 109:9296ab0bfc11 262
Kojto 109:9296ab0bfc11 263 /** \brief Get CBAR
Kojto 109:9296ab0bfc11 264
Kojto 109:9296ab0bfc11 265 This function returns the value of the Configuration Base Address register.
Kojto 109:9296ab0bfc11 266
Kojto 109:9296ab0bfc11 267 \return Configuration Base Address register value
Kojto 109:9296ab0bfc11 268 */
Kojto 109:9296ab0bfc11 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 109:9296ab0bfc11 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 109:9296ab0bfc11 271 return(__regCBAR);
Kojto 109:9296ab0bfc11 272 }
Kojto 109:9296ab0bfc11 273
Kojto 109:9296ab0bfc11 274 /** \brief Get TTBR0
Kojto 109:9296ab0bfc11 275
Kojto 109:9296ab0bfc11 276 This function returns the value of the Translation Table Base Register 0.
Kojto 109:9296ab0bfc11 277
Kojto 109:9296ab0bfc11 278 \return Translation Table Base Register 0 value
Kojto 109:9296ab0bfc11 279 */
Kojto 109:9296ab0bfc11 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 109:9296ab0bfc11 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 109:9296ab0bfc11 282 return(__regTTBR0);
Kojto 109:9296ab0bfc11 283 }
Kojto 109:9296ab0bfc11 284
Kojto 109:9296ab0bfc11 285 /** \brief Set TTBR0
Kojto 109:9296ab0bfc11 286
Kojto 109:9296ab0bfc11 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 109:9296ab0bfc11 288
Kojto 109:9296ab0bfc11 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 109:9296ab0bfc11 290 */
Kojto 109:9296ab0bfc11 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 109:9296ab0bfc11 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 109:9296ab0bfc11 293 __regTTBR0 = ttbr0;
Kojto 109:9296ab0bfc11 294 __ISB();
Kojto 109:9296ab0bfc11 295 }
Kojto 109:9296ab0bfc11 296
Kojto 109:9296ab0bfc11 297 /** \brief Get DACR
Kojto 109:9296ab0bfc11 298
Kojto 109:9296ab0bfc11 299 This function returns the value of the Domain Access Control Register.
Kojto 109:9296ab0bfc11 300
Kojto 109:9296ab0bfc11 301 \return Domain Access Control Register value
Kojto 109:9296ab0bfc11 302 */
Kojto 109:9296ab0bfc11 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 109:9296ab0bfc11 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 109:9296ab0bfc11 305 return(__regDACR);
Kojto 109:9296ab0bfc11 306 }
Kojto 109:9296ab0bfc11 307
Kojto 109:9296ab0bfc11 308 /** \brief Set DACR
Kojto 109:9296ab0bfc11 309
Kojto 109:9296ab0bfc11 310 This function assigns the given value to the Domain Access Control Register.
Kojto 109:9296ab0bfc11 311
Kojto 109:9296ab0bfc11 312 \param [in] dacr Domain Access Control Register value to set
Kojto 109:9296ab0bfc11 313 */
Kojto 109:9296ab0bfc11 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 109:9296ab0bfc11 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 109:9296ab0bfc11 316 __regDACR = dacr;
Kojto 109:9296ab0bfc11 317 __ISB();
Kojto 109:9296ab0bfc11 318 }
Kojto 109:9296ab0bfc11 319
Kojto 109:9296ab0bfc11 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 109:9296ab0bfc11 321
Kojto 109:9296ab0bfc11 322 /** \brief Set SCTLR
Kojto 109:9296ab0bfc11 323
Kojto 109:9296ab0bfc11 324 This function assigns the given value to the System Control Register.
Kojto 109:9296ab0bfc11 325
Kojto 109:9296ab0bfc11 326 \param [in] sctlr System Control Register value to set
Kojto 109:9296ab0bfc11 327 */
Kojto 109:9296ab0bfc11 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 109:9296ab0bfc11 329 {
Kojto 109:9296ab0bfc11 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 109:9296ab0bfc11 331 __regSCTLR = sctlr;
Kojto 109:9296ab0bfc11 332 }
Kojto 109:9296ab0bfc11 333
Kojto 109:9296ab0bfc11 334 /** \brief Get SCTLR
Kojto 109:9296ab0bfc11 335
Kojto 109:9296ab0bfc11 336 This function returns the value of the System Control Register.
Kojto 109:9296ab0bfc11 337
Kojto 109:9296ab0bfc11 338 \return System Control Register value
Kojto 109:9296ab0bfc11 339 */
Kojto 109:9296ab0bfc11 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 109:9296ab0bfc11 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 109:9296ab0bfc11 342 return(__regSCTLR);
Kojto 109:9296ab0bfc11 343 }
Kojto 109:9296ab0bfc11 344
Kojto 109:9296ab0bfc11 345 /** \brief Enable Caches
Kojto 109:9296ab0bfc11 346
Kojto 109:9296ab0bfc11 347 Enable Caches
Kojto 109:9296ab0bfc11 348 */
Kojto 109:9296ab0bfc11 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 109:9296ab0bfc11 350 // Set I bit 12 to enable I Cache
Kojto 109:9296ab0bfc11 351 // Set C bit 2 to enable D Cache
Kojto 109:9296ab0bfc11 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 109:9296ab0bfc11 353 }
Kojto 109:9296ab0bfc11 354
Kojto 109:9296ab0bfc11 355 /** \brief Disable Caches
Kojto 109:9296ab0bfc11 356
Kojto 109:9296ab0bfc11 357 Disable Caches
Kojto 109:9296ab0bfc11 358 */
Kojto 109:9296ab0bfc11 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 109:9296ab0bfc11 360 // Clear I bit 12 to disable I Cache
Kojto 109:9296ab0bfc11 361 // Clear C bit 2 to disable D Cache
Kojto 109:9296ab0bfc11 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 109:9296ab0bfc11 363 __ISB();
Kojto 109:9296ab0bfc11 364 }
Kojto 109:9296ab0bfc11 365
Kojto 109:9296ab0bfc11 366 /** \brief Enable BTAC
Kojto 109:9296ab0bfc11 367
Kojto 109:9296ab0bfc11 368 Enable BTAC
Kojto 109:9296ab0bfc11 369 */
Kojto 109:9296ab0bfc11 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 109:9296ab0bfc11 371 // Set Z bit 11 to enable branch prediction
Kojto 109:9296ab0bfc11 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 109:9296ab0bfc11 373 __ISB();
Kojto 109:9296ab0bfc11 374 }
Kojto 109:9296ab0bfc11 375
Kojto 109:9296ab0bfc11 376 /** \brief Disable BTAC
Kojto 109:9296ab0bfc11 377
Kojto 109:9296ab0bfc11 378 Disable BTAC
Kojto 109:9296ab0bfc11 379 */
Kojto 109:9296ab0bfc11 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 109:9296ab0bfc11 381 // Clear Z bit 11 to disable branch prediction
Kojto 109:9296ab0bfc11 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 109:9296ab0bfc11 383 }
Kojto 109:9296ab0bfc11 384
Kojto 109:9296ab0bfc11 385
Kojto 109:9296ab0bfc11 386 /** \brief Enable MMU
Kojto 109:9296ab0bfc11 387
Kojto 109:9296ab0bfc11 388 Enable MMU
Kojto 109:9296ab0bfc11 389 */
Kojto 109:9296ab0bfc11 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 109:9296ab0bfc11 391 // Set M bit 0 to enable the MMU
Kojto 109:9296ab0bfc11 392 // Set AFE bit to enable simplified access permissions model
Kojto 109:9296ab0bfc11 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 109:9296ab0bfc11 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 109:9296ab0bfc11 395 __ISB();
Kojto 109:9296ab0bfc11 396 }
Kojto 109:9296ab0bfc11 397
Kojto 109:9296ab0bfc11 398 /** \brief Disable MMU
Kojto 109:9296ab0bfc11 399
Kojto 109:9296ab0bfc11 400 Disable MMU
Kojto 109:9296ab0bfc11 401 */
Kojto 109:9296ab0bfc11 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 109:9296ab0bfc11 403 // Clear M bit 0 to disable the MMU
Kojto 109:9296ab0bfc11 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 109:9296ab0bfc11 405 __ISB();
Kojto 109:9296ab0bfc11 406 }
Kojto 109:9296ab0bfc11 407
Kojto 109:9296ab0bfc11 408 /******************************** TLB maintenance operations ************************************************/
Kojto 109:9296ab0bfc11 409 /** \brief Invalidate the whole tlb
Kojto 109:9296ab0bfc11 410
Kojto 109:9296ab0bfc11 411 TLBIALL. Invalidate the whole tlb
Kojto 109:9296ab0bfc11 412 */
Kojto 109:9296ab0bfc11 413
Kojto 109:9296ab0bfc11 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 109:9296ab0bfc11 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 109:9296ab0bfc11 416 __TLBIALL = 0;
Kojto 109:9296ab0bfc11 417 __DSB();
Kojto 109:9296ab0bfc11 418 __ISB();
Kojto 109:9296ab0bfc11 419 }
Kojto 109:9296ab0bfc11 420
Kojto 109:9296ab0bfc11 421 /******************************** BTB maintenance operations ************************************************/
Kojto 109:9296ab0bfc11 422 /** \brief Invalidate entire branch predictor array
Kojto 109:9296ab0bfc11 423
Kojto 109:9296ab0bfc11 424 BPIALL. Branch Predictor Invalidate All.
Kojto 109:9296ab0bfc11 425 */
Kojto 109:9296ab0bfc11 426
Kojto 109:9296ab0bfc11 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 109:9296ab0bfc11 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 109:9296ab0bfc11 429 __BPIALL = 0;
Kojto 109:9296ab0bfc11 430 __DSB(); //ensure completion of the invalidation
Kojto 109:9296ab0bfc11 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 109:9296ab0bfc11 432 }
Kojto 109:9296ab0bfc11 433
Kojto 109:9296ab0bfc11 434
Kojto 109:9296ab0bfc11 435 /******************************** L1 cache operations ******************************************************/
Kojto 109:9296ab0bfc11 436
Kojto 109:9296ab0bfc11 437 /** \brief Invalidate the whole I$
Kojto 109:9296ab0bfc11 438
Kojto 109:9296ab0bfc11 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 109:9296ab0bfc11 440 */
Kojto 109:9296ab0bfc11 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 109:9296ab0bfc11 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 109:9296ab0bfc11 443 __ICIALLU = 0;
Kojto 109:9296ab0bfc11 444 __DSB(); //ensure completion of the invalidation
Kojto 109:9296ab0bfc11 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 109:9296ab0bfc11 446 }
Kojto 109:9296ab0bfc11 447
Kojto 109:9296ab0bfc11 448 /** \brief Clean D$ by MVA
Kojto 109:9296ab0bfc11 449
Kojto 109:9296ab0bfc11 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 109:9296ab0bfc11 451 */
Kojto 109:9296ab0bfc11 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 109:9296ab0bfc11 454 __DCCMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 456 }
Kojto 109:9296ab0bfc11 457
Kojto 109:9296ab0bfc11 458 /** \brief Invalidate D$ by MVA
Kojto 109:9296ab0bfc11 459
Kojto 109:9296ab0bfc11 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 109:9296ab0bfc11 461 */
Kojto 109:9296ab0bfc11 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 109:9296ab0bfc11 464 __DCIMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 466 }
Kojto 109:9296ab0bfc11 467
Kojto 109:9296ab0bfc11 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 109:9296ab0bfc11 469
Kojto 109:9296ab0bfc11 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 109:9296ab0bfc11 471 */
Kojto 109:9296ab0bfc11 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 109:9296ab0bfc11 474 __DCCIMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 476 }
Kojto 109:9296ab0bfc11 477
Kojto 109:9296ab0bfc11 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 109:9296ab0bfc11 479
Kojto 109:9296ab0bfc11 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 109:9296ab0bfc11 481 */
Kojto 109:9296ab0bfc11 482 #pragma push
Kojto 109:9296ab0bfc11 483 #pragma arm
Kojto 109:9296ab0bfc11 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 109:9296ab0bfc11 485 ARM
Kojto 109:9296ab0bfc11 486
Kojto 109:9296ab0bfc11 487 PUSH {R4-R11}
Kojto 109:9296ab0bfc11 488
Kojto 109:9296ab0bfc11 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 109:9296ab0bfc11 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 109:9296ab0bfc11 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 109:9296ab0bfc11 492 BEQ Finished // If 0, no need to clean
Kojto 109:9296ab0bfc11 493
Kojto 109:9296ab0bfc11 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 109:9296ab0bfc11 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 109:9296ab0bfc11 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 109:9296ab0bfc11 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 109:9296ab0bfc11 498 CMP R1, #2
Kojto 109:9296ab0bfc11 499 BLT Skip // No cache or only instruction cache at this level
Kojto 109:9296ab0bfc11 500
Kojto 109:9296ab0bfc11 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 109:9296ab0bfc11 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 109:9296ab0bfc11 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 109:9296ab0bfc11 504 AND R2, R1, #7 // Extract the line length field
Kojto 109:9296ab0bfc11 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 109:9296ab0bfc11 506 LDR R4, =0x3FF
Kojto 109:9296ab0bfc11 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 109:9296ab0bfc11 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 109:9296ab0bfc11 509 LDR R7, =0x7FFF
Kojto 109:9296ab0bfc11 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 109:9296ab0bfc11 511
Kojto 109:9296ab0bfc11 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 109:9296ab0bfc11 513
Kojto 109:9296ab0bfc11 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 109:9296ab0bfc11 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 109:9296ab0bfc11 516 CMP R0, #0
Kojto 109:9296ab0bfc11 517 BNE Dccsw
Kojto 109:9296ab0bfc11 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 109:9296ab0bfc11 519 B cont
Kojto 109:9296ab0bfc11 520 Dccsw CMP R0, #1
Kojto 109:9296ab0bfc11 521 BNE Dccisw
Kojto 109:9296ab0bfc11 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 109:9296ab0bfc11 523 B cont
Kojto 109:9296ab0bfc11 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 109:9296ab0bfc11 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 109:9296ab0bfc11 526 BGE Loop3
Kojto 109:9296ab0bfc11 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 109:9296ab0bfc11 528 BGE Loop2
Kojto 109:9296ab0bfc11 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 109:9296ab0bfc11 530 CMP R3, R10
Kojto 109:9296ab0bfc11 531 BGT Loop1
Kojto 109:9296ab0bfc11 532
Kojto 109:9296ab0bfc11 533 Finished
Kojto 109:9296ab0bfc11 534 DSB
Kojto 109:9296ab0bfc11 535 POP {R4-R11}
Kojto 109:9296ab0bfc11 536 BX lr
Kojto 109:9296ab0bfc11 537
Kojto 109:9296ab0bfc11 538 }
Kojto 109:9296ab0bfc11 539 #pragma pop
Kojto 109:9296ab0bfc11 540
Kojto 109:9296ab0bfc11 541
Kojto 109:9296ab0bfc11 542 /** \brief Invalidate the whole D$
Kojto 109:9296ab0bfc11 543
Kojto 109:9296ab0bfc11 544 DCISW. Invalidate by Set/Way
Kojto 109:9296ab0bfc11 545 */
Kojto 109:9296ab0bfc11 546
Kojto 109:9296ab0bfc11 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 109:9296ab0bfc11 548 __v7_all_cache(0);
Kojto 109:9296ab0bfc11 549 }
Kojto 109:9296ab0bfc11 550
Kojto 109:9296ab0bfc11 551 /** \brief Clean the whole D$
Kojto 109:9296ab0bfc11 552
Kojto 109:9296ab0bfc11 553 DCCSW. Clean by Set/Way
Kojto 109:9296ab0bfc11 554 */
Kojto 109:9296ab0bfc11 555
Kojto 109:9296ab0bfc11 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 109:9296ab0bfc11 557 __v7_all_cache(1);
Kojto 109:9296ab0bfc11 558 }
Kojto 109:9296ab0bfc11 559
Kojto 109:9296ab0bfc11 560 /** \brief Clean and invalidate the whole D$
Kojto 109:9296ab0bfc11 561
Kojto 109:9296ab0bfc11 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 109:9296ab0bfc11 563 */
Kojto 109:9296ab0bfc11 564
Kojto 109:9296ab0bfc11 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 109:9296ab0bfc11 566 __v7_all_cache(2);
Kojto 109:9296ab0bfc11 567 }
Kojto 109:9296ab0bfc11 568
Kojto 109:9296ab0bfc11 569 #include "core_ca_mmu.h"
Kojto 109:9296ab0bfc11 570
Kojto 109:9296ab0bfc11 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 109:9296ab0bfc11 572
Kojto 109:9296ab0bfc11 573 #error IAR Compiler support not implemented for Cortex-A
Kojto 109:9296ab0bfc11 574
Kojto 109:9296ab0bfc11 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 109:9296ab0bfc11 576 /* GNU gcc specific functions */
Kojto 109:9296ab0bfc11 577
Kojto 109:9296ab0bfc11 578 #define MODE_USR 0x10
Kojto 109:9296ab0bfc11 579 #define MODE_FIQ 0x11
Kojto 109:9296ab0bfc11 580 #define MODE_IRQ 0x12
Kojto 109:9296ab0bfc11 581 #define MODE_SVC 0x13
Kojto 109:9296ab0bfc11 582 #define MODE_MON 0x16
Kojto 109:9296ab0bfc11 583 #define MODE_ABT 0x17
Kojto 109:9296ab0bfc11 584 #define MODE_HYP 0x1A
Kojto 109:9296ab0bfc11 585 #define MODE_UND 0x1B
Kojto 109:9296ab0bfc11 586 #define MODE_SYS 0x1F
Kojto 109:9296ab0bfc11 587
Kojto 109:9296ab0bfc11 588
Kojto 109:9296ab0bfc11 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 109:9296ab0bfc11 590 {
Kojto 109:9296ab0bfc11 591 __ASM volatile ("cpsie i");
Kojto 109:9296ab0bfc11 592 }
Kojto 109:9296ab0bfc11 593
Kojto 109:9296ab0bfc11 594 /** \brief Disable IRQ Interrupts
Kojto 109:9296ab0bfc11 595
Kojto 109:9296ab0bfc11 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 109:9296ab0bfc11 597 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 598 */
Kojto 109:9296ab0bfc11 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 109:9296ab0bfc11 600 {
Kojto 109:9296ab0bfc11 601 uint32_t result;
Kojto 109:9296ab0bfc11 602
Kojto 109:9296ab0bfc11 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 109:9296ab0bfc11 604 __ASM volatile ("cpsid i");
Kojto 109:9296ab0bfc11 605 return(result & 0x80);
Kojto 109:9296ab0bfc11 606 }
Kojto 109:9296ab0bfc11 607
Kojto 109:9296ab0bfc11 608
Kojto 109:9296ab0bfc11 609 /** \brief Get APSR Register
Kojto 109:9296ab0bfc11 610
Kojto 109:9296ab0bfc11 611 This function returns the content of the APSR Register.
Kojto 109:9296ab0bfc11 612
Kojto 109:9296ab0bfc11 613 \return APSR Register value
Kojto 109:9296ab0bfc11 614 */
Kojto 109:9296ab0bfc11 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 109:9296ab0bfc11 616 {
Kojto 109:9296ab0bfc11 617 #if 1
Kojto 109:9296ab0bfc11 618 register uint32_t __regAPSR;
Kojto 109:9296ab0bfc11 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 109:9296ab0bfc11 620 #else
Kojto 109:9296ab0bfc11 621 register uint32_t __regAPSR __ASM("apsr");
Kojto 109:9296ab0bfc11 622 #endif
Kojto 109:9296ab0bfc11 623 return(__regAPSR);
Kojto 109:9296ab0bfc11 624 }
Kojto 109:9296ab0bfc11 625
Kojto 109:9296ab0bfc11 626
Kojto 109:9296ab0bfc11 627 /** \brief Get CPSR Register
Kojto 109:9296ab0bfc11 628
Kojto 109:9296ab0bfc11 629 This function returns the content of the CPSR Register.
Kojto 109:9296ab0bfc11 630
Kojto 109:9296ab0bfc11 631 \return CPSR Register value
Kojto 109:9296ab0bfc11 632 */
Kojto 109:9296ab0bfc11 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 109:9296ab0bfc11 634 {
Kojto 109:9296ab0bfc11 635 #if 1
Kojto 109:9296ab0bfc11 636 register uint32_t __regCPSR;
Kojto 109:9296ab0bfc11 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 109:9296ab0bfc11 638 #else
Kojto 109:9296ab0bfc11 639 register uint32_t __regCPSR __ASM("cpsr");
Kojto 109:9296ab0bfc11 640 #endif
Kojto 109:9296ab0bfc11 641 return(__regCPSR);
Kojto 109:9296ab0bfc11 642 }
Kojto 109:9296ab0bfc11 643
Kojto 109:9296ab0bfc11 644 #if 0
Kojto 109:9296ab0bfc11 645 /** \brief Set Stack Pointer
Kojto 109:9296ab0bfc11 646
Kojto 109:9296ab0bfc11 647 This function assigns the given value to the current stack pointer.
Kojto 109:9296ab0bfc11 648
Kojto 109:9296ab0bfc11 649 \param [in] topOfStack Stack Pointer value to set
Kojto 109:9296ab0bfc11 650 */
Kojto 109:9296ab0bfc11 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 109:9296ab0bfc11 652 {
Kojto 109:9296ab0bfc11 653 register uint32_t __regSP __ASM("sp");
Kojto 109:9296ab0bfc11 654 __regSP = topOfStack;
Kojto 109:9296ab0bfc11 655 }
Kojto 109:9296ab0bfc11 656 #endif
Kojto 109:9296ab0bfc11 657
Kojto 109:9296ab0bfc11 658 /** \brief Get link register
Kojto 109:9296ab0bfc11 659
Kojto 109:9296ab0bfc11 660 This function returns the value of the link register
Kojto 109:9296ab0bfc11 661
Kojto 109:9296ab0bfc11 662 \return Value of link register
Kojto 109:9296ab0bfc11 663 */
Kojto 109:9296ab0bfc11 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 109:9296ab0bfc11 665 {
Kojto 109:9296ab0bfc11 666 register uint32_t __reglr __ASM("lr");
Kojto 109:9296ab0bfc11 667 return(__reglr);
Kojto 109:9296ab0bfc11 668 }
Kojto 109:9296ab0bfc11 669
Kojto 109:9296ab0bfc11 670 #if 0
Kojto 109:9296ab0bfc11 671 /** \brief Set link register
Kojto 109:9296ab0bfc11 672
Kojto 109:9296ab0bfc11 673 This function sets the value of the link register
Kojto 109:9296ab0bfc11 674
Kojto 109:9296ab0bfc11 675 \param [in] lr LR value to set
Kojto 109:9296ab0bfc11 676 */
Kojto 109:9296ab0bfc11 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 109:9296ab0bfc11 678 {
Kojto 109:9296ab0bfc11 679 register uint32_t __reglr __ASM("lr");
Kojto 109:9296ab0bfc11 680 __reglr = lr;
Kojto 109:9296ab0bfc11 681 }
Kojto 109:9296ab0bfc11 682 #endif
Kojto 109:9296ab0bfc11 683
Kojto 109:9296ab0bfc11 684 /** \brief Set Process Stack Pointer
Kojto 109:9296ab0bfc11 685
Kojto 109:9296ab0bfc11 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 109:9296ab0bfc11 687
Kojto 109:9296ab0bfc11 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 109:9296ab0bfc11 689 */
Kojto 109:9296ab0bfc11 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 109:9296ab0bfc11 691 {
Kojto 109:9296ab0bfc11 692 __asm__ volatile (
Kojto 109:9296ab0bfc11 693 ".ARM;"
Kojto 109:9296ab0bfc11 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 109:9296ab0bfc11 695
Kojto 109:9296ab0bfc11 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 109:9296ab0bfc11 697 "MRS R1, CPSR;"
Kojto 109:9296ab0bfc11 698 "CPS %0;" /* ;no effect in USR mode */
Kojto 109:9296ab0bfc11 699 "MOV SP, R0;"
Kojto 109:9296ab0bfc11 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 109:9296ab0bfc11 701 "ISB;"
Kojto 109:9296ab0bfc11 702 //"BX LR;"
Kojto 109:9296ab0bfc11 703 :
Kojto 109:9296ab0bfc11 704 : "i"(MODE_SYS)
Kojto 109:9296ab0bfc11 705 : "r0", "r1");
Kojto 109:9296ab0bfc11 706 return;
Kojto 109:9296ab0bfc11 707 }
Kojto 109:9296ab0bfc11 708
Kojto 109:9296ab0bfc11 709 /** \brief Set User Mode
Kojto 109:9296ab0bfc11 710
Kojto 109:9296ab0bfc11 711 This function changes the processor state to User Mode
Kojto 109:9296ab0bfc11 712 */
Kojto 109:9296ab0bfc11 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 109:9296ab0bfc11 714 {
Kojto 109:9296ab0bfc11 715 __asm__ volatile (
Kojto 109:9296ab0bfc11 716 ".ARM;"
Kojto 109:9296ab0bfc11 717
Kojto 109:9296ab0bfc11 718 "CPS %0;"
Kojto 109:9296ab0bfc11 719 //"BX LR;"
Kojto 109:9296ab0bfc11 720 :
Kojto 109:9296ab0bfc11 721 : "i"(MODE_USR)
Kojto 109:9296ab0bfc11 722 : );
Kojto 109:9296ab0bfc11 723 return;
Kojto 109:9296ab0bfc11 724 }
Kojto 109:9296ab0bfc11 725
Kojto 109:9296ab0bfc11 726
Kojto 109:9296ab0bfc11 727 /** \brief Enable FIQ
Kojto 109:9296ab0bfc11 728
Kojto 109:9296ab0bfc11 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 109:9296ab0bfc11 730 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 731 */
Kojto 109:9296ab0bfc11 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 109:9296ab0bfc11 733
Kojto 109:9296ab0bfc11 734
Kojto 109:9296ab0bfc11 735 /** \brief Disable FIQ
Kojto 109:9296ab0bfc11 736
Kojto 109:9296ab0bfc11 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 109:9296ab0bfc11 738 Can only be executed in Privileged modes.
Kojto 109:9296ab0bfc11 739 */
Kojto 109:9296ab0bfc11 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 109:9296ab0bfc11 741
Kojto 109:9296ab0bfc11 742
Kojto 109:9296ab0bfc11 743 /** \brief Get FPSCR
Kojto 109:9296ab0bfc11 744
Kojto 109:9296ab0bfc11 745 This function returns the current value of the Floating Point Status/Control register.
Kojto 109:9296ab0bfc11 746
Kojto 109:9296ab0bfc11 747 \return Floating Point Status/Control register value
Kojto 109:9296ab0bfc11 748 */
Kojto 109:9296ab0bfc11 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 109:9296ab0bfc11 750 {
Kojto 109:9296ab0bfc11 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 109:9296ab0bfc11 752 #if 1
Kojto 109:9296ab0bfc11 753 uint32_t result;
Kojto 109:9296ab0bfc11 754
Kojto 109:9296ab0bfc11 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 109:9296ab0bfc11 756 return (result);
Kojto 109:9296ab0bfc11 757 #else
Kojto 109:9296ab0bfc11 758 register uint32_t __regfpscr __ASM("fpscr");
Kojto 109:9296ab0bfc11 759 return(__regfpscr);
Kojto 109:9296ab0bfc11 760 #endif
Kojto 109:9296ab0bfc11 761 #else
Kojto 109:9296ab0bfc11 762 return(0);
Kojto 109:9296ab0bfc11 763 #endif
Kojto 109:9296ab0bfc11 764 }
Kojto 109:9296ab0bfc11 765
Kojto 109:9296ab0bfc11 766
Kojto 109:9296ab0bfc11 767 /** \brief Set FPSCR
Kojto 109:9296ab0bfc11 768
Kojto 109:9296ab0bfc11 769 This function assigns the given value to the Floating Point Status/Control register.
Kojto 109:9296ab0bfc11 770
Kojto 109:9296ab0bfc11 771 \param [in] fpscr Floating Point Status/Control value to set
Kojto 109:9296ab0bfc11 772 */
Kojto 109:9296ab0bfc11 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 109:9296ab0bfc11 774 {
Kojto 109:9296ab0bfc11 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 109:9296ab0bfc11 776 #if 1
Kojto 109:9296ab0bfc11 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 109:9296ab0bfc11 778 #else
Kojto 109:9296ab0bfc11 779 register uint32_t __regfpscr __ASM("fpscr");
Kojto 109:9296ab0bfc11 780 __regfpscr = (fpscr);
Kojto 109:9296ab0bfc11 781 #endif
Kojto 109:9296ab0bfc11 782 #endif
Kojto 109:9296ab0bfc11 783 }
Kojto 109:9296ab0bfc11 784
Kojto 109:9296ab0bfc11 785 /** \brief Get FPEXC
Kojto 109:9296ab0bfc11 786
Kojto 109:9296ab0bfc11 787 This function returns the current value of the Floating Point Exception Control register.
Kojto 109:9296ab0bfc11 788
Kojto 109:9296ab0bfc11 789 \return Floating Point Exception Control register value
Kojto 109:9296ab0bfc11 790 */
Kojto 109:9296ab0bfc11 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 109:9296ab0bfc11 792 {
Kojto 109:9296ab0bfc11 793 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 794 #if 1
Kojto 109:9296ab0bfc11 795 uint32_t result;
Kojto 109:9296ab0bfc11 796
Kojto 109:9296ab0bfc11 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 109:9296ab0bfc11 798 return (result);
Kojto 109:9296ab0bfc11 799 #else
Kojto 109:9296ab0bfc11 800 register uint32_t __regfpexc __ASM("fpexc");
Kojto 109:9296ab0bfc11 801 return(__regfpexc);
Kojto 109:9296ab0bfc11 802 #endif
Kojto 109:9296ab0bfc11 803 #else
Kojto 109:9296ab0bfc11 804 return(0);
Kojto 109:9296ab0bfc11 805 #endif
Kojto 109:9296ab0bfc11 806 }
Kojto 109:9296ab0bfc11 807
Kojto 109:9296ab0bfc11 808
Kojto 109:9296ab0bfc11 809 /** \brief Set FPEXC
Kojto 109:9296ab0bfc11 810
Kojto 109:9296ab0bfc11 811 This function assigns the given value to the Floating Point Exception Control register.
Kojto 109:9296ab0bfc11 812
Kojto 109:9296ab0bfc11 813 \param [in] fpscr Floating Point Exception Control value to set
Kojto 109:9296ab0bfc11 814 */
Kojto 109:9296ab0bfc11 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 109:9296ab0bfc11 816 {
Kojto 109:9296ab0bfc11 817 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 818 #if 1
Kojto 109:9296ab0bfc11 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 109:9296ab0bfc11 820 #else
Kojto 109:9296ab0bfc11 821 register uint32_t __regfpexc __ASM("fpexc");
Kojto 109:9296ab0bfc11 822 __regfpexc = (fpexc);
Kojto 109:9296ab0bfc11 823 #endif
Kojto 109:9296ab0bfc11 824 #endif
Kojto 109:9296ab0bfc11 825 }
Kojto 109:9296ab0bfc11 826
Kojto 109:9296ab0bfc11 827 /** \brief Get CPACR
Kojto 109:9296ab0bfc11 828
Kojto 109:9296ab0bfc11 829 This function returns the current value of the Coprocessor Access Control register.
Kojto 109:9296ab0bfc11 830
Kojto 109:9296ab0bfc11 831 \return Coprocessor Access Control register value
Kojto 109:9296ab0bfc11 832 */
Kojto 109:9296ab0bfc11 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 109:9296ab0bfc11 834 {
Kojto 109:9296ab0bfc11 835 #if 1
Kojto 109:9296ab0bfc11 836 register uint32_t __regCPACR;
Kojto 109:9296ab0bfc11 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 109:9296ab0bfc11 838 #else
Kojto 109:9296ab0bfc11 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 109:9296ab0bfc11 840 #endif
Kojto 109:9296ab0bfc11 841 return __regCPACR;
Kojto 109:9296ab0bfc11 842 }
Kojto 109:9296ab0bfc11 843
Kojto 109:9296ab0bfc11 844 /** \brief Set CPACR
Kojto 109:9296ab0bfc11 845
Kojto 109:9296ab0bfc11 846 This function assigns the given value to the Coprocessor Access Control register.
Kojto 109:9296ab0bfc11 847
Kojto 109:9296ab0bfc11 848 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 109:9296ab0bfc11 849 */
Kojto 109:9296ab0bfc11 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 109:9296ab0bfc11 851 {
Kojto 109:9296ab0bfc11 852 #if 1
Kojto 109:9296ab0bfc11 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 109:9296ab0bfc11 854 #else
Kojto 109:9296ab0bfc11 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 109:9296ab0bfc11 856 __regCPACR = cpacr;
Kojto 109:9296ab0bfc11 857 #endif
Kojto 109:9296ab0bfc11 858 __ISB();
Kojto 109:9296ab0bfc11 859 }
Kojto 109:9296ab0bfc11 860
Kojto 109:9296ab0bfc11 861 /** \brief Get CBAR
Kojto 109:9296ab0bfc11 862
Kojto 109:9296ab0bfc11 863 This function returns the value of the Configuration Base Address register.
Kojto 109:9296ab0bfc11 864
Kojto 109:9296ab0bfc11 865 \return Configuration Base Address register value
Kojto 109:9296ab0bfc11 866 */
Kojto 109:9296ab0bfc11 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 109:9296ab0bfc11 868 #if 1
Kojto 109:9296ab0bfc11 869 register uint32_t __regCBAR;
Kojto 109:9296ab0bfc11 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 109:9296ab0bfc11 871 #else
Kojto 109:9296ab0bfc11 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 109:9296ab0bfc11 873 #endif
Kojto 109:9296ab0bfc11 874 return(__regCBAR);
Kojto 109:9296ab0bfc11 875 }
Kojto 109:9296ab0bfc11 876
Kojto 109:9296ab0bfc11 877 /** \brief Get TTBR0
Kojto 109:9296ab0bfc11 878
Kojto 109:9296ab0bfc11 879 This function returns the value of the Translation Table Base Register 0.
Kojto 109:9296ab0bfc11 880
Kojto 109:9296ab0bfc11 881 \return Translation Table Base Register 0 value
Kojto 109:9296ab0bfc11 882 */
Kojto 109:9296ab0bfc11 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 109:9296ab0bfc11 884 #if 1
Kojto 109:9296ab0bfc11 885 register uint32_t __regTTBR0;
Kojto 109:9296ab0bfc11 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 109:9296ab0bfc11 887 #else
Kojto 109:9296ab0bfc11 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 109:9296ab0bfc11 889 #endif
Kojto 109:9296ab0bfc11 890 return(__regTTBR0);
Kojto 109:9296ab0bfc11 891 }
Kojto 109:9296ab0bfc11 892
Kojto 109:9296ab0bfc11 893 /** \brief Set TTBR0
Kojto 109:9296ab0bfc11 894
Kojto 109:9296ab0bfc11 895 This function assigns the given value to the Translation Table Base Register 0.
Kojto 109:9296ab0bfc11 896
Kojto 109:9296ab0bfc11 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 109:9296ab0bfc11 898 */
Kojto 109:9296ab0bfc11 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 109:9296ab0bfc11 900 #if 1
Kojto 109:9296ab0bfc11 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 109:9296ab0bfc11 902 #else
Kojto 109:9296ab0bfc11 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 109:9296ab0bfc11 904 __regTTBR0 = ttbr0;
Kojto 109:9296ab0bfc11 905 #endif
Kojto 109:9296ab0bfc11 906 __ISB();
Kojto 109:9296ab0bfc11 907 }
Kojto 109:9296ab0bfc11 908
Kojto 109:9296ab0bfc11 909 /** \brief Get DACR
Kojto 109:9296ab0bfc11 910
Kojto 109:9296ab0bfc11 911 This function returns the value of the Domain Access Control Register.
Kojto 109:9296ab0bfc11 912
Kojto 109:9296ab0bfc11 913 \return Domain Access Control Register value
Kojto 109:9296ab0bfc11 914 */
Kojto 109:9296ab0bfc11 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 109:9296ab0bfc11 916 #if 1
Kojto 109:9296ab0bfc11 917 register uint32_t __regDACR;
Kojto 109:9296ab0bfc11 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 109:9296ab0bfc11 919 #else
Kojto 109:9296ab0bfc11 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 109:9296ab0bfc11 921 #endif
Kojto 109:9296ab0bfc11 922 return(__regDACR);
Kojto 109:9296ab0bfc11 923 }
Kojto 109:9296ab0bfc11 924
Kojto 109:9296ab0bfc11 925 /** \brief Set DACR
Kojto 109:9296ab0bfc11 926
Kojto 109:9296ab0bfc11 927 This function assigns the given value to the Domain Access Control Register.
Kojto 109:9296ab0bfc11 928
Kojto 109:9296ab0bfc11 929 \param [in] dacr Domain Access Control Register value to set
Kojto 109:9296ab0bfc11 930 */
Kojto 109:9296ab0bfc11 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 109:9296ab0bfc11 932 #if 1
Kojto 109:9296ab0bfc11 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 109:9296ab0bfc11 934 #else
Kojto 109:9296ab0bfc11 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 109:9296ab0bfc11 936 __regDACR = dacr;
Kojto 109:9296ab0bfc11 937 #endif
Kojto 109:9296ab0bfc11 938 __ISB();
Kojto 109:9296ab0bfc11 939 }
Kojto 109:9296ab0bfc11 940
Kojto 109:9296ab0bfc11 941 /******************************** Cache and BTAC enable ****************************************************/
Kojto 109:9296ab0bfc11 942
Kojto 109:9296ab0bfc11 943 /** \brief Set SCTLR
Kojto 109:9296ab0bfc11 944
Kojto 109:9296ab0bfc11 945 This function assigns the given value to the System Control Register.
Kojto 109:9296ab0bfc11 946
Kojto 109:9296ab0bfc11 947 \param [in] sctlr System Control Register value to set
Kojto 109:9296ab0bfc11 948 */
Kojto 109:9296ab0bfc11 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 109:9296ab0bfc11 950 {
Kojto 109:9296ab0bfc11 951 #if 1
Kojto 109:9296ab0bfc11 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 109:9296ab0bfc11 953 #else
Kojto 109:9296ab0bfc11 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 109:9296ab0bfc11 955 __regSCTLR = sctlr;
Kojto 109:9296ab0bfc11 956 #endif
Kojto 109:9296ab0bfc11 957 }
Kojto 109:9296ab0bfc11 958
Kojto 109:9296ab0bfc11 959 /** \brief Get SCTLR
Kojto 109:9296ab0bfc11 960
Kojto 109:9296ab0bfc11 961 This function returns the value of the System Control Register.
Kojto 109:9296ab0bfc11 962
Kojto 109:9296ab0bfc11 963 \return System Control Register value
Kojto 109:9296ab0bfc11 964 */
Kojto 109:9296ab0bfc11 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 109:9296ab0bfc11 966 #if 1
Kojto 109:9296ab0bfc11 967 register uint32_t __regSCTLR;
Kojto 109:9296ab0bfc11 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 109:9296ab0bfc11 969 #else
Kojto 109:9296ab0bfc11 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 109:9296ab0bfc11 971 #endif
Kojto 109:9296ab0bfc11 972 return(__regSCTLR);
Kojto 109:9296ab0bfc11 973 }
Kojto 109:9296ab0bfc11 974
Kojto 109:9296ab0bfc11 975 /** \brief Enable Caches
Kojto 109:9296ab0bfc11 976
Kojto 109:9296ab0bfc11 977 Enable Caches
Kojto 109:9296ab0bfc11 978 */
Kojto 109:9296ab0bfc11 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 109:9296ab0bfc11 980 // Set I bit 12 to enable I Cache
Kojto 109:9296ab0bfc11 981 // Set C bit 2 to enable D Cache
Kojto 109:9296ab0bfc11 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 109:9296ab0bfc11 983 }
Kojto 109:9296ab0bfc11 984
Kojto 109:9296ab0bfc11 985 /** \brief Disable Caches
Kojto 109:9296ab0bfc11 986
Kojto 109:9296ab0bfc11 987 Disable Caches
Kojto 109:9296ab0bfc11 988 */
Kojto 109:9296ab0bfc11 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 109:9296ab0bfc11 990 // Clear I bit 12 to disable I Cache
Kojto 109:9296ab0bfc11 991 // Clear C bit 2 to disable D Cache
Kojto 109:9296ab0bfc11 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 109:9296ab0bfc11 993 __ISB();
Kojto 109:9296ab0bfc11 994 }
Kojto 109:9296ab0bfc11 995
Kojto 109:9296ab0bfc11 996 /** \brief Enable BTAC
Kojto 109:9296ab0bfc11 997
Kojto 109:9296ab0bfc11 998 Enable BTAC
Kojto 109:9296ab0bfc11 999 */
Kojto 109:9296ab0bfc11 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 109:9296ab0bfc11 1001 // Set Z bit 11 to enable branch prediction
Kojto 109:9296ab0bfc11 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 109:9296ab0bfc11 1003 __ISB();
Kojto 109:9296ab0bfc11 1004 }
Kojto 109:9296ab0bfc11 1005
Kojto 109:9296ab0bfc11 1006 /** \brief Disable BTAC
Kojto 109:9296ab0bfc11 1007
Kojto 109:9296ab0bfc11 1008 Disable BTAC
Kojto 109:9296ab0bfc11 1009 */
Kojto 109:9296ab0bfc11 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 109:9296ab0bfc11 1011 // Clear Z bit 11 to disable branch prediction
Kojto 109:9296ab0bfc11 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 109:9296ab0bfc11 1013 }
Kojto 109:9296ab0bfc11 1014
Kojto 109:9296ab0bfc11 1015
Kojto 109:9296ab0bfc11 1016 /** \brief Enable MMU
Kojto 109:9296ab0bfc11 1017
Kojto 109:9296ab0bfc11 1018 Enable MMU
Kojto 109:9296ab0bfc11 1019 */
Kojto 109:9296ab0bfc11 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 109:9296ab0bfc11 1021 // Set M bit 0 to enable the MMU
Kojto 109:9296ab0bfc11 1022 // Set AFE bit to enable simplified access permissions model
Kojto 109:9296ab0bfc11 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 109:9296ab0bfc11 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 109:9296ab0bfc11 1025 __ISB();
Kojto 109:9296ab0bfc11 1026 }
Kojto 109:9296ab0bfc11 1027
Kojto 109:9296ab0bfc11 1028 /** \brief Disable MMU
Kojto 109:9296ab0bfc11 1029
Kojto 109:9296ab0bfc11 1030 Disable MMU
Kojto 109:9296ab0bfc11 1031 */
Kojto 109:9296ab0bfc11 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 109:9296ab0bfc11 1033 // Clear M bit 0 to disable the MMU
Kojto 109:9296ab0bfc11 1034 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 109:9296ab0bfc11 1035 __ISB();
Kojto 109:9296ab0bfc11 1036 }
Kojto 109:9296ab0bfc11 1037
Kojto 109:9296ab0bfc11 1038 /******************************** TLB maintenance operations ************************************************/
Kojto 109:9296ab0bfc11 1039 /** \brief Invalidate the whole tlb
Kojto 109:9296ab0bfc11 1040
Kojto 109:9296ab0bfc11 1041 TLBIALL. Invalidate the whole tlb
Kojto 109:9296ab0bfc11 1042 */
Kojto 109:9296ab0bfc11 1043
Kojto 109:9296ab0bfc11 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 109:9296ab0bfc11 1045 #if 1
Kojto 109:9296ab0bfc11 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 109:9296ab0bfc11 1047 #else
Kojto 109:9296ab0bfc11 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 109:9296ab0bfc11 1049 __TLBIALL = 0;
Kojto 109:9296ab0bfc11 1050 #endif
Kojto 109:9296ab0bfc11 1051 __DSB();
Kojto 109:9296ab0bfc11 1052 __ISB();
Kojto 109:9296ab0bfc11 1053 }
Kojto 109:9296ab0bfc11 1054
Kojto 109:9296ab0bfc11 1055 /******************************** BTB maintenance operations ************************************************/
Kojto 109:9296ab0bfc11 1056 /** \brief Invalidate entire branch predictor array
Kojto 109:9296ab0bfc11 1057
Kojto 109:9296ab0bfc11 1058 BPIALL. Branch Predictor Invalidate All.
Kojto 109:9296ab0bfc11 1059 */
Kojto 109:9296ab0bfc11 1060
Kojto 109:9296ab0bfc11 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 109:9296ab0bfc11 1062 #if 1
Kojto 109:9296ab0bfc11 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 109:9296ab0bfc11 1064 #else
Kojto 109:9296ab0bfc11 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 109:9296ab0bfc11 1066 __BPIALL = 0;
Kojto 109:9296ab0bfc11 1067 #endif
Kojto 109:9296ab0bfc11 1068 __DSB(); //ensure completion of the invalidation
Kojto 109:9296ab0bfc11 1069 __ISB(); //ensure instruction fetch path sees new state
Kojto 109:9296ab0bfc11 1070 }
Kojto 109:9296ab0bfc11 1071
Kojto 109:9296ab0bfc11 1072
Kojto 109:9296ab0bfc11 1073 /******************************** L1 cache operations ******************************************************/
Kojto 109:9296ab0bfc11 1074
Kojto 109:9296ab0bfc11 1075 /** \brief Invalidate the whole I$
Kojto 109:9296ab0bfc11 1076
Kojto 109:9296ab0bfc11 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 109:9296ab0bfc11 1078 */
Kojto 109:9296ab0bfc11 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 109:9296ab0bfc11 1080 #if 1
Kojto 109:9296ab0bfc11 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 109:9296ab0bfc11 1082 #else
Kojto 109:9296ab0bfc11 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 109:9296ab0bfc11 1084 __ICIALLU = 0;
Kojto 109:9296ab0bfc11 1085 #endif
Kojto 109:9296ab0bfc11 1086 __DSB(); //ensure completion of the invalidation
Kojto 109:9296ab0bfc11 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 109:9296ab0bfc11 1088 }
Kojto 109:9296ab0bfc11 1089
Kojto 109:9296ab0bfc11 1090 /** \brief Clean D$ by MVA
Kojto 109:9296ab0bfc11 1091
Kojto 109:9296ab0bfc11 1092 DCCMVAC. Data cache clean by MVA to PoC
Kojto 109:9296ab0bfc11 1093 */
Kojto 109:9296ab0bfc11 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 1095 #if 1
Kojto 109:9296ab0bfc11 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 109:9296ab0bfc11 1097 #else
Kojto 109:9296ab0bfc11 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 109:9296ab0bfc11 1099 __DCCMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 1100 #endif
Kojto 109:9296ab0bfc11 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 1102 }
Kojto 109:9296ab0bfc11 1103
Kojto 109:9296ab0bfc11 1104 /** \brief Invalidate D$ by MVA
Kojto 109:9296ab0bfc11 1105
Kojto 109:9296ab0bfc11 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 109:9296ab0bfc11 1107 */
Kojto 109:9296ab0bfc11 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 1109 #if 1
Kojto 109:9296ab0bfc11 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 109:9296ab0bfc11 1111 #else
Kojto 109:9296ab0bfc11 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 109:9296ab0bfc11 1113 __DCIMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 1114 #endif
Kojto 109:9296ab0bfc11 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 1116 }
Kojto 109:9296ab0bfc11 1117
Kojto 109:9296ab0bfc11 1118 /** \brief Clean and Invalidate D$ by MVA
Kojto 109:9296ab0bfc11 1119
Kojto 109:9296ab0bfc11 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 109:9296ab0bfc11 1121 */
Kojto 109:9296ab0bfc11 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 109:9296ab0bfc11 1123 #if 1
Kojto 109:9296ab0bfc11 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 109:9296ab0bfc11 1125 #else
Kojto 109:9296ab0bfc11 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 109:9296ab0bfc11 1127 __DCCIMVAC = (uint32_t)va;
Kojto 109:9296ab0bfc11 1128 #endif
Kojto 109:9296ab0bfc11 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 109:9296ab0bfc11 1130 }
Kojto 109:9296ab0bfc11 1131
Kojto 109:9296ab0bfc11 1132 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 109:9296ab0bfc11 1133
Kojto 109:9296ab0bfc11 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 109:9296ab0bfc11 1135 */
Kojto 109:9296ab0bfc11 1136 extern void __v7_all_cache(uint32_t op);
Kojto 109:9296ab0bfc11 1137
Kojto 109:9296ab0bfc11 1138
Kojto 109:9296ab0bfc11 1139 /** \brief Invalidate the whole D$
Kojto 109:9296ab0bfc11 1140
Kojto 109:9296ab0bfc11 1141 DCISW. Invalidate by Set/Way
Kojto 109:9296ab0bfc11 1142 */
Kojto 109:9296ab0bfc11 1143
Kojto 109:9296ab0bfc11 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 109:9296ab0bfc11 1145 __v7_all_cache(0);
Kojto 109:9296ab0bfc11 1146 }
Kojto 109:9296ab0bfc11 1147
Kojto 109:9296ab0bfc11 1148 /** \brief Clean the whole D$
Kojto 109:9296ab0bfc11 1149
Kojto 109:9296ab0bfc11 1150 DCCSW. Clean by Set/Way
Kojto 109:9296ab0bfc11 1151 */
Kojto 109:9296ab0bfc11 1152
Kojto 109:9296ab0bfc11 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 109:9296ab0bfc11 1154 __v7_all_cache(1);
Kojto 109:9296ab0bfc11 1155 }
Kojto 109:9296ab0bfc11 1156
Kojto 109:9296ab0bfc11 1157 /** \brief Clean and invalidate the whole D$
Kojto 109:9296ab0bfc11 1158
Kojto 109:9296ab0bfc11 1159 DCCISW. Clean and Invalidate by Set/Way
Kojto 109:9296ab0bfc11 1160 */
Kojto 109:9296ab0bfc11 1161
Kojto 109:9296ab0bfc11 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 109:9296ab0bfc11 1163 __v7_all_cache(2);
Kojto 109:9296ab0bfc11 1164 }
Kojto 109:9296ab0bfc11 1165
Kojto 109:9296ab0bfc11 1166 #include "core_ca_mmu.h"
Kojto 109:9296ab0bfc11 1167
Kojto 109:9296ab0bfc11 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 109:9296ab0bfc11 1169
Kojto 109:9296ab0bfc11 1170 #error TASKING Compiler support not implemented for Cortex-A
Kojto 109:9296ab0bfc11 1171
Kojto 109:9296ab0bfc11 1172 #endif
Kojto 109:9296ab0bfc11 1173
Kojto 109:9296ab0bfc11 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 109:9296ab0bfc11 1175
Kojto 109:9296ab0bfc11 1176
Kojto 109:9296ab0bfc11 1177 #endif /* __CORE_CAFUNC_H__ */