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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L073RZ/core_cm0plus.h@116:c0f6e94411f5, 2016-03-15 (annotated)

Committer:
Kojto
Date:
Tue Mar 15 14:34:00 2016 +0000
Revision:
116:c0f6e94411f5
Parent:
TARGET_ARM_MPS2_BEID/core_cm0plus.h@110:165afa46840b
Child:
128:9bcdf88f62b0
Release 116 of the mbed library



Changes:

- new targets - NUCLEO_L073RZ

- fixes to IOTSS BEID platform

- LPC824, LPC1549 and LPC11U68 - fix PWMOut SCT bugs

- STM32F7 - Cube driver

- STM32F4 - add RTC LSI macro, defined as 0

- STM32F3 - fix multiple ADC clock initialization

- retarget - binary mode fix for GCC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 108:34e6b704fe68 1 /**************************************************************************//**
Kojto 108:34e6b704fe68 2 * @file core_cm0plus.h
Kojto 108:34e6b704fe68 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 108:34e6b704fe68 6 *
Kojto 108:34e6b704fe68 7 * @note
Kojto 108:34e6b704fe68 8 *
Kojto 108:34e6b704fe68 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 108:34e6b704fe68 11
Kojto 108:34e6b704fe68 12 All rights reserved.
Kojto 108:34e6b704fe68 13 Redistribution and use in source and binary forms, with or without
Kojto 108:34e6b704fe68 14 modification, are permitted provided that the following conditions are met:
Kojto 108:34e6b704fe68 15 - Redistributions of source code must retain the above copyright
Kojto 108:34e6b704fe68 16 notice, this list of conditions and the following disclaimer.
Kojto 108:34e6b704fe68 17 - Redistributions in binary form must reproduce the above copyright
Kojto 108:34e6b704fe68 18 notice, this list of conditions and the following disclaimer in the
Kojto 108:34e6b704fe68 19 documentation and/or other materials provided with the distribution.
Kojto 108:34e6b704fe68 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 108:34e6b704fe68 21 to endorse or promote products derived from this software without
Kojto 108:34e6b704fe68 22 specific prior written permission.
Kojto 108:34e6b704fe68 23 *
Kojto 108:34e6b704fe68 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 108:34e6b704fe68 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 108:34e6b704fe68 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 108:34e6b704fe68 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 108:34e6b704fe68 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 108:34e6b704fe68 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 108:34e6b704fe68 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 108:34e6b704fe68 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 108:34e6b704fe68 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 108:34e6b704fe68 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 108:34e6b704fe68 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 108:34e6b704fe68 35 ---------------------------------------------------------------------------*/
Kojto 108:34e6b704fe68 36
Kojto 108:34e6b704fe68 37
Kojto 108:34e6b704fe68 38 #if defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 108:34e6b704fe68 40 #endif
Kojto 108:34e6b704fe68 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 108:34e6b704fe68 45 #ifdef __cplusplus
Kojto 108:34e6b704fe68 46 extern "C" {
Kojto 108:34e6b704fe68 47 #endif
Kojto 108:34e6b704fe68 48
Kojto 108:34e6b704fe68 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 108:34e6b704fe68 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 108:34e6b704fe68 51
Kojto 108:34e6b704fe68 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 108:34e6b704fe68 53 Function definitions in header files are used to allow 'inlining'.
Kojto 108:34e6b704fe68 54
Kojto 108:34e6b704fe68 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 108:34e6b704fe68 56 Unions are used for effective representation of core registers.
Kojto 108:34e6b704fe68 57
Kojto 108:34e6b704fe68 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 108:34e6b704fe68 59 Function-like macros are used to allow more efficient code.
Kojto 108:34e6b704fe68 60 */
Kojto 108:34e6b704fe68 61
Kojto 108:34e6b704fe68 62
Kojto 108:34e6b704fe68 63 /*******************************************************************************
Kojto 108:34e6b704fe68 64 * CMSIS definitions
Kojto 108:34e6b704fe68 65 ******************************************************************************/
Kojto 108:34e6b704fe68 66 /** \ingroup Cortex-M0+
Kojto 108:34e6b704fe68 67 @{
Kojto 108:34e6b704fe68 68 */
Kojto 108:34e6b704fe68 69
Kojto 108:34e6b704fe68 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 108:34e6b704fe68 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 108:34e6b704fe68 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 108:34e6b704fe68 75
Kojto 108:34e6b704fe68 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 108:34e6b704fe68 77
Kojto 108:34e6b704fe68 78
Kojto 108:34e6b704fe68 79 #if defined ( __CC_ARM )
Kojto 108:34e6b704fe68 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 108:34e6b704fe68 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 108:34e6b704fe68 82 #define __STATIC_INLINE static __inline
Kojto 108:34e6b704fe68 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 108:34e6b704fe68 89 #elif defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 108:34e6b704fe68 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 108:34e6b704fe68 92 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 108:34e6b704fe68 96 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 97
Kojto 108:34e6b704fe68 98 #elif defined ( __TASKING__ )
Kojto 108:34e6b704fe68 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 108:34e6b704fe68 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 108:34e6b704fe68 101 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 108:34e6b704fe68 109 #endif
Kojto 108:34e6b704fe68 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 108:34e6b704fe68 113 */
Kojto 108:34e6b704fe68 114 #define __FPU_USED 0
Kojto 108:34e6b704fe68 115
Kojto 108:34e6b704fe68 116 #if defined ( __CC_ARM )
Kojto 108:34e6b704fe68 117 #if defined __TARGET_FPU_VFP
Kojto 108:34e6b704fe68 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 119 #endif
Kojto 108:34e6b704fe68 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 108:34e6b704fe68 126 #elif defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 127 #if defined __ARMVFP__
Kojto 108:34e6b704fe68 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 129 #endif
Kojto 108:34e6b704fe68 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 108:34e6b704fe68 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 134 #endif
Kojto 108:34e6b704fe68 135
Kojto 108:34e6b704fe68 136 #elif defined ( __TASKING__ )
Kojto 108:34e6b704fe68 137 #if defined __FPU_VFP__
Kojto 108:34e6b704fe68 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 108:34e6b704fe68 145 #endif
Kojto 108:34e6b704fe68 146
Kojto 108:34e6b704fe68 147 #include <stdint.h> /* standard types definitions */
Kojto 108:34e6b704fe68 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 108:34e6b704fe68 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 108:34e6b704fe68 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 108:34e6b704fe68 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 108:34e6b704fe68 156
Kojto 108:34e6b704fe68 157 #ifndef __CMSIS_GENERIC
Kojto 108:34e6b704fe68 158
Kojto 108:34e6b704fe68 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 108:34e6b704fe68 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 108:34e6b704fe68 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 108:34e6b704fe68 166 /* check device defines and use defaults */
Kojto 108:34e6b704fe68 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 108:34e6b704fe68 168 #ifndef __CM0PLUS_REV
Kojto 108:34e6b704fe68 169 #define __CM0PLUS_REV 0x0000
Kojto 108:34e6b704fe68 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 108:34e6b704fe68 171 #endif
Kojto 108:34e6b704fe68 172
Kojto 108:34e6b704fe68 173 #ifndef __MPU_PRESENT
Kojto 108:34e6b704fe68 174 #define __MPU_PRESENT 0
Kojto 108:34e6b704fe68 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 108:34e6b704fe68 176 #endif
Kojto 108:34e6b704fe68 177
Kojto 108:34e6b704fe68 178 #ifndef __VTOR_PRESENT
Kojto 108:34e6b704fe68 179 #define __VTOR_PRESENT 0
Kojto 108:34e6b704fe68 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 108:34e6b704fe68 181 #endif
Kojto 108:34e6b704fe68 182
Kojto 108:34e6b704fe68 183 #ifndef __NVIC_PRIO_BITS
Kojto 108:34e6b704fe68 184 #define __NVIC_PRIO_BITS 2
Kojto 108:34e6b704fe68 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 108:34e6b704fe68 186 #endif
Kojto 108:34e6b704fe68 187
Kojto 108:34e6b704fe68 188 #ifndef __Vendor_SysTickConfig
Kojto 108:34e6b704fe68 189 #define __Vendor_SysTickConfig 0
Kojto 108:34e6b704fe68 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 108:34e6b704fe68 191 #endif
Kojto 108:34e6b704fe68 192 #endif
Kojto 108:34e6b704fe68 193
Kojto 108:34e6b704fe68 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 108:34e6b704fe68 195 /**
Kojto 108:34e6b704fe68 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 108:34e6b704fe68 197
Kojto 108:34e6b704fe68 198 <strong>IO Type Qualifiers</strong> are used
Kojto 108:34e6b704fe68 199 \li to specify the access to peripheral variables.
Kojto 108:34e6b704fe68 200 \li for automatic generation of peripheral register debug information.
Kojto 108:34e6b704fe68 201 */
Kojto 108:34e6b704fe68 202 #ifdef __cplusplus
Kojto 108:34e6b704fe68 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 108:34e6b704fe68 204 #else
Kojto 108:34e6b704fe68 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 108:34e6b704fe68 206 #endif
Kojto 108:34e6b704fe68 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 108:34e6b704fe68 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 108:34e6b704fe68 209
Kojto 108:34e6b704fe68 210 /*@} end of group Cortex-M0+ */
Kojto 108:34e6b704fe68 211
Kojto 108:34e6b704fe68 212
Kojto 108:34e6b704fe68 213
Kojto 108:34e6b704fe68 214 /*******************************************************************************
Kojto 108:34e6b704fe68 215 * Register Abstraction
Kojto 108:34e6b704fe68 216 Core Register contain:
Kojto 108:34e6b704fe68 217 - Core Register
Kojto 108:34e6b704fe68 218 - Core NVIC Register
Kojto 108:34e6b704fe68 219 - Core SCB Register
Kojto 108:34e6b704fe68 220 - Core SysTick Register
Kojto 108:34e6b704fe68 221 - Core MPU Register
Kojto 108:34e6b704fe68 222 ******************************************************************************/
Kojto 108:34e6b704fe68 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 108:34e6b704fe68 224 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 108:34e6b704fe68 225 */
Kojto 108:34e6b704fe68 226
Kojto 108:34e6b704fe68 227 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 228 \defgroup CMSIS_CORE Status and Control Registers
Kojto 108:34e6b704fe68 229 \brief Core Register type definitions.
Kojto 108:34e6b704fe68 230 @{
Kojto 108:34e6b704fe68 231 */
Kojto 108:34e6b704fe68 232
Kojto 108:34e6b704fe68 233 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 108:34e6b704fe68 234 */
Kojto 108:34e6b704fe68 235 typedef union
Kojto 108:34e6b704fe68 236 {
Kojto 108:34e6b704fe68 237 struct
Kojto 108:34e6b704fe68 238 {
Kojto 110:165afa46840b 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 108:34e6b704fe68 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 108:34e6b704fe68 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 108:34e6b704fe68 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 108:34e6b704fe68 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 108:34e6b704fe68 244 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 245 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 246 } APSR_Type;
Kojto 108:34e6b704fe68 247
Kojto 110:165afa46840b 248 /* APSR Register Definitions */
Kojto 110:165afa46840b 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 257
Kojto 110:165afa46840b 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 260
Kojto 108:34e6b704fe68 261
Kojto 108:34e6b704fe68 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 108:34e6b704fe68 263 */
Kojto 108:34e6b704fe68 264 typedef union
Kojto 108:34e6b704fe68 265 {
Kojto 108:34e6b704fe68 266 struct
Kojto 108:34e6b704fe68 267 {
Kojto 108:34e6b704fe68 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 108:34e6b704fe68 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 108:34e6b704fe68 270 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 271 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 272 } IPSR_Type;
Kojto 108:34e6b704fe68 273
Kojto 110:165afa46840b 274 /* IPSR Register Definitions */
Kojto 110:165afa46840b 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 277
Kojto 108:34e6b704fe68 278
Kojto 108:34e6b704fe68 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 108:34e6b704fe68 280 */
Kojto 108:34e6b704fe68 281 typedef union
Kojto 108:34e6b704fe68 282 {
Kojto 108:34e6b704fe68 283 struct
Kojto 108:34e6b704fe68 284 {
Kojto 108:34e6b704fe68 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 108:34e6b704fe68 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 108:34e6b704fe68 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 108:34e6b704fe68 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 108:34e6b704fe68 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 108:34e6b704fe68 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 108:34e6b704fe68 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 108:34e6b704fe68 293 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 294 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 295 } xPSR_Type;
Kojto 108:34e6b704fe68 296
Kojto 110:165afa46840b 297 /* xPSR Register Definitions */
Kojto 110:165afa46840b 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 312
Kojto 110:165afa46840b 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 315
Kojto 108:34e6b704fe68 316
Kojto 108:34e6b704fe68 317 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 108:34e6b704fe68 318 */
Kojto 108:34e6b704fe68 319 typedef union
Kojto 108:34e6b704fe68 320 {
Kojto 108:34e6b704fe68 321 struct
Kojto 108:34e6b704fe68 322 {
Kojto 108:34e6b704fe68 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 108:34e6b704fe68 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 108:34e6b704fe68 326 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 327 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 328 } CONTROL_Type;
Kojto 108:34e6b704fe68 329
Kojto 110:165afa46840b 330 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 333
Kojto 110:165afa46840b 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 336
Kojto 108:34e6b704fe68 337 /*@} end of group CMSIS_CORE */
Kojto 108:34e6b704fe68 338
Kojto 108:34e6b704fe68 339
Kojto 108:34e6b704fe68 340 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 108:34e6b704fe68 342 \brief Type definitions for the NVIC Registers
Kojto 108:34e6b704fe68 343 @{
Kojto 108:34e6b704fe68 344 */
Kojto 108:34e6b704fe68 345
Kojto 108:34e6b704fe68 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 108:34e6b704fe68 347 */
Kojto 108:34e6b704fe68 348 typedef struct
Kojto 108:34e6b704fe68 349 {
Kojto 108:34e6b704fe68 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 108:34e6b704fe68 351 uint32_t RESERVED0[31];
Kojto 108:34e6b704fe68 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 108:34e6b704fe68 353 uint32_t RSERVED1[31];
Kojto 108:34e6b704fe68 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 108:34e6b704fe68 355 uint32_t RESERVED2[31];
Kojto 108:34e6b704fe68 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 108:34e6b704fe68 357 uint32_t RESERVED3[31];
Kojto 108:34e6b704fe68 358 uint32_t RESERVED4[64];
Kojto 108:34e6b704fe68 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 108:34e6b704fe68 360 } NVIC_Type;
Kojto 108:34e6b704fe68 361
Kojto 108:34e6b704fe68 362 /*@} end of group CMSIS_NVIC */
Kojto 108:34e6b704fe68 363
Kojto 108:34e6b704fe68 364
Kojto 108:34e6b704fe68 365 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 366 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 108:34e6b704fe68 367 \brief Type definitions for the System Control Block Registers
Kojto 108:34e6b704fe68 368 @{
Kojto 108:34e6b704fe68 369 */
Kojto 108:34e6b704fe68 370
Kojto 108:34e6b704fe68 371 /** \brief Structure type to access the System Control Block (SCB).
Kojto 108:34e6b704fe68 372 */
Kojto 108:34e6b704fe68 373 typedef struct
Kojto 108:34e6b704fe68 374 {
Kojto 108:34e6b704fe68 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 108:34e6b704fe68 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 108:34e6b704fe68 377 #if (__VTOR_PRESENT == 1)
Kojto 108:34e6b704fe68 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 108:34e6b704fe68 379 #else
Kojto 108:34e6b704fe68 380 uint32_t RESERVED0;
Kojto 108:34e6b704fe68 381 #endif
Kojto 108:34e6b704fe68 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 108:34e6b704fe68 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 108:34e6b704fe68 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 108:34e6b704fe68 385 uint32_t RESERVED1;
Kojto 108:34e6b704fe68 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 108:34e6b704fe68 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 108:34e6b704fe68 388 } SCB_Type;
Kojto 108:34e6b704fe68 389
Kojto 108:34e6b704fe68 390 /* SCB CPUID Register Definitions */
Kojto 108:34e6b704fe68 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 108:34e6b704fe68 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 108:34e6b704fe68 393
Kojto 108:34e6b704fe68 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 108:34e6b704fe68 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 108:34e6b704fe68 396
Kojto 108:34e6b704fe68 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 108:34e6b704fe68 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 108:34e6b704fe68 399
Kojto 108:34e6b704fe68 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 108:34e6b704fe68 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 108:34e6b704fe68 402
Kojto 108:34e6b704fe68 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 108:34e6b704fe68 405
Kojto 108:34e6b704fe68 406 /* SCB Interrupt Control State Register Definitions */
Kojto 108:34e6b704fe68 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 108:34e6b704fe68 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 108:34e6b704fe68 409
Kojto 108:34e6b704fe68 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 108:34e6b704fe68 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 108:34e6b704fe68 412
Kojto 108:34e6b704fe68 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 108:34e6b704fe68 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 108:34e6b704fe68 415
Kojto 108:34e6b704fe68 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 108:34e6b704fe68 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 108:34e6b704fe68 418
Kojto 108:34e6b704fe68 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 108:34e6b704fe68 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 108:34e6b704fe68 421
Kojto 108:34e6b704fe68 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 108:34e6b704fe68 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 108:34e6b704fe68 424
Kojto 108:34e6b704fe68 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 108:34e6b704fe68 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 108:34e6b704fe68 427
Kojto 108:34e6b704fe68 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 108:34e6b704fe68 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 108:34e6b704fe68 430
Kojto 108:34e6b704fe68 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 108:34e6b704fe68 433
Kojto 108:34e6b704fe68 434 #if (__VTOR_PRESENT == 1)
Kojto 108:34e6b704fe68 435 /* SCB Interrupt Control State Register Definitions */
Kojto 108:34e6b704fe68 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 108:34e6b704fe68 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 108:34e6b704fe68 438 #endif
Kojto 108:34e6b704fe68 439
Kojto 108:34e6b704fe68 440 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 108:34e6b704fe68 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 108:34e6b704fe68 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 108:34e6b704fe68 443
Kojto 108:34e6b704fe68 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 108:34e6b704fe68 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 108:34e6b704fe68 446
Kojto 108:34e6b704fe68 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 108:34e6b704fe68 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 108:34e6b704fe68 449
Kojto 108:34e6b704fe68 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 108:34e6b704fe68 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 108:34e6b704fe68 452
Kojto 108:34e6b704fe68 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 108:34e6b704fe68 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 108:34e6b704fe68 455
Kojto 108:34e6b704fe68 456 /* SCB System Control Register Definitions */
Kojto 108:34e6b704fe68 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 108:34e6b704fe68 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 108:34e6b704fe68 459
Kojto 108:34e6b704fe68 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 108:34e6b704fe68 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 108:34e6b704fe68 462
Kojto 108:34e6b704fe68 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 108:34e6b704fe68 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 108:34e6b704fe68 465
Kojto 108:34e6b704fe68 466 /* SCB Configuration Control Register Definitions */
Kojto 108:34e6b704fe68 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 108:34e6b704fe68 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 108:34e6b704fe68 469
Kojto 108:34e6b704fe68 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 108:34e6b704fe68 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 108:34e6b704fe68 472
Kojto 108:34e6b704fe68 473 /* SCB System Handler Control and State Register Definitions */
Kojto 108:34e6b704fe68 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 108:34e6b704fe68 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 108:34e6b704fe68 476
Kojto 108:34e6b704fe68 477 /*@} end of group CMSIS_SCB */
Kojto 108:34e6b704fe68 478
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 108:34e6b704fe68 482 \brief Type definitions for the System Timer Registers.
Kojto 108:34e6b704fe68 483 @{
Kojto 108:34e6b704fe68 484 */
Kojto 108:34e6b704fe68 485
Kojto 108:34e6b704fe68 486 /** \brief Structure type to access the System Timer (SysTick).
Kojto 108:34e6b704fe68 487 */
Kojto 108:34e6b704fe68 488 typedef struct
Kojto 108:34e6b704fe68 489 {
Kojto 108:34e6b704fe68 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 108:34e6b704fe68 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 108:34e6b704fe68 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 108:34e6b704fe68 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 108:34e6b704fe68 494 } SysTick_Type;
Kojto 108:34e6b704fe68 495
Kojto 108:34e6b704fe68 496 /* SysTick Control / Status Register Definitions */
Kojto 108:34e6b704fe68 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 108:34e6b704fe68 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 108:34e6b704fe68 499
Kojto 108:34e6b704fe68 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 108:34e6b704fe68 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 108:34e6b704fe68 502
Kojto 108:34e6b704fe68 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 108:34e6b704fe68 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 108:34e6b704fe68 505
Kojto 108:34e6b704fe68 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 108:34e6b704fe68 508
Kojto 108:34e6b704fe68 509 /* SysTick Reload Register Definitions */
Kojto 108:34e6b704fe68 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 108:34e6b704fe68 512
Kojto 108:34e6b704fe68 513 /* SysTick Current Register Definitions */
Kojto 108:34e6b704fe68 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 108:34e6b704fe68 516
Kojto 108:34e6b704fe68 517 /* SysTick Calibration Register Definitions */
Kojto 108:34e6b704fe68 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 108:34e6b704fe68 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 108:34e6b704fe68 520
Kojto 108:34e6b704fe68 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 108:34e6b704fe68 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 108:34e6b704fe68 523
Kojto 108:34e6b704fe68 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 108:34e6b704fe68 526
Kojto 108:34e6b704fe68 527 /*@} end of group CMSIS_SysTick */
Kojto 108:34e6b704fe68 528
Kojto 108:34e6b704fe68 529 #if (__MPU_PRESENT == 1)
Kojto 108:34e6b704fe68 530 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 108:34e6b704fe68 532 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 108:34e6b704fe68 533 @{
Kojto 108:34e6b704fe68 534 */
Kojto 108:34e6b704fe68 535
Kojto 108:34e6b704fe68 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 108:34e6b704fe68 537 */
Kojto 108:34e6b704fe68 538 typedef struct
Kojto 108:34e6b704fe68 539 {
Kojto 108:34e6b704fe68 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 108:34e6b704fe68 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 108:34e6b704fe68 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 108:34e6b704fe68 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 108:34e6b704fe68 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 108:34e6b704fe68 545 } MPU_Type;
Kojto 108:34e6b704fe68 546
Kojto 108:34e6b704fe68 547 /* MPU Type Register */
Kojto 108:34e6b704fe68 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 108:34e6b704fe68 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 108:34e6b704fe68 550
Kojto 108:34e6b704fe68 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 108:34e6b704fe68 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 108:34e6b704fe68 553
Kojto 108:34e6b704fe68 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 108:34e6b704fe68 556
Kojto 108:34e6b704fe68 557 /* MPU Control Register */
Kojto 108:34e6b704fe68 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 108:34e6b704fe68 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 108:34e6b704fe68 560
Kojto 108:34e6b704fe68 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 108:34e6b704fe68 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 108:34e6b704fe68 563
Kojto 108:34e6b704fe68 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 108:34e6b704fe68 566
Kojto 108:34e6b704fe68 567 /* MPU Region Number Register */
Kojto 108:34e6b704fe68 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 108:34e6b704fe68 570
Kojto 108:34e6b704fe68 571 /* MPU Region Base Address Register */
Kojto 108:34e6b704fe68 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 108:34e6b704fe68 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 108:34e6b704fe68 574
Kojto 108:34e6b704fe68 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 108:34e6b704fe68 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 108:34e6b704fe68 577
Kojto 108:34e6b704fe68 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 108:34e6b704fe68 580
Kojto 108:34e6b704fe68 581 /* MPU Region Attribute and Size Register */
Kojto 108:34e6b704fe68 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 108:34e6b704fe68 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 108:34e6b704fe68 584
Kojto 108:34e6b704fe68 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 108:34e6b704fe68 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 108:34e6b704fe68 587
Kojto 108:34e6b704fe68 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 108:34e6b704fe68 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 108:34e6b704fe68 590
Kojto 108:34e6b704fe68 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 108:34e6b704fe68 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 108:34e6b704fe68 593
Kojto 108:34e6b704fe68 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 108:34e6b704fe68 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 108:34e6b704fe68 596
Kojto 108:34e6b704fe68 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 108:34e6b704fe68 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 108:34e6b704fe68 599
Kojto 108:34e6b704fe68 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 108:34e6b704fe68 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 108:34e6b704fe68 602
Kojto 108:34e6b704fe68 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 108:34e6b704fe68 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 108:34e6b704fe68 605
Kojto 108:34e6b704fe68 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 108:34e6b704fe68 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 108:34e6b704fe68 608
Kojto 108:34e6b704fe68 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 108:34e6b704fe68 611
Kojto 108:34e6b704fe68 612 /*@} end of group CMSIS_MPU */
Kojto 108:34e6b704fe68 613 #endif
Kojto 108:34e6b704fe68 614
Kojto 108:34e6b704fe68 615
Kojto 108:34e6b704fe68 616 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 108:34e6b704fe68 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 108:34e6b704fe68 619 are only accessible over DAP and not via processor. Therefore
Kojto 108:34e6b704fe68 620 they are not covered by the Cortex-M0 header file.
Kojto 108:34e6b704fe68 621 @{
Kojto 108:34e6b704fe68 622 */
Kojto 108:34e6b704fe68 623 /*@} end of group CMSIS_CoreDebug */
Kojto 108:34e6b704fe68 624
Kojto 108:34e6b704fe68 625
Kojto 108:34e6b704fe68 626 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 627 \defgroup CMSIS_core_base Core Definitions
Kojto 108:34e6b704fe68 628 \brief Definitions for base addresses, unions, and structures.
Kojto 108:34e6b704fe68 629 @{
Kojto 108:34e6b704fe68 630 */
Kojto 108:34e6b704fe68 631
Kojto 108:34e6b704fe68 632 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 108:34e6b704fe68 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 108:34e6b704fe68 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 108:34e6b704fe68 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 108:34e6b704fe68 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 108:34e6b704fe68 637
Kojto 108:34e6b704fe68 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 108:34e6b704fe68 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 108:34e6b704fe68 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 108:34e6b704fe68 641
Kojto 108:34e6b704fe68 642 #if (__MPU_PRESENT == 1)
Kojto 108:34e6b704fe68 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 108:34e6b704fe68 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 108:34e6b704fe68 645 #endif
Kojto 108:34e6b704fe68 646
Kojto 108:34e6b704fe68 647 /*@} */
Kojto 108:34e6b704fe68 648
Kojto 108:34e6b704fe68 649
Kojto 108:34e6b704fe68 650
Kojto 108:34e6b704fe68 651 /*******************************************************************************
Kojto 108:34e6b704fe68 652 * Hardware Abstraction Layer
Kojto 108:34e6b704fe68 653 Core Function Interface contains:
Kojto 108:34e6b704fe68 654 - Core NVIC Functions
Kojto 108:34e6b704fe68 655 - Core SysTick Functions
Kojto 108:34e6b704fe68 656 - Core Register Access Functions
Kojto 108:34e6b704fe68 657 ******************************************************************************/
Kojto 108:34e6b704fe68 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 108:34e6b704fe68 659 */
Kojto 108:34e6b704fe68 660
Kojto 108:34e6b704fe68 661
Kojto 108:34e6b704fe68 662
Kojto 108:34e6b704fe68 663 /* ########################## NVIC functions #################################### */
Kojto 108:34e6b704fe68 664 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 108:34e6b704fe68 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 108:34e6b704fe68 666 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 108:34e6b704fe68 667 @{
Kojto 108:34e6b704fe68 668 */
Kojto 108:34e6b704fe68 669
Kojto 108:34e6b704fe68 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 108:34e6b704fe68 671 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 108:34e6b704fe68 675
Kojto 108:34e6b704fe68 676
Kojto 108:34e6b704fe68 677 /** \brief Enable External Interrupt
Kojto 108:34e6b704fe68 678
Kojto 108:34e6b704fe68 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 108:34e6b704fe68 680
Kojto 108:34e6b704fe68 681 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 682 */
Kojto 108:34e6b704fe68 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 684 {
Kojto 110:165afa46840b 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 108:34e6b704fe68 686 }
Kojto 108:34e6b704fe68 687
Kojto 108:34e6b704fe68 688
Kojto 108:34e6b704fe68 689 /** \brief Disable External Interrupt
Kojto 108:34e6b704fe68 690
Kojto 108:34e6b704fe68 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 108:34e6b704fe68 692
Kojto 108:34e6b704fe68 693 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 694 */
Kojto 108:34e6b704fe68 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 696 {
Kojto 110:165afa46840b 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 108:34e6b704fe68 698 }
Kojto 108:34e6b704fe68 699
Kojto 108:34e6b704fe68 700
Kojto 108:34e6b704fe68 701 /** \brief Get Pending Interrupt
Kojto 108:34e6b704fe68 702
Kojto 108:34e6b704fe68 703 The function reads the pending register in the NVIC and returns the pending bit
Kojto 108:34e6b704fe68 704 for the specified interrupt.
Kojto 108:34e6b704fe68 705
Kojto 108:34e6b704fe68 706 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 707
Kojto 108:34e6b704fe68 708 \return 0 Interrupt status is not pending.
Kojto 108:34e6b704fe68 709 \return 1 Interrupt status is pending.
Kojto 108:34e6b704fe68 710 */
Kojto 108:34e6b704fe68 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 712 {
Kojto 110:165afa46840b 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 108:34e6b704fe68 714 }
Kojto 108:34e6b704fe68 715
Kojto 108:34e6b704fe68 716
Kojto 108:34e6b704fe68 717 /** \brief Set Pending Interrupt
Kojto 108:34e6b704fe68 718
Kojto 108:34e6b704fe68 719 The function sets the pending bit of an external interrupt.
Kojto 108:34e6b704fe68 720
Kojto 108:34e6b704fe68 721 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 722 */
Kojto 108:34e6b704fe68 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 724 {
Kojto 110:165afa46840b 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 108:34e6b704fe68 726 }
Kojto 108:34e6b704fe68 727
Kojto 108:34e6b704fe68 728
Kojto 108:34e6b704fe68 729 /** \brief Clear Pending Interrupt
Kojto 108:34e6b704fe68 730
Kojto 108:34e6b704fe68 731 The function clears the pending bit of an external interrupt.
Kojto 108:34e6b704fe68 732
Kojto 108:34e6b704fe68 733 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 734 */
Kojto 108:34e6b704fe68 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 736 {
Kojto 110:165afa46840b 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 108:34e6b704fe68 738 }
Kojto 108:34e6b704fe68 739
Kojto 108:34e6b704fe68 740
Kojto 108:34e6b704fe68 741 /** \brief Set Interrupt Priority
Kojto 108:34e6b704fe68 742
Kojto 108:34e6b704fe68 743 The function sets the priority of an interrupt.
Kojto 108:34e6b704fe68 744
Kojto 108:34e6b704fe68 745 \note The priority cannot be set for every core interrupt.
Kojto 108:34e6b704fe68 746
Kojto 108:34e6b704fe68 747 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 748 \param [in] priority Priority to set.
Kojto 108:34e6b704fe68 749 */
Kojto 108:34e6b704fe68 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 108:34e6b704fe68 751 {
Kojto 110:165afa46840b 752 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 755 }
Kojto 108:34e6b704fe68 756 else {
Kojto 110:165afa46840b 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 759 }
Kojto 108:34e6b704fe68 760 }
Kojto 108:34e6b704fe68 761
Kojto 108:34e6b704fe68 762
Kojto 108:34e6b704fe68 763 /** \brief Get Interrupt Priority
Kojto 108:34e6b704fe68 764
Kojto 108:34e6b704fe68 765 The function reads the priority of an interrupt. The interrupt
Kojto 108:34e6b704fe68 766 number can be positive to specify an external (device specific)
Kojto 108:34e6b704fe68 767 interrupt, or negative to specify an internal (core) interrupt.
Kojto 108:34e6b704fe68 768
Kojto 108:34e6b704fe68 769
Kojto 108:34e6b704fe68 770 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 771 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 108:34e6b704fe68 772 priority bits of the microcontroller.
Kojto 108:34e6b704fe68 773 */
Kojto 108:34e6b704fe68 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 775 {
Kojto 108:34e6b704fe68 776
Kojto 110:165afa46840b 777 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 779 }
Kojto 108:34e6b704fe68 780 else {
Kojto 110:165afa46840b 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 782 }
Kojto 108:34e6b704fe68 783 }
Kojto 108:34e6b704fe68 784
Kojto 108:34e6b704fe68 785
Kojto 108:34e6b704fe68 786 /** \brief System Reset
Kojto 108:34e6b704fe68 787
Kojto 108:34e6b704fe68 788 The function initiates a system reset request to reset the MCU.
Kojto 108:34e6b704fe68 789 */
Kojto 108:34e6b704fe68 790 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 108:34e6b704fe68 791 {
Kojto 108:34e6b704fe68 792 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 108:34e6b704fe68 793 buffered write are completed before reset */
Kojto 110:165afa46840b 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 108:34e6b704fe68 795 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 108:34e6b704fe68 796 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 797 while(1) { __NOP(); } /* wait until reset */
Kojto 108:34e6b704fe68 798 }
Kojto 108:34e6b704fe68 799
Kojto 108:34e6b704fe68 800 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 108:34e6b704fe68 801
Kojto 108:34e6b704fe68 802
Kojto 108:34e6b704fe68 803
Kojto 108:34e6b704fe68 804 /* ################################## SysTick function ############################################ */
Kojto 108:34e6b704fe68 805 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 108:34e6b704fe68 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 108:34e6b704fe68 807 \brief Functions that configure the System.
Kojto 108:34e6b704fe68 808 @{
Kojto 108:34e6b704fe68 809 */
Kojto 108:34e6b704fe68 810
Kojto 108:34e6b704fe68 811 #if (__Vendor_SysTickConfig == 0)
Kojto 108:34e6b704fe68 812
Kojto 108:34e6b704fe68 813 /** \brief System Tick Configuration
Kojto 108:34e6b704fe68 814
Kojto 108:34e6b704fe68 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 108:34e6b704fe68 816 Counter is in free running mode to generate periodic interrupts.
Kojto 108:34e6b704fe68 817
Kojto 108:34e6b704fe68 818 \param [in] ticks Number of ticks between two interrupts.
Kojto 108:34e6b704fe68 819
Kojto 108:34e6b704fe68 820 \return 0 Function succeeded.
Kojto 108:34e6b704fe68 821 \return 1 Function failed.
Kojto 108:34e6b704fe68 822
Kojto 108:34e6b704fe68 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 108:34e6b704fe68 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 108:34e6b704fe68 825 must contain a vendor-specific implementation of this function.
Kojto 108:34e6b704fe68 826
Kojto 108:34e6b704fe68 827 */
Kojto 108:34e6b704fe68 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 108:34e6b704fe68 829 {
Kojto 110:165afa46840b 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 108:34e6b704fe68 831
Kojto 110:165afa46840b 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 108:34e6b704fe68 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 108:34e6b704fe68 836 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 838 return (0UL); /* Function successful */
Kojto 108:34e6b704fe68 839 }
Kojto 108:34e6b704fe68 840
Kojto 108:34e6b704fe68 841 #endif
Kojto 108:34e6b704fe68 842
Kojto 108:34e6b704fe68 843 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 108:34e6b704fe68 844
Kojto 108:34e6b704fe68 845
Kojto 108:34e6b704fe68 846
Kojto 108:34e6b704fe68 847
Kojto 110:165afa46840b 848 #ifdef __cplusplus
Kojto 110:165afa46840b 849 }
Kojto 110:165afa46840b 850 #endif
Kojto 110:165afa46840b 851
Kojto 108:34e6b704fe68 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 108:34e6b704fe68 853
Kojto 108:34e6b704fe68 854 #endif /* __CMSIS_GENERIC */