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mbed 2

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TARGET_ARM_MPS2_BEID/core_cm0plus.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Child:
110:165afa46840b
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 108:34e6b704fe68 1 /**************************************************************************//**
Kojto 108:34e6b704fe68 2 * @file core_cm0plus.h
Kojto 108:34e6b704fe68 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 108:34e6b704fe68 4 * @version V3.20
Kojto 108:34e6b704fe68 5 * @date 25. February 2013
Kojto 108:34e6b704fe68 6 *
Kojto 108:34e6b704fe68 7 * @note
Kojto 108:34e6b704fe68 8 *
Kojto 108:34e6b704fe68 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 108:34e6b704fe68 11
Kojto 108:34e6b704fe68 12 All rights reserved.
Kojto 108:34e6b704fe68 13 Redistribution and use in source and binary forms, with or without
Kojto 108:34e6b704fe68 14 modification, are permitted provided that the following conditions are met:
Kojto 108:34e6b704fe68 15 - Redistributions of source code must retain the above copyright
Kojto 108:34e6b704fe68 16 notice, this list of conditions and the following disclaimer.
Kojto 108:34e6b704fe68 17 - Redistributions in binary form must reproduce the above copyright
Kojto 108:34e6b704fe68 18 notice, this list of conditions and the following disclaimer in the
Kojto 108:34e6b704fe68 19 documentation and/or other materials provided with the distribution.
Kojto 108:34e6b704fe68 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 108:34e6b704fe68 21 to endorse or promote products derived from this software without
Kojto 108:34e6b704fe68 22 specific prior written permission.
Kojto 108:34e6b704fe68 23 *
Kojto 108:34e6b704fe68 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 108:34e6b704fe68 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 108:34e6b704fe68 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 108:34e6b704fe68 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 108:34e6b704fe68 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 108:34e6b704fe68 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 108:34e6b704fe68 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 108:34e6b704fe68 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 108:34e6b704fe68 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 108:34e6b704fe68 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 108:34e6b704fe68 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 108:34e6b704fe68 35 ---------------------------------------------------------------------------*/
Kojto 108:34e6b704fe68 36
Kojto 108:34e6b704fe68 37
Kojto 108:34e6b704fe68 38 #if defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 108:34e6b704fe68 40 #endif
Kojto 108:34e6b704fe68 41
Kojto 108:34e6b704fe68 42 #ifdef __cplusplus
Kojto 108:34e6b704fe68 43 extern "C" {
Kojto 108:34e6b704fe68 44 #endif
Kojto 108:34e6b704fe68 45
Kojto 108:34e6b704fe68 46 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 108:34e6b704fe68 47 #define __CORE_CM0PLUS_H_GENERIC
Kojto 108:34e6b704fe68 48
Kojto 108:34e6b704fe68 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 108:34e6b704fe68 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 108:34e6b704fe68 51
Kojto 108:34e6b704fe68 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 108:34e6b704fe68 53 Function definitions in header files are used to allow 'inlining'.
Kojto 108:34e6b704fe68 54
Kojto 108:34e6b704fe68 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 108:34e6b704fe68 56 Unions are used for effective representation of core registers.
Kojto 108:34e6b704fe68 57
Kojto 108:34e6b704fe68 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 108:34e6b704fe68 59 Function-like macros are used to allow more efficient code.
Kojto 108:34e6b704fe68 60 */
Kojto 108:34e6b704fe68 61
Kojto 108:34e6b704fe68 62
Kojto 108:34e6b704fe68 63 /*******************************************************************************
Kojto 108:34e6b704fe68 64 * CMSIS definitions
Kojto 108:34e6b704fe68 65 ******************************************************************************/
Kojto 108:34e6b704fe68 66 /** \ingroup Cortex-M0+
Kojto 108:34e6b704fe68 67 @{
Kojto 108:34e6b704fe68 68 */
Kojto 108:34e6b704fe68 69
Kojto 108:34e6b704fe68 70 /* CMSIS CM0P definitions */
Kojto 108:34e6b704fe68 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 108:34e6b704fe68 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 108:34e6b704fe68 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 108:34e6b704fe68 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 108:34e6b704fe68 75
Kojto 108:34e6b704fe68 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 108:34e6b704fe68 77
Kojto 108:34e6b704fe68 78
Kojto 108:34e6b704fe68 79 #if defined ( __CC_ARM )
Kojto 108:34e6b704fe68 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 108:34e6b704fe68 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 108:34e6b704fe68 82 #define __STATIC_INLINE static __inline
Kojto 108:34e6b704fe68 83
Kojto 108:34e6b704fe68 84 #elif defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 108:34e6b704fe68 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 108:34e6b704fe68 87 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 88
Kojto 108:34e6b704fe68 89 #elif defined ( __GNUC__ )
Kojto 108:34e6b704fe68 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 108:34e6b704fe68 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 108:34e6b704fe68 92 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 93
Kojto 108:34e6b704fe68 94 #elif defined ( __TASKING__ )
Kojto 108:34e6b704fe68 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 108:34e6b704fe68 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 108:34e6b704fe68 97 #define __STATIC_INLINE static inline
Kojto 108:34e6b704fe68 98
Kojto 108:34e6b704fe68 99 #endif
Kojto 108:34e6b704fe68 100
Kojto 108:34e6b704fe68 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 108:34e6b704fe68 102 */
Kojto 108:34e6b704fe68 103 #define __FPU_USED 0
Kojto 108:34e6b704fe68 104
Kojto 108:34e6b704fe68 105 #if defined ( __CC_ARM )
Kojto 108:34e6b704fe68 106 #if defined __TARGET_FPU_VFP
Kojto 108:34e6b704fe68 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 108 #endif
Kojto 108:34e6b704fe68 109
Kojto 108:34e6b704fe68 110 #elif defined ( __ICCARM__ )
Kojto 108:34e6b704fe68 111 #if defined __ARMVFP__
Kojto 108:34e6b704fe68 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 113 #endif
Kojto 108:34e6b704fe68 114
Kojto 108:34e6b704fe68 115 #elif defined ( __GNUC__ )
Kojto 108:34e6b704fe68 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 108:34e6b704fe68 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 118 #endif
Kojto 108:34e6b704fe68 119
Kojto 108:34e6b704fe68 120 #elif defined ( __TASKING__ )
Kojto 108:34e6b704fe68 121 #if defined __FPU_VFP__
Kojto 108:34e6b704fe68 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 108:34e6b704fe68 123 #endif
Kojto 108:34e6b704fe68 124 #endif
Kojto 108:34e6b704fe68 125
Kojto 108:34e6b704fe68 126 #include <stdint.h> /* standard types definitions */
Kojto 108:34e6b704fe68 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 108:34e6b704fe68 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 108:34e6b704fe68 129
Kojto 108:34e6b704fe68 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 108:34e6b704fe68 131
Kojto 108:34e6b704fe68 132 #ifndef __CMSIS_GENERIC
Kojto 108:34e6b704fe68 133
Kojto 108:34e6b704fe68 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 108:34e6b704fe68 135 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 108:34e6b704fe68 136
Kojto 108:34e6b704fe68 137 /* check device defines and use defaults */
Kojto 108:34e6b704fe68 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 108:34e6b704fe68 139 #ifndef __CM0PLUS_REV
Kojto 108:34e6b704fe68 140 #define __CM0PLUS_REV 0x0000
Kojto 108:34e6b704fe68 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 108:34e6b704fe68 142 #endif
Kojto 108:34e6b704fe68 143
Kojto 108:34e6b704fe68 144 #ifndef __MPU_PRESENT
Kojto 108:34e6b704fe68 145 #define __MPU_PRESENT 0
Kojto 108:34e6b704fe68 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 108:34e6b704fe68 147 #endif
Kojto 108:34e6b704fe68 148
Kojto 108:34e6b704fe68 149 #ifndef __VTOR_PRESENT
Kojto 108:34e6b704fe68 150 #define __VTOR_PRESENT 0
Kojto 108:34e6b704fe68 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 108:34e6b704fe68 152 #endif
Kojto 108:34e6b704fe68 153
Kojto 108:34e6b704fe68 154 #ifndef __NVIC_PRIO_BITS
Kojto 108:34e6b704fe68 155 #define __NVIC_PRIO_BITS 2
Kojto 108:34e6b704fe68 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 108:34e6b704fe68 157 #endif
Kojto 108:34e6b704fe68 158
Kojto 108:34e6b704fe68 159 #ifndef __Vendor_SysTickConfig
Kojto 108:34e6b704fe68 160 #define __Vendor_SysTickConfig 0
Kojto 108:34e6b704fe68 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 108:34e6b704fe68 162 #endif
Kojto 108:34e6b704fe68 163 #endif
Kojto 108:34e6b704fe68 164
Kojto 108:34e6b704fe68 165 /* IO definitions (access restrictions to peripheral registers) */
Kojto 108:34e6b704fe68 166 /**
Kojto 108:34e6b704fe68 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 108:34e6b704fe68 168
Kojto 108:34e6b704fe68 169 <strong>IO Type Qualifiers</strong> are used
Kojto 108:34e6b704fe68 170 \li to specify the access to peripheral variables.
Kojto 108:34e6b704fe68 171 \li for automatic generation of peripheral register debug information.
Kojto 108:34e6b704fe68 172 */
Kojto 108:34e6b704fe68 173 #ifdef __cplusplus
Kojto 108:34e6b704fe68 174 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 108:34e6b704fe68 175 #else
Kojto 108:34e6b704fe68 176 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 108:34e6b704fe68 177 #endif
Kojto 108:34e6b704fe68 178 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 108:34e6b704fe68 179 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 108:34e6b704fe68 180
Kojto 108:34e6b704fe68 181 /*@} end of group Cortex-M0+ */
Kojto 108:34e6b704fe68 182
Kojto 108:34e6b704fe68 183
Kojto 108:34e6b704fe68 184
Kojto 108:34e6b704fe68 185 /*******************************************************************************
Kojto 108:34e6b704fe68 186 * Register Abstraction
Kojto 108:34e6b704fe68 187 Core Register contain:
Kojto 108:34e6b704fe68 188 - Core Register
Kojto 108:34e6b704fe68 189 - Core NVIC Register
Kojto 108:34e6b704fe68 190 - Core SCB Register
Kojto 108:34e6b704fe68 191 - Core SysTick Register
Kojto 108:34e6b704fe68 192 - Core MPU Register
Kojto 108:34e6b704fe68 193 ******************************************************************************/
Kojto 108:34e6b704fe68 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 108:34e6b704fe68 195 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 108:34e6b704fe68 196 */
Kojto 108:34e6b704fe68 197
Kojto 108:34e6b704fe68 198 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 199 \defgroup CMSIS_CORE Status and Control Registers
Kojto 108:34e6b704fe68 200 \brief Core Register type definitions.
Kojto 108:34e6b704fe68 201 @{
Kojto 108:34e6b704fe68 202 */
Kojto 108:34e6b704fe68 203
Kojto 108:34e6b704fe68 204 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 108:34e6b704fe68 205 */
Kojto 108:34e6b704fe68 206 typedef union
Kojto 108:34e6b704fe68 207 {
Kojto 108:34e6b704fe68 208 struct
Kojto 108:34e6b704fe68 209 {
Kojto 108:34e6b704fe68 210 #if (__CORTEX_M != 0x04)
Kojto 108:34e6b704fe68 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 108:34e6b704fe68 212 #else
Kojto 108:34e6b704fe68 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 108:34e6b704fe68 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 108:34e6b704fe68 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 108:34e6b704fe68 216 #endif
Kojto 108:34e6b704fe68 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 108:34e6b704fe68 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 108:34e6b704fe68 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 108:34e6b704fe68 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 108:34e6b704fe68 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 108:34e6b704fe68 222 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 223 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 224 } APSR_Type;
Kojto 108:34e6b704fe68 225
Kojto 108:34e6b704fe68 226
Kojto 108:34e6b704fe68 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 108:34e6b704fe68 228 */
Kojto 108:34e6b704fe68 229 typedef union
Kojto 108:34e6b704fe68 230 {
Kojto 108:34e6b704fe68 231 struct
Kojto 108:34e6b704fe68 232 {
Kojto 108:34e6b704fe68 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 108:34e6b704fe68 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 108:34e6b704fe68 235 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 236 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 237 } IPSR_Type;
Kojto 108:34e6b704fe68 238
Kojto 108:34e6b704fe68 239
Kojto 108:34e6b704fe68 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 108:34e6b704fe68 241 */
Kojto 108:34e6b704fe68 242 typedef union
Kojto 108:34e6b704fe68 243 {
Kojto 108:34e6b704fe68 244 struct
Kojto 108:34e6b704fe68 245 {
Kojto 108:34e6b704fe68 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 108:34e6b704fe68 247 #if (__CORTEX_M != 0x04)
Kojto 108:34e6b704fe68 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 108:34e6b704fe68 249 #else
Kojto 108:34e6b704fe68 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 108:34e6b704fe68 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 108:34e6b704fe68 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 108:34e6b704fe68 253 #endif
Kojto 108:34e6b704fe68 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 108:34e6b704fe68 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 108:34e6b704fe68 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 108:34e6b704fe68 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 108:34e6b704fe68 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 108:34e6b704fe68 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 108:34e6b704fe68 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 108:34e6b704fe68 261 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 262 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 263 } xPSR_Type;
Kojto 108:34e6b704fe68 264
Kojto 108:34e6b704fe68 265
Kojto 108:34e6b704fe68 266 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 108:34e6b704fe68 267 */
Kojto 108:34e6b704fe68 268 typedef union
Kojto 108:34e6b704fe68 269 {
Kojto 108:34e6b704fe68 270 struct
Kojto 108:34e6b704fe68 271 {
Kojto 108:34e6b704fe68 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 108:34e6b704fe68 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 108:34e6b704fe68 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 108:34e6b704fe68 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 108:34e6b704fe68 276 } b; /*!< Structure used for bit access */
Kojto 108:34e6b704fe68 277 uint32_t w; /*!< Type used for word access */
Kojto 108:34e6b704fe68 278 } CONTROL_Type;
Kojto 108:34e6b704fe68 279
Kojto 108:34e6b704fe68 280 /*@} end of group CMSIS_CORE */
Kojto 108:34e6b704fe68 281
Kojto 108:34e6b704fe68 282
Kojto 108:34e6b704fe68 283 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 108:34e6b704fe68 285 \brief Type definitions for the NVIC Registers
Kojto 108:34e6b704fe68 286 @{
Kojto 108:34e6b704fe68 287 */
Kojto 108:34e6b704fe68 288
Kojto 108:34e6b704fe68 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 108:34e6b704fe68 290 */
Kojto 108:34e6b704fe68 291 typedef struct
Kojto 108:34e6b704fe68 292 {
Kojto 108:34e6b704fe68 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 108:34e6b704fe68 294 uint32_t RESERVED0[31];
Kojto 108:34e6b704fe68 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 108:34e6b704fe68 296 uint32_t RSERVED1[31];
Kojto 108:34e6b704fe68 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 108:34e6b704fe68 298 uint32_t RESERVED2[31];
Kojto 108:34e6b704fe68 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 108:34e6b704fe68 300 uint32_t RESERVED3[31];
Kojto 108:34e6b704fe68 301 uint32_t RESERVED4[64];
Kojto 108:34e6b704fe68 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 108:34e6b704fe68 303 } NVIC_Type;
Kojto 108:34e6b704fe68 304
Kojto 108:34e6b704fe68 305 /*@} end of group CMSIS_NVIC */
Kojto 108:34e6b704fe68 306
Kojto 108:34e6b704fe68 307
Kojto 108:34e6b704fe68 308 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 309 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 108:34e6b704fe68 310 \brief Type definitions for the System Control Block Registers
Kojto 108:34e6b704fe68 311 @{
Kojto 108:34e6b704fe68 312 */
Kojto 108:34e6b704fe68 313
Kojto 108:34e6b704fe68 314 /** \brief Structure type to access the System Control Block (SCB).
Kojto 108:34e6b704fe68 315 */
Kojto 108:34e6b704fe68 316 typedef struct
Kojto 108:34e6b704fe68 317 {
Kojto 108:34e6b704fe68 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 108:34e6b704fe68 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 108:34e6b704fe68 320 #if (__VTOR_PRESENT == 1)
Kojto 108:34e6b704fe68 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 108:34e6b704fe68 322 #else
Kojto 108:34e6b704fe68 323 uint32_t RESERVED0;
Kojto 108:34e6b704fe68 324 #endif
Kojto 108:34e6b704fe68 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 108:34e6b704fe68 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 108:34e6b704fe68 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 108:34e6b704fe68 328 uint32_t RESERVED1;
Kojto 108:34e6b704fe68 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 108:34e6b704fe68 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 108:34e6b704fe68 331 } SCB_Type;
Kojto 108:34e6b704fe68 332
Kojto 108:34e6b704fe68 333 /* SCB CPUID Register Definitions */
Kojto 108:34e6b704fe68 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 108:34e6b704fe68 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 108:34e6b704fe68 336
Kojto 108:34e6b704fe68 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 108:34e6b704fe68 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 108:34e6b704fe68 339
Kojto 108:34e6b704fe68 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 108:34e6b704fe68 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 108:34e6b704fe68 342
Kojto 108:34e6b704fe68 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 108:34e6b704fe68 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 108:34e6b704fe68 345
Kojto 108:34e6b704fe68 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 108:34e6b704fe68 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 108:34e6b704fe68 348
Kojto 108:34e6b704fe68 349 /* SCB Interrupt Control State Register Definitions */
Kojto 108:34e6b704fe68 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 108:34e6b704fe68 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 108:34e6b704fe68 352
Kojto 108:34e6b704fe68 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 108:34e6b704fe68 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 108:34e6b704fe68 355
Kojto 108:34e6b704fe68 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 108:34e6b704fe68 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 108:34e6b704fe68 358
Kojto 108:34e6b704fe68 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 108:34e6b704fe68 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 108:34e6b704fe68 361
Kojto 108:34e6b704fe68 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 108:34e6b704fe68 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 108:34e6b704fe68 364
Kojto 108:34e6b704fe68 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 108:34e6b704fe68 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 108:34e6b704fe68 367
Kojto 108:34e6b704fe68 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 108:34e6b704fe68 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 108:34e6b704fe68 370
Kojto 108:34e6b704fe68 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 108:34e6b704fe68 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 108:34e6b704fe68 373
Kojto 108:34e6b704fe68 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 108:34e6b704fe68 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 108:34e6b704fe68 376
Kojto 108:34e6b704fe68 377 #if (__VTOR_PRESENT == 1)
Kojto 108:34e6b704fe68 378 /* SCB Interrupt Control State Register Definitions */
Kojto 108:34e6b704fe68 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 108:34e6b704fe68 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 108:34e6b704fe68 381 #endif
Kojto 108:34e6b704fe68 382
Kojto 108:34e6b704fe68 383 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 108:34e6b704fe68 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 108:34e6b704fe68 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 108:34e6b704fe68 386
Kojto 108:34e6b704fe68 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 108:34e6b704fe68 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 108:34e6b704fe68 389
Kojto 108:34e6b704fe68 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 108:34e6b704fe68 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 108:34e6b704fe68 392
Kojto 108:34e6b704fe68 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 108:34e6b704fe68 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 108:34e6b704fe68 395
Kojto 108:34e6b704fe68 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 108:34e6b704fe68 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 108:34e6b704fe68 398
Kojto 108:34e6b704fe68 399 /* SCB System Control Register Definitions */
Kojto 108:34e6b704fe68 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 108:34e6b704fe68 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 108:34e6b704fe68 402
Kojto 108:34e6b704fe68 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 108:34e6b704fe68 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 108:34e6b704fe68 405
Kojto 108:34e6b704fe68 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 108:34e6b704fe68 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 108:34e6b704fe68 408
Kojto 108:34e6b704fe68 409 /* SCB Configuration Control Register Definitions */
Kojto 108:34e6b704fe68 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 108:34e6b704fe68 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 108:34e6b704fe68 412
Kojto 108:34e6b704fe68 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 108:34e6b704fe68 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 108:34e6b704fe68 415
Kojto 108:34e6b704fe68 416 /* SCB System Handler Control and State Register Definitions */
Kojto 108:34e6b704fe68 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 108:34e6b704fe68 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 108:34e6b704fe68 419
Kojto 108:34e6b704fe68 420 /*@} end of group CMSIS_SCB */
Kojto 108:34e6b704fe68 421
Kojto 108:34e6b704fe68 422
Kojto 108:34e6b704fe68 423 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 108:34e6b704fe68 425 \brief Type definitions for the System Timer Registers.
Kojto 108:34e6b704fe68 426 @{
Kojto 108:34e6b704fe68 427 */
Kojto 108:34e6b704fe68 428
Kojto 108:34e6b704fe68 429 /** \brief Structure type to access the System Timer (SysTick).
Kojto 108:34e6b704fe68 430 */
Kojto 108:34e6b704fe68 431 typedef struct
Kojto 108:34e6b704fe68 432 {
Kojto 108:34e6b704fe68 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 108:34e6b704fe68 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 108:34e6b704fe68 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 108:34e6b704fe68 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 108:34e6b704fe68 437 } SysTick_Type;
Kojto 108:34e6b704fe68 438
Kojto 108:34e6b704fe68 439 /* SysTick Control / Status Register Definitions */
Kojto 108:34e6b704fe68 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 108:34e6b704fe68 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 108:34e6b704fe68 442
Kojto 108:34e6b704fe68 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 108:34e6b704fe68 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 108:34e6b704fe68 445
Kojto 108:34e6b704fe68 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 108:34e6b704fe68 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 108:34e6b704fe68 448
Kojto 108:34e6b704fe68 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 108:34e6b704fe68 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 108:34e6b704fe68 451
Kojto 108:34e6b704fe68 452 /* SysTick Reload Register Definitions */
Kojto 108:34e6b704fe68 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 108:34e6b704fe68 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 108:34e6b704fe68 455
Kojto 108:34e6b704fe68 456 /* SysTick Current Register Definitions */
Kojto 108:34e6b704fe68 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 108:34e6b704fe68 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 108:34e6b704fe68 459
Kojto 108:34e6b704fe68 460 /* SysTick Calibration Register Definitions */
Kojto 108:34e6b704fe68 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 108:34e6b704fe68 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 108:34e6b704fe68 463
Kojto 108:34e6b704fe68 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 108:34e6b704fe68 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 108:34e6b704fe68 466
Kojto 108:34e6b704fe68 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 108:34e6b704fe68 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 108:34e6b704fe68 469
Kojto 108:34e6b704fe68 470 /*@} end of group CMSIS_SysTick */
Kojto 108:34e6b704fe68 471
Kojto 108:34e6b704fe68 472 #if (__MPU_PRESENT == 1)
Kojto 108:34e6b704fe68 473 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 108:34e6b704fe68 475 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 108:34e6b704fe68 476 @{
Kojto 108:34e6b704fe68 477 */
Kojto 108:34e6b704fe68 478
Kojto 108:34e6b704fe68 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 108:34e6b704fe68 480 */
Kojto 108:34e6b704fe68 481 typedef struct
Kojto 108:34e6b704fe68 482 {
Kojto 108:34e6b704fe68 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 108:34e6b704fe68 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 108:34e6b704fe68 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 108:34e6b704fe68 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 108:34e6b704fe68 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 108:34e6b704fe68 488 } MPU_Type;
Kojto 108:34e6b704fe68 489
Kojto 108:34e6b704fe68 490 /* MPU Type Register */
Kojto 108:34e6b704fe68 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 108:34e6b704fe68 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 108:34e6b704fe68 493
Kojto 108:34e6b704fe68 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 108:34e6b704fe68 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 108:34e6b704fe68 496
Kojto 108:34e6b704fe68 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 108:34e6b704fe68 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Kojto 108:34e6b704fe68 499
Kojto 108:34e6b704fe68 500 /* MPU Control Register */
Kojto 108:34e6b704fe68 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 108:34e6b704fe68 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 108:34e6b704fe68 503
Kojto 108:34e6b704fe68 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 108:34e6b704fe68 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 108:34e6b704fe68 506
Kojto 108:34e6b704fe68 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 108:34e6b704fe68 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Kojto 108:34e6b704fe68 509
Kojto 108:34e6b704fe68 510 /* MPU Region Number Register */
Kojto 108:34e6b704fe68 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 108:34e6b704fe68 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Kojto 108:34e6b704fe68 513
Kojto 108:34e6b704fe68 514 /* MPU Region Base Address Register */
Kojto 108:34e6b704fe68 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 108:34e6b704fe68 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 108:34e6b704fe68 517
Kojto 108:34e6b704fe68 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 108:34e6b704fe68 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 108:34e6b704fe68 520
Kojto 108:34e6b704fe68 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 108:34e6b704fe68 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Kojto 108:34e6b704fe68 523
Kojto 108:34e6b704fe68 524 /* MPU Region Attribute and Size Register */
Kojto 108:34e6b704fe68 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 108:34e6b704fe68 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 108:34e6b704fe68 527
Kojto 108:34e6b704fe68 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 108:34e6b704fe68 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 108:34e6b704fe68 530
Kojto 108:34e6b704fe68 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 108:34e6b704fe68 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 108:34e6b704fe68 533
Kojto 108:34e6b704fe68 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 108:34e6b704fe68 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 108:34e6b704fe68 536
Kojto 108:34e6b704fe68 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 108:34e6b704fe68 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 108:34e6b704fe68 539
Kojto 108:34e6b704fe68 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 108:34e6b704fe68 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 108:34e6b704fe68 542
Kojto 108:34e6b704fe68 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 108:34e6b704fe68 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 108:34e6b704fe68 545
Kojto 108:34e6b704fe68 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 108:34e6b704fe68 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 108:34e6b704fe68 548
Kojto 108:34e6b704fe68 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 108:34e6b704fe68 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 108:34e6b704fe68 551
Kojto 108:34e6b704fe68 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 108:34e6b704fe68 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 108:34e6b704fe68 554
Kojto 108:34e6b704fe68 555 /*@} end of group CMSIS_MPU */
Kojto 108:34e6b704fe68 556 #endif
Kojto 108:34e6b704fe68 557
Kojto 108:34e6b704fe68 558
Kojto 108:34e6b704fe68 559 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 108:34e6b704fe68 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 108:34e6b704fe68 562 are only accessible over DAP and not via processor. Therefore
Kojto 108:34e6b704fe68 563 they are not covered by the Cortex-M0 header file.
Kojto 108:34e6b704fe68 564 @{
Kojto 108:34e6b704fe68 565 */
Kojto 108:34e6b704fe68 566 /*@} end of group CMSIS_CoreDebug */
Kojto 108:34e6b704fe68 567
Kojto 108:34e6b704fe68 568
Kojto 108:34e6b704fe68 569 /** \ingroup CMSIS_core_register
Kojto 108:34e6b704fe68 570 \defgroup CMSIS_core_base Core Definitions
Kojto 108:34e6b704fe68 571 \brief Definitions for base addresses, unions, and structures.
Kojto 108:34e6b704fe68 572 @{
Kojto 108:34e6b704fe68 573 */
Kojto 108:34e6b704fe68 574
Kojto 108:34e6b704fe68 575 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 108:34e6b704fe68 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 108:34e6b704fe68 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 108:34e6b704fe68 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 108:34e6b704fe68 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 108:34e6b704fe68 580
Kojto 108:34e6b704fe68 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 108:34e6b704fe68 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 108:34e6b704fe68 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 108:34e6b704fe68 584
Kojto 108:34e6b704fe68 585 #if (__MPU_PRESENT == 1)
Kojto 108:34e6b704fe68 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 108:34e6b704fe68 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 108:34e6b704fe68 588 #endif
Kojto 108:34e6b704fe68 589
Kojto 108:34e6b704fe68 590 /*@} */
Kojto 108:34e6b704fe68 591
Kojto 108:34e6b704fe68 592
Kojto 108:34e6b704fe68 593
Kojto 108:34e6b704fe68 594 /*******************************************************************************
Kojto 108:34e6b704fe68 595 * Hardware Abstraction Layer
Kojto 108:34e6b704fe68 596 Core Function Interface contains:
Kojto 108:34e6b704fe68 597 - Core NVIC Functions
Kojto 108:34e6b704fe68 598 - Core SysTick Functions
Kojto 108:34e6b704fe68 599 - Core Register Access Functions
Kojto 108:34e6b704fe68 600 ******************************************************************************/
Kojto 108:34e6b704fe68 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 108:34e6b704fe68 602 */
Kojto 108:34e6b704fe68 603
Kojto 108:34e6b704fe68 604
Kojto 108:34e6b704fe68 605
Kojto 108:34e6b704fe68 606 /* ########################## NVIC functions #################################### */
Kojto 108:34e6b704fe68 607 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 108:34e6b704fe68 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 108:34e6b704fe68 609 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 108:34e6b704fe68 610 @{
Kojto 108:34e6b704fe68 611 */
Kojto 108:34e6b704fe68 612
Kojto 108:34e6b704fe68 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 108:34e6b704fe68 614 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 108:34e6b704fe68 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 108:34e6b704fe68 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 108:34e6b704fe68 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 108:34e6b704fe68 618
Kojto 108:34e6b704fe68 619
Kojto 108:34e6b704fe68 620 /** \brief Enable External Interrupt
Kojto 108:34e6b704fe68 621
Kojto 108:34e6b704fe68 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 108:34e6b704fe68 623
Kojto 108:34e6b704fe68 624 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 625 */
Kojto 108:34e6b704fe68 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 627 {
Kojto 108:34e6b704fe68 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 108:34e6b704fe68 629 }
Kojto 108:34e6b704fe68 630
Kojto 108:34e6b704fe68 631
Kojto 108:34e6b704fe68 632 /** \brief Disable External Interrupt
Kojto 108:34e6b704fe68 633
Kojto 108:34e6b704fe68 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 108:34e6b704fe68 635
Kojto 108:34e6b704fe68 636 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 637 */
Kojto 108:34e6b704fe68 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 639 {
Kojto 108:34e6b704fe68 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 108:34e6b704fe68 641 }
Kojto 108:34e6b704fe68 642
Kojto 108:34e6b704fe68 643
Kojto 108:34e6b704fe68 644 /** \brief Get Pending Interrupt
Kojto 108:34e6b704fe68 645
Kojto 108:34e6b704fe68 646 The function reads the pending register in the NVIC and returns the pending bit
Kojto 108:34e6b704fe68 647 for the specified interrupt.
Kojto 108:34e6b704fe68 648
Kojto 108:34e6b704fe68 649 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 650
Kojto 108:34e6b704fe68 651 \return 0 Interrupt status is not pending.
Kojto 108:34e6b704fe68 652 \return 1 Interrupt status is pending.
Kojto 108:34e6b704fe68 653 */
Kojto 108:34e6b704fe68 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 655 {
Kojto 108:34e6b704fe68 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 108:34e6b704fe68 657 }
Kojto 108:34e6b704fe68 658
Kojto 108:34e6b704fe68 659
Kojto 108:34e6b704fe68 660 /** \brief Set Pending Interrupt
Kojto 108:34e6b704fe68 661
Kojto 108:34e6b704fe68 662 The function sets the pending bit of an external interrupt.
Kojto 108:34e6b704fe68 663
Kojto 108:34e6b704fe68 664 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 665 */
Kojto 108:34e6b704fe68 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 667 {
Kojto 108:34e6b704fe68 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 108:34e6b704fe68 669 }
Kojto 108:34e6b704fe68 670
Kojto 108:34e6b704fe68 671
Kojto 108:34e6b704fe68 672 /** \brief Clear Pending Interrupt
Kojto 108:34e6b704fe68 673
Kojto 108:34e6b704fe68 674 The function clears the pending bit of an external interrupt.
Kojto 108:34e6b704fe68 675
Kojto 108:34e6b704fe68 676 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 108:34e6b704fe68 677 */
Kojto 108:34e6b704fe68 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 679 {
Kojto 108:34e6b704fe68 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 108:34e6b704fe68 681 }
Kojto 108:34e6b704fe68 682
Kojto 108:34e6b704fe68 683
Kojto 108:34e6b704fe68 684 /** \brief Set Interrupt Priority
Kojto 108:34e6b704fe68 685
Kojto 108:34e6b704fe68 686 The function sets the priority of an interrupt.
Kojto 108:34e6b704fe68 687
Kojto 108:34e6b704fe68 688 \note The priority cannot be set for every core interrupt.
Kojto 108:34e6b704fe68 689
Kojto 108:34e6b704fe68 690 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 691 \param [in] priority Priority to set.
Kojto 108:34e6b704fe68 692 */
Kojto 108:34e6b704fe68 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 108:34e6b704fe68 694 {
Kojto 108:34e6b704fe68 695 if(IRQn < 0) {
Kojto 108:34e6b704fe68 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 108:34e6b704fe68 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 108:34e6b704fe68 698 else {
Kojto 108:34e6b704fe68 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 108:34e6b704fe68 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 108:34e6b704fe68 701 }
Kojto 108:34e6b704fe68 702
Kojto 108:34e6b704fe68 703
Kojto 108:34e6b704fe68 704 /** \brief Get Interrupt Priority
Kojto 108:34e6b704fe68 705
Kojto 108:34e6b704fe68 706 The function reads the priority of an interrupt. The interrupt
Kojto 108:34e6b704fe68 707 number can be positive to specify an external (device specific)
Kojto 108:34e6b704fe68 708 interrupt, or negative to specify an internal (core) interrupt.
Kojto 108:34e6b704fe68 709
Kojto 108:34e6b704fe68 710
Kojto 108:34e6b704fe68 711 \param [in] IRQn Interrupt number.
Kojto 108:34e6b704fe68 712 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 108:34e6b704fe68 713 priority bits of the microcontroller.
Kojto 108:34e6b704fe68 714 */
Kojto 108:34e6b704fe68 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 108:34e6b704fe68 716 {
Kojto 108:34e6b704fe68 717
Kojto 108:34e6b704fe68 718 if(IRQn < 0) {
Kojto 108:34e6b704fe68 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 108:34e6b704fe68 720 else {
Kojto 108:34e6b704fe68 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 108:34e6b704fe68 722 }
Kojto 108:34e6b704fe68 723
Kojto 108:34e6b704fe68 724
Kojto 108:34e6b704fe68 725 /** \brief System Reset
Kojto 108:34e6b704fe68 726
Kojto 108:34e6b704fe68 727 The function initiates a system reset request to reset the MCU.
Kojto 108:34e6b704fe68 728 */
Kojto 108:34e6b704fe68 729 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 108:34e6b704fe68 730 {
Kojto 108:34e6b704fe68 731 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 108:34e6b704fe68 732 buffered write are completed before reset */
Kojto 108:34e6b704fe68 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 108:34e6b704fe68 734 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 108:34e6b704fe68 735 __DSB(); /* Ensure completion of memory access */
Kojto 108:34e6b704fe68 736 while(1); /* wait until reset */
Kojto 108:34e6b704fe68 737 }
Kojto 108:34e6b704fe68 738
Kojto 108:34e6b704fe68 739 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 108:34e6b704fe68 740
Kojto 108:34e6b704fe68 741
Kojto 108:34e6b704fe68 742
Kojto 108:34e6b704fe68 743 /* ################################## SysTick function ############################################ */
Kojto 108:34e6b704fe68 744 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 108:34e6b704fe68 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 108:34e6b704fe68 746 \brief Functions that configure the System.
Kojto 108:34e6b704fe68 747 @{
Kojto 108:34e6b704fe68 748 */
Kojto 108:34e6b704fe68 749
Kojto 108:34e6b704fe68 750 #if (__Vendor_SysTickConfig == 0)
Kojto 108:34e6b704fe68 751
Kojto 108:34e6b704fe68 752 /** \brief System Tick Configuration
Kojto 108:34e6b704fe68 753
Kojto 108:34e6b704fe68 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 108:34e6b704fe68 755 Counter is in free running mode to generate periodic interrupts.
Kojto 108:34e6b704fe68 756
Kojto 108:34e6b704fe68 757 \param [in] ticks Number of ticks between two interrupts.
Kojto 108:34e6b704fe68 758
Kojto 108:34e6b704fe68 759 \return 0 Function succeeded.
Kojto 108:34e6b704fe68 760 \return 1 Function failed.
Kojto 108:34e6b704fe68 761
Kojto 108:34e6b704fe68 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 108:34e6b704fe68 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 108:34e6b704fe68 764 must contain a vendor-specific implementation of this function.
Kojto 108:34e6b704fe68 765
Kojto 108:34e6b704fe68 766 */
Kojto 108:34e6b704fe68 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 108:34e6b704fe68 768 {
Kojto 108:34e6b704fe68 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 108:34e6b704fe68 770
Kojto 108:34e6b704fe68 771 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 108:34e6b704fe68 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 108:34e6b704fe68 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 108:34e6b704fe68 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 108:34e6b704fe68 775 SysTick_CTRL_TICKINT_Msk |
Kojto 108:34e6b704fe68 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 108:34e6b704fe68 777 return (0); /* Function successful */
Kojto 108:34e6b704fe68 778 }
Kojto 108:34e6b704fe68 779
Kojto 108:34e6b704fe68 780 #endif
Kojto 108:34e6b704fe68 781
Kojto 108:34e6b704fe68 782 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 108:34e6b704fe68 783
Kojto 108:34e6b704fe68 784
Kojto 108:34e6b704fe68 785
Kojto 108:34e6b704fe68 786
Kojto 108:34e6b704fe68 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 108:34e6b704fe68 788
Kojto 108:34e6b704fe68 789 #endif /* __CMSIS_GENERIC */
Kojto 108:34e6b704fe68 790
Kojto 108:34e6b704fe68 791 #ifdef __cplusplus
Kojto 108:34e6b704fe68 792 }
Kojto 108:34e6b704fe68 793 #endif