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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RZ_A1H/core_cm0plus.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file core_cm0plus.h
bogdanm 92:4fc01daae5a5 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #if defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 92:4fc01daae5a5 40 #endif
bogdanm 92:4fc01daae5a5 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 92:4fc01daae5a5 45 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 46 extern "C" {
bogdanm 92:4fc01daae5a5 47 #endif
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 92:4fc01daae5a5 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 92:4fc01daae5a5 51
bogdanm 92:4fc01daae5a5 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 92:4fc01daae5a5 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 92:4fc01daae5a5 56 Unions are used for effective representation of core registers.
bogdanm 92:4fc01daae5a5 57
bogdanm 92:4fc01daae5a5 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 92:4fc01daae5a5 59 Function-like macros are used to allow more efficient code.
bogdanm 92:4fc01daae5a5 60 */
bogdanm 92:4fc01daae5a5 61
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 /*******************************************************************************
bogdanm 92:4fc01daae5a5 64 * CMSIS definitions
bogdanm 92:4fc01daae5a5 65 ******************************************************************************/
bogdanm 92:4fc01daae5a5 66 /** \ingroup Cortex-M0+
bogdanm 92:4fc01daae5a5 67 @{
bogdanm 92:4fc01daae5a5 68 */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 92:4fc01daae5a5 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 92:4fc01daae5a5 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 92:4fc01daae5a5 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 92:4fc01daae5a5 82 #define __STATIC_INLINE static __inline
bogdanm 92:4fc01daae5a5 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 92:4fc01daae5a5 89 #elif defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 92:4fc01daae5a5 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 92:4fc01daae5a5 92 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 92:4fc01daae5a5 96 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 97
bogdanm 92:4fc01daae5a5 98 #elif defined ( __TASKING__ )
bogdanm 92:4fc01daae5a5 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 92:4fc01daae5a5 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 92:4fc01daae5a5 101 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 92:4fc01daae5a5 109 #endif
bogdanm 92:4fc01daae5a5 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 92:4fc01daae5a5 113 */
bogdanm 92:4fc01daae5a5 114 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 115
bogdanm 92:4fc01daae5a5 116 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 117 #if defined __TARGET_FPU_VFP
bogdanm 92:4fc01daae5a5 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 119 #endif
bogdanm 92:4fc01daae5a5 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 92:4fc01daae5a5 126 #elif defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 127 #if defined __ARMVFP__
bogdanm 92:4fc01daae5a5 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 129 #endif
bogdanm 92:4fc01daae5a5 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
bogdanm 92:4fc01daae5a5 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 134 #endif
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 #elif defined ( __TASKING__ )
bogdanm 92:4fc01daae5a5 137 #if defined __FPU_VFP__
bogdanm 92:4fc01daae5a5 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
bogdanm 92:4fc01daae5a5 145 #endif
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 #include <stdint.h> /* standard types definitions */
bogdanm 92:4fc01daae5a5 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 92:4fc01daae5a5 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 92:4fc01daae5a5 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 92:4fc01daae5a5 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 92:4fc01daae5a5 156
bogdanm 92:4fc01daae5a5 157 #ifndef __CMSIS_GENERIC
bogdanm 92:4fc01daae5a5 158
bogdanm 92:4fc01daae5a5 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 92:4fc01daae5a5 160 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 92:4fc01daae5a5 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 92:4fc01daae5a5 166 /* check device defines and use defaults */
bogdanm 92:4fc01daae5a5 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 92:4fc01daae5a5 168 #ifndef __CM0PLUS_REV
bogdanm 92:4fc01daae5a5 169 #define __CM0PLUS_REV 0x0000
bogdanm 92:4fc01daae5a5 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 171 #endif
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173 #ifndef __MPU_PRESENT
bogdanm 92:4fc01daae5a5 174 #define __MPU_PRESENT 0
bogdanm 92:4fc01daae5a5 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 176 #endif
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 #ifndef __VTOR_PRESENT
bogdanm 92:4fc01daae5a5 179 #define __VTOR_PRESENT 0
bogdanm 92:4fc01daae5a5 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 181 #endif
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183 #ifndef __NVIC_PRIO_BITS
bogdanm 92:4fc01daae5a5 184 #define __NVIC_PRIO_BITS 2
bogdanm 92:4fc01daae5a5 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 186 #endif
bogdanm 92:4fc01daae5a5 187
bogdanm 92:4fc01daae5a5 188 #ifndef __Vendor_SysTickConfig
bogdanm 92:4fc01daae5a5 189 #define __Vendor_SysTickConfig 0
bogdanm 92:4fc01daae5a5 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 191 #endif
bogdanm 92:4fc01daae5a5 192 #endif
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 92:4fc01daae5a5 195 /**
bogdanm 92:4fc01daae5a5 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 <strong>IO Type Qualifiers</strong> are used
bogdanm 92:4fc01daae5a5 199 \li to specify the access to peripheral variables.
bogdanm 92:4fc01daae5a5 200 \li for automatic generation of peripheral register debug information.
bogdanm 92:4fc01daae5a5 201 */
bogdanm 92:4fc01daae5a5 202 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 203 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 204 #else
bogdanm 92:4fc01daae5a5 205 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 206 #endif
bogdanm 92:4fc01daae5a5 207 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 92:4fc01daae5a5 208 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 92:4fc01daae5a5 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
bogdanm 92:4fc01daae5a5 218 /*@} end of group Cortex-M0+ */
bogdanm 92:4fc01daae5a5 219
bogdanm 92:4fc01daae5a5 220
bogdanm 92:4fc01daae5a5 221
bogdanm 92:4fc01daae5a5 222 /*******************************************************************************
bogdanm 92:4fc01daae5a5 223 * Register Abstraction
bogdanm 92:4fc01daae5a5 224 Core Register contain:
bogdanm 92:4fc01daae5a5 225 - Core Register
bogdanm 92:4fc01daae5a5 226 - Core NVIC Register
bogdanm 92:4fc01daae5a5 227 - Core SCB Register
bogdanm 92:4fc01daae5a5 228 - Core SysTick Register
bogdanm 92:4fc01daae5a5 229 - Core MPU Register
bogdanm 92:4fc01daae5a5 230 ******************************************************************************/
bogdanm 92:4fc01daae5a5 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 92:4fc01daae5a5 232 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 92:4fc01daae5a5 233 */
bogdanm 92:4fc01daae5a5 234
bogdanm 92:4fc01daae5a5 235 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 236 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 92:4fc01daae5a5 237 \brief Core Register type definitions.
bogdanm 92:4fc01daae5a5 238 @{
bogdanm 92:4fc01daae5a5 239 */
bogdanm 92:4fc01daae5a5 240
bogdanm 92:4fc01daae5a5 241 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 92:4fc01daae5a5 242 */
bogdanm 92:4fc01daae5a5 243 typedef union
bogdanm 92:4fc01daae5a5 244 {
bogdanm 92:4fc01daae5a5 245 struct
bogdanm 92:4fc01daae5a5 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 92:4fc01daae5a5 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 92:4fc01daae5a5 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 92:4fc01daae5a5 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 92:4fc01daae5a5 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 92:4fc01daae5a5 252 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 253 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 254 } APSR_Type;
bogdanm 92:4fc01daae5a5 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 92:4fc01daae5a5 271 */
bogdanm 92:4fc01daae5a5 272 typedef union
bogdanm 92:4fc01daae5a5 273 {
bogdanm 92:4fc01daae5a5 274 struct
bogdanm 92:4fc01daae5a5 275 {
bogdanm 92:4fc01daae5a5 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 92:4fc01daae5a5 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 92:4fc01daae5a5 278 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 279 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 280 } IPSR_Type;
bogdanm 92:4fc01daae5a5 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
bogdanm 92:4fc01daae5a5 286
bogdanm 92:4fc01daae5a5 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 92:4fc01daae5a5 288 */
bogdanm 92:4fc01daae5a5 289 typedef union
bogdanm 92:4fc01daae5a5 290 {
bogdanm 92:4fc01daae5a5 291 struct
bogdanm 92:4fc01daae5a5 292 {
bogdanm 92:4fc01daae5a5 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 92:4fc01daae5a5 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 92:4fc01daae5a5 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 92:4fc01daae5a5 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 92:4fc01daae5a5 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 92:4fc01daae5a5 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 92:4fc01daae5a5 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 92:4fc01daae5a5 301 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 302 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 303 } xPSR_Type;
bogdanm 92:4fc01daae5a5 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
bogdanm 92:4fc01daae5a5 324
bogdanm 92:4fc01daae5a5 325 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 92:4fc01daae5a5 326 */
bogdanm 92:4fc01daae5a5 327 typedef union
bogdanm 92:4fc01daae5a5 328 {
bogdanm 92:4fc01daae5a5 329 struct
bogdanm 92:4fc01daae5a5 330 {
bogdanm 92:4fc01daae5a5 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 92:4fc01daae5a5 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 92:4fc01daae5a5 334 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 335 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 336 } CONTROL_Type;
bogdanm 92:4fc01daae5a5 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
bogdanm 92:4fc01daae5a5 345 /*@} end of group CMSIS_CORE */
bogdanm 92:4fc01daae5a5 346
bogdanm 92:4fc01daae5a5 347
bogdanm 92:4fc01daae5a5 348 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 92:4fc01daae5a5 350 \brief Type definitions for the NVIC Registers
bogdanm 92:4fc01daae5a5 351 @{
bogdanm 92:4fc01daae5a5 352 */
bogdanm 92:4fc01daae5a5 353
bogdanm 92:4fc01daae5a5 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 92:4fc01daae5a5 355 */
bogdanm 92:4fc01daae5a5 356 typedef struct
bogdanm 92:4fc01daae5a5 357 {
bogdanm 92:4fc01daae5a5 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 92:4fc01daae5a5 359 uint32_t RESERVED0[31];
bogdanm 92:4fc01daae5a5 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 92:4fc01daae5a5 361 uint32_t RSERVED1[31];
bogdanm 92:4fc01daae5a5 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 92:4fc01daae5a5 363 uint32_t RESERVED2[31];
bogdanm 92:4fc01daae5a5 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 92:4fc01daae5a5 365 uint32_t RESERVED3[31];
bogdanm 92:4fc01daae5a5 366 uint32_t RESERVED4[64];
bogdanm 92:4fc01daae5a5 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 92:4fc01daae5a5 368 } NVIC_Type;
bogdanm 92:4fc01daae5a5 369
bogdanm 92:4fc01daae5a5 370 /*@} end of group CMSIS_NVIC */
bogdanm 92:4fc01daae5a5 371
bogdanm 92:4fc01daae5a5 372
bogdanm 92:4fc01daae5a5 373 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 374 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 92:4fc01daae5a5 375 \brief Type definitions for the System Control Block Registers
bogdanm 92:4fc01daae5a5 376 @{
bogdanm 92:4fc01daae5a5 377 */
bogdanm 92:4fc01daae5a5 378
bogdanm 92:4fc01daae5a5 379 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 92:4fc01daae5a5 380 */
bogdanm 92:4fc01daae5a5 381 typedef struct
bogdanm 92:4fc01daae5a5 382 {
bogdanm 92:4fc01daae5a5 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 92:4fc01daae5a5 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 92:4fc01daae5a5 385 #if (__VTOR_PRESENT == 1)
bogdanm 92:4fc01daae5a5 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 92:4fc01daae5a5 387 #else
bogdanm 92:4fc01daae5a5 388 uint32_t RESERVED0;
bogdanm 92:4fc01daae5a5 389 #endif
bogdanm 92:4fc01daae5a5 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 92:4fc01daae5a5 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 92:4fc01daae5a5 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 92:4fc01daae5a5 393 uint32_t RESERVED1;
bogdanm 92:4fc01daae5a5 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 92:4fc01daae5a5 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 92:4fc01daae5a5 396 } SCB_Type;
bogdanm 92:4fc01daae5a5 397
bogdanm 92:4fc01daae5a5 398 /* SCB CPUID Register Definitions */
bogdanm 92:4fc01daae5a5 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 92:4fc01daae5a5 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 92:4fc01daae5a5 401
bogdanm 92:4fc01daae5a5 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 92:4fc01daae5a5 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 92:4fc01daae5a5 404
bogdanm 92:4fc01daae5a5 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 92:4fc01daae5a5 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 92:4fc01daae5a5 407
bogdanm 92:4fc01daae5a5 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 92:4fc01daae5a5 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 92:4fc01daae5a5 410
bogdanm 92:4fc01daae5a5 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 92:4fc01daae5a5 413
bogdanm 92:4fc01daae5a5 414 /* SCB Interrupt Control State Register Definitions */
bogdanm 92:4fc01daae5a5 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 92:4fc01daae5a5 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 92:4fc01daae5a5 417
bogdanm 92:4fc01daae5a5 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 92:4fc01daae5a5 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 92:4fc01daae5a5 420
bogdanm 92:4fc01daae5a5 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 92:4fc01daae5a5 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 92:4fc01daae5a5 423
bogdanm 92:4fc01daae5a5 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 92:4fc01daae5a5 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 92:4fc01daae5a5 426
bogdanm 92:4fc01daae5a5 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 92:4fc01daae5a5 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 92:4fc01daae5a5 429
bogdanm 92:4fc01daae5a5 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 92:4fc01daae5a5 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 92:4fc01daae5a5 432
bogdanm 92:4fc01daae5a5 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 92:4fc01daae5a5 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 92:4fc01daae5a5 435
bogdanm 92:4fc01daae5a5 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 92:4fc01daae5a5 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 92:4fc01daae5a5 438
bogdanm 92:4fc01daae5a5 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 92:4fc01daae5a5 441
bogdanm 92:4fc01daae5a5 442 #if (__VTOR_PRESENT == 1)
bogdanm 92:4fc01daae5a5 443 /* SCB Interrupt Control State Register Definitions */
bogdanm 92:4fc01daae5a5 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 92:4fc01daae5a5 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 92:4fc01daae5a5 446 #endif
bogdanm 92:4fc01daae5a5 447
bogdanm 92:4fc01daae5a5 448 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 92:4fc01daae5a5 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 92:4fc01daae5a5 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 92:4fc01daae5a5 451
bogdanm 92:4fc01daae5a5 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 92:4fc01daae5a5 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 92:4fc01daae5a5 454
bogdanm 92:4fc01daae5a5 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 92:4fc01daae5a5 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 92:4fc01daae5a5 457
bogdanm 92:4fc01daae5a5 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 92:4fc01daae5a5 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 92:4fc01daae5a5 460
bogdanm 92:4fc01daae5a5 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 92:4fc01daae5a5 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 92:4fc01daae5a5 463
bogdanm 92:4fc01daae5a5 464 /* SCB System Control Register Definitions */
bogdanm 92:4fc01daae5a5 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 92:4fc01daae5a5 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 92:4fc01daae5a5 467
bogdanm 92:4fc01daae5a5 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 92:4fc01daae5a5 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 92:4fc01daae5a5 470
bogdanm 92:4fc01daae5a5 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 92:4fc01daae5a5 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 92:4fc01daae5a5 473
bogdanm 92:4fc01daae5a5 474 /* SCB Configuration Control Register Definitions */
bogdanm 92:4fc01daae5a5 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 92:4fc01daae5a5 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 92:4fc01daae5a5 477
bogdanm 92:4fc01daae5a5 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 92:4fc01daae5a5 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 92:4fc01daae5a5 480
bogdanm 92:4fc01daae5a5 481 /* SCB System Handler Control and State Register Definitions */
bogdanm 92:4fc01daae5a5 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 92:4fc01daae5a5 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 92:4fc01daae5a5 484
bogdanm 92:4fc01daae5a5 485 /*@} end of group CMSIS_SCB */
bogdanm 92:4fc01daae5a5 486
bogdanm 92:4fc01daae5a5 487
bogdanm 92:4fc01daae5a5 488 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 92:4fc01daae5a5 490 \brief Type definitions for the System Timer Registers.
bogdanm 92:4fc01daae5a5 491 @{
bogdanm 92:4fc01daae5a5 492 */
bogdanm 92:4fc01daae5a5 493
bogdanm 92:4fc01daae5a5 494 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 92:4fc01daae5a5 495 */
bogdanm 92:4fc01daae5a5 496 typedef struct
bogdanm 92:4fc01daae5a5 497 {
bogdanm 92:4fc01daae5a5 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 92:4fc01daae5a5 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 92:4fc01daae5a5 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 92:4fc01daae5a5 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 92:4fc01daae5a5 502 } SysTick_Type;
bogdanm 92:4fc01daae5a5 503
bogdanm 92:4fc01daae5a5 504 /* SysTick Control / Status Register Definitions */
bogdanm 92:4fc01daae5a5 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 92:4fc01daae5a5 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 92:4fc01daae5a5 507
bogdanm 92:4fc01daae5a5 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 92:4fc01daae5a5 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 92:4fc01daae5a5 510
bogdanm 92:4fc01daae5a5 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 92:4fc01daae5a5 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 92:4fc01daae5a5 513
bogdanm 92:4fc01daae5a5 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 92:4fc01daae5a5 516
bogdanm 92:4fc01daae5a5 517 /* SysTick Reload Register Definitions */
bogdanm 92:4fc01daae5a5 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 92:4fc01daae5a5 520
bogdanm 92:4fc01daae5a5 521 /* SysTick Current Register Definitions */
bogdanm 92:4fc01daae5a5 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 92:4fc01daae5a5 524
bogdanm 92:4fc01daae5a5 525 /* SysTick Calibration Register Definitions */
bogdanm 92:4fc01daae5a5 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 92:4fc01daae5a5 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 92:4fc01daae5a5 528
bogdanm 92:4fc01daae5a5 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 92:4fc01daae5a5 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 92:4fc01daae5a5 531
bogdanm 92:4fc01daae5a5 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 92:4fc01daae5a5 534
bogdanm 92:4fc01daae5a5 535 /*@} end of group CMSIS_SysTick */
bogdanm 92:4fc01daae5a5 536
bogdanm 92:4fc01daae5a5 537 #if (__MPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 538 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 92:4fc01daae5a5 540 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 92:4fc01daae5a5 541 @{
bogdanm 92:4fc01daae5a5 542 */
bogdanm 92:4fc01daae5a5 543
bogdanm 92:4fc01daae5a5 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 92:4fc01daae5a5 545 */
bogdanm 92:4fc01daae5a5 546 typedef struct
bogdanm 92:4fc01daae5a5 547 {
bogdanm 92:4fc01daae5a5 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 92:4fc01daae5a5 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 92:4fc01daae5a5 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 92:4fc01daae5a5 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 92:4fc01daae5a5 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 553 } MPU_Type;
bogdanm 92:4fc01daae5a5 554
bogdanm 92:4fc01daae5a5 555 /* MPU Type Register */
bogdanm 92:4fc01daae5a5 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 92:4fc01daae5a5 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 92:4fc01daae5a5 558
bogdanm 92:4fc01daae5a5 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 92:4fc01daae5a5 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 92:4fc01daae5a5 561
bogdanm 92:4fc01daae5a5 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 92:4fc01daae5a5 564
bogdanm 92:4fc01daae5a5 565 /* MPU Control Register */
bogdanm 92:4fc01daae5a5 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 92:4fc01daae5a5 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 92:4fc01daae5a5 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 92:4fc01daae5a5 571
bogdanm 92:4fc01daae5a5 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575 /* MPU Region Number Register */
bogdanm 92:4fc01daae5a5 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
bogdanm 92:4fc01daae5a5 578
bogdanm 92:4fc01daae5a5 579 /* MPU Region Base Address Register */
bogdanm 92:4fc01daae5a5 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 92:4fc01daae5a5 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 92:4fc01daae5a5 582
bogdanm 92:4fc01daae5a5 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 92:4fc01daae5a5 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 92:4fc01daae5a5 585
bogdanm 92:4fc01daae5a5 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
bogdanm 92:4fc01daae5a5 588
bogdanm 92:4fc01daae5a5 589 /* MPU Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 92:4fc01daae5a5 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 92:4fc01daae5a5 592
bogdanm 92:4fc01daae5a5 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 92:4fc01daae5a5 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 92:4fc01daae5a5 595
bogdanm 92:4fc01daae5a5 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 92:4fc01daae5a5 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 92:4fc01daae5a5 598
bogdanm 92:4fc01daae5a5 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 92:4fc01daae5a5 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 92:4fc01daae5a5 601
bogdanm 92:4fc01daae5a5 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 92:4fc01daae5a5 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 92:4fc01daae5a5 604
bogdanm 92:4fc01daae5a5 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 92:4fc01daae5a5 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 92:4fc01daae5a5 607
bogdanm 92:4fc01daae5a5 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 92:4fc01daae5a5 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 92:4fc01daae5a5 610
bogdanm 92:4fc01daae5a5 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 92:4fc01daae5a5 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 92:4fc01daae5a5 613
bogdanm 92:4fc01daae5a5 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 92:4fc01daae5a5 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 92:4fc01daae5a5 616
bogdanm 92:4fc01daae5a5 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 92:4fc01daae5a5 619
bogdanm 92:4fc01daae5a5 620 /*@} end of group CMSIS_MPU */
bogdanm 92:4fc01daae5a5 621 #endif
bogdanm 92:4fc01daae5a5 622
bogdanm 92:4fc01daae5a5 623
bogdanm 92:4fc01daae5a5 624 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 92:4fc01daae5a5 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 92:4fc01daae5a5 627 are only accessible over DAP and not via processor. Therefore
bogdanm 92:4fc01daae5a5 628 they are not covered by the Cortex-M0 header file.
bogdanm 92:4fc01daae5a5 629 @{
bogdanm 92:4fc01daae5a5 630 */
bogdanm 92:4fc01daae5a5 631 /*@} end of group CMSIS_CoreDebug */
bogdanm 92:4fc01daae5a5 632
bogdanm 92:4fc01daae5a5 633
bogdanm 92:4fc01daae5a5 634 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 635 \defgroup CMSIS_core_base Core Definitions
bogdanm 92:4fc01daae5a5 636 \brief Definitions for base addresses, unions, and structures.
bogdanm 92:4fc01daae5a5 637 @{
bogdanm 92:4fc01daae5a5 638 */
bogdanm 92:4fc01daae5a5 639
bogdanm 92:4fc01daae5a5 640 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 92:4fc01daae5a5 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 92:4fc01daae5a5 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 92:4fc01daae5a5 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 92:4fc01daae5a5 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 92:4fc01daae5a5 645
bogdanm 92:4fc01daae5a5 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 92:4fc01daae5a5 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 92:4fc01daae5a5 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 92:4fc01daae5a5 649
bogdanm 92:4fc01daae5a5 650 #if (__MPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 92:4fc01daae5a5 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 92:4fc01daae5a5 653 #endif
bogdanm 92:4fc01daae5a5 654
bogdanm 92:4fc01daae5a5 655 /*@} */
bogdanm 92:4fc01daae5a5 656
bogdanm 92:4fc01daae5a5 657
bogdanm 92:4fc01daae5a5 658
bogdanm 92:4fc01daae5a5 659 /*******************************************************************************
bogdanm 92:4fc01daae5a5 660 * Hardware Abstraction Layer
bogdanm 92:4fc01daae5a5 661 Core Function Interface contains:
bogdanm 92:4fc01daae5a5 662 - Core NVIC Functions
bogdanm 92:4fc01daae5a5 663 - Core SysTick Functions
bogdanm 92:4fc01daae5a5 664 - Core Register Access Functions
bogdanm 92:4fc01daae5a5 665 ******************************************************************************/
bogdanm 92:4fc01daae5a5 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 92:4fc01daae5a5 667 */
bogdanm 92:4fc01daae5a5 668
bogdanm 92:4fc01daae5a5 669
bogdanm 92:4fc01daae5a5 670
bogdanm 92:4fc01daae5a5 671 /* ########################## NVIC functions #################################### */
bogdanm 92:4fc01daae5a5 672 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 92:4fc01daae5a5 674 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 92:4fc01daae5a5 675 @{
bogdanm 92:4fc01daae5a5 676 */
bogdanm 92:4fc01daae5a5 677
bogdanm 92:4fc01daae5a5 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 92:4fc01daae5a5 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 92:4fc01daae5a5 683
bogdanm 92:4fc01daae5a5 684
bogdanm 92:4fc01daae5a5 685 /** \brief Enable External Interrupt
bogdanm 92:4fc01daae5a5 686
bogdanm 92:4fc01daae5a5 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 92:4fc01daae5a5 688
bogdanm 92:4fc01daae5a5 689 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 690 */
bogdanm 92:4fc01daae5a5 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 92:4fc01daae5a5 694 }
bogdanm 92:4fc01daae5a5 695
bogdanm 92:4fc01daae5a5 696
bogdanm 92:4fc01daae5a5 697 /** \brief Disable External Interrupt
bogdanm 92:4fc01daae5a5 698
bogdanm 92:4fc01daae5a5 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 92:4fc01daae5a5 700
bogdanm 92:4fc01daae5a5 701 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 702 */
bogdanm 92:4fc01daae5a5 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
bogdanm 92:4fc01daae5a5 708 }
bogdanm 92:4fc01daae5a5 709
bogdanm 92:4fc01daae5a5 710
bogdanm 92:4fc01daae5a5 711 /** \brief Get Pending Interrupt
bogdanm 92:4fc01daae5a5 712
bogdanm 92:4fc01daae5a5 713 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 92:4fc01daae5a5 714 for the specified interrupt.
bogdanm 92:4fc01daae5a5 715
bogdanm 92:4fc01daae5a5 716 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 717
bogdanm 92:4fc01daae5a5 718 \return 0 Interrupt status is not pending.
bogdanm 92:4fc01daae5a5 719 \return 1 Interrupt status is pending.
bogdanm 92:4fc01daae5a5 720 */
bogdanm 92:4fc01daae5a5 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 92:4fc01daae5a5 724 }
bogdanm 92:4fc01daae5a5 725
bogdanm 92:4fc01daae5a5 726
bogdanm 92:4fc01daae5a5 727 /** \brief Set Pending Interrupt
bogdanm 92:4fc01daae5a5 728
bogdanm 92:4fc01daae5a5 729 The function sets the pending bit of an external interrupt.
bogdanm 92:4fc01daae5a5 730
bogdanm 92:4fc01daae5a5 731 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 732 */
bogdanm 92:4fc01daae5a5 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 92:4fc01daae5a5 736 }
bogdanm 92:4fc01daae5a5 737
bogdanm 92:4fc01daae5a5 738
bogdanm 92:4fc01daae5a5 739 /** \brief Clear Pending Interrupt
bogdanm 92:4fc01daae5a5 740
bogdanm 92:4fc01daae5a5 741 The function clears the pending bit of an external interrupt.
bogdanm 92:4fc01daae5a5 742
bogdanm 92:4fc01daae5a5 743 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 744 */
bogdanm 92:4fc01daae5a5 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 92:4fc01daae5a5 748 }
bogdanm 92:4fc01daae5a5 749
bogdanm 92:4fc01daae5a5 750
bogdanm 92:4fc01daae5a5 751 /** \brief Set Interrupt Priority
bogdanm 92:4fc01daae5a5 752
bogdanm 92:4fc01daae5a5 753 The function sets the priority of an interrupt.
bogdanm 92:4fc01daae5a5 754
bogdanm 92:4fc01daae5a5 755 \note The priority cannot be set for every core interrupt.
bogdanm 92:4fc01daae5a5 756
bogdanm 92:4fc01daae5a5 757 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 758 \param [in] priority Priority to set.
bogdanm 92:4fc01daae5a5 759 */
bogdanm 92:4fc01daae5a5 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 92:4fc01daae5a5 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
bogdanm 92:4fc01daae5a5 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
bogdanm 92:4fc01daae5a5 770 }
bogdanm 92:4fc01daae5a5 771
bogdanm 92:4fc01daae5a5 772
bogdanm 92:4fc01daae5a5 773 /** \brief Get Interrupt Priority
bogdanm 92:4fc01daae5a5 774
bogdanm 92:4fc01daae5a5 775 The function reads the priority of an interrupt. The interrupt
bogdanm 92:4fc01daae5a5 776 number can be positive to specify an external (device specific)
bogdanm 92:4fc01daae5a5 777 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 92:4fc01daae5a5 778
bogdanm 92:4fc01daae5a5 779
bogdanm 92:4fc01daae5a5 780 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 781 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 92:4fc01daae5a5 782 priority bits of the microcontroller.
bogdanm 92:4fc01daae5a5 783 */
bogdanm 92:4fc01daae5a5 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 785 {
bogdanm 92:4fc01daae5a5 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
bogdanm 92:4fc01daae5a5 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
bogdanm 92:4fc01daae5a5 793 }
bogdanm 92:4fc01daae5a5 794
bogdanm 92:4fc01daae5a5 795
bogdanm 92:4fc01daae5a5 796 /** \brief System Reset
bogdanm 92:4fc01daae5a5 797
bogdanm 92:4fc01daae5a5 798 The function initiates a system reset request to reset the MCU.
bogdanm 92:4fc01daae5a5 799 */
bogdanm 92:4fc01daae5a5 800 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 92:4fc01daae5a5 801 {
bogdanm 92:4fc01daae5a5 802 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 92:4fc01daae5a5 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 92:4fc01daae5a5 805 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 92:4fc01daae5a5 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
bogdanm 92:4fc01daae5a5 808 }
bogdanm 92:4fc01daae5a5 809
bogdanm 92:4fc01daae5a5 810 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 92:4fc01daae5a5 811
bogdanm 92:4fc01daae5a5 812
bogdanm 92:4fc01daae5a5 813
bogdanm 92:4fc01daae5a5 814 /* ################################## SysTick function ############################################ */
bogdanm 92:4fc01daae5a5 815 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 92:4fc01daae5a5 817 \brief Functions that configure the System.
bogdanm 92:4fc01daae5a5 818 @{
bogdanm 92:4fc01daae5a5 819 */
bogdanm 92:4fc01daae5a5 820
bogdanm 92:4fc01daae5a5 821 #if (__Vendor_SysTickConfig == 0)
bogdanm 92:4fc01daae5a5 822
bogdanm 92:4fc01daae5a5 823 /** \brief System Tick Configuration
bogdanm 92:4fc01daae5a5 824
bogdanm 92:4fc01daae5a5 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 92:4fc01daae5a5 826 Counter is in free running mode to generate periodic interrupts.
bogdanm 92:4fc01daae5a5 827
bogdanm 92:4fc01daae5a5 828 \param [in] ticks Number of ticks between two interrupts.
bogdanm 92:4fc01daae5a5 829
bogdanm 92:4fc01daae5a5 830 \return 0 Function succeeded.
bogdanm 92:4fc01daae5a5 831 \return 1 Function failed.
bogdanm 92:4fc01daae5a5 832
bogdanm 92:4fc01daae5a5 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 92:4fc01daae5a5 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 92:4fc01daae5a5 835 must contain a vendor-specific implementation of this function.
bogdanm 92:4fc01daae5a5 836
bogdanm 92:4fc01daae5a5 837 */
bogdanm 92:4fc01daae5a5 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 92:4fc01daae5a5 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
bogdanm 92:4fc01daae5a5 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 92:4fc01daae5a5 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 92:4fc01daae5a5 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
bogdanm 92:4fc01daae5a5 849 }
bogdanm 92:4fc01daae5a5 850
bogdanm 92:4fc01daae5a5 851 #endif
bogdanm 92:4fc01daae5a5 852
bogdanm 92:4fc01daae5a5 853 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 92:4fc01daae5a5 854
bogdanm 92:4fc01daae5a5 855
bogdanm 92:4fc01daae5a5 856
bogdanm 92:4fc01daae5a5 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
bogdanm 92:4fc01daae5a5 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 92:4fc01daae5a5 863
bogdanm 92:4fc01daae5a5 864 #endif /* __CMSIS_GENERIC */