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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_RZ_A1H/core_cm0plus.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Child:
110:165afa46840b
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file core_cm0plus.h
bogdanm 92:4fc01daae5a5 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
bogdanm 92:4fc01daae5a5 4 * @version V3.20
bogdanm 92:4fc01daae5a5 5 * @date 25. February 2013
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
bogdanm 92:4fc01daae5a5 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #if defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 92:4fc01daae5a5 40 #endif
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 #ifndef __CORE_CM0PLUS_H_GENERIC
bogdanm 92:4fc01daae5a5 47 #define __CORE_CM0PLUS_H_GENERIC
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 92:4fc01daae5a5 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 92:4fc01daae5a5 51
bogdanm 92:4fc01daae5a5 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 92:4fc01daae5a5 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 92:4fc01daae5a5 56 Unions are used for effective representation of core registers.
bogdanm 92:4fc01daae5a5 57
bogdanm 92:4fc01daae5a5 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 92:4fc01daae5a5 59 Function-like macros are used to allow more efficient code.
bogdanm 92:4fc01daae5a5 60 */
bogdanm 92:4fc01daae5a5 61
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 /*******************************************************************************
bogdanm 92:4fc01daae5a5 64 * CMSIS definitions
bogdanm 92:4fc01daae5a5 65 ******************************************************************************/
bogdanm 92:4fc01daae5a5 66 /** \ingroup Cortex-M0+
bogdanm 92:4fc01daae5a5 67 @{
bogdanm 92:4fc01daae5a5 68 */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 /* CMSIS CM0P definitions */
bogdanm 92:4fc01daae5a5 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 92:4fc01daae5a5 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 92:4fc01daae5a5 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 92:4fc01daae5a5 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 92:4fc01daae5a5 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 92:4fc01daae5a5 82 #define __STATIC_INLINE static __inline
bogdanm 92:4fc01daae5a5 83
bogdanm 92:4fc01daae5a5 84 #elif defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 92:4fc01daae5a5 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 92:4fc01daae5a5 87 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 88
bogdanm 92:4fc01daae5a5 89 #elif defined ( __GNUC__ )
bogdanm 92:4fc01daae5a5 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 92:4fc01daae5a5 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 92:4fc01daae5a5 92 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 #elif defined ( __TASKING__ )
bogdanm 92:4fc01daae5a5 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 92:4fc01daae5a5 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 92:4fc01daae5a5 97 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 98
bogdanm 92:4fc01daae5a5 99 #endif
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
bogdanm 92:4fc01daae5a5 102 */
bogdanm 92:4fc01daae5a5 103 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 106 #if defined __TARGET_FPU_VFP
bogdanm 92:4fc01daae5a5 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 108 #endif
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110 #elif defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 111 #if defined __ARMVFP__
bogdanm 92:4fc01daae5a5 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 113 #endif
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115 #elif defined ( __GNUC__ )
bogdanm 92:4fc01daae5a5 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 92:4fc01daae5a5 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 118 #endif
bogdanm 92:4fc01daae5a5 119
bogdanm 92:4fc01daae5a5 120 #elif defined ( __TASKING__ )
bogdanm 92:4fc01daae5a5 121 #if defined __FPU_VFP__
bogdanm 92:4fc01daae5a5 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 123 #endif
bogdanm 92:4fc01daae5a5 124 #endif
bogdanm 92:4fc01daae5a5 125
bogdanm 92:4fc01daae5a5 126 #include <stdint.h> /* standard types definitions */
bogdanm 92:4fc01daae5a5 127 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 92:4fc01daae5a5 128 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 92:4fc01daae5a5 131
bogdanm 92:4fc01daae5a5 132 #ifndef __CMSIS_GENERIC
bogdanm 92:4fc01daae5a5 133
bogdanm 92:4fc01daae5a5 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 92:4fc01daae5a5 135 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 /* check device defines and use defaults */
bogdanm 92:4fc01daae5a5 138 #if defined __CHECK_DEVICE_DEFINES
bogdanm 92:4fc01daae5a5 139 #ifndef __CM0PLUS_REV
bogdanm 92:4fc01daae5a5 140 #define __CM0PLUS_REV 0x0000
bogdanm 92:4fc01daae5a5 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 142 #endif
bogdanm 92:4fc01daae5a5 143
bogdanm 92:4fc01daae5a5 144 #ifndef __MPU_PRESENT
bogdanm 92:4fc01daae5a5 145 #define __MPU_PRESENT 0
bogdanm 92:4fc01daae5a5 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 147 #endif
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 #ifndef __VTOR_PRESENT
bogdanm 92:4fc01daae5a5 150 #define __VTOR_PRESENT 0
bogdanm 92:4fc01daae5a5 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 152 #endif
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 #ifndef __NVIC_PRIO_BITS
bogdanm 92:4fc01daae5a5 155 #define __NVIC_PRIO_BITS 2
bogdanm 92:4fc01daae5a5 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 157 #endif
bogdanm 92:4fc01daae5a5 158
bogdanm 92:4fc01daae5a5 159 #ifndef __Vendor_SysTickConfig
bogdanm 92:4fc01daae5a5 160 #define __Vendor_SysTickConfig 0
bogdanm 92:4fc01daae5a5 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 162 #endif
bogdanm 92:4fc01daae5a5 163 #endif
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 92:4fc01daae5a5 166 /**
bogdanm 92:4fc01daae5a5 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 <strong>IO Type Qualifiers</strong> are used
bogdanm 92:4fc01daae5a5 170 \li to specify the access to peripheral variables.
bogdanm 92:4fc01daae5a5 171 \li for automatic generation of peripheral register debug information.
bogdanm 92:4fc01daae5a5 172 */
bogdanm 92:4fc01daae5a5 173 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 174 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 175 #else
bogdanm 92:4fc01daae5a5 176 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 177 #endif
bogdanm 92:4fc01daae5a5 178 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 92:4fc01daae5a5 179 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 92:4fc01daae5a5 180
bogdanm 92:4fc01daae5a5 181 /*@} end of group Cortex-M0+ */
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183
bogdanm 92:4fc01daae5a5 184
bogdanm 92:4fc01daae5a5 185 /*******************************************************************************
bogdanm 92:4fc01daae5a5 186 * Register Abstraction
bogdanm 92:4fc01daae5a5 187 Core Register contain:
bogdanm 92:4fc01daae5a5 188 - Core Register
bogdanm 92:4fc01daae5a5 189 - Core NVIC Register
bogdanm 92:4fc01daae5a5 190 - Core SCB Register
bogdanm 92:4fc01daae5a5 191 - Core SysTick Register
bogdanm 92:4fc01daae5a5 192 - Core MPU Register
bogdanm 92:4fc01daae5a5 193 ******************************************************************************/
bogdanm 92:4fc01daae5a5 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 92:4fc01daae5a5 195 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 92:4fc01daae5a5 196 */
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 199 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 92:4fc01daae5a5 200 \brief Core Register type definitions.
bogdanm 92:4fc01daae5a5 201 @{
bogdanm 92:4fc01daae5a5 202 */
bogdanm 92:4fc01daae5a5 203
bogdanm 92:4fc01daae5a5 204 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 92:4fc01daae5a5 205 */
bogdanm 92:4fc01daae5a5 206 typedef union
bogdanm 92:4fc01daae5a5 207 {
bogdanm 92:4fc01daae5a5 208 struct
bogdanm 92:4fc01daae5a5 209 {
bogdanm 92:4fc01daae5a5 210 #if (__CORTEX_M != 0x04)
bogdanm 92:4fc01daae5a5 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 92:4fc01daae5a5 212 #else
bogdanm 92:4fc01daae5a5 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 92:4fc01daae5a5 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 92:4fc01daae5a5 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 92:4fc01daae5a5 216 #endif
bogdanm 92:4fc01daae5a5 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 92:4fc01daae5a5 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 92:4fc01daae5a5 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 92:4fc01daae5a5 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 92:4fc01daae5a5 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 92:4fc01daae5a5 222 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 223 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 224 } APSR_Type;
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226
bogdanm 92:4fc01daae5a5 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 92:4fc01daae5a5 228 */
bogdanm 92:4fc01daae5a5 229 typedef union
bogdanm 92:4fc01daae5a5 230 {
bogdanm 92:4fc01daae5a5 231 struct
bogdanm 92:4fc01daae5a5 232 {
bogdanm 92:4fc01daae5a5 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 92:4fc01daae5a5 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 92:4fc01daae5a5 235 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 236 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 237 } IPSR_Type;
bogdanm 92:4fc01daae5a5 238
bogdanm 92:4fc01daae5a5 239
bogdanm 92:4fc01daae5a5 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 92:4fc01daae5a5 241 */
bogdanm 92:4fc01daae5a5 242 typedef union
bogdanm 92:4fc01daae5a5 243 {
bogdanm 92:4fc01daae5a5 244 struct
bogdanm 92:4fc01daae5a5 245 {
bogdanm 92:4fc01daae5a5 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 92:4fc01daae5a5 247 #if (__CORTEX_M != 0x04)
bogdanm 92:4fc01daae5a5 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 92:4fc01daae5a5 249 #else
bogdanm 92:4fc01daae5a5 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 92:4fc01daae5a5 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 92:4fc01daae5a5 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 92:4fc01daae5a5 253 #endif
bogdanm 92:4fc01daae5a5 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 92:4fc01daae5a5 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 92:4fc01daae5a5 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 92:4fc01daae5a5 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 92:4fc01daae5a5 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 92:4fc01daae5a5 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 92:4fc01daae5a5 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 92:4fc01daae5a5 261 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 262 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 263 } xPSR_Type;
bogdanm 92:4fc01daae5a5 264
bogdanm 92:4fc01daae5a5 265
bogdanm 92:4fc01daae5a5 266 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 92:4fc01daae5a5 267 */
bogdanm 92:4fc01daae5a5 268 typedef union
bogdanm 92:4fc01daae5a5 269 {
bogdanm 92:4fc01daae5a5 270 struct
bogdanm 92:4fc01daae5a5 271 {
bogdanm 92:4fc01daae5a5 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 92:4fc01daae5a5 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 92:4fc01daae5a5 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 92:4fc01daae5a5 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 92:4fc01daae5a5 276 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 277 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 278 } CONTROL_Type;
bogdanm 92:4fc01daae5a5 279
bogdanm 92:4fc01daae5a5 280 /*@} end of group CMSIS_CORE */
bogdanm 92:4fc01daae5a5 281
bogdanm 92:4fc01daae5a5 282
bogdanm 92:4fc01daae5a5 283 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 92:4fc01daae5a5 285 \brief Type definitions for the NVIC Registers
bogdanm 92:4fc01daae5a5 286 @{
bogdanm 92:4fc01daae5a5 287 */
bogdanm 92:4fc01daae5a5 288
bogdanm 92:4fc01daae5a5 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 92:4fc01daae5a5 290 */
bogdanm 92:4fc01daae5a5 291 typedef struct
bogdanm 92:4fc01daae5a5 292 {
bogdanm 92:4fc01daae5a5 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 92:4fc01daae5a5 294 uint32_t RESERVED0[31];
bogdanm 92:4fc01daae5a5 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 92:4fc01daae5a5 296 uint32_t RSERVED1[31];
bogdanm 92:4fc01daae5a5 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 92:4fc01daae5a5 298 uint32_t RESERVED2[31];
bogdanm 92:4fc01daae5a5 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 92:4fc01daae5a5 300 uint32_t RESERVED3[31];
bogdanm 92:4fc01daae5a5 301 uint32_t RESERVED4[64];
bogdanm 92:4fc01daae5a5 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 92:4fc01daae5a5 303 } NVIC_Type;
bogdanm 92:4fc01daae5a5 304
bogdanm 92:4fc01daae5a5 305 /*@} end of group CMSIS_NVIC */
bogdanm 92:4fc01daae5a5 306
bogdanm 92:4fc01daae5a5 307
bogdanm 92:4fc01daae5a5 308 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 309 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 92:4fc01daae5a5 310 \brief Type definitions for the System Control Block Registers
bogdanm 92:4fc01daae5a5 311 @{
bogdanm 92:4fc01daae5a5 312 */
bogdanm 92:4fc01daae5a5 313
bogdanm 92:4fc01daae5a5 314 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 92:4fc01daae5a5 315 */
bogdanm 92:4fc01daae5a5 316 typedef struct
bogdanm 92:4fc01daae5a5 317 {
bogdanm 92:4fc01daae5a5 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 92:4fc01daae5a5 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 92:4fc01daae5a5 320 #if (__VTOR_PRESENT == 1)
bogdanm 92:4fc01daae5a5 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 92:4fc01daae5a5 322 #else
bogdanm 92:4fc01daae5a5 323 uint32_t RESERVED0;
bogdanm 92:4fc01daae5a5 324 #endif
bogdanm 92:4fc01daae5a5 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 92:4fc01daae5a5 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 92:4fc01daae5a5 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 92:4fc01daae5a5 328 uint32_t RESERVED1;
bogdanm 92:4fc01daae5a5 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 92:4fc01daae5a5 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 92:4fc01daae5a5 331 } SCB_Type;
bogdanm 92:4fc01daae5a5 332
bogdanm 92:4fc01daae5a5 333 /* SCB CPUID Register Definitions */
bogdanm 92:4fc01daae5a5 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 92:4fc01daae5a5 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 92:4fc01daae5a5 336
bogdanm 92:4fc01daae5a5 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 92:4fc01daae5a5 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 92:4fc01daae5a5 339
bogdanm 92:4fc01daae5a5 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 92:4fc01daae5a5 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 92:4fc01daae5a5 342
bogdanm 92:4fc01daae5a5 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 92:4fc01daae5a5 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 92:4fc01daae5a5 345
bogdanm 92:4fc01daae5a5 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 92:4fc01daae5a5 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 92:4fc01daae5a5 348
bogdanm 92:4fc01daae5a5 349 /* SCB Interrupt Control State Register Definitions */
bogdanm 92:4fc01daae5a5 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 92:4fc01daae5a5 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 92:4fc01daae5a5 352
bogdanm 92:4fc01daae5a5 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 92:4fc01daae5a5 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 92:4fc01daae5a5 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 92:4fc01daae5a5 358
bogdanm 92:4fc01daae5a5 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 92:4fc01daae5a5 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 92:4fc01daae5a5 361
bogdanm 92:4fc01daae5a5 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 92:4fc01daae5a5 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 92:4fc01daae5a5 364
bogdanm 92:4fc01daae5a5 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 92:4fc01daae5a5 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 92:4fc01daae5a5 367
bogdanm 92:4fc01daae5a5 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 92:4fc01daae5a5 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 92:4fc01daae5a5 370
bogdanm 92:4fc01daae5a5 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 92:4fc01daae5a5 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 92:4fc01daae5a5 373
bogdanm 92:4fc01daae5a5 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 92:4fc01daae5a5 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 92:4fc01daae5a5 376
bogdanm 92:4fc01daae5a5 377 #if (__VTOR_PRESENT == 1)
bogdanm 92:4fc01daae5a5 378 /* SCB Interrupt Control State Register Definitions */
bogdanm 92:4fc01daae5a5 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 92:4fc01daae5a5 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 92:4fc01daae5a5 381 #endif
bogdanm 92:4fc01daae5a5 382
bogdanm 92:4fc01daae5a5 383 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 92:4fc01daae5a5 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 92:4fc01daae5a5 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 92:4fc01daae5a5 386
bogdanm 92:4fc01daae5a5 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 92:4fc01daae5a5 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 92:4fc01daae5a5 389
bogdanm 92:4fc01daae5a5 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 92:4fc01daae5a5 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 92:4fc01daae5a5 392
bogdanm 92:4fc01daae5a5 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 92:4fc01daae5a5 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 92:4fc01daae5a5 395
bogdanm 92:4fc01daae5a5 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 92:4fc01daae5a5 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 92:4fc01daae5a5 398
bogdanm 92:4fc01daae5a5 399 /* SCB System Control Register Definitions */
bogdanm 92:4fc01daae5a5 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 92:4fc01daae5a5 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 92:4fc01daae5a5 402
bogdanm 92:4fc01daae5a5 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 92:4fc01daae5a5 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 92:4fc01daae5a5 405
bogdanm 92:4fc01daae5a5 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 92:4fc01daae5a5 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 92:4fc01daae5a5 408
bogdanm 92:4fc01daae5a5 409 /* SCB Configuration Control Register Definitions */
bogdanm 92:4fc01daae5a5 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 92:4fc01daae5a5 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 92:4fc01daae5a5 412
bogdanm 92:4fc01daae5a5 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 92:4fc01daae5a5 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 92:4fc01daae5a5 415
bogdanm 92:4fc01daae5a5 416 /* SCB System Handler Control and State Register Definitions */
bogdanm 92:4fc01daae5a5 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 92:4fc01daae5a5 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 92:4fc01daae5a5 419
bogdanm 92:4fc01daae5a5 420 /*@} end of group CMSIS_SCB */
bogdanm 92:4fc01daae5a5 421
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 92:4fc01daae5a5 425 \brief Type definitions for the System Timer Registers.
bogdanm 92:4fc01daae5a5 426 @{
bogdanm 92:4fc01daae5a5 427 */
bogdanm 92:4fc01daae5a5 428
bogdanm 92:4fc01daae5a5 429 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 92:4fc01daae5a5 430 */
bogdanm 92:4fc01daae5a5 431 typedef struct
bogdanm 92:4fc01daae5a5 432 {
bogdanm 92:4fc01daae5a5 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 92:4fc01daae5a5 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 92:4fc01daae5a5 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 92:4fc01daae5a5 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 92:4fc01daae5a5 437 } SysTick_Type;
bogdanm 92:4fc01daae5a5 438
bogdanm 92:4fc01daae5a5 439 /* SysTick Control / Status Register Definitions */
bogdanm 92:4fc01daae5a5 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 92:4fc01daae5a5 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 92:4fc01daae5a5 442
bogdanm 92:4fc01daae5a5 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 92:4fc01daae5a5 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 92:4fc01daae5a5 445
bogdanm 92:4fc01daae5a5 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 92:4fc01daae5a5 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 92:4fc01daae5a5 448
bogdanm 92:4fc01daae5a5 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 92:4fc01daae5a5 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 92:4fc01daae5a5 451
bogdanm 92:4fc01daae5a5 452 /* SysTick Reload Register Definitions */
bogdanm 92:4fc01daae5a5 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 92:4fc01daae5a5 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 92:4fc01daae5a5 455
bogdanm 92:4fc01daae5a5 456 /* SysTick Current Register Definitions */
bogdanm 92:4fc01daae5a5 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 92:4fc01daae5a5 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 92:4fc01daae5a5 459
bogdanm 92:4fc01daae5a5 460 /* SysTick Calibration Register Definitions */
bogdanm 92:4fc01daae5a5 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 92:4fc01daae5a5 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 92:4fc01daae5a5 463
bogdanm 92:4fc01daae5a5 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 92:4fc01daae5a5 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 92:4fc01daae5a5 466
bogdanm 92:4fc01daae5a5 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 92:4fc01daae5a5 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 92:4fc01daae5a5 469
bogdanm 92:4fc01daae5a5 470 /*@} end of group CMSIS_SysTick */
bogdanm 92:4fc01daae5a5 471
bogdanm 92:4fc01daae5a5 472 #if (__MPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 473 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 92:4fc01daae5a5 475 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 92:4fc01daae5a5 476 @{
bogdanm 92:4fc01daae5a5 477 */
bogdanm 92:4fc01daae5a5 478
bogdanm 92:4fc01daae5a5 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 92:4fc01daae5a5 480 */
bogdanm 92:4fc01daae5a5 481 typedef struct
bogdanm 92:4fc01daae5a5 482 {
bogdanm 92:4fc01daae5a5 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 92:4fc01daae5a5 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 92:4fc01daae5a5 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 92:4fc01daae5a5 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 92:4fc01daae5a5 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 488 } MPU_Type;
bogdanm 92:4fc01daae5a5 489
bogdanm 92:4fc01daae5a5 490 /* MPU Type Register */
bogdanm 92:4fc01daae5a5 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 92:4fc01daae5a5 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 92:4fc01daae5a5 493
bogdanm 92:4fc01daae5a5 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 92:4fc01daae5a5 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 92:4fc01daae5a5 496
bogdanm 92:4fc01daae5a5 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 92:4fc01daae5a5 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 92:4fc01daae5a5 499
bogdanm 92:4fc01daae5a5 500 /* MPU Control Register */
bogdanm 92:4fc01daae5a5 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 92:4fc01daae5a5 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 92:4fc01daae5a5 503
bogdanm 92:4fc01daae5a5 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 92:4fc01daae5a5 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 92:4fc01daae5a5 506
bogdanm 92:4fc01daae5a5 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 92:4fc01daae5a5 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 92:4fc01daae5a5 509
bogdanm 92:4fc01daae5a5 510 /* MPU Region Number Register */
bogdanm 92:4fc01daae5a5 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 92:4fc01daae5a5 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 92:4fc01daae5a5 513
bogdanm 92:4fc01daae5a5 514 /* MPU Region Base Address Register */
bogdanm 92:4fc01daae5a5 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 92:4fc01daae5a5 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 92:4fc01daae5a5 517
bogdanm 92:4fc01daae5a5 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 92:4fc01daae5a5 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 92:4fc01daae5a5 520
bogdanm 92:4fc01daae5a5 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 92:4fc01daae5a5 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 92:4fc01daae5a5 523
bogdanm 92:4fc01daae5a5 524 /* MPU Region Attribute and Size Register */
bogdanm 92:4fc01daae5a5 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 92:4fc01daae5a5 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 92:4fc01daae5a5 527
bogdanm 92:4fc01daae5a5 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 92:4fc01daae5a5 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 92:4fc01daae5a5 530
bogdanm 92:4fc01daae5a5 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 92:4fc01daae5a5 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 92:4fc01daae5a5 533
bogdanm 92:4fc01daae5a5 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 92:4fc01daae5a5 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 92:4fc01daae5a5 536
bogdanm 92:4fc01daae5a5 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 92:4fc01daae5a5 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 92:4fc01daae5a5 539
bogdanm 92:4fc01daae5a5 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 92:4fc01daae5a5 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 92:4fc01daae5a5 542
bogdanm 92:4fc01daae5a5 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 92:4fc01daae5a5 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 92:4fc01daae5a5 545
bogdanm 92:4fc01daae5a5 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 92:4fc01daae5a5 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 92:4fc01daae5a5 548
bogdanm 92:4fc01daae5a5 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 92:4fc01daae5a5 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 92:4fc01daae5a5 551
bogdanm 92:4fc01daae5a5 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 92:4fc01daae5a5 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 92:4fc01daae5a5 554
bogdanm 92:4fc01daae5a5 555 /*@} end of group CMSIS_MPU */
bogdanm 92:4fc01daae5a5 556 #endif
bogdanm 92:4fc01daae5a5 557
bogdanm 92:4fc01daae5a5 558
bogdanm 92:4fc01daae5a5 559 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 92:4fc01daae5a5 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 92:4fc01daae5a5 562 are only accessible over DAP and not via processor. Therefore
bogdanm 92:4fc01daae5a5 563 they are not covered by the Cortex-M0 header file.
bogdanm 92:4fc01daae5a5 564 @{
bogdanm 92:4fc01daae5a5 565 */
bogdanm 92:4fc01daae5a5 566 /*@} end of group CMSIS_CoreDebug */
bogdanm 92:4fc01daae5a5 567
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 570 \defgroup CMSIS_core_base Core Definitions
bogdanm 92:4fc01daae5a5 571 \brief Definitions for base addresses, unions, and structures.
bogdanm 92:4fc01daae5a5 572 @{
bogdanm 92:4fc01daae5a5 573 */
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 92:4fc01daae5a5 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 92:4fc01daae5a5 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 92:4fc01daae5a5 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 92:4fc01daae5a5 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 92:4fc01daae5a5 580
bogdanm 92:4fc01daae5a5 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 92:4fc01daae5a5 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 92:4fc01daae5a5 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 92:4fc01daae5a5 584
bogdanm 92:4fc01daae5a5 585 #if (__MPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 92:4fc01daae5a5 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 92:4fc01daae5a5 588 #endif
bogdanm 92:4fc01daae5a5 589
bogdanm 92:4fc01daae5a5 590 /*@} */
bogdanm 92:4fc01daae5a5 591
bogdanm 92:4fc01daae5a5 592
bogdanm 92:4fc01daae5a5 593
bogdanm 92:4fc01daae5a5 594 /*******************************************************************************
bogdanm 92:4fc01daae5a5 595 * Hardware Abstraction Layer
bogdanm 92:4fc01daae5a5 596 Core Function Interface contains:
bogdanm 92:4fc01daae5a5 597 - Core NVIC Functions
bogdanm 92:4fc01daae5a5 598 - Core SysTick Functions
bogdanm 92:4fc01daae5a5 599 - Core Register Access Functions
bogdanm 92:4fc01daae5a5 600 ******************************************************************************/
bogdanm 92:4fc01daae5a5 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 92:4fc01daae5a5 602 */
bogdanm 92:4fc01daae5a5 603
bogdanm 92:4fc01daae5a5 604
bogdanm 92:4fc01daae5a5 605
bogdanm 92:4fc01daae5a5 606 /* ########################## NVIC functions #################################### */
bogdanm 92:4fc01daae5a5 607 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 92:4fc01daae5a5 609 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 92:4fc01daae5a5 610 @{
bogdanm 92:4fc01daae5a5 611 */
bogdanm 92:4fc01daae5a5 612
bogdanm 92:4fc01daae5a5 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 92:4fc01daae5a5 614 /* The following MACROS handle generation of the register offset and byte masks */
bogdanm 92:4fc01daae5a5 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
bogdanm 92:4fc01daae5a5 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
bogdanm 92:4fc01daae5a5 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
bogdanm 92:4fc01daae5a5 618
bogdanm 92:4fc01daae5a5 619
bogdanm 92:4fc01daae5a5 620 /** \brief Enable External Interrupt
bogdanm 92:4fc01daae5a5 621
bogdanm 92:4fc01daae5a5 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 92:4fc01daae5a5 623
bogdanm 92:4fc01daae5a5 624 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 625 */
bogdanm 92:4fc01daae5a5 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 627 {
bogdanm 92:4fc01daae5a5 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 92:4fc01daae5a5 629 }
bogdanm 92:4fc01daae5a5 630
bogdanm 92:4fc01daae5a5 631
bogdanm 92:4fc01daae5a5 632 /** \brief Disable External Interrupt
bogdanm 92:4fc01daae5a5 633
bogdanm 92:4fc01daae5a5 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 92:4fc01daae5a5 635
bogdanm 92:4fc01daae5a5 636 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 637 */
bogdanm 92:4fc01daae5a5 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 639 {
bogdanm 92:4fc01daae5a5 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 92:4fc01daae5a5 641 }
bogdanm 92:4fc01daae5a5 642
bogdanm 92:4fc01daae5a5 643
bogdanm 92:4fc01daae5a5 644 /** \brief Get Pending Interrupt
bogdanm 92:4fc01daae5a5 645
bogdanm 92:4fc01daae5a5 646 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 92:4fc01daae5a5 647 for the specified interrupt.
bogdanm 92:4fc01daae5a5 648
bogdanm 92:4fc01daae5a5 649 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 650
bogdanm 92:4fc01daae5a5 651 \return 0 Interrupt status is not pending.
bogdanm 92:4fc01daae5a5 652 \return 1 Interrupt status is pending.
bogdanm 92:4fc01daae5a5 653 */
bogdanm 92:4fc01daae5a5 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 655 {
bogdanm 92:4fc01daae5a5 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
bogdanm 92:4fc01daae5a5 657 }
bogdanm 92:4fc01daae5a5 658
bogdanm 92:4fc01daae5a5 659
bogdanm 92:4fc01daae5a5 660 /** \brief Set Pending Interrupt
bogdanm 92:4fc01daae5a5 661
bogdanm 92:4fc01daae5a5 662 The function sets the pending bit of an external interrupt.
bogdanm 92:4fc01daae5a5 663
bogdanm 92:4fc01daae5a5 664 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 665 */
bogdanm 92:4fc01daae5a5 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 667 {
bogdanm 92:4fc01daae5a5 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 92:4fc01daae5a5 669 }
bogdanm 92:4fc01daae5a5 670
bogdanm 92:4fc01daae5a5 671
bogdanm 92:4fc01daae5a5 672 /** \brief Clear Pending Interrupt
bogdanm 92:4fc01daae5a5 673
bogdanm 92:4fc01daae5a5 674 The function clears the pending bit of an external interrupt.
bogdanm 92:4fc01daae5a5 675
bogdanm 92:4fc01daae5a5 676 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 92:4fc01daae5a5 677 */
bogdanm 92:4fc01daae5a5 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 679 {
bogdanm 92:4fc01daae5a5 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 92:4fc01daae5a5 681 }
bogdanm 92:4fc01daae5a5 682
bogdanm 92:4fc01daae5a5 683
bogdanm 92:4fc01daae5a5 684 /** \brief Set Interrupt Priority
bogdanm 92:4fc01daae5a5 685
bogdanm 92:4fc01daae5a5 686 The function sets the priority of an interrupt.
bogdanm 92:4fc01daae5a5 687
bogdanm 92:4fc01daae5a5 688 \note The priority cannot be set for every core interrupt.
bogdanm 92:4fc01daae5a5 689
bogdanm 92:4fc01daae5a5 690 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 691 \param [in] priority Priority to set.
bogdanm 92:4fc01daae5a5 692 */
bogdanm 92:4fc01daae5a5 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 92:4fc01daae5a5 694 {
bogdanm 92:4fc01daae5a5 695 if(IRQn < 0) {
bogdanm 92:4fc01daae5a5 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 92:4fc01daae5a5 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 92:4fc01daae5a5 698 else {
bogdanm 92:4fc01daae5a5 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 92:4fc01daae5a5 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 92:4fc01daae5a5 701 }
bogdanm 92:4fc01daae5a5 702
bogdanm 92:4fc01daae5a5 703
bogdanm 92:4fc01daae5a5 704 /** \brief Get Interrupt Priority
bogdanm 92:4fc01daae5a5 705
bogdanm 92:4fc01daae5a5 706 The function reads the priority of an interrupt. The interrupt
bogdanm 92:4fc01daae5a5 707 number can be positive to specify an external (device specific)
bogdanm 92:4fc01daae5a5 708 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 92:4fc01daae5a5 709
bogdanm 92:4fc01daae5a5 710
bogdanm 92:4fc01daae5a5 711 \param [in] IRQn Interrupt number.
bogdanm 92:4fc01daae5a5 712 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 92:4fc01daae5a5 713 priority bits of the microcontroller.
bogdanm 92:4fc01daae5a5 714 */
bogdanm 92:4fc01daae5a5 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 92:4fc01daae5a5 716 {
bogdanm 92:4fc01daae5a5 717
bogdanm 92:4fc01daae5a5 718 if(IRQn < 0) {
bogdanm 92:4fc01daae5a5 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
bogdanm 92:4fc01daae5a5 720 else {
bogdanm 92:4fc01daae5a5 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 92:4fc01daae5a5 722 }
bogdanm 92:4fc01daae5a5 723
bogdanm 92:4fc01daae5a5 724
bogdanm 92:4fc01daae5a5 725 /** \brief System Reset
bogdanm 92:4fc01daae5a5 726
bogdanm 92:4fc01daae5a5 727 The function initiates a system reset request to reset the MCU.
bogdanm 92:4fc01daae5a5 728 */
bogdanm 92:4fc01daae5a5 729 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 92:4fc01daae5a5 730 {
bogdanm 92:4fc01daae5a5 731 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 92:4fc01daae5a5 732 buffered write are completed before reset */
bogdanm 92:4fc01daae5a5 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 92:4fc01daae5a5 734 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 92:4fc01daae5a5 735 __DSB(); /* Ensure completion of memory access */
bogdanm 92:4fc01daae5a5 736 while(1); /* wait until reset */
bogdanm 92:4fc01daae5a5 737 }
bogdanm 92:4fc01daae5a5 738
bogdanm 92:4fc01daae5a5 739 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 92:4fc01daae5a5 740
bogdanm 92:4fc01daae5a5 741
bogdanm 92:4fc01daae5a5 742
bogdanm 92:4fc01daae5a5 743 /* ################################## SysTick function ############################################ */
bogdanm 92:4fc01daae5a5 744 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 92:4fc01daae5a5 746 \brief Functions that configure the System.
bogdanm 92:4fc01daae5a5 747 @{
bogdanm 92:4fc01daae5a5 748 */
bogdanm 92:4fc01daae5a5 749
bogdanm 92:4fc01daae5a5 750 #if (__Vendor_SysTickConfig == 0)
bogdanm 92:4fc01daae5a5 751
bogdanm 92:4fc01daae5a5 752 /** \brief System Tick Configuration
bogdanm 92:4fc01daae5a5 753
bogdanm 92:4fc01daae5a5 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 92:4fc01daae5a5 755 Counter is in free running mode to generate periodic interrupts.
bogdanm 92:4fc01daae5a5 756
bogdanm 92:4fc01daae5a5 757 \param [in] ticks Number of ticks between two interrupts.
bogdanm 92:4fc01daae5a5 758
bogdanm 92:4fc01daae5a5 759 \return 0 Function succeeded.
bogdanm 92:4fc01daae5a5 760 \return 1 Function failed.
bogdanm 92:4fc01daae5a5 761
bogdanm 92:4fc01daae5a5 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 92:4fc01daae5a5 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 92:4fc01daae5a5 764 must contain a vendor-specific implementation of this function.
bogdanm 92:4fc01daae5a5 765
bogdanm 92:4fc01daae5a5 766 */
bogdanm 92:4fc01daae5a5 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 92:4fc01daae5a5 768 {
bogdanm 92:4fc01daae5a5 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 92:4fc01daae5a5 770
bogdanm 92:4fc01daae5a5 771 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 92:4fc01daae5a5 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 92:4fc01daae5a5 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 92:4fc01daae5a5 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 92:4fc01daae5a5 775 SysTick_CTRL_TICKINT_Msk |
bogdanm 92:4fc01daae5a5 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 92:4fc01daae5a5 777 return (0); /* Function successful */
bogdanm 92:4fc01daae5a5 778 }
bogdanm 92:4fc01daae5a5 779
bogdanm 92:4fc01daae5a5 780 #endif
bogdanm 92:4fc01daae5a5 781
bogdanm 92:4fc01daae5a5 782 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 92:4fc01daae5a5 783
bogdanm 92:4fc01daae5a5 784
bogdanm 92:4fc01daae5a5 785
bogdanm 92:4fc01daae5a5 786
bogdanm 92:4fc01daae5a5 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 92:4fc01daae5a5 788
bogdanm 92:4fc01daae5a5 789 #endif /* __CMSIS_GENERIC */
bogdanm 92:4fc01daae5a5 790
bogdanm 92:4fc01daae5a5 791 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 792 }
bogdanm 92:4fc01daae5a5 793 #endif