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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F410RB/core_caFunc.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
130:d75b3fe1f5cb 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 110:165afa46840b 1 /**************************************************************************//**
Kojto 110:165afa46840b 2 * @file core_caFunc.h
Kojto 110:165afa46840b 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 110:165afa46840b 4 * @version V3.10
Kojto 110:165afa46840b 5 * @date 30 Oct 2013
Kojto 110:165afa46840b 6 *
Kojto 110:165afa46840b 7 * @note
Kojto 110:165afa46840b 8 *
Kojto 110:165afa46840b 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 110:165afa46840b 11
Kojto 110:165afa46840b 12 All rights reserved.
Kojto 110:165afa46840b 13 Redistribution and use in source and binary forms, with or without
Kojto 110:165afa46840b 14 modification, are permitted provided that the following conditions are met:
Kojto 110:165afa46840b 15 - Redistributions of source code must retain the above copyright
Kojto 110:165afa46840b 16 notice, this list of conditions and the following disclaimer.
Kojto 110:165afa46840b 17 - Redistributions in binary form must reproduce the above copyright
Kojto 110:165afa46840b 18 notice, this list of conditions and the following disclaimer in the
Kojto 110:165afa46840b 19 documentation and/or other materials provided with the distribution.
Kojto 110:165afa46840b 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 110:165afa46840b 21 to endorse or promote products derived from this software without
Kojto 110:165afa46840b 22 specific prior written permission.
Kojto 110:165afa46840b 23 *
Kojto 110:165afa46840b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 110:165afa46840b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 110:165afa46840b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 110:165afa46840b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 110:165afa46840b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 110:165afa46840b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 110:165afa46840b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 110:165afa46840b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 110:165afa46840b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 110:165afa46840b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 110:165afa46840b 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 110:165afa46840b 35 ---------------------------------------------------------------------------*/
Kojto 110:165afa46840b 36
Kojto 110:165afa46840b 37
Kojto 110:165afa46840b 38 #ifndef __CORE_CAFUNC_H__
Kojto 110:165afa46840b 39 #define __CORE_CAFUNC_H__
Kojto 110:165afa46840b 40
Kojto 110:165afa46840b 41
Kojto 110:165afa46840b 42 /* ########################### Core Function Access ########################### */
Kojto 110:165afa46840b 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 110:165afa46840b 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 110:165afa46840b 45 @{
Kojto 110:165afa46840b 46 */
Kojto 110:165afa46840b 47
Kojto 110:165afa46840b 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 110:165afa46840b 49 /* ARM armcc specific functions */
Kojto 110:165afa46840b 50
Kojto 110:165afa46840b 51 #if (__ARMCC_VERSION < 400677)
Kojto 110:165afa46840b 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 110:165afa46840b 53 #endif
Kojto 110:165afa46840b 54
Kojto 110:165afa46840b 55 #define MODE_USR 0x10
Kojto 110:165afa46840b 56 #define MODE_FIQ 0x11
Kojto 110:165afa46840b 57 #define MODE_IRQ 0x12
Kojto 110:165afa46840b 58 #define MODE_SVC 0x13
Kojto 110:165afa46840b 59 #define MODE_MON 0x16
Kojto 110:165afa46840b 60 #define MODE_ABT 0x17
Kojto 110:165afa46840b 61 #define MODE_HYP 0x1A
Kojto 110:165afa46840b 62 #define MODE_UND 0x1B
Kojto 110:165afa46840b 63 #define MODE_SYS 0x1F
Kojto 110:165afa46840b 64
Kojto 110:165afa46840b 65 /** \brief Get APSR Register
Kojto 110:165afa46840b 66
Kojto 110:165afa46840b 67 This function returns the content of the APSR Register.
Kojto 110:165afa46840b 68
Kojto 110:165afa46840b 69 \return APSR Register value
Kojto 110:165afa46840b 70 */
Kojto 110:165afa46840b 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 110:165afa46840b 72 {
Kojto 110:165afa46840b 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 110:165afa46840b 74 return(__regAPSR);
Kojto 110:165afa46840b 75 }
Kojto 110:165afa46840b 76
Kojto 110:165afa46840b 77
Kojto 110:165afa46840b 78 /** \brief Get CPSR Register
Kojto 110:165afa46840b 79
Kojto 110:165afa46840b 80 This function returns the content of the CPSR Register.
Kojto 110:165afa46840b 81
Kojto 110:165afa46840b 82 \return CPSR Register value
Kojto 110:165afa46840b 83 */
Kojto 110:165afa46840b 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 110:165afa46840b 85 {
Kojto 110:165afa46840b 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 110:165afa46840b 87 return(__regCPSR);
Kojto 110:165afa46840b 88 }
Kojto 110:165afa46840b 89
Kojto 110:165afa46840b 90 /** \brief Set Stack Pointer
Kojto 110:165afa46840b 91
Kojto 110:165afa46840b 92 This function assigns the given value to the current stack pointer.
Kojto 110:165afa46840b 93
Kojto 110:165afa46840b 94 \param [in] topOfStack Stack Pointer value to set
Kojto 110:165afa46840b 95 */
Kojto 110:165afa46840b 96 register uint32_t __regSP __ASM("sp");
Kojto 110:165afa46840b 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 110:165afa46840b 98 {
Kojto 110:165afa46840b 99 __regSP = topOfStack;
Kojto 110:165afa46840b 100 }
Kojto 110:165afa46840b 101
Kojto 110:165afa46840b 102
Kojto 110:165afa46840b 103 /** \brief Get link register
Kojto 110:165afa46840b 104
Kojto 110:165afa46840b 105 This function returns the value of the link register
Kojto 110:165afa46840b 106
Kojto 110:165afa46840b 107 \return Value of link register
Kojto 110:165afa46840b 108 */
Kojto 110:165afa46840b 109 register uint32_t __reglr __ASM("lr");
Kojto 110:165afa46840b 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 110:165afa46840b 111 {
Kojto 110:165afa46840b 112 return(__reglr);
Kojto 110:165afa46840b 113 }
Kojto 110:165afa46840b 114
Kojto 110:165afa46840b 115 /** \brief Set link register
Kojto 110:165afa46840b 116
Kojto 110:165afa46840b 117 This function sets the value of the link register
Kojto 110:165afa46840b 118
Kojto 110:165afa46840b 119 \param [in] lr LR value to set
Kojto 110:165afa46840b 120 */
Kojto 110:165afa46840b 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 110:165afa46840b 122 {
Kojto 110:165afa46840b 123 __reglr = lr;
Kojto 110:165afa46840b 124 }
Kojto 110:165afa46840b 125
Kojto 110:165afa46840b 126 /** \brief Set Process Stack Pointer
Kojto 110:165afa46840b 127
Kojto 110:165afa46840b 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 110:165afa46840b 129
Kojto 110:165afa46840b 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 110:165afa46840b 131 */
Kojto 110:165afa46840b 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 110:165afa46840b 133 {
Kojto 110:165afa46840b 134 ARM
Kojto 110:165afa46840b 135 PRESERVE8
Kojto 110:165afa46840b 136
Kojto 110:165afa46840b 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 110:165afa46840b 138 MRS R1, CPSR
Kojto 110:165afa46840b 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 110:165afa46840b 140 MOV SP, R0
Kojto 110:165afa46840b 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 110:165afa46840b 142 ISB
Kojto 110:165afa46840b 143 BX LR
Kojto 110:165afa46840b 144
Kojto 110:165afa46840b 145 }
Kojto 110:165afa46840b 146
Kojto 110:165afa46840b 147 /** \brief Set User Mode
Kojto 110:165afa46840b 148
Kojto 110:165afa46840b 149 This function changes the processor state to User Mode
Kojto 110:165afa46840b 150 */
Kojto 110:165afa46840b 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 110:165afa46840b 152 {
Kojto 110:165afa46840b 153 ARM
Kojto 110:165afa46840b 154
Kojto 110:165afa46840b 155 CPS #MODE_USR
Kojto 110:165afa46840b 156 BX LR
Kojto 110:165afa46840b 157 }
Kojto 110:165afa46840b 158
Kojto 110:165afa46840b 159
Kojto 110:165afa46840b 160 /** \brief Enable FIQ
Kojto 110:165afa46840b 161
Kojto 110:165afa46840b 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 110:165afa46840b 163 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 164 */
Kojto 110:165afa46840b 165 #define __enable_fault_irq __enable_fiq
Kojto 110:165afa46840b 166
Kojto 110:165afa46840b 167
Kojto 110:165afa46840b 168 /** \brief Disable FIQ
Kojto 110:165afa46840b 169
Kojto 110:165afa46840b 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 110:165afa46840b 171 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 172 */
Kojto 110:165afa46840b 173 #define __disable_fault_irq __disable_fiq
Kojto 110:165afa46840b 174
Kojto 110:165afa46840b 175
Kojto 110:165afa46840b 176 /** \brief Get FPSCR
Kojto 110:165afa46840b 177
Kojto 110:165afa46840b 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 110:165afa46840b 179
Kojto 110:165afa46840b 180 \return Floating Point Status/Control register value
Kojto 110:165afa46840b 181 */
Kojto 110:165afa46840b 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 110:165afa46840b 183 {
Kojto 110:165afa46840b 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 110:165afa46840b 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 110:165afa46840b 186 return(__regfpscr);
Kojto 110:165afa46840b 187 #else
Kojto 110:165afa46840b 188 return(0);
Kojto 110:165afa46840b 189 #endif
Kojto 110:165afa46840b 190 }
Kojto 110:165afa46840b 191
Kojto 110:165afa46840b 192
Kojto 110:165afa46840b 193 /** \brief Set FPSCR
Kojto 110:165afa46840b 194
Kojto 110:165afa46840b 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 110:165afa46840b 196
Kojto 110:165afa46840b 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 110:165afa46840b 198 */
Kojto 110:165afa46840b 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 110:165afa46840b 200 {
Kojto 110:165afa46840b 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 110:165afa46840b 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 110:165afa46840b 203 __regfpscr = (fpscr);
Kojto 110:165afa46840b 204 #endif
Kojto 110:165afa46840b 205 }
Kojto 110:165afa46840b 206
Kojto 110:165afa46840b 207 /** \brief Get FPEXC
Kojto 110:165afa46840b 208
Kojto 110:165afa46840b 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 110:165afa46840b 210
Kojto 110:165afa46840b 211 \return Floating Point Exception Control register value
Kojto 110:165afa46840b 212 */
Kojto 110:165afa46840b 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 110:165afa46840b 214 {
Kojto 110:165afa46840b 215 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 110:165afa46840b 217 return(__regfpexc);
Kojto 110:165afa46840b 218 #else
Kojto 110:165afa46840b 219 return(0);
Kojto 110:165afa46840b 220 #endif
Kojto 110:165afa46840b 221 }
Kojto 110:165afa46840b 222
Kojto 110:165afa46840b 223
Kojto 110:165afa46840b 224 /** \brief Set FPEXC
Kojto 110:165afa46840b 225
Kojto 110:165afa46840b 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 110:165afa46840b 227
Kojto 110:165afa46840b 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 110:165afa46840b 229 */
Kojto 110:165afa46840b 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 110:165afa46840b 231 {
Kojto 110:165afa46840b 232 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 110:165afa46840b 234 __regfpexc = (fpexc);
Kojto 110:165afa46840b 235 #endif
Kojto 110:165afa46840b 236 }
Kojto 110:165afa46840b 237
Kojto 110:165afa46840b 238 /** \brief Get CPACR
Kojto 110:165afa46840b 239
Kojto 110:165afa46840b 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 110:165afa46840b 241
Kojto 110:165afa46840b 242 \return Coprocessor Access Control register value
Kojto 110:165afa46840b 243 */
Kojto 110:165afa46840b 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 110:165afa46840b 245 {
Kojto 110:165afa46840b 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 110:165afa46840b 247 return __regCPACR;
Kojto 110:165afa46840b 248 }
Kojto 110:165afa46840b 249
Kojto 110:165afa46840b 250 /** \brief Set CPACR
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 110:165afa46840b 253
Kojto 110:165afa46840b 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 110:165afa46840b 255 */
Kojto 110:165afa46840b 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 110:165afa46840b 257 {
Kojto 110:165afa46840b 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 110:165afa46840b 259 __regCPACR = cpacr;
Kojto 110:165afa46840b 260 __ISB();
Kojto 110:165afa46840b 261 }
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 /** \brief Get CBAR
Kojto 110:165afa46840b 264
Kojto 110:165afa46840b 265 This function returns the value of the Configuration Base Address register.
Kojto 110:165afa46840b 266
Kojto 110:165afa46840b 267 \return Configuration Base Address register value
Kojto 110:165afa46840b 268 */
Kojto 110:165afa46840b 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 110:165afa46840b 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 110:165afa46840b 271 return(__regCBAR);
Kojto 110:165afa46840b 272 }
Kojto 110:165afa46840b 273
Kojto 110:165afa46840b 274 /** \brief Get TTBR0
Kojto 110:165afa46840b 275
Kojto 110:165afa46840b 276 This function returns the value of the Translation Table Base Register 0.
Kojto 110:165afa46840b 277
Kojto 110:165afa46840b 278 \return Translation Table Base Register 0 value
Kojto 110:165afa46840b 279 */
Kojto 110:165afa46840b 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 110:165afa46840b 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 110:165afa46840b 282 return(__regTTBR0);
Kojto 110:165afa46840b 283 }
Kojto 110:165afa46840b 284
Kojto 110:165afa46840b 285 /** \brief Set TTBR0
Kojto 110:165afa46840b 286
Kojto 110:165afa46840b 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 110:165afa46840b 288
Kojto 110:165afa46840b 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 110:165afa46840b 290 */
Kojto 110:165afa46840b 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 110:165afa46840b 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 110:165afa46840b 293 __regTTBR0 = ttbr0;
Kojto 110:165afa46840b 294 __ISB();
Kojto 110:165afa46840b 295 }
Kojto 110:165afa46840b 296
Kojto 110:165afa46840b 297 /** \brief Get DACR
Kojto 110:165afa46840b 298
Kojto 110:165afa46840b 299 This function returns the value of the Domain Access Control Register.
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 \return Domain Access Control Register value
Kojto 110:165afa46840b 302 */
Kojto 110:165afa46840b 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 110:165afa46840b 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 110:165afa46840b 305 return(__regDACR);
Kojto 110:165afa46840b 306 }
Kojto 110:165afa46840b 307
Kojto 110:165afa46840b 308 /** \brief Set DACR
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 This function assigns the given value to the Domain Access Control Register.
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 \param [in] dacr Domain Access Control Register value to set
Kojto 110:165afa46840b 313 */
Kojto 110:165afa46840b 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 110:165afa46840b 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 110:165afa46840b 316 __regDACR = dacr;
Kojto 110:165afa46840b 317 __ISB();
Kojto 110:165afa46840b 318 }
Kojto 110:165afa46840b 319
Kojto 110:165afa46840b 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 110:165afa46840b 321
Kojto 110:165afa46840b 322 /** \brief Set SCTLR
Kojto 110:165afa46840b 323
Kojto 110:165afa46840b 324 This function assigns the given value to the System Control Register.
Kojto 110:165afa46840b 325
Kojto 110:165afa46840b 326 \param [in] sctlr System Control Register value to set
Kojto 110:165afa46840b 327 */
Kojto 110:165afa46840b 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 110:165afa46840b 329 {
Kojto 110:165afa46840b 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 110:165afa46840b 331 __regSCTLR = sctlr;
Kojto 110:165afa46840b 332 }
Kojto 110:165afa46840b 333
Kojto 110:165afa46840b 334 /** \brief Get SCTLR
Kojto 110:165afa46840b 335
Kojto 110:165afa46840b 336 This function returns the value of the System Control Register.
Kojto 110:165afa46840b 337
Kojto 110:165afa46840b 338 \return System Control Register value
Kojto 110:165afa46840b 339 */
Kojto 110:165afa46840b 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 110:165afa46840b 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 110:165afa46840b 342 return(__regSCTLR);
Kojto 110:165afa46840b 343 }
Kojto 110:165afa46840b 344
Kojto 110:165afa46840b 345 /** \brief Enable Caches
Kojto 110:165afa46840b 346
Kojto 110:165afa46840b 347 Enable Caches
Kojto 110:165afa46840b 348 */
Kojto 110:165afa46840b 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 110:165afa46840b 350 // Set I bit 12 to enable I Cache
Kojto 110:165afa46840b 351 // Set C bit 2 to enable D Cache
Kojto 110:165afa46840b 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 110:165afa46840b 353 }
Kojto 110:165afa46840b 354
Kojto 110:165afa46840b 355 /** \brief Disable Caches
Kojto 110:165afa46840b 356
Kojto 110:165afa46840b 357 Disable Caches
Kojto 110:165afa46840b 358 */
Kojto 110:165afa46840b 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 110:165afa46840b 360 // Clear I bit 12 to disable I Cache
Kojto 110:165afa46840b 361 // Clear C bit 2 to disable D Cache
Kojto 110:165afa46840b 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 110:165afa46840b 363 __ISB();
Kojto 110:165afa46840b 364 }
Kojto 110:165afa46840b 365
Kojto 110:165afa46840b 366 /** \brief Enable BTAC
Kojto 110:165afa46840b 367
Kojto 110:165afa46840b 368 Enable BTAC
Kojto 110:165afa46840b 369 */
Kojto 110:165afa46840b 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 110:165afa46840b 371 // Set Z bit 11 to enable branch prediction
Kojto 110:165afa46840b 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 110:165afa46840b 373 __ISB();
Kojto 110:165afa46840b 374 }
Kojto 110:165afa46840b 375
Kojto 110:165afa46840b 376 /** \brief Disable BTAC
Kojto 110:165afa46840b 377
Kojto 110:165afa46840b 378 Disable BTAC
Kojto 110:165afa46840b 379 */
Kojto 110:165afa46840b 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 110:165afa46840b 381 // Clear Z bit 11 to disable branch prediction
Kojto 110:165afa46840b 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 110:165afa46840b 383 }
Kojto 110:165afa46840b 384
Kojto 110:165afa46840b 385
Kojto 110:165afa46840b 386 /** \brief Enable MMU
Kojto 110:165afa46840b 387
Kojto 110:165afa46840b 388 Enable MMU
Kojto 110:165afa46840b 389 */
Kojto 110:165afa46840b 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 110:165afa46840b 391 // Set M bit 0 to enable the MMU
Kojto 110:165afa46840b 392 // Set AFE bit to enable simplified access permissions model
Kojto 110:165afa46840b 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 110:165afa46840b 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 110:165afa46840b 395 __ISB();
Kojto 110:165afa46840b 396 }
Kojto 110:165afa46840b 397
Kojto 110:165afa46840b 398 /** \brief Disable MMU
Kojto 110:165afa46840b 399
Kojto 110:165afa46840b 400 Disable MMU
Kojto 110:165afa46840b 401 */
Kojto 110:165afa46840b 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 110:165afa46840b 403 // Clear M bit 0 to disable the MMU
Kojto 110:165afa46840b 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 110:165afa46840b 405 __ISB();
Kojto 110:165afa46840b 406 }
Kojto 110:165afa46840b 407
Kojto 110:165afa46840b 408 /******************************** TLB maintenance operations ************************************************/
Kojto 110:165afa46840b 409 /** \brief Invalidate the whole tlb
Kojto 110:165afa46840b 410
Kojto 110:165afa46840b 411 TLBIALL. Invalidate the whole tlb
Kojto 110:165afa46840b 412 */
Kojto 110:165afa46840b 413
Kojto 110:165afa46840b 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 110:165afa46840b 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 110:165afa46840b 416 __TLBIALL = 0;
Kojto 110:165afa46840b 417 __DSB();
Kojto 110:165afa46840b 418 __ISB();
Kojto 110:165afa46840b 419 }
Kojto 110:165afa46840b 420
Kojto 110:165afa46840b 421 /******************************** BTB maintenance operations ************************************************/
Kojto 110:165afa46840b 422 /** \brief Invalidate entire branch predictor array
Kojto 110:165afa46840b 423
Kojto 110:165afa46840b 424 BPIALL. Branch Predictor Invalidate All.
Kojto 110:165afa46840b 425 */
Kojto 110:165afa46840b 426
Kojto 110:165afa46840b 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 110:165afa46840b 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 110:165afa46840b 429 __BPIALL = 0;
Kojto 110:165afa46840b 430 __DSB(); //ensure completion of the invalidation
Kojto 110:165afa46840b 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 110:165afa46840b 432 }
Kojto 110:165afa46840b 433
Kojto 110:165afa46840b 434
Kojto 110:165afa46840b 435 /******************************** L1 cache operations ******************************************************/
Kojto 110:165afa46840b 436
Kojto 110:165afa46840b 437 /** \brief Invalidate the whole I$
Kojto 110:165afa46840b 438
Kojto 110:165afa46840b 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 110:165afa46840b 440 */
Kojto 110:165afa46840b 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 110:165afa46840b 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 110:165afa46840b 443 __ICIALLU = 0;
Kojto 110:165afa46840b 444 __DSB(); //ensure completion of the invalidation
Kojto 110:165afa46840b 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 110:165afa46840b 446 }
Kojto 110:165afa46840b 447
Kojto 110:165afa46840b 448 /** \brief Clean D$ by MVA
Kojto 110:165afa46840b 449
Kojto 110:165afa46840b 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 110:165afa46840b 451 */
Kojto 110:165afa46840b 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 110:165afa46840b 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 110:165afa46840b 454 __DCCMVAC = (uint32_t)va;
Kojto 110:165afa46840b 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 456 }
Kojto 110:165afa46840b 457
Kojto 110:165afa46840b 458 /** \brief Invalidate D$ by MVA
Kojto 110:165afa46840b 459
Kojto 110:165afa46840b 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 110:165afa46840b 461 */
Kojto 110:165afa46840b 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 110:165afa46840b 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 110:165afa46840b 464 __DCIMVAC = (uint32_t)va;
Kojto 110:165afa46840b 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 466 }
Kojto 110:165afa46840b 467
Kojto 110:165afa46840b 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 110:165afa46840b 469
Kojto 110:165afa46840b 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 110:165afa46840b 471 */
Kojto 110:165afa46840b 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 110:165afa46840b 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 110:165afa46840b 474 __DCCIMVAC = (uint32_t)va;
Kojto 110:165afa46840b 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 476 }
Kojto 110:165afa46840b 477
Kojto 110:165afa46840b 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 110:165afa46840b 479
Kojto 110:165afa46840b 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 110:165afa46840b 481 */
Kojto 110:165afa46840b 482 #pragma push
Kojto 110:165afa46840b 483 #pragma arm
Kojto 110:165afa46840b 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 110:165afa46840b 485 ARM
Kojto 110:165afa46840b 486
Kojto 110:165afa46840b 487 PUSH {R4-R11}
Kojto 110:165afa46840b 488
Kojto 110:165afa46840b 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 110:165afa46840b 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 110:165afa46840b 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 110:165afa46840b 492 BEQ Finished // If 0, no need to clean
Kojto 110:165afa46840b 493
Kojto 110:165afa46840b 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 110:165afa46840b 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 110:165afa46840b 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 110:165afa46840b 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 110:165afa46840b 498 CMP R1, #2
Kojto 110:165afa46840b 499 BLT Skip // No cache or only instruction cache at this level
Kojto 110:165afa46840b 500
Kojto 110:165afa46840b 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 110:165afa46840b 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 110:165afa46840b 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 110:165afa46840b 504 AND R2, R1, #7 // Extract the line length field
Kojto 110:165afa46840b 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 110:165afa46840b 506 LDR R4, =0x3FF
Kojto 110:165afa46840b 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 110:165afa46840b 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 110:165afa46840b 509 LDR R7, =0x7FFF
Kojto 110:165afa46840b 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 110:165afa46840b 511
Kojto 110:165afa46840b 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 110:165afa46840b 513
Kojto 110:165afa46840b 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 110:165afa46840b 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 110:165afa46840b 516 CMP R0, #0
Kojto 110:165afa46840b 517 BNE Dccsw
Kojto 110:165afa46840b 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 110:165afa46840b 519 B cont
Kojto 110:165afa46840b 520 Dccsw CMP R0, #1
Kojto 110:165afa46840b 521 BNE Dccisw
Kojto 110:165afa46840b 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 110:165afa46840b 523 B cont
Kojto 110:165afa46840b 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 110:165afa46840b 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 110:165afa46840b 526 BGE Loop3
Kojto 110:165afa46840b 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 110:165afa46840b 528 BGE Loop2
Kojto 110:165afa46840b 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 110:165afa46840b 530 CMP R3, R10
Kojto 110:165afa46840b 531 BGT Loop1
Kojto 110:165afa46840b 532
Kojto 110:165afa46840b 533 Finished
Kojto 110:165afa46840b 534 DSB
Kojto 110:165afa46840b 535 POP {R4-R11}
Kojto 110:165afa46840b 536 BX lr
Kojto 110:165afa46840b 537
Kojto 110:165afa46840b 538 }
Kojto 110:165afa46840b 539 #pragma pop
Kojto 110:165afa46840b 540
Kojto 110:165afa46840b 541
Kojto 110:165afa46840b 542 /** \brief Invalidate the whole D$
Kojto 110:165afa46840b 543
Kojto 110:165afa46840b 544 DCISW. Invalidate by Set/Way
Kojto 110:165afa46840b 545 */
Kojto 110:165afa46840b 546
Kojto 110:165afa46840b 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 110:165afa46840b 548 __v7_all_cache(0);
Kojto 110:165afa46840b 549 }
Kojto 110:165afa46840b 550
Kojto 110:165afa46840b 551 /** \brief Clean the whole D$
Kojto 110:165afa46840b 552
Kojto 110:165afa46840b 553 DCCSW. Clean by Set/Way
Kojto 110:165afa46840b 554 */
Kojto 110:165afa46840b 555
Kojto 110:165afa46840b 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 110:165afa46840b 557 __v7_all_cache(1);
Kojto 110:165afa46840b 558 }
Kojto 110:165afa46840b 559
Kojto 110:165afa46840b 560 /** \brief Clean and invalidate the whole D$
Kojto 110:165afa46840b 561
Kojto 110:165afa46840b 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 110:165afa46840b 563 */
Kojto 110:165afa46840b 564
Kojto 110:165afa46840b 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 110:165afa46840b 566 __v7_all_cache(2);
Kojto 110:165afa46840b 567 }
Kojto 110:165afa46840b 568
Kojto 110:165afa46840b 569 #include "core_ca_mmu.h"
Kojto 110:165afa46840b 570
Kojto 110:165afa46840b 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 110:165afa46840b 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
<> 130:d75b3fe1f5cb 814 /** \brief Clean the whole D$
<> 130:d75b3fe1f5cb 815
<> 130:d75b3fe1f5cb 816 DCCSW. Clean by Set/Way
<> 130:d75b3fe1f5cb 817 */
<> 130:d75b3fe1f5cb 818
<> 130:d75b3fe1f5cb 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 130:d75b3fe1f5cb 820 __v7_all_cache(1);
<> 130:d75b3fe1f5cb 821 }
<> 130:d75b3fe1f5cb 822
<> 130:d75b3fe1f5cb 823 /** \brief Clean and invalidate the whole D$
<> 130:d75b3fe1f5cb 824
<> 130:d75b3fe1f5cb 825 DCCISW. Clean and Invalidate by Set/Way
<> 130:d75b3fe1f5cb 826 */
<> 130:d75b3fe1f5cb 827
<> 130:d75b3fe1f5cb 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 130:d75b3fe1f5cb 829 __v7_all_cache(2);
<> 130:d75b3fe1f5cb 830 }
Kojto 121:6c34061e7c34 831 /** \brief Clean and Invalidate D$ by MVA
Kojto 121:6c34061e7c34 832
Kojto 121:6c34061e7c34 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 121:6c34061e7c34 834 */
Kojto 121:6c34061e7c34 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 121:6c34061e7c34 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 121:6c34061e7c34 837 __DMB();
Kojto 121:6c34061e7c34 838 }
Kojto 121:6c34061e7c34 839
Kojto 115:87f2f5183dfb 840 #include "core_ca_mmu.h"
Kojto 110:165afa46840b 841
Kojto 110:165afa46840b 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 110:165afa46840b 843 /* GNU gcc specific functions */
Kojto 110:165afa46840b 844
Kojto 110:165afa46840b 845 #define MODE_USR 0x10
Kojto 110:165afa46840b 846 #define MODE_FIQ 0x11
Kojto 110:165afa46840b 847 #define MODE_IRQ 0x12
Kojto 110:165afa46840b 848 #define MODE_SVC 0x13
Kojto 110:165afa46840b 849 #define MODE_MON 0x16
Kojto 110:165afa46840b 850 #define MODE_ABT 0x17
Kojto 110:165afa46840b 851 #define MODE_HYP 0x1A
Kojto 110:165afa46840b 852 #define MODE_UND 0x1B
Kojto 110:165afa46840b 853 #define MODE_SYS 0x1F
Kojto 110:165afa46840b 854
Kojto 110:165afa46840b 855
Kojto 110:165afa46840b 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 110:165afa46840b 857 {
Kojto 110:165afa46840b 858 __ASM volatile ("cpsie i");
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860
Kojto 110:165afa46840b 861 /** \brief Disable IRQ Interrupts
Kojto 110:165afa46840b 862
Kojto 110:165afa46840b 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 110:165afa46840b 864 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 865 */
Kojto 110:165afa46840b 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 110:165afa46840b 867 {
Kojto 110:165afa46840b 868 uint32_t result;
Kojto 110:165afa46840b 869
Kojto 110:165afa46840b 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 110:165afa46840b 871 __ASM volatile ("cpsid i");
Kojto 110:165afa46840b 872 return(result & 0x80);
Kojto 110:165afa46840b 873 }
Kojto 110:165afa46840b 874
Kojto 110:165afa46840b 875
Kojto 110:165afa46840b 876 /** \brief Get APSR Register
Kojto 110:165afa46840b 877
Kojto 110:165afa46840b 878 This function returns the content of the APSR Register.
Kojto 110:165afa46840b 879
Kojto 110:165afa46840b 880 \return APSR Register value
Kojto 110:165afa46840b 881 */
Kojto 110:165afa46840b 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 110:165afa46840b 883 {
Kojto 110:165afa46840b 884 #if 1
Kojto 110:165afa46840b 885 register uint32_t __regAPSR;
Kojto 110:165afa46840b 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 110:165afa46840b 887 #else
Kojto 110:165afa46840b 888 register uint32_t __regAPSR __ASM("apsr");
Kojto 110:165afa46840b 889 #endif
Kojto 110:165afa46840b 890 return(__regAPSR);
Kojto 110:165afa46840b 891 }
Kojto 110:165afa46840b 892
Kojto 110:165afa46840b 893
Kojto 110:165afa46840b 894 /** \brief Get CPSR Register
Kojto 110:165afa46840b 895
Kojto 110:165afa46840b 896 This function returns the content of the CPSR Register.
Kojto 110:165afa46840b 897
Kojto 110:165afa46840b 898 \return CPSR Register value
Kojto 110:165afa46840b 899 */
Kojto 110:165afa46840b 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 110:165afa46840b 901 {
Kojto 110:165afa46840b 902 #if 1
Kojto 110:165afa46840b 903 register uint32_t __regCPSR;
Kojto 110:165afa46840b 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 110:165afa46840b 905 #else
Kojto 110:165afa46840b 906 register uint32_t __regCPSR __ASM("cpsr");
Kojto 110:165afa46840b 907 #endif
Kojto 110:165afa46840b 908 return(__regCPSR);
Kojto 110:165afa46840b 909 }
Kojto 110:165afa46840b 910
Kojto 110:165afa46840b 911 #if 0
Kojto 110:165afa46840b 912 /** \brief Set Stack Pointer
Kojto 110:165afa46840b 913
Kojto 110:165afa46840b 914 This function assigns the given value to the current stack pointer.
Kojto 110:165afa46840b 915
Kojto 110:165afa46840b 916 \param [in] topOfStack Stack Pointer value to set
Kojto 110:165afa46840b 917 */
Kojto 110:165afa46840b 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 110:165afa46840b 919 {
Kojto 110:165afa46840b 920 register uint32_t __regSP __ASM("sp");
Kojto 110:165afa46840b 921 __regSP = topOfStack;
Kojto 110:165afa46840b 922 }
Kojto 110:165afa46840b 923 #endif
Kojto 110:165afa46840b 924
Kojto 110:165afa46840b 925 /** \brief Get link register
Kojto 110:165afa46840b 926
Kojto 110:165afa46840b 927 This function returns the value of the link register
Kojto 110:165afa46840b 928
Kojto 110:165afa46840b 929 \return Value of link register
Kojto 110:165afa46840b 930 */
Kojto 110:165afa46840b 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 110:165afa46840b 932 {
Kojto 110:165afa46840b 933 register uint32_t __reglr __ASM("lr");
Kojto 110:165afa46840b 934 return(__reglr);
Kojto 110:165afa46840b 935 }
Kojto 110:165afa46840b 936
Kojto 110:165afa46840b 937 #if 0
Kojto 110:165afa46840b 938 /** \brief Set link register
Kojto 110:165afa46840b 939
Kojto 110:165afa46840b 940 This function sets the value of the link register
Kojto 110:165afa46840b 941
Kojto 110:165afa46840b 942 \param [in] lr LR value to set
Kojto 110:165afa46840b 943 */
Kojto 110:165afa46840b 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 110:165afa46840b 945 {
Kojto 110:165afa46840b 946 register uint32_t __reglr __ASM("lr");
Kojto 110:165afa46840b 947 __reglr = lr;
Kojto 110:165afa46840b 948 }
Kojto 110:165afa46840b 949 #endif
Kojto 110:165afa46840b 950
Kojto 110:165afa46840b 951 /** \brief Set Process Stack Pointer
Kojto 110:165afa46840b 952
Kojto 110:165afa46840b 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 110:165afa46840b 954
Kojto 110:165afa46840b 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 110:165afa46840b 956 */
Kojto 110:165afa46840b 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 110:165afa46840b 958 {
Kojto 110:165afa46840b 959 __asm__ volatile (
Kojto 110:165afa46840b 960 ".ARM;"
Kojto 110:165afa46840b 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 110:165afa46840b 962
Kojto 110:165afa46840b 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 110:165afa46840b 964 "MRS R1, CPSR;"
Kojto 110:165afa46840b 965 "CPS %0;" /* ;no effect in USR mode */
Kojto 110:165afa46840b 966 "MOV SP, R0;"
Kojto 110:165afa46840b 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 110:165afa46840b 968 "ISB;"
Kojto 110:165afa46840b 969 //"BX LR;"
Kojto 110:165afa46840b 970 :
Kojto 110:165afa46840b 971 : "i"(MODE_SYS)
Kojto 110:165afa46840b 972 : "r0", "r1");
Kojto 110:165afa46840b 973 return;
Kojto 110:165afa46840b 974 }
Kojto 110:165afa46840b 975
Kojto 110:165afa46840b 976 /** \brief Set User Mode
Kojto 110:165afa46840b 977
Kojto 110:165afa46840b 978 This function changes the processor state to User Mode
Kojto 110:165afa46840b 979 */
Kojto 110:165afa46840b 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 110:165afa46840b 981 {
Kojto 110:165afa46840b 982 __asm__ volatile (
Kojto 110:165afa46840b 983 ".ARM;"
Kojto 110:165afa46840b 984
Kojto 110:165afa46840b 985 "CPS %0;"
Kojto 110:165afa46840b 986 //"BX LR;"
Kojto 110:165afa46840b 987 :
Kojto 110:165afa46840b 988 : "i"(MODE_USR)
Kojto 110:165afa46840b 989 : );
Kojto 110:165afa46840b 990 return;
Kojto 110:165afa46840b 991 }
Kojto 110:165afa46840b 992
Kojto 110:165afa46840b 993
Kojto 110:165afa46840b 994 /** \brief Enable FIQ
Kojto 110:165afa46840b 995
Kojto 110:165afa46840b 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 110:165afa46840b 997 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 998 */
Kojto 110:165afa46840b 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 110:165afa46840b 1000
Kojto 110:165afa46840b 1001
Kojto 110:165afa46840b 1002 /** \brief Disable FIQ
Kojto 110:165afa46840b 1003
Kojto 110:165afa46840b 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 110:165afa46840b 1005 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 1006 */
Kojto 110:165afa46840b 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 110:165afa46840b 1008
Kojto 110:165afa46840b 1009
Kojto 110:165afa46840b 1010 /** \brief Get FPSCR
Kojto 110:165afa46840b 1011
Kojto 110:165afa46840b 1012 This function returns the current value of the Floating Point Status/Control register.
Kojto 110:165afa46840b 1013
Kojto 110:165afa46840b 1014 \return Floating Point Status/Control register value
Kojto 110:165afa46840b 1015 */
Kojto 110:165afa46840b 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 110:165afa46840b 1017 {
Kojto 110:165afa46840b 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 110:165afa46840b 1019 #if 1
Kojto 110:165afa46840b 1020 uint32_t result;
Kojto 110:165afa46840b 1021
Kojto 110:165afa46840b 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 110:165afa46840b 1023 return (result);
Kojto 110:165afa46840b 1024 #else
Kojto 110:165afa46840b 1025 register uint32_t __regfpscr __ASM("fpscr");
Kojto 110:165afa46840b 1026 return(__regfpscr);
Kojto 110:165afa46840b 1027 #endif
Kojto 110:165afa46840b 1028 #else
Kojto 110:165afa46840b 1029 return(0);
Kojto 110:165afa46840b 1030 #endif
Kojto 110:165afa46840b 1031 }
Kojto 110:165afa46840b 1032
Kojto 110:165afa46840b 1033
Kojto 110:165afa46840b 1034 /** \brief Set FPSCR
Kojto 110:165afa46840b 1035
Kojto 110:165afa46840b 1036 This function assigns the given value to the Floating Point Status/Control register.
Kojto 110:165afa46840b 1037
Kojto 110:165afa46840b 1038 \param [in] fpscr Floating Point Status/Control value to set
Kojto 110:165afa46840b 1039 */
Kojto 110:165afa46840b 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 110:165afa46840b 1041 {
Kojto 110:165afa46840b 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 110:165afa46840b 1043 #if 1
Kojto 110:165afa46840b 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 110:165afa46840b 1045 #else
Kojto 110:165afa46840b 1046 register uint32_t __regfpscr __ASM("fpscr");
Kojto 110:165afa46840b 1047 __regfpscr = (fpscr);
Kojto 110:165afa46840b 1048 #endif
Kojto 110:165afa46840b 1049 #endif
Kojto 110:165afa46840b 1050 }
Kojto 110:165afa46840b 1051
Kojto 110:165afa46840b 1052 /** \brief Get FPEXC
Kojto 110:165afa46840b 1053
Kojto 110:165afa46840b 1054 This function returns the current value of the Floating Point Exception Control register.
Kojto 110:165afa46840b 1055
Kojto 110:165afa46840b 1056 \return Floating Point Exception Control register value
Kojto 110:165afa46840b 1057 */
Kojto 110:165afa46840b 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 110:165afa46840b 1059 {
Kojto 110:165afa46840b 1060 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 1061 #if 1
Kojto 110:165afa46840b 1062 uint32_t result;
Kojto 110:165afa46840b 1063
Kojto 110:165afa46840b 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 110:165afa46840b 1065 return (result);
Kojto 110:165afa46840b 1066 #else
Kojto 110:165afa46840b 1067 register uint32_t __regfpexc __ASM("fpexc");
Kojto 110:165afa46840b 1068 return(__regfpexc);
Kojto 110:165afa46840b 1069 #endif
Kojto 110:165afa46840b 1070 #else
Kojto 110:165afa46840b 1071 return(0);
Kojto 110:165afa46840b 1072 #endif
Kojto 110:165afa46840b 1073 }
Kojto 110:165afa46840b 1074
Kojto 110:165afa46840b 1075
Kojto 110:165afa46840b 1076 /** \brief Set FPEXC
Kojto 110:165afa46840b 1077
Kojto 110:165afa46840b 1078 This function assigns the given value to the Floating Point Exception Control register.
Kojto 110:165afa46840b 1079
Kojto 110:165afa46840b 1080 \param [in] fpscr Floating Point Exception Control value to set
Kojto 110:165afa46840b 1081 */
Kojto 110:165afa46840b 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 110:165afa46840b 1083 {
Kojto 110:165afa46840b 1084 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 1085 #if 1
Kojto 110:165afa46840b 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 110:165afa46840b 1087 #else
Kojto 110:165afa46840b 1088 register uint32_t __regfpexc __ASM("fpexc");
Kojto 110:165afa46840b 1089 __regfpexc = (fpexc);
Kojto 110:165afa46840b 1090 #endif
Kojto 110:165afa46840b 1091 #endif
Kojto 110:165afa46840b 1092 }
Kojto 110:165afa46840b 1093
Kojto 110:165afa46840b 1094 /** \brief Get CPACR
Kojto 110:165afa46840b 1095
Kojto 110:165afa46840b 1096 This function returns the current value of the Coprocessor Access Control register.
Kojto 110:165afa46840b 1097
Kojto 110:165afa46840b 1098 \return Coprocessor Access Control register value
Kojto 110:165afa46840b 1099 */
Kojto 110:165afa46840b 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 110:165afa46840b 1101 {
Kojto 110:165afa46840b 1102 #if 1
Kojto 110:165afa46840b 1103 register uint32_t __regCPACR;
Kojto 110:165afa46840b 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 110:165afa46840b 1105 #else
Kojto 110:165afa46840b 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 110:165afa46840b 1107 #endif
Kojto 110:165afa46840b 1108 return __regCPACR;
Kojto 110:165afa46840b 1109 }
Kojto 110:165afa46840b 1110
Kojto 110:165afa46840b 1111 /** \brief Set CPACR
Kojto 110:165afa46840b 1112
Kojto 110:165afa46840b 1113 This function assigns the given value to the Coprocessor Access Control register.
Kojto 110:165afa46840b 1114
Kojto 110:165afa46840b 1115 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 110:165afa46840b 1116 */
Kojto 110:165afa46840b 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 110:165afa46840b 1118 {
Kojto 110:165afa46840b 1119 #if 1
Kojto 110:165afa46840b 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 110:165afa46840b 1121 #else
Kojto 110:165afa46840b 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 110:165afa46840b 1123 __regCPACR = cpacr;
Kojto 110:165afa46840b 1124 #endif
Kojto 110:165afa46840b 1125 __ISB();
Kojto 110:165afa46840b 1126 }
Kojto 110:165afa46840b 1127
Kojto 110:165afa46840b 1128 /** \brief Get CBAR
Kojto 110:165afa46840b 1129
Kojto 110:165afa46840b 1130 This function returns the value of the Configuration Base Address register.
Kojto 110:165afa46840b 1131
Kojto 110:165afa46840b 1132 \return Configuration Base Address register value
Kojto 110:165afa46840b 1133 */
Kojto 110:165afa46840b 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 110:165afa46840b 1135 #if 1
Kojto 110:165afa46840b 1136 register uint32_t __regCBAR;
Kojto 110:165afa46840b 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 110:165afa46840b 1138 #else
Kojto 110:165afa46840b 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 110:165afa46840b 1140 #endif
Kojto 110:165afa46840b 1141 return(__regCBAR);
Kojto 110:165afa46840b 1142 }
Kojto 110:165afa46840b 1143
Kojto 110:165afa46840b 1144 /** \brief Get TTBR0
Kojto 110:165afa46840b 1145
Kojto 110:165afa46840b 1146 This function returns the value of the Translation Table Base Register 0.
Kojto 110:165afa46840b 1147
Kojto 110:165afa46840b 1148 \return Translation Table Base Register 0 value
Kojto 110:165afa46840b 1149 */
Kojto 110:165afa46840b 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 110:165afa46840b 1151 #if 1
Kojto 110:165afa46840b 1152 register uint32_t __regTTBR0;
Kojto 110:165afa46840b 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 110:165afa46840b 1154 #else
Kojto 110:165afa46840b 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 110:165afa46840b 1156 #endif
Kojto 110:165afa46840b 1157 return(__regTTBR0);
Kojto 110:165afa46840b 1158 }
Kojto 110:165afa46840b 1159
Kojto 110:165afa46840b 1160 /** \brief Set TTBR0
Kojto 110:165afa46840b 1161
Kojto 110:165afa46840b 1162 This function assigns the given value to the Translation Table Base Register 0.
Kojto 110:165afa46840b 1163
Kojto 110:165afa46840b 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 110:165afa46840b 1165 */
Kojto 110:165afa46840b 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 110:165afa46840b 1167 #if 1
Kojto 110:165afa46840b 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 110:165afa46840b 1169 #else
Kojto 110:165afa46840b 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 110:165afa46840b 1171 __regTTBR0 = ttbr0;
Kojto 110:165afa46840b 1172 #endif
Kojto 110:165afa46840b 1173 __ISB();
Kojto 110:165afa46840b 1174 }
Kojto 110:165afa46840b 1175
Kojto 110:165afa46840b 1176 /** \brief Get DACR
Kojto 110:165afa46840b 1177
Kojto 110:165afa46840b 1178 This function returns the value of the Domain Access Control Register.
Kojto 110:165afa46840b 1179
Kojto 110:165afa46840b 1180 \return Domain Access Control Register value
Kojto 110:165afa46840b 1181 */
Kojto 110:165afa46840b 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 110:165afa46840b 1183 #if 1
Kojto 110:165afa46840b 1184 register uint32_t __regDACR;
Kojto 110:165afa46840b 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 110:165afa46840b 1186 #else
Kojto 110:165afa46840b 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 110:165afa46840b 1188 #endif
Kojto 110:165afa46840b 1189 return(__regDACR);
Kojto 110:165afa46840b 1190 }
Kojto 110:165afa46840b 1191
Kojto 110:165afa46840b 1192 /** \brief Set DACR
Kojto 110:165afa46840b 1193
Kojto 110:165afa46840b 1194 This function assigns the given value to the Domain Access Control Register.
Kojto 110:165afa46840b 1195
Kojto 110:165afa46840b 1196 \param [in] dacr Domain Access Control Register value to set
Kojto 110:165afa46840b 1197 */
Kojto 110:165afa46840b 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 110:165afa46840b 1199 #if 1
Kojto 110:165afa46840b 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 110:165afa46840b 1201 #else
Kojto 110:165afa46840b 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 110:165afa46840b 1203 __regDACR = dacr;
Kojto 110:165afa46840b 1204 #endif
Kojto 110:165afa46840b 1205 __ISB();
Kojto 110:165afa46840b 1206 }
Kojto 110:165afa46840b 1207
Kojto 110:165afa46840b 1208 /******************************** Cache and BTAC enable ****************************************************/
Kojto 110:165afa46840b 1209
Kojto 110:165afa46840b 1210 /** \brief Set SCTLR
Kojto 110:165afa46840b 1211
Kojto 110:165afa46840b 1212 This function assigns the given value to the System Control Register.
Kojto 110:165afa46840b 1213
Kojto 110:165afa46840b 1214 \param [in] sctlr System Control Register value to set
Kojto 110:165afa46840b 1215 */
Kojto 110:165afa46840b 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 110:165afa46840b 1217 {
Kojto 110:165afa46840b 1218 #if 1
Kojto 110:165afa46840b 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 110:165afa46840b 1220 #else
Kojto 110:165afa46840b 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 110:165afa46840b 1222 __regSCTLR = sctlr;
Kojto 110:165afa46840b 1223 #endif
Kojto 110:165afa46840b 1224 }
Kojto 110:165afa46840b 1225
Kojto 110:165afa46840b 1226 /** \brief Get SCTLR
Kojto 110:165afa46840b 1227
Kojto 110:165afa46840b 1228 This function returns the value of the System Control Register.
Kojto 110:165afa46840b 1229
Kojto 110:165afa46840b 1230 \return System Control Register value
Kojto 110:165afa46840b 1231 */
Kojto 110:165afa46840b 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 110:165afa46840b 1233 #if 1
Kojto 110:165afa46840b 1234 register uint32_t __regSCTLR;
Kojto 110:165afa46840b 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 110:165afa46840b 1236 #else
Kojto 110:165afa46840b 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 110:165afa46840b 1238 #endif
Kojto 110:165afa46840b 1239 return(__regSCTLR);
Kojto 110:165afa46840b 1240 }
Kojto 110:165afa46840b 1241
Kojto 110:165afa46840b 1242 /** \brief Enable Caches
Kojto 110:165afa46840b 1243
Kojto 110:165afa46840b 1244 Enable Caches
Kojto 110:165afa46840b 1245 */
Kojto 110:165afa46840b 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 110:165afa46840b 1247 // Set I bit 12 to enable I Cache
Kojto 110:165afa46840b 1248 // Set C bit 2 to enable D Cache
Kojto 110:165afa46840b 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 110:165afa46840b 1250 }
Kojto 110:165afa46840b 1251
Kojto 110:165afa46840b 1252 /** \brief Disable Caches
Kojto 110:165afa46840b 1253
Kojto 110:165afa46840b 1254 Disable Caches
Kojto 110:165afa46840b 1255 */
Kojto 110:165afa46840b 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 110:165afa46840b 1257 // Clear I bit 12 to disable I Cache
Kojto 110:165afa46840b 1258 // Clear C bit 2 to disable D Cache
Kojto 110:165afa46840b 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 110:165afa46840b 1260 __ISB();
Kojto 110:165afa46840b 1261 }
Kojto 110:165afa46840b 1262
Kojto 110:165afa46840b 1263 /** \brief Enable BTAC
Kojto 110:165afa46840b 1264
Kojto 110:165afa46840b 1265 Enable BTAC
Kojto 110:165afa46840b 1266 */
Kojto 110:165afa46840b 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 110:165afa46840b 1268 // Set Z bit 11 to enable branch prediction
Kojto 110:165afa46840b 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 110:165afa46840b 1270 __ISB();
Kojto 110:165afa46840b 1271 }
Kojto 110:165afa46840b 1272
Kojto 110:165afa46840b 1273 /** \brief Disable BTAC
Kojto 110:165afa46840b 1274
Kojto 110:165afa46840b 1275 Disable BTAC
Kojto 110:165afa46840b 1276 */
Kojto 110:165afa46840b 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 110:165afa46840b 1278 // Clear Z bit 11 to disable branch prediction
Kojto 110:165afa46840b 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 110:165afa46840b 1280 }
Kojto 110:165afa46840b 1281
Kojto 110:165afa46840b 1282
Kojto 110:165afa46840b 1283 /** \brief Enable MMU
Kojto 110:165afa46840b 1284
Kojto 110:165afa46840b 1285 Enable MMU
Kojto 110:165afa46840b 1286 */
Kojto 110:165afa46840b 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 110:165afa46840b 1288 // Set M bit 0 to enable the MMU
Kojto 110:165afa46840b 1289 // Set AFE bit to enable simplified access permissions model
Kojto 110:165afa46840b 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 110:165afa46840b 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 110:165afa46840b 1292 __ISB();
Kojto 110:165afa46840b 1293 }
Kojto 110:165afa46840b 1294
Kojto 110:165afa46840b 1295 /** \brief Disable MMU
Kojto 110:165afa46840b 1296
Kojto 110:165afa46840b 1297 Disable MMU
Kojto 110:165afa46840b 1298 */
Kojto 110:165afa46840b 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 110:165afa46840b 1300 // Clear M bit 0 to disable the MMU
Kojto 110:165afa46840b 1301 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 110:165afa46840b 1302 __ISB();
Kojto 110:165afa46840b 1303 }
Kojto 110:165afa46840b 1304
Kojto 110:165afa46840b 1305 /******************************** TLB maintenance operations ************************************************/
Kojto 110:165afa46840b 1306 /** \brief Invalidate the whole tlb
Kojto 110:165afa46840b 1307
Kojto 110:165afa46840b 1308 TLBIALL. Invalidate the whole tlb
Kojto 110:165afa46840b 1309 */
Kojto 110:165afa46840b 1310
Kojto 110:165afa46840b 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 110:165afa46840b 1312 #if 1
Kojto 110:165afa46840b 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 110:165afa46840b 1314 #else
Kojto 110:165afa46840b 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 110:165afa46840b 1316 __TLBIALL = 0;
Kojto 110:165afa46840b 1317 #endif
Kojto 110:165afa46840b 1318 __DSB();
Kojto 110:165afa46840b 1319 __ISB();
Kojto 110:165afa46840b 1320 }
Kojto 110:165afa46840b 1321
Kojto 110:165afa46840b 1322 /******************************** BTB maintenance operations ************************************************/
Kojto 110:165afa46840b 1323 /** \brief Invalidate entire branch predictor array
Kojto 110:165afa46840b 1324
Kojto 110:165afa46840b 1325 BPIALL. Branch Predictor Invalidate All.
Kojto 110:165afa46840b 1326 */
Kojto 110:165afa46840b 1327
Kojto 110:165afa46840b 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 110:165afa46840b 1329 #if 1
Kojto 110:165afa46840b 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 110:165afa46840b 1331 #else
Kojto 110:165afa46840b 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 110:165afa46840b 1333 __BPIALL = 0;
Kojto 110:165afa46840b 1334 #endif
Kojto 110:165afa46840b 1335 __DSB(); //ensure completion of the invalidation
Kojto 110:165afa46840b 1336 __ISB(); //ensure instruction fetch path sees new state
Kojto 110:165afa46840b 1337 }
Kojto 110:165afa46840b 1338
Kojto 110:165afa46840b 1339
Kojto 110:165afa46840b 1340 /******************************** L1 cache operations ******************************************************/
Kojto 110:165afa46840b 1341
Kojto 110:165afa46840b 1342 /** \brief Invalidate the whole I$
Kojto 110:165afa46840b 1343
Kojto 110:165afa46840b 1344 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 110:165afa46840b 1345 */
Kojto 110:165afa46840b 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 110:165afa46840b 1347 #if 1
Kojto 110:165afa46840b 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 110:165afa46840b 1349 #else
Kojto 110:165afa46840b 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 110:165afa46840b 1351 __ICIALLU = 0;
Kojto 110:165afa46840b 1352 #endif
Kojto 110:165afa46840b 1353 __DSB(); //ensure completion of the invalidation
Kojto 110:165afa46840b 1354 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 110:165afa46840b 1355 }
Kojto 110:165afa46840b 1356
Kojto 110:165afa46840b 1357 /** \brief Clean D$ by MVA
Kojto 110:165afa46840b 1358
Kojto 110:165afa46840b 1359 DCCMVAC. Data cache clean by MVA to PoC
Kojto 110:165afa46840b 1360 */
Kojto 110:165afa46840b 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 110:165afa46840b 1362 #if 1
Kojto 110:165afa46840b 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 110:165afa46840b 1364 #else
Kojto 110:165afa46840b 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 110:165afa46840b 1366 __DCCMVAC = (uint32_t)va;
Kojto 110:165afa46840b 1367 #endif
Kojto 110:165afa46840b 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 1369 }
Kojto 110:165afa46840b 1370
Kojto 110:165afa46840b 1371 /** \brief Invalidate D$ by MVA
Kojto 110:165afa46840b 1372
Kojto 110:165afa46840b 1373 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 110:165afa46840b 1374 */
Kojto 110:165afa46840b 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 110:165afa46840b 1376 #if 1
Kojto 110:165afa46840b 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 110:165afa46840b 1378 #else
Kojto 110:165afa46840b 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 110:165afa46840b 1380 __DCIMVAC = (uint32_t)va;
Kojto 110:165afa46840b 1381 #endif
Kojto 110:165afa46840b 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 1383 }
Kojto 110:165afa46840b 1384
Kojto 110:165afa46840b 1385 /** \brief Clean and Invalidate D$ by MVA
Kojto 110:165afa46840b 1386
Kojto 110:165afa46840b 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 110:165afa46840b 1388 */
Kojto 110:165afa46840b 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 110:165afa46840b 1390 #if 1
Kojto 110:165afa46840b 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 110:165afa46840b 1392 #else
Kojto 110:165afa46840b 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 110:165afa46840b 1394 __DCCIMVAC = (uint32_t)va;
Kojto 110:165afa46840b 1395 #endif
Kojto 110:165afa46840b 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 1397 }
Kojto 110:165afa46840b 1398
Kojto 110:165afa46840b 1399 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 110:165afa46840b 1400
Kojto 110:165afa46840b 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 110:165afa46840b 1402 */
Kojto 110:165afa46840b 1403 extern void __v7_all_cache(uint32_t op);
Kojto 110:165afa46840b 1404
Kojto 110:165afa46840b 1405
Kojto 110:165afa46840b 1406 /** \brief Invalidate the whole D$
Kojto 110:165afa46840b 1407
Kojto 110:165afa46840b 1408 DCISW. Invalidate by Set/Way
Kojto 110:165afa46840b 1409 */
Kojto 110:165afa46840b 1410
Kojto 110:165afa46840b 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 110:165afa46840b 1412 __v7_all_cache(0);
Kojto 110:165afa46840b 1413 }
Kojto 110:165afa46840b 1414
Kojto 110:165afa46840b 1415 /** \brief Clean the whole D$
Kojto 110:165afa46840b 1416
Kojto 110:165afa46840b 1417 DCCSW. Clean by Set/Way
Kojto 110:165afa46840b 1418 */
Kojto 110:165afa46840b 1419
Kojto 110:165afa46840b 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 110:165afa46840b 1421 __v7_all_cache(1);
Kojto 110:165afa46840b 1422 }
Kojto 110:165afa46840b 1423
Kojto 110:165afa46840b 1424 /** \brief Clean and invalidate the whole D$
Kojto 110:165afa46840b 1425
Kojto 110:165afa46840b 1426 DCCISW. Clean and Invalidate by Set/Way
Kojto 110:165afa46840b 1427 */
Kojto 110:165afa46840b 1428
Kojto 110:165afa46840b 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 110:165afa46840b 1430 __v7_all_cache(2);
Kojto 110:165afa46840b 1431 }
Kojto 110:165afa46840b 1432
Kojto 110:165afa46840b 1433 #include "core_ca_mmu.h"
Kojto 110:165afa46840b 1434
Kojto 110:165afa46840b 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 110:165afa46840b 1436
Kojto 110:165afa46840b 1437 #error TASKING Compiler support not implemented for Cortex-A
Kojto 110:165afa46840b 1438
Kojto 110:165afa46840b 1439 #endif
Kojto 110:165afa46840b 1440
Kojto 110:165afa46840b 1441 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 110:165afa46840b 1442
Kojto 110:165afa46840b 1443
Kojto 110:165afa46840b 1444 #endif /* __CORE_CAFUNC_H__ */