mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F410RB/core_caFunc.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Child:
115:87f2f5183dfb
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 110:165afa46840b 1 /**************************************************************************//**
Kojto 110:165afa46840b 2 * @file core_caFunc.h
Kojto 110:165afa46840b 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 110:165afa46840b 4 * @version V3.10
Kojto 110:165afa46840b 5 * @date 30 Oct 2013
Kojto 110:165afa46840b 6 *
Kojto 110:165afa46840b 7 * @note
Kojto 110:165afa46840b 8 *
Kojto 110:165afa46840b 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 110:165afa46840b 11
Kojto 110:165afa46840b 12 All rights reserved.
Kojto 110:165afa46840b 13 Redistribution and use in source and binary forms, with or without
Kojto 110:165afa46840b 14 modification, are permitted provided that the following conditions are met:
Kojto 110:165afa46840b 15 - Redistributions of source code must retain the above copyright
Kojto 110:165afa46840b 16 notice, this list of conditions and the following disclaimer.
Kojto 110:165afa46840b 17 - Redistributions in binary form must reproduce the above copyright
Kojto 110:165afa46840b 18 notice, this list of conditions and the following disclaimer in the
Kojto 110:165afa46840b 19 documentation and/or other materials provided with the distribution.
Kojto 110:165afa46840b 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 110:165afa46840b 21 to endorse or promote products derived from this software without
Kojto 110:165afa46840b 22 specific prior written permission.
Kojto 110:165afa46840b 23 *
Kojto 110:165afa46840b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 110:165afa46840b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 110:165afa46840b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 110:165afa46840b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 110:165afa46840b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 110:165afa46840b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 110:165afa46840b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 110:165afa46840b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 110:165afa46840b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 110:165afa46840b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 110:165afa46840b 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 110:165afa46840b 35 ---------------------------------------------------------------------------*/
Kojto 110:165afa46840b 36
Kojto 110:165afa46840b 37
Kojto 110:165afa46840b 38 #ifndef __CORE_CAFUNC_H__
Kojto 110:165afa46840b 39 #define __CORE_CAFUNC_H__
Kojto 110:165afa46840b 40
Kojto 110:165afa46840b 41
Kojto 110:165afa46840b 42 /* ########################### Core Function Access ########################### */
Kojto 110:165afa46840b 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 110:165afa46840b 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 110:165afa46840b 45 @{
Kojto 110:165afa46840b 46 */
Kojto 110:165afa46840b 47
Kojto 110:165afa46840b 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 110:165afa46840b 49 /* ARM armcc specific functions */
Kojto 110:165afa46840b 50
Kojto 110:165afa46840b 51 #if (__ARMCC_VERSION < 400677)
Kojto 110:165afa46840b 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 110:165afa46840b 53 #endif
Kojto 110:165afa46840b 54
Kojto 110:165afa46840b 55 #define MODE_USR 0x10
Kojto 110:165afa46840b 56 #define MODE_FIQ 0x11
Kojto 110:165afa46840b 57 #define MODE_IRQ 0x12
Kojto 110:165afa46840b 58 #define MODE_SVC 0x13
Kojto 110:165afa46840b 59 #define MODE_MON 0x16
Kojto 110:165afa46840b 60 #define MODE_ABT 0x17
Kojto 110:165afa46840b 61 #define MODE_HYP 0x1A
Kojto 110:165afa46840b 62 #define MODE_UND 0x1B
Kojto 110:165afa46840b 63 #define MODE_SYS 0x1F
Kojto 110:165afa46840b 64
Kojto 110:165afa46840b 65 /** \brief Get APSR Register
Kojto 110:165afa46840b 66
Kojto 110:165afa46840b 67 This function returns the content of the APSR Register.
Kojto 110:165afa46840b 68
Kojto 110:165afa46840b 69 \return APSR Register value
Kojto 110:165afa46840b 70 */
Kojto 110:165afa46840b 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 110:165afa46840b 72 {
Kojto 110:165afa46840b 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 110:165afa46840b 74 return(__regAPSR);
Kojto 110:165afa46840b 75 }
Kojto 110:165afa46840b 76
Kojto 110:165afa46840b 77
Kojto 110:165afa46840b 78 /** \brief Get CPSR Register
Kojto 110:165afa46840b 79
Kojto 110:165afa46840b 80 This function returns the content of the CPSR Register.
Kojto 110:165afa46840b 81
Kojto 110:165afa46840b 82 \return CPSR Register value
Kojto 110:165afa46840b 83 */
Kojto 110:165afa46840b 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 110:165afa46840b 85 {
Kojto 110:165afa46840b 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 110:165afa46840b 87 return(__regCPSR);
Kojto 110:165afa46840b 88 }
Kojto 110:165afa46840b 89
Kojto 110:165afa46840b 90 /** \brief Set Stack Pointer
Kojto 110:165afa46840b 91
Kojto 110:165afa46840b 92 This function assigns the given value to the current stack pointer.
Kojto 110:165afa46840b 93
Kojto 110:165afa46840b 94 \param [in] topOfStack Stack Pointer value to set
Kojto 110:165afa46840b 95 */
Kojto 110:165afa46840b 96 register uint32_t __regSP __ASM("sp");
Kojto 110:165afa46840b 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 110:165afa46840b 98 {
Kojto 110:165afa46840b 99 __regSP = topOfStack;
Kojto 110:165afa46840b 100 }
Kojto 110:165afa46840b 101
Kojto 110:165afa46840b 102
Kojto 110:165afa46840b 103 /** \brief Get link register
Kojto 110:165afa46840b 104
Kojto 110:165afa46840b 105 This function returns the value of the link register
Kojto 110:165afa46840b 106
Kojto 110:165afa46840b 107 \return Value of link register
Kojto 110:165afa46840b 108 */
Kojto 110:165afa46840b 109 register uint32_t __reglr __ASM("lr");
Kojto 110:165afa46840b 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 110:165afa46840b 111 {
Kojto 110:165afa46840b 112 return(__reglr);
Kojto 110:165afa46840b 113 }
Kojto 110:165afa46840b 114
Kojto 110:165afa46840b 115 /** \brief Set link register
Kojto 110:165afa46840b 116
Kojto 110:165afa46840b 117 This function sets the value of the link register
Kojto 110:165afa46840b 118
Kojto 110:165afa46840b 119 \param [in] lr LR value to set
Kojto 110:165afa46840b 120 */
Kojto 110:165afa46840b 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 110:165afa46840b 122 {
Kojto 110:165afa46840b 123 __reglr = lr;
Kojto 110:165afa46840b 124 }
Kojto 110:165afa46840b 125
Kojto 110:165afa46840b 126 /** \brief Set Process Stack Pointer
Kojto 110:165afa46840b 127
Kojto 110:165afa46840b 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 110:165afa46840b 129
Kojto 110:165afa46840b 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 110:165afa46840b 131 */
Kojto 110:165afa46840b 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 110:165afa46840b 133 {
Kojto 110:165afa46840b 134 ARM
Kojto 110:165afa46840b 135 PRESERVE8
Kojto 110:165afa46840b 136
Kojto 110:165afa46840b 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 110:165afa46840b 138 MRS R1, CPSR
Kojto 110:165afa46840b 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 110:165afa46840b 140 MOV SP, R0
Kojto 110:165afa46840b 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 110:165afa46840b 142 ISB
Kojto 110:165afa46840b 143 BX LR
Kojto 110:165afa46840b 144
Kojto 110:165afa46840b 145 }
Kojto 110:165afa46840b 146
Kojto 110:165afa46840b 147 /** \brief Set User Mode
Kojto 110:165afa46840b 148
Kojto 110:165afa46840b 149 This function changes the processor state to User Mode
Kojto 110:165afa46840b 150 */
Kojto 110:165afa46840b 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 110:165afa46840b 152 {
Kojto 110:165afa46840b 153 ARM
Kojto 110:165afa46840b 154
Kojto 110:165afa46840b 155 CPS #MODE_USR
Kojto 110:165afa46840b 156 BX LR
Kojto 110:165afa46840b 157 }
Kojto 110:165afa46840b 158
Kojto 110:165afa46840b 159
Kojto 110:165afa46840b 160 /** \brief Enable FIQ
Kojto 110:165afa46840b 161
Kojto 110:165afa46840b 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 110:165afa46840b 163 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 164 */
Kojto 110:165afa46840b 165 #define __enable_fault_irq __enable_fiq
Kojto 110:165afa46840b 166
Kojto 110:165afa46840b 167
Kojto 110:165afa46840b 168 /** \brief Disable FIQ
Kojto 110:165afa46840b 169
Kojto 110:165afa46840b 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 110:165afa46840b 171 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 172 */
Kojto 110:165afa46840b 173 #define __disable_fault_irq __disable_fiq
Kojto 110:165afa46840b 174
Kojto 110:165afa46840b 175
Kojto 110:165afa46840b 176 /** \brief Get FPSCR
Kojto 110:165afa46840b 177
Kojto 110:165afa46840b 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 110:165afa46840b 179
Kojto 110:165afa46840b 180 \return Floating Point Status/Control register value
Kojto 110:165afa46840b 181 */
Kojto 110:165afa46840b 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 110:165afa46840b 183 {
Kojto 110:165afa46840b 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 110:165afa46840b 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 110:165afa46840b 186 return(__regfpscr);
Kojto 110:165afa46840b 187 #else
Kojto 110:165afa46840b 188 return(0);
Kojto 110:165afa46840b 189 #endif
Kojto 110:165afa46840b 190 }
Kojto 110:165afa46840b 191
Kojto 110:165afa46840b 192
Kojto 110:165afa46840b 193 /** \brief Set FPSCR
Kojto 110:165afa46840b 194
Kojto 110:165afa46840b 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 110:165afa46840b 196
Kojto 110:165afa46840b 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 110:165afa46840b 198 */
Kojto 110:165afa46840b 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 110:165afa46840b 200 {
Kojto 110:165afa46840b 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 110:165afa46840b 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 110:165afa46840b 203 __regfpscr = (fpscr);
Kojto 110:165afa46840b 204 #endif
Kojto 110:165afa46840b 205 }
Kojto 110:165afa46840b 206
Kojto 110:165afa46840b 207 /** \brief Get FPEXC
Kojto 110:165afa46840b 208
Kojto 110:165afa46840b 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 110:165afa46840b 210
Kojto 110:165afa46840b 211 \return Floating Point Exception Control register value
Kojto 110:165afa46840b 212 */
Kojto 110:165afa46840b 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 110:165afa46840b 214 {
Kojto 110:165afa46840b 215 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 110:165afa46840b 217 return(__regfpexc);
Kojto 110:165afa46840b 218 #else
Kojto 110:165afa46840b 219 return(0);
Kojto 110:165afa46840b 220 #endif
Kojto 110:165afa46840b 221 }
Kojto 110:165afa46840b 222
Kojto 110:165afa46840b 223
Kojto 110:165afa46840b 224 /** \brief Set FPEXC
Kojto 110:165afa46840b 225
Kojto 110:165afa46840b 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 110:165afa46840b 227
Kojto 110:165afa46840b 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 110:165afa46840b 229 */
Kojto 110:165afa46840b 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 110:165afa46840b 231 {
Kojto 110:165afa46840b 232 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 110:165afa46840b 234 __regfpexc = (fpexc);
Kojto 110:165afa46840b 235 #endif
Kojto 110:165afa46840b 236 }
Kojto 110:165afa46840b 237
Kojto 110:165afa46840b 238 /** \brief Get CPACR
Kojto 110:165afa46840b 239
Kojto 110:165afa46840b 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 110:165afa46840b 241
Kojto 110:165afa46840b 242 \return Coprocessor Access Control register value
Kojto 110:165afa46840b 243 */
Kojto 110:165afa46840b 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 110:165afa46840b 245 {
Kojto 110:165afa46840b 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 110:165afa46840b 247 return __regCPACR;
Kojto 110:165afa46840b 248 }
Kojto 110:165afa46840b 249
Kojto 110:165afa46840b 250 /** \brief Set CPACR
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 110:165afa46840b 253
Kojto 110:165afa46840b 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 110:165afa46840b 255 */
Kojto 110:165afa46840b 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 110:165afa46840b 257 {
Kojto 110:165afa46840b 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 110:165afa46840b 259 __regCPACR = cpacr;
Kojto 110:165afa46840b 260 __ISB();
Kojto 110:165afa46840b 261 }
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 /** \brief Get CBAR
Kojto 110:165afa46840b 264
Kojto 110:165afa46840b 265 This function returns the value of the Configuration Base Address register.
Kojto 110:165afa46840b 266
Kojto 110:165afa46840b 267 \return Configuration Base Address register value
Kojto 110:165afa46840b 268 */
Kojto 110:165afa46840b 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 110:165afa46840b 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 110:165afa46840b 271 return(__regCBAR);
Kojto 110:165afa46840b 272 }
Kojto 110:165afa46840b 273
Kojto 110:165afa46840b 274 /** \brief Get TTBR0
Kojto 110:165afa46840b 275
Kojto 110:165afa46840b 276 This function returns the value of the Translation Table Base Register 0.
Kojto 110:165afa46840b 277
Kojto 110:165afa46840b 278 \return Translation Table Base Register 0 value
Kojto 110:165afa46840b 279 */
Kojto 110:165afa46840b 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 110:165afa46840b 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 110:165afa46840b 282 return(__regTTBR0);
Kojto 110:165afa46840b 283 }
Kojto 110:165afa46840b 284
Kojto 110:165afa46840b 285 /** \brief Set TTBR0
Kojto 110:165afa46840b 286
Kojto 110:165afa46840b 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 110:165afa46840b 288
Kojto 110:165afa46840b 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 110:165afa46840b 290 */
Kojto 110:165afa46840b 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 110:165afa46840b 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 110:165afa46840b 293 __regTTBR0 = ttbr0;
Kojto 110:165afa46840b 294 __ISB();
Kojto 110:165afa46840b 295 }
Kojto 110:165afa46840b 296
Kojto 110:165afa46840b 297 /** \brief Get DACR
Kojto 110:165afa46840b 298
Kojto 110:165afa46840b 299 This function returns the value of the Domain Access Control Register.
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 \return Domain Access Control Register value
Kojto 110:165afa46840b 302 */
Kojto 110:165afa46840b 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 110:165afa46840b 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 110:165afa46840b 305 return(__regDACR);
Kojto 110:165afa46840b 306 }
Kojto 110:165afa46840b 307
Kojto 110:165afa46840b 308 /** \brief Set DACR
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 This function assigns the given value to the Domain Access Control Register.
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 \param [in] dacr Domain Access Control Register value to set
Kojto 110:165afa46840b 313 */
Kojto 110:165afa46840b 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 110:165afa46840b 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 110:165afa46840b 316 __regDACR = dacr;
Kojto 110:165afa46840b 317 __ISB();
Kojto 110:165afa46840b 318 }
Kojto 110:165afa46840b 319
Kojto 110:165afa46840b 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 110:165afa46840b 321
Kojto 110:165afa46840b 322 /** \brief Set SCTLR
Kojto 110:165afa46840b 323
Kojto 110:165afa46840b 324 This function assigns the given value to the System Control Register.
Kojto 110:165afa46840b 325
Kojto 110:165afa46840b 326 \param [in] sctlr System Control Register value to set
Kojto 110:165afa46840b 327 */
Kojto 110:165afa46840b 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 110:165afa46840b 329 {
Kojto 110:165afa46840b 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 110:165afa46840b 331 __regSCTLR = sctlr;
Kojto 110:165afa46840b 332 }
Kojto 110:165afa46840b 333
Kojto 110:165afa46840b 334 /** \brief Get SCTLR
Kojto 110:165afa46840b 335
Kojto 110:165afa46840b 336 This function returns the value of the System Control Register.
Kojto 110:165afa46840b 337
Kojto 110:165afa46840b 338 \return System Control Register value
Kojto 110:165afa46840b 339 */
Kojto 110:165afa46840b 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 110:165afa46840b 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 110:165afa46840b 342 return(__regSCTLR);
Kojto 110:165afa46840b 343 }
Kojto 110:165afa46840b 344
Kojto 110:165afa46840b 345 /** \brief Enable Caches
Kojto 110:165afa46840b 346
Kojto 110:165afa46840b 347 Enable Caches
Kojto 110:165afa46840b 348 */
Kojto 110:165afa46840b 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 110:165afa46840b 350 // Set I bit 12 to enable I Cache
Kojto 110:165afa46840b 351 // Set C bit 2 to enable D Cache
Kojto 110:165afa46840b 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 110:165afa46840b 353 }
Kojto 110:165afa46840b 354
Kojto 110:165afa46840b 355 /** \brief Disable Caches
Kojto 110:165afa46840b 356
Kojto 110:165afa46840b 357 Disable Caches
Kojto 110:165afa46840b 358 */
Kojto 110:165afa46840b 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 110:165afa46840b 360 // Clear I bit 12 to disable I Cache
Kojto 110:165afa46840b 361 // Clear C bit 2 to disable D Cache
Kojto 110:165afa46840b 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 110:165afa46840b 363 __ISB();
Kojto 110:165afa46840b 364 }
Kojto 110:165afa46840b 365
Kojto 110:165afa46840b 366 /** \brief Enable BTAC
Kojto 110:165afa46840b 367
Kojto 110:165afa46840b 368 Enable BTAC
Kojto 110:165afa46840b 369 */
Kojto 110:165afa46840b 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 110:165afa46840b 371 // Set Z bit 11 to enable branch prediction
Kojto 110:165afa46840b 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 110:165afa46840b 373 __ISB();
Kojto 110:165afa46840b 374 }
Kojto 110:165afa46840b 375
Kojto 110:165afa46840b 376 /** \brief Disable BTAC
Kojto 110:165afa46840b 377
Kojto 110:165afa46840b 378 Disable BTAC
Kojto 110:165afa46840b 379 */
Kojto 110:165afa46840b 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 110:165afa46840b 381 // Clear Z bit 11 to disable branch prediction
Kojto 110:165afa46840b 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 110:165afa46840b 383 }
Kojto 110:165afa46840b 384
Kojto 110:165afa46840b 385
Kojto 110:165afa46840b 386 /** \brief Enable MMU
Kojto 110:165afa46840b 387
Kojto 110:165afa46840b 388 Enable MMU
Kojto 110:165afa46840b 389 */
Kojto 110:165afa46840b 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 110:165afa46840b 391 // Set M bit 0 to enable the MMU
Kojto 110:165afa46840b 392 // Set AFE bit to enable simplified access permissions model
Kojto 110:165afa46840b 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 110:165afa46840b 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 110:165afa46840b 395 __ISB();
Kojto 110:165afa46840b 396 }
Kojto 110:165afa46840b 397
Kojto 110:165afa46840b 398 /** \brief Disable MMU
Kojto 110:165afa46840b 399
Kojto 110:165afa46840b 400 Disable MMU
Kojto 110:165afa46840b 401 */
Kojto 110:165afa46840b 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 110:165afa46840b 403 // Clear M bit 0 to disable the MMU
Kojto 110:165afa46840b 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 110:165afa46840b 405 __ISB();
Kojto 110:165afa46840b 406 }
Kojto 110:165afa46840b 407
Kojto 110:165afa46840b 408 /******************************** TLB maintenance operations ************************************************/
Kojto 110:165afa46840b 409 /** \brief Invalidate the whole tlb
Kojto 110:165afa46840b 410
Kojto 110:165afa46840b 411 TLBIALL. Invalidate the whole tlb
Kojto 110:165afa46840b 412 */
Kojto 110:165afa46840b 413
Kojto 110:165afa46840b 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 110:165afa46840b 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 110:165afa46840b 416 __TLBIALL = 0;
Kojto 110:165afa46840b 417 __DSB();
Kojto 110:165afa46840b 418 __ISB();
Kojto 110:165afa46840b 419 }
Kojto 110:165afa46840b 420
Kojto 110:165afa46840b 421 /******************************** BTB maintenance operations ************************************************/
Kojto 110:165afa46840b 422 /** \brief Invalidate entire branch predictor array
Kojto 110:165afa46840b 423
Kojto 110:165afa46840b 424 BPIALL. Branch Predictor Invalidate All.
Kojto 110:165afa46840b 425 */
Kojto 110:165afa46840b 426
Kojto 110:165afa46840b 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 110:165afa46840b 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 110:165afa46840b 429 __BPIALL = 0;
Kojto 110:165afa46840b 430 __DSB(); //ensure completion of the invalidation
Kojto 110:165afa46840b 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 110:165afa46840b 432 }
Kojto 110:165afa46840b 433
Kojto 110:165afa46840b 434
Kojto 110:165afa46840b 435 /******************************** L1 cache operations ******************************************************/
Kojto 110:165afa46840b 436
Kojto 110:165afa46840b 437 /** \brief Invalidate the whole I$
Kojto 110:165afa46840b 438
Kojto 110:165afa46840b 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 110:165afa46840b 440 */
Kojto 110:165afa46840b 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 110:165afa46840b 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 110:165afa46840b 443 __ICIALLU = 0;
Kojto 110:165afa46840b 444 __DSB(); //ensure completion of the invalidation
Kojto 110:165afa46840b 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 110:165afa46840b 446 }
Kojto 110:165afa46840b 447
Kojto 110:165afa46840b 448 /** \brief Clean D$ by MVA
Kojto 110:165afa46840b 449
Kojto 110:165afa46840b 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 110:165afa46840b 451 */
Kojto 110:165afa46840b 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 110:165afa46840b 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 110:165afa46840b 454 __DCCMVAC = (uint32_t)va;
Kojto 110:165afa46840b 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 456 }
Kojto 110:165afa46840b 457
Kojto 110:165afa46840b 458 /** \brief Invalidate D$ by MVA
Kojto 110:165afa46840b 459
Kojto 110:165afa46840b 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 110:165afa46840b 461 */
Kojto 110:165afa46840b 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 110:165afa46840b 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 110:165afa46840b 464 __DCIMVAC = (uint32_t)va;
Kojto 110:165afa46840b 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 466 }
Kojto 110:165afa46840b 467
Kojto 110:165afa46840b 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 110:165afa46840b 469
Kojto 110:165afa46840b 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 110:165afa46840b 471 */
Kojto 110:165afa46840b 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 110:165afa46840b 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 110:165afa46840b 474 __DCCIMVAC = (uint32_t)va;
Kojto 110:165afa46840b 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 476 }
Kojto 110:165afa46840b 477
Kojto 110:165afa46840b 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 110:165afa46840b 479
Kojto 110:165afa46840b 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 110:165afa46840b 481 */
Kojto 110:165afa46840b 482 #pragma push
Kojto 110:165afa46840b 483 #pragma arm
Kojto 110:165afa46840b 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 110:165afa46840b 485 ARM
Kojto 110:165afa46840b 486
Kojto 110:165afa46840b 487 PUSH {R4-R11}
Kojto 110:165afa46840b 488
Kojto 110:165afa46840b 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 110:165afa46840b 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 110:165afa46840b 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 110:165afa46840b 492 BEQ Finished // If 0, no need to clean
Kojto 110:165afa46840b 493
Kojto 110:165afa46840b 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 110:165afa46840b 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 110:165afa46840b 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 110:165afa46840b 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 110:165afa46840b 498 CMP R1, #2
Kojto 110:165afa46840b 499 BLT Skip // No cache or only instruction cache at this level
Kojto 110:165afa46840b 500
Kojto 110:165afa46840b 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 110:165afa46840b 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 110:165afa46840b 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 110:165afa46840b 504 AND R2, R1, #7 // Extract the line length field
Kojto 110:165afa46840b 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 110:165afa46840b 506 LDR R4, =0x3FF
Kojto 110:165afa46840b 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 110:165afa46840b 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 110:165afa46840b 509 LDR R7, =0x7FFF
Kojto 110:165afa46840b 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 110:165afa46840b 511
Kojto 110:165afa46840b 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 110:165afa46840b 513
Kojto 110:165afa46840b 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 110:165afa46840b 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 110:165afa46840b 516 CMP R0, #0
Kojto 110:165afa46840b 517 BNE Dccsw
Kojto 110:165afa46840b 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 110:165afa46840b 519 B cont
Kojto 110:165afa46840b 520 Dccsw CMP R0, #1
Kojto 110:165afa46840b 521 BNE Dccisw
Kojto 110:165afa46840b 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 110:165afa46840b 523 B cont
Kojto 110:165afa46840b 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 110:165afa46840b 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 110:165afa46840b 526 BGE Loop3
Kojto 110:165afa46840b 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 110:165afa46840b 528 BGE Loop2
Kojto 110:165afa46840b 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 110:165afa46840b 530 CMP R3, R10
Kojto 110:165afa46840b 531 BGT Loop1
Kojto 110:165afa46840b 532
Kojto 110:165afa46840b 533 Finished
Kojto 110:165afa46840b 534 DSB
Kojto 110:165afa46840b 535 POP {R4-R11}
Kojto 110:165afa46840b 536 BX lr
Kojto 110:165afa46840b 537
Kojto 110:165afa46840b 538 }
Kojto 110:165afa46840b 539 #pragma pop
Kojto 110:165afa46840b 540
Kojto 110:165afa46840b 541
Kojto 110:165afa46840b 542 /** \brief Invalidate the whole D$
Kojto 110:165afa46840b 543
Kojto 110:165afa46840b 544 DCISW. Invalidate by Set/Way
Kojto 110:165afa46840b 545 */
Kojto 110:165afa46840b 546
Kojto 110:165afa46840b 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 110:165afa46840b 548 __v7_all_cache(0);
Kojto 110:165afa46840b 549 }
Kojto 110:165afa46840b 550
Kojto 110:165afa46840b 551 /** \brief Clean the whole D$
Kojto 110:165afa46840b 552
Kojto 110:165afa46840b 553 DCCSW. Clean by Set/Way
Kojto 110:165afa46840b 554 */
Kojto 110:165afa46840b 555
Kojto 110:165afa46840b 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 110:165afa46840b 557 __v7_all_cache(1);
Kojto 110:165afa46840b 558 }
Kojto 110:165afa46840b 559
Kojto 110:165afa46840b 560 /** \brief Clean and invalidate the whole D$
Kojto 110:165afa46840b 561
Kojto 110:165afa46840b 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 110:165afa46840b 563 */
Kojto 110:165afa46840b 564
Kojto 110:165afa46840b 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 110:165afa46840b 566 __v7_all_cache(2);
Kojto 110:165afa46840b 567 }
Kojto 110:165afa46840b 568
Kojto 110:165afa46840b 569 #include "core_ca_mmu.h"
Kojto 110:165afa46840b 570
Kojto 110:165afa46840b 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 110:165afa46840b 572
Kojto 110:165afa46840b 573 #error IAR Compiler support not implemented for Cortex-A
Kojto 110:165afa46840b 574
Kojto 110:165afa46840b 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 110:165afa46840b 576 /* GNU gcc specific functions */
Kojto 110:165afa46840b 577
Kojto 110:165afa46840b 578 #define MODE_USR 0x10
Kojto 110:165afa46840b 579 #define MODE_FIQ 0x11
Kojto 110:165afa46840b 580 #define MODE_IRQ 0x12
Kojto 110:165afa46840b 581 #define MODE_SVC 0x13
Kojto 110:165afa46840b 582 #define MODE_MON 0x16
Kojto 110:165afa46840b 583 #define MODE_ABT 0x17
Kojto 110:165afa46840b 584 #define MODE_HYP 0x1A
Kojto 110:165afa46840b 585 #define MODE_UND 0x1B
Kojto 110:165afa46840b 586 #define MODE_SYS 0x1F
Kojto 110:165afa46840b 587
Kojto 110:165afa46840b 588
Kojto 110:165afa46840b 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 110:165afa46840b 590 {
Kojto 110:165afa46840b 591 __ASM volatile ("cpsie i");
Kojto 110:165afa46840b 592 }
Kojto 110:165afa46840b 593
Kojto 110:165afa46840b 594 /** \brief Disable IRQ Interrupts
Kojto 110:165afa46840b 595
Kojto 110:165afa46840b 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 110:165afa46840b 597 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 598 */
Kojto 110:165afa46840b 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 110:165afa46840b 600 {
Kojto 110:165afa46840b 601 uint32_t result;
Kojto 110:165afa46840b 602
Kojto 110:165afa46840b 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 110:165afa46840b 604 __ASM volatile ("cpsid i");
Kojto 110:165afa46840b 605 return(result & 0x80);
Kojto 110:165afa46840b 606 }
Kojto 110:165afa46840b 607
Kojto 110:165afa46840b 608
Kojto 110:165afa46840b 609 /** \brief Get APSR Register
Kojto 110:165afa46840b 610
Kojto 110:165afa46840b 611 This function returns the content of the APSR Register.
Kojto 110:165afa46840b 612
Kojto 110:165afa46840b 613 \return APSR Register value
Kojto 110:165afa46840b 614 */
Kojto 110:165afa46840b 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 110:165afa46840b 616 {
Kojto 110:165afa46840b 617 #if 1
Kojto 110:165afa46840b 618 register uint32_t __regAPSR;
Kojto 110:165afa46840b 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 110:165afa46840b 620 #else
Kojto 110:165afa46840b 621 register uint32_t __regAPSR __ASM("apsr");
Kojto 110:165afa46840b 622 #endif
Kojto 110:165afa46840b 623 return(__regAPSR);
Kojto 110:165afa46840b 624 }
Kojto 110:165afa46840b 625
Kojto 110:165afa46840b 626
Kojto 110:165afa46840b 627 /** \brief Get CPSR Register
Kojto 110:165afa46840b 628
Kojto 110:165afa46840b 629 This function returns the content of the CPSR Register.
Kojto 110:165afa46840b 630
Kojto 110:165afa46840b 631 \return CPSR Register value
Kojto 110:165afa46840b 632 */
Kojto 110:165afa46840b 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 110:165afa46840b 634 {
Kojto 110:165afa46840b 635 #if 1
Kojto 110:165afa46840b 636 register uint32_t __regCPSR;
Kojto 110:165afa46840b 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 110:165afa46840b 638 #else
Kojto 110:165afa46840b 639 register uint32_t __regCPSR __ASM("cpsr");
Kojto 110:165afa46840b 640 #endif
Kojto 110:165afa46840b 641 return(__regCPSR);
Kojto 110:165afa46840b 642 }
Kojto 110:165afa46840b 643
Kojto 110:165afa46840b 644 #if 0
Kojto 110:165afa46840b 645 /** \brief Set Stack Pointer
Kojto 110:165afa46840b 646
Kojto 110:165afa46840b 647 This function assigns the given value to the current stack pointer.
Kojto 110:165afa46840b 648
Kojto 110:165afa46840b 649 \param [in] topOfStack Stack Pointer value to set
Kojto 110:165afa46840b 650 */
Kojto 110:165afa46840b 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 110:165afa46840b 652 {
Kojto 110:165afa46840b 653 register uint32_t __regSP __ASM("sp");
Kojto 110:165afa46840b 654 __regSP = topOfStack;
Kojto 110:165afa46840b 655 }
Kojto 110:165afa46840b 656 #endif
Kojto 110:165afa46840b 657
Kojto 110:165afa46840b 658 /** \brief Get link register
Kojto 110:165afa46840b 659
Kojto 110:165afa46840b 660 This function returns the value of the link register
Kojto 110:165afa46840b 661
Kojto 110:165afa46840b 662 \return Value of link register
Kojto 110:165afa46840b 663 */
Kojto 110:165afa46840b 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 110:165afa46840b 665 {
Kojto 110:165afa46840b 666 register uint32_t __reglr __ASM("lr");
Kojto 110:165afa46840b 667 return(__reglr);
Kojto 110:165afa46840b 668 }
Kojto 110:165afa46840b 669
Kojto 110:165afa46840b 670 #if 0
Kojto 110:165afa46840b 671 /** \brief Set link register
Kojto 110:165afa46840b 672
Kojto 110:165afa46840b 673 This function sets the value of the link register
Kojto 110:165afa46840b 674
Kojto 110:165afa46840b 675 \param [in] lr LR value to set
Kojto 110:165afa46840b 676 */
Kojto 110:165afa46840b 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 110:165afa46840b 678 {
Kojto 110:165afa46840b 679 register uint32_t __reglr __ASM("lr");
Kojto 110:165afa46840b 680 __reglr = lr;
Kojto 110:165afa46840b 681 }
Kojto 110:165afa46840b 682 #endif
Kojto 110:165afa46840b 683
Kojto 110:165afa46840b 684 /** \brief Set Process Stack Pointer
Kojto 110:165afa46840b 685
Kojto 110:165afa46840b 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 110:165afa46840b 687
Kojto 110:165afa46840b 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 110:165afa46840b 689 */
Kojto 110:165afa46840b 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 110:165afa46840b 691 {
Kojto 110:165afa46840b 692 __asm__ volatile (
Kojto 110:165afa46840b 693 ".ARM;"
Kojto 110:165afa46840b 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 110:165afa46840b 695
Kojto 110:165afa46840b 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 110:165afa46840b 697 "MRS R1, CPSR;"
Kojto 110:165afa46840b 698 "CPS %0;" /* ;no effect in USR mode */
Kojto 110:165afa46840b 699 "MOV SP, R0;"
Kojto 110:165afa46840b 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 110:165afa46840b 701 "ISB;"
Kojto 110:165afa46840b 702 //"BX LR;"
Kojto 110:165afa46840b 703 :
Kojto 110:165afa46840b 704 : "i"(MODE_SYS)
Kojto 110:165afa46840b 705 : "r0", "r1");
Kojto 110:165afa46840b 706 return;
Kojto 110:165afa46840b 707 }
Kojto 110:165afa46840b 708
Kojto 110:165afa46840b 709 /** \brief Set User Mode
Kojto 110:165afa46840b 710
Kojto 110:165afa46840b 711 This function changes the processor state to User Mode
Kojto 110:165afa46840b 712 */
Kojto 110:165afa46840b 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 110:165afa46840b 714 {
Kojto 110:165afa46840b 715 __asm__ volatile (
Kojto 110:165afa46840b 716 ".ARM;"
Kojto 110:165afa46840b 717
Kojto 110:165afa46840b 718 "CPS %0;"
Kojto 110:165afa46840b 719 //"BX LR;"
Kojto 110:165afa46840b 720 :
Kojto 110:165afa46840b 721 : "i"(MODE_USR)
Kojto 110:165afa46840b 722 : );
Kojto 110:165afa46840b 723 return;
Kojto 110:165afa46840b 724 }
Kojto 110:165afa46840b 725
Kojto 110:165afa46840b 726
Kojto 110:165afa46840b 727 /** \brief Enable FIQ
Kojto 110:165afa46840b 728
Kojto 110:165afa46840b 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 110:165afa46840b 730 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 731 */
Kojto 110:165afa46840b 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 110:165afa46840b 733
Kojto 110:165afa46840b 734
Kojto 110:165afa46840b 735 /** \brief Disable FIQ
Kojto 110:165afa46840b 736
Kojto 110:165afa46840b 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 110:165afa46840b 738 Can only be executed in Privileged modes.
Kojto 110:165afa46840b 739 */
Kojto 110:165afa46840b 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 110:165afa46840b 741
Kojto 110:165afa46840b 742
Kojto 110:165afa46840b 743 /** \brief Get FPSCR
Kojto 110:165afa46840b 744
Kojto 110:165afa46840b 745 This function returns the current value of the Floating Point Status/Control register.
Kojto 110:165afa46840b 746
Kojto 110:165afa46840b 747 \return Floating Point Status/Control register value
Kojto 110:165afa46840b 748 */
Kojto 110:165afa46840b 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 110:165afa46840b 750 {
Kojto 110:165afa46840b 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 110:165afa46840b 752 #if 1
Kojto 110:165afa46840b 753 uint32_t result;
Kojto 110:165afa46840b 754
Kojto 110:165afa46840b 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 110:165afa46840b 756 return (result);
Kojto 110:165afa46840b 757 #else
Kojto 110:165afa46840b 758 register uint32_t __regfpscr __ASM("fpscr");
Kojto 110:165afa46840b 759 return(__regfpscr);
Kojto 110:165afa46840b 760 #endif
Kojto 110:165afa46840b 761 #else
Kojto 110:165afa46840b 762 return(0);
Kojto 110:165afa46840b 763 #endif
Kojto 110:165afa46840b 764 }
Kojto 110:165afa46840b 765
Kojto 110:165afa46840b 766
Kojto 110:165afa46840b 767 /** \brief Set FPSCR
Kojto 110:165afa46840b 768
Kojto 110:165afa46840b 769 This function assigns the given value to the Floating Point Status/Control register.
Kojto 110:165afa46840b 770
Kojto 110:165afa46840b 771 \param [in] fpscr Floating Point Status/Control value to set
Kojto 110:165afa46840b 772 */
Kojto 110:165afa46840b 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 110:165afa46840b 774 {
Kojto 110:165afa46840b 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 110:165afa46840b 776 #if 1
Kojto 110:165afa46840b 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 110:165afa46840b 778 #else
Kojto 110:165afa46840b 779 register uint32_t __regfpscr __ASM("fpscr");
Kojto 110:165afa46840b 780 __regfpscr = (fpscr);
Kojto 110:165afa46840b 781 #endif
Kojto 110:165afa46840b 782 #endif
Kojto 110:165afa46840b 783 }
Kojto 110:165afa46840b 784
Kojto 110:165afa46840b 785 /** \brief Get FPEXC
Kojto 110:165afa46840b 786
Kojto 110:165afa46840b 787 This function returns the current value of the Floating Point Exception Control register.
Kojto 110:165afa46840b 788
Kojto 110:165afa46840b 789 \return Floating Point Exception Control register value
Kojto 110:165afa46840b 790 */
Kojto 110:165afa46840b 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 110:165afa46840b 792 {
Kojto 110:165afa46840b 793 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 794 #if 1
Kojto 110:165afa46840b 795 uint32_t result;
Kojto 110:165afa46840b 796
Kojto 110:165afa46840b 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 110:165afa46840b 798 return (result);
Kojto 110:165afa46840b 799 #else
Kojto 110:165afa46840b 800 register uint32_t __regfpexc __ASM("fpexc");
Kojto 110:165afa46840b 801 return(__regfpexc);
Kojto 110:165afa46840b 802 #endif
Kojto 110:165afa46840b 803 #else
Kojto 110:165afa46840b 804 return(0);
Kojto 110:165afa46840b 805 #endif
Kojto 110:165afa46840b 806 }
Kojto 110:165afa46840b 807
Kojto 110:165afa46840b 808
Kojto 110:165afa46840b 809 /** \brief Set FPEXC
Kojto 110:165afa46840b 810
Kojto 110:165afa46840b 811 This function assigns the given value to the Floating Point Exception Control register.
Kojto 110:165afa46840b 812
Kojto 110:165afa46840b 813 \param [in] fpscr Floating Point Exception Control value to set
Kojto 110:165afa46840b 814 */
Kojto 110:165afa46840b 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 110:165afa46840b 816 {
Kojto 110:165afa46840b 817 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 818 #if 1
Kojto 110:165afa46840b 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 110:165afa46840b 820 #else
Kojto 110:165afa46840b 821 register uint32_t __regfpexc __ASM("fpexc");
Kojto 110:165afa46840b 822 __regfpexc = (fpexc);
Kojto 110:165afa46840b 823 #endif
Kojto 110:165afa46840b 824 #endif
Kojto 110:165afa46840b 825 }
Kojto 110:165afa46840b 826
Kojto 110:165afa46840b 827 /** \brief Get CPACR
Kojto 110:165afa46840b 828
Kojto 110:165afa46840b 829 This function returns the current value of the Coprocessor Access Control register.
Kojto 110:165afa46840b 830
Kojto 110:165afa46840b 831 \return Coprocessor Access Control register value
Kojto 110:165afa46840b 832 */
Kojto 110:165afa46840b 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 110:165afa46840b 834 {
Kojto 110:165afa46840b 835 #if 1
Kojto 110:165afa46840b 836 register uint32_t __regCPACR;
Kojto 110:165afa46840b 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 110:165afa46840b 838 #else
Kojto 110:165afa46840b 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 110:165afa46840b 840 #endif
Kojto 110:165afa46840b 841 return __regCPACR;
Kojto 110:165afa46840b 842 }
Kojto 110:165afa46840b 843
Kojto 110:165afa46840b 844 /** \brief Set CPACR
Kojto 110:165afa46840b 845
Kojto 110:165afa46840b 846 This function assigns the given value to the Coprocessor Access Control register.
Kojto 110:165afa46840b 847
Kojto 110:165afa46840b 848 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 110:165afa46840b 849 */
Kojto 110:165afa46840b 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 110:165afa46840b 851 {
Kojto 110:165afa46840b 852 #if 1
Kojto 110:165afa46840b 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 110:165afa46840b 854 #else
Kojto 110:165afa46840b 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 110:165afa46840b 856 __regCPACR = cpacr;
Kojto 110:165afa46840b 857 #endif
Kojto 110:165afa46840b 858 __ISB();
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860
Kojto 110:165afa46840b 861 /** \brief Get CBAR
Kojto 110:165afa46840b 862
Kojto 110:165afa46840b 863 This function returns the value of the Configuration Base Address register.
Kojto 110:165afa46840b 864
Kojto 110:165afa46840b 865 \return Configuration Base Address register value
Kojto 110:165afa46840b 866 */
Kojto 110:165afa46840b 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 110:165afa46840b 868 #if 1
Kojto 110:165afa46840b 869 register uint32_t __regCBAR;
Kojto 110:165afa46840b 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 110:165afa46840b 871 #else
Kojto 110:165afa46840b 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 110:165afa46840b 873 #endif
Kojto 110:165afa46840b 874 return(__regCBAR);
Kojto 110:165afa46840b 875 }
Kojto 110:165afa46840b 876
Kojto 110:165afa46840b 877 /** \brief Get TTBR0
Kojto 110:165afa46840b 878
Kojto 110:165afa46840b 879 This function returns the value of the Translation Table Base Register 0.
Kojto 110:165afa46840b 880
Kojto 110:165afa46840b 881 \return Translation Table Base Register 0 value
Kojto 110:165afa46840b 882 */
Kojto 110:165afa46840b 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 110:165afa46840b 884 #if 1
Kojto 110:165afa46840b 885 register uint32_t __regTTBR0;
Kojto 110:165afa46840b 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 110:165afa46840b 887 #else
Kojto 110:165afa46840b 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 110:165afa46840b 889 #endif
Kojto 110:165afa46840b 890 return(__regTTBR0);
Kojto 110:165afa46840b 891 }
Kojto 110:165afa46840b 892
Kojto 110:165afa46840b 893 /** \brief Set TTBR0
Kojto 110:165afa46840b 894
Kojto 110:165afa46840b 895 This function assigns the given value to the Translation Table Base Register 0.
Kojto 110:165afa46840b 896
Kojto 110:165afa46840b 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 110:165afa46840b 898 */
Kojto 110:165afa46840b 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 110:165afa46840b 900 #if 1
Kojto 110:165afa46840b 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 110:165afa46840b 902 #else
Kojto 110:165afa46840b 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 110:165afa46840b 904 __regTTBR0 = ttbr0;
Kojto 110:165afa46840b 905 #endif
Kojto 110:165afa46840b 906 __ISB();
Kojto 110:165afa46840b 907 }
Kojto 110:165afa46840b 908
Kojto 110:165afa46840b 909 /** \brief Get DACR
Kojto 110:165afa46840b 910
Kojto 110:165afa46840b 911 This function returns the value of the Domain Access Control Register.
Kojto 110:165afa46840b 912
Kojto 110:165afa46840b 913 \return Domain Access Control Register value
Kojto 110:165afa46840b 914 */
Kojto 110:165afa46840b 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 110:165afa46840b 916 #if 1
Kojto 110:165afa46840b 917 register uint32_t __regDACR;
Kojto 110:165afa46840b 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 110:165afa46840b 919 #else
Kojto 110:165afa46840b 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 110:165afa46840b 921 #endif
Kojto 110:165afa46840b 922 return(__regDACR);
Kojto 110:165afa46840b 923 }
Kojto 110:165afa46840b 924
Kojto 110:165afa46840b 925 /** \brief Set DACR
Kojto 110:165afa46840b 926
Kojto 110:165afa46840b 927 This function assigns the given value to the Domain Access Control Register.
Kojto 110:165afa46840b 928
Kojto 110:165afa46840b 929 \param [in] dacr Domain Access Control Register value to set
Kojto 110:165afa46840b 930 */
Kojto 110:165afa46840b 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 110:165afa46840b 932 #if 1
Kojto 110:165afa46840b 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 110:165afa46840b 934 #else
Kojto 110:165afa46840b 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 110:165afa46840b 936 __regDACR = dacr;
Kojto 110:165afa46840b 937 #endif
Kojto 110:165afa46840b 938 __ISB();
Kojto 110:165afa46840b 939 }
Kojto 110:165afa46840b 940
Kojto 110:165afa46840b 941 /******************************** Cache and BTAC enable ****************************************************/
Kojto 110:165afa46840b 942
Kojto 110:165afa46840b 943 /** \brief Set SCTLR
Kojto 110:165afa46840b 944
Kojto 110:165afa46840b 945 This function assigns the given value to the System Control Register.
Kojto 110:165afa46840b 946
Kojto 110:165afa46840b 947 \param [in] sctlr System Control Register value to set
Kojto 110:165afa46840b 948 */
Kojto 110:165afa46840b 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 110:165afa46840b 950 {
Kojto 110:165afa46840b 951 #if 1
Kojto 110:165afa46840b 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 110:165afa46840b 953 #else
Kojto 110:165afa46840b 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 110:165afa46840b 955 __regSCTLR = sctlr;
Kojto 110:165afa46840b 956 #endif
Kojto 110:165afa46840b 957 }
Kojto 110:165afa46840b 958
Kojto 110:165afa46840b 959 /** \brief Get SCTLR
Kojto 110:165afa46840b 960
Kojto 110:165afa46840b 961 This function returns the value of the System Control Register.
Kojto 110:165afa46840b 962
Kojto 110:165afa46840b 963 \return System Control Register value
Kojto 110:165afa46840b 964 */
Kojto 110:165afa46840b 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 110:165afa46840b 966 #if 1
Kojto 110:165afa46840b 967 register uint32_t __regSCTLR;
Kojto 110:165afa46840b 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 110:165afa46840b 969 #else
Kojto 110:165afa46840b 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 110:165afa46840b 971 #endif
Kojto 110:165afa46840b 972 return(__regSCTLR);
Kojto 110:165afa46840b 973 }
Kojto 110:165afa46840b 974
Kojto 110:165afa46840b 975 /** \brief Enable Caches
Kojto 110:165afa46840b 976
Kojto 110:165afa46840b 977 Enable Caches
Kojto 110:165afa46840b 978 */
Kojto 110:165afa46840b 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 110:165afa46840b 980 // Set I bit 12 to enable I Cache
Kojto 110:165afa46840b 981 // Set C bit 2 to enable D Cache
Kojto 110:165afa46840b 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 110:165afa46840b 983 }
Kojto 110:165afa46840b 984
Kojto 110:165afa46840b 985 /** \brief Disable Caches
Kojto 110:165afa46840b 986
Kojto 110:165afa46840b 987 Disable Caches
Kojto 110:165afa46840b 988 */
Kojto 110:165afa46840b 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 110:165afa46840b 990 // Clear I bit 12 to disable I Cache
Kojto 110:165afa46840b 991 // Clear C bit 2 to disable D Cache
Kojto 110:165afa46840b 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 110:165afa46840b 993 __ISB();
Kojto 110:165afa46840b 994 }
Kojto 110:165afa46840b 995
Kojto 110:165afa46840b 996 /** \brief Enable BTAC
Kojto 110:165afa46840b 997
Kojto 110:165afa46840b 998 Enable BTAC
Kojto 110:165afa46840b 999 */
Kojto 110:165afa46840b 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 110:165afa46840b 1001 // Set Z bit 11 to enable branch prediction
Kojto 110:165afa46840b 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 110:165afa46840b 1003 __ISB();
Kojto 110:165afa46840b 1004 }
Kojto 110:165afa46840b 1005
Kojto 110:165afa46840b 1006 /** \brief Disable BTAC
Kojto 110:165afa46840b 1007
Kojto 110:165afa46840b 1008 Disable BTAC
Kojto 110:165afa46840b 1009 */
Kojto 110:165afa46840b 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 110:165afa46840b 1011 // Clear Z bit 11 to disable branch prediction
Kojto 110:165afa46840b 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 110:165afa46840b 1013 }
Kojto 110:165afa46840b 1014
Kojto 110:165afa46840b 1015
Kojto 110:165afa46840b 1016 /** \brief Enable MMU
Kojto 110:165afa46840b 1017
Kojto 110:165afa46840b 1018 Enable MMU
Kojto 110:165afa46840b 1019 */
Kojto 110:165afa46840b 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 110:165afa46840b 1021 // Set M bit 0 to enable the MMU
Kojto 110:165afa46840b 1022 // Set AFE bit to enable simplified access permissions model
Kojto 110:165afa46840b 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 110:165afa46840b 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 110:165afa46840b 1025 __ISB();
Kojto 110:165afa46840b 1026 }
Kojto 110:165afa46840b 1027
Kojto 110:165afa46840b 1028 /** \brief Disable MMU
Kojto 110:165afa46840b 1029
Kojto 110:165afa46840b 1030 Disable MMU
Kojto 110:165afa46840b 1031 */
Kojto 110:165afa46840b 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 110:165afa46840b 1033 // Clear M bit 0 to disable the MMU
Kojto 110:165afa46840b 1034 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 110:165afa46840b 1035 __ISB();
Kojto 110:165afa46840b 1036 }
Kojto 110:165afa46840b 1037
Kojto 110:165afa46840b 1038 /******************************** TLB maintenance operations ************************************************/
Kojto 110:165afa46840b 1039 /** \brief Invalidate the whole tlb
Kojto 110:165afa46840b 1040
Kojto 110:165afa46840b 1041 TLBIALL. Invalidate the whole tlb
Kojto 110:165afa46840b 1042 */
Kojto 110:165afa46840b 1043
Kojto 110:165afa46840b 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 110:165afa46840b 1045 #if 1
Kojto 110:165afa46840b 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 110:165afa46840b 1047 #else
Kojto 110:165afa46840b 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 110:165afa46840b 1049 __TLBIALL = 0;
Kojto 110:165afa46840b 1050 #endif
Kojto 110:165afa46840b 1051 __DSB();
Kojto 110:165afa46840b 1052 __ISB();
Kojto 110:165afa46840b 1053 }
Kojto 110:165afa46840b 1054
Kojto 110:165afa46840b 1055 /******************************** BTB maintenance operations ************************************************/
Kojto 110:165afa46840b 1056 /** \brief Invalidate entire branch predictor array
Kojto 110:165afa46840b 1057
Kojto 110:165afa46840b 1058 BPIALL. Branch Predictor Invalidate All.
Kojto 110:165afa46840b 1059 */
Kojto 110:165afa46840b 1060
Kojto 110:165afa46840b 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 110:165afa46840b 1062 #if 1
Kojto 110:165afa46840b 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 110:165afa46840b 1064 #else
Kojto 110:165afa46840b 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 110:165afa46840b 1066 __BPIALL = 0;
Kojto 110:165afa46840b 1067 #endif
Kojto 110:165afa46840b 1068 __DSB(); //ensure completion of the invalidation
Kojto 110:165afa46840b 1069 __ISB(); //ensure instruction fetch path sees new state
Kojto 110:165afa46840b 1070 }
Kojto 110:165afa46840b 1071
Kojto 110:165afa46840b 1072
Kojto 110:165afa46840b 1073 /******************************** L1 cache operations ******************************************************/
Kojto 110:165afa46840b 1074
Kojto 110:165afa46840b 1075 /** \brief Invalidate the whole I$
Kojto 110:165afa46840b 1076
Kojto 110:165afa46840b 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 110:165afa46840b 1078 */
Kojto 110:165afa46840b 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 110:165afa46840b 1080 #if 1
Kojto 110:165afa46840b 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 110:165afa46840b 1082 #else
Kojto 110:165afa46840b 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 110:165afa46840b 1084 __ICIALLU = 0;
Kojto 110:165afa46840b 1085 #endif
Kojto 110:165afa46840b 1086 __DSB(); //ensure completion of the invalidation
Kojto 110:165afa46840b 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 110:165afa46840b 1088 }
Kojto 110:165afa46840b 1089
Kojto 110:165afa46840b 1090 /** \brief Clean D$ by MVA
Kojto 110:165afa46840b 1091
Kojto 110:165afa46840b 1092 DCCMVAC. Data cache clean by MVA to PoC
Kojto 110:165afa46840b 1093 */
Kojto 110:165afa46840b 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 110:165afa46840b 1095 #if 1
Kojto 110:165afa46840b 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 110:165afa46840b 1097 #else
Kojto 110:165afa46840b 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 110:165afa46840b 1099 __DCCMVAC = (uint32_t)va;
Kojto 110:165afa46840b 1100 #endif
Kojto 110:165afa46840b 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 1102 }
Kojto 110:165afa46840b 1103
Kojto 110:165afa46840b 1104 /** \brief Invalidate D$ by MVA
Kojto 110:165afa46840b 1105
Kojto 110:165afa46840b 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 110:165afa46840b 1107 */
Kojto 110:165afa46840b 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 110:165afa46840b 1109 #if 1
Kojto 110:165afa46840b 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 110:165afa46840b 1111 #else
Kojto 110:165afa46840b 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 110:165afa46840b 1113 __DCIMVAC = (uint32_t)va;
Kojto 110:165afa46840b 1114 #endif
Kojto 110:165afa46840b 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 1116 }
Kojto 110:165afa46840b 1117
Kojto 110:165afa46840b 1118 /** \brief Clean and Invalidate D$ by MVA
Kojto 110:165afa46840b 1119
Kojto 110:165afa46840b 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 110:165afa46840b 1121 */
Kojto 110:165afa46840b 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 110:165afa46840b 1123 #if 1
Kojto 110:165afa46840b 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 110:165afa46840b 1125 #else
Kojto 110:165afa46840b 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 110:165afa46840b 1127 __DCCIMVAC = (uint32_t)va;
Kojto 110:165afa46840b 1128 #endif
Kojto 110:165afa46840b 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 110:165afa46840b 1130 }
Kojto 110:165afa46840b 1131
Kojto 110:165afa46840b 1132 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 110:165afa46840b 1133
Kojto 110:165afa46840b 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 110:165afa46840b 1135 */
Kojto 110:165afa46840b 1136 extern void __v7_all_cache(uint32_t op);
Kojto 110:165afa46840b 1137
Kojto 110:165afa46840b 1138
Kojto 110:165afa46840b 1139 /** \brief Invalidate the whole D$
Kojto 110:165afa46840b 1140
Kojto 110:165afa46840b 1141 DCISW. Invalidate by Set/Way
Kojto 110:165afa46840b 1142 */
Kojto 110:165afa46840b 1143
Kojto 110:165afa46840b 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 110:165afa46840b 1145 __v7_all_cache(0);
Kojto 110:165afa46840b 1146 }
Kojto 110:165afa46840b 1147
Kojto 110:165afa46840b 1148 /** \brief Clean the whole D$
Kojto 110:165afa46840b 1149
Kojto 110:165afa46840b 1150 DCCSW. Clean by Set/Way
Kojto 110:165afa46840b 1151 */
Kojto 110:165afa46840b 1152
Kojto 110:165afa46840b 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 110:165afa46840b 1154 __v7_all_cache(1);
Kojto 110:165afa46840b 1155 }
Kojto 110:165afa46840b 1156
Kojto 110:165afa46840b 1157 /** \brief Clean and invalidate the whole D$
Kojto 110:165afa46840b 1158
Kojto 110:165afa46840b 1159 DCCISW. Clean and Invalidate by Set/Way
Kojto 110:165afa46840b 1160 */
Kojto 110:165afa46840b 1161
Kojto 110:165afa46840b 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 110:165afa46840b 1163 __v7_all_cache(2);
Kojto 110:165afa46840b 1164 }
Kojto 110:165afa46840b 1165
Kojto 110:165afa46840b 1166 #include "core_ca_mmu.h"
Kojto 110:165afa46840b 1167
Kojto 110:165afa46840b 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 110:165afa46840b 1169
Kojto 110:165afa46840b 1170 #error TASKING Compiler support not implemented for Cortex-A
Kojto 110:165afa46840b 1171
Kojto 110:165afa46840b 1172 #endif
Kojto 110:165afa46840b 1173
Kojto 110:165afa46840b 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 110:165afa46840b 1175
Kojto 110:165afa46840b 1176
Kojto 110:165afa46840b 1177 #endif /* __CORE_CAFUNC_H__ */