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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC11U35_401/core_cm0plus.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 74:a842253909c9 1 /**************************************************************************//**
bogdanm 74:a842253909c9 2 * @file core_cm0plus.h
bogdanm 74:a842253909c9 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 74:a842253909c9 6 *
bogdanm 74:a842253909c9 7 * @note
bogdanm 74:a842253909c9 8 *
bogdanm 74:a842253909c9 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 74:a842253909c9 11
bogdanm 74:a842253909c9 12 All rights reserved.
bogdanm 74:a842253909c9 13 Redistribution and use in source and binary forms, with or without
bogdanm 74:a842253909c9 14 modification, are permitted provided that the following conditions are met:
bogdanm 74:a842253909c9 15 - Redistributions of source code must retain the above copyright
bogdanm 74:a842253909c9 16 notice, this list of conditions and the following disclaimer.
bogdanm 74:a842253909c9 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 74:a842253909c9 18 notice, this list of conditions and the following disclaimer in the
bogdanm 74:a842253909c9 19 documentation and/or other materials provided with the distribution.
bogdanm 74:a842253909c9 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 74:a842253909c9 21 to endorse or promote products derived from this software without
bogdanm 74:a842253909c9 22 specific prior written permission.
bogdanm 74:a842253909c9 23 *
bogdanm 74:a842253909c9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 74:a842253909c9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 74:a842253909c9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 74:a842253909c9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 74:a842253909c9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 74:a842253909c9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 74:a842253909c9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 74:a842253909c9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 74:a842253909c9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 74:a842253909c9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 74:a842253909c9 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 74:a842253909c9 35 ---------------------------------------------------------------------------*/
bogdanm 74:a842253909c9 36
bogdanm 74:a842253909c9 37
bogdanm 74:a842253909c9 38 #if defined ( __ICCARM__ )
bogdanm 74:a842253909c9 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 74:a842253909c9 40 #endif
bogdanm 74:a842253909c9 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 74:a842253909c9 45 #ifdef __cplusplus
bogdanm 74:a842253909c9 46 extern "C" {
bogdanm 74:a842253909c9 47 #endif
bogdanm 74:a842253909c9 48
bogdanm 74:a842253909c9 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 74:a842253909c9 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 74:a842253909c9 51
bogdanm 74:a842253909c9 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 74:a842253909c9 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 74:a842253909c9 54
bogdanm 74:a842253909c9 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 74:a842253909c9 56 Unions are used for effective representation of core registers.
bogdanm 74:a842253909c9 57
bogdanm 74:a842253909c9 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 74:a842253909c9 59 Function-like macros are used to allow more efficient code.
bogdanm 74:a842253909c9 60 */
bogdanm 74:a842253909c9 61
bogdanm 74:a842253909c9 62
bogdanm 74:a842253909c9 63 /*******************************************************************************
bogdanm 74:a842253909c9 64 * CMSIS definitions
bogdanm 74:a842253909c9 65 ******************************************************************************/
bogdanm 74:a842253909c9 66 /** \ingroup Cortex-M0+
bogdanm 74:a842253909c9 67 @{
bogdanm 74:a842253909c9 68 */
bogdanm 74:a842253909c9 69
bogdanm 74:a842253909c9 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 74:a842253909c9 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 74:a842253909c9 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 74:a842253909c9 75
bogdanm 74:a842253909c9 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 74:a842253909c9 77
bogdanm 74:a842253909c9 78
bogdanm 74:a842253909c9 79 #if defined ( __CC_ARM )
bogdanm 74:a842253909c9 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 74:a842253909c9 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 74:a842253909c9 82 #define __STATIC_INLINE static __inline
bogdanm 74:a842253909c9 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 74:a842253909c9 89 #elif defined ( __ICCARM__ )
bogdanm 74:a842253909c9 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 74:a842253909c9 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 74:a842253909c9 92 #define __STATIC_INLINE static inline
bogdanm 74:a842253909c9 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 74:a842253909c9 96 #define __STATIC_INLINE static inline
bogdanm 74:a842253909c9 97
bogdanm 74:a842253909c9 98 #elif defined ( __TASKING__ )
bogdanm 74:a842253909c9 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 74:a842253909c9 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 74:a842253909c9 101 #define __STATIC_INLINE static inline
bogdanm 74:a842253909c9 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 74:a842253909c9 109 #endif
bogdanm 74:a842253909c9 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 74:a842253909c9 113 */
bogdanm 74:a842253909c9 114 #define __FPU_USED 0
bogdanm 74:a842253909c9 115
bogdanm 74:a842253909c9 116 #if defined ( __CC_ARM )
bogdanm 74:a842253909c9 117 #if defined __TARGET_FPU_VFP
bogdanm 74:a842253909c9 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 119 #endif
bogdanm 74:a842253909c9 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 74:a842253909c9 126 #elif defined ( __ICCARM__ )
bogdanm 74:a842253909c9 127 #if defined __ARMVFP__
bogdanm 74:a842253909c9 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 129 #endif
bogdanm 74:a842253909c9 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
bogdanm 74:a842253909c9 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 134 #endif
bogdanm 74:a842253909c9 135
bogdanm 74:a842253909c9 136 #elif defined ( __TASKING__ )
bogdanm 74:a842253909c9 137 #if defined __FPU_VFP__
bogdanm 74:a842253909c9 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
bogdanm 74:a842253909c9 145 #endif
bogdanm 74:a842253909c9 146
bogdanm 74:a842253909c9 147 #include <stdint.h> /* standard types definitions */
bogdanm 74:a842253909c9 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 74:a842253909c9 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 74:a842253909c9 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 74:a842253909c9 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 74:a842253909c9 156
bogdanm 74:a842253909c9 157 #ifndef __CMSIS_GENERIC
bogdanm 74:a842253909c9 158
bogdanm 74:a842253909c9 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 74:a842253909c9 160 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 74:a842253909c9 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 74:a842253909c9 166 /* check device defines and use defaults */
bogdanm 74:a842253909c9 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 74:a842253909c9 168 #ifndef __CM0PLUS_REV
bogdanm 74:a842253909c9 169 #define __CM0PLUS_REV 0x0000
bogdanm 74:a842253909c9 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 74:a842253909c9 171 #endif
bogdanm 74:a842253909c9 172
bogdanm 74:a842253909c9 173 #ifndef __MPU_PRESENT
bogdanm 74:a842253909c9 174 #define __MPU_PRESENT 0
bogdanm 74:a842253909c9 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 74:a842253909c9 176 #endif
bogdanm 74:a842253909c9 177
bogdanm 74:a842253909c9 178 #ifndef __VTOR_PRESENT
bogdanm 74:a842253909c9 179 #define __VTOR_PRESENT 0
bogdanm 74:a842253909c9 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 74:a842253909c9 181 #endif
bogdanm 74:a842253909c9 182
bogdanm 74:a842253909c9 183 #ifndef __NVIC_PRIO_BITS
bogdanm 74:a842253909c9 184 #define __NVIC_PRIO_BITS 2
bogdanm 74:a842253909c9 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 74:a842253909c9 186 #endif
bogdanm 74:a842253909c9 187
bogdanm 74:a842253909c9 188 #ifndef __Vendor_SysTickConfig
bogdanm 74:a842253909c9 189 #define __Vendor_SysTickConfig 0
bogdanm 74:a842253909c9 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 74:a842253909c9 191 #endif
bogdanm 74:a842253909c9 192 #endif
bogdanm 74:a842253909c9 193
bogdanm 74:a842253909c9 194 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 74:a842253909c9 195 /**
bogdanm 74:a842253909c9 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 74:a842253909c9 197
bogdanm 74:a842253909c9 198 <strong>IO Type Qualifiers</strong> are used
bogdanm 74:a842253909c9 199 \li to specify the access to peripheral variables.
bogdanm 74:a842253909c9 200 \li for automatic generation of peripheral register debug information.
bogdanm 74:a842253909c9 201 */
bogdanm 74:a842253909c9 202 #ifdef __cplusplus
bogdanm 74:a842253909c9 203 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 74:a842253909c9 204 #else
bogdanm 74:a842253909c9 205 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 74:a842253909c9 206 #endif
bogdanm 74:a842253909c9 207 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 74:a842253909c9 208 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 74:a842253909c9 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
bogdanm 74:a842253909c9 218 /*@} end of group Cortex-M0+ */
bogdanm 74:a842253909c9 219
bogdanm 74:a842253909c9 220
bogdanm 74:a842253909c9 221
bogdanm 74:a842253909c9 222 /*******************************************************************************
bogdanm 74:a842253909c9 223 * Register Abstraction
bogdanm 74:a842253909c9 224 Core Register contain:
bogdanm 74:a842253909c9 225 - Core Register
bogdanm 74:a842253909c9 226 - Core NVIC Register
bogdanm 74:a842253909c9 227 - Core SCB Register
bogdanm 74:a842253909c9 228 - Core SysTick Register
bogdanm 74:a842253909c9 229 - Core MPU Register
bogdanm 74:a842253909c9 230 ******************************************************************************/
bogdanm 74:a842253909c9 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 74:a842253909c9 232 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 74:a842253909c9 233 */
bogdanm 74:a842253909c9 234
bogdanm 74:a842253909c9 235 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 236 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 74:a842253909c9 237 \brief Core Register type definitions.
bogdanm 74:a842253909c9 238 @{
bogdanm 74:a842253909c9 239 */
bogdanm 74:a842253909c9 240
bogdanm 74:a842253909c9 241 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 74:a842253909c9 242 */
bogdanm 74:a842253909c9 243 typedef union
bogdanm 74:a842253909c9 244 {
bogdanm 74:a842253909c9 245 struct
bogdanm 74:a842253909c9 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 74:a842253909c9 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 74:a842253909c9 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 74:a842253909c9 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 74:a842253909c9 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 74:a842253909c9 252 } b; /*!< Structure used for bit access */
bogdanm 74:a842253909c9 253 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 254 } APSR_Type;
bogdanm 74:a842253909c9 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
bogdanm 74:a842253909c9 269
bogdanm 74:a842253909c9 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 74:a842253909c9 271 */
bogdanm 74:a842253909c9 272 typedef union
bogdanm 74:a842253909c9 273 {
bogdanm 74:a842253909c9 274 struct
bogdanm 74:a842253909c9 275 {
bogdanm 74:a842253909c9 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 74:a842253909c9 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 74:a842253909c9 278 } b; /*!< Structure used for bit access */
bogdanm 74:a842253909c9 279 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 280 } IPSR_Type;
bogdanm 74:a842253909c9 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
bogdanm 74:a842253909c9 286
bogdanm 74:a842253909c9 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 74:a842253909c9 288 */
bogdanm 74:a842253909c9 289 typedef union
bogdanm 74:a842253909c9 290 {
bogdanm 74:a842253909c9 291 struct
bogdanm 74:a842253909c9 292 {
bogdanm 74:a842253909c9 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 74:a842253909c9 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 74:a842253909c9 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 74:a842253909c9 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 74:a842253909c9 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 74:a842253909c9 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 74:a842253909c9 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 74:a842253909c9 301 } b; /*!< Structure used for bit access */
bogdanm 74:a842253909c9 302 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 303 } xPSR_Type;
bogdanm 74:a842253909c9 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
bogdanm 74:a842253909c9 324
bogdanm 74:a842253909c9 325 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 74:a842253909c9 326 */
bogdanm 74:a842253909c9 327 typedef union
bogdanm 74:a842253909c9 328 {
bogdanm 74:a842253909c9 329 struct
bogdanm 74:a842253909c9 330 {
bogdanm 74:a842253909c9 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 74:a842253909c9 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 74:a842253909c9 334 } b; /*!< Structure used for bit access */
bogdanm 74:a842253909c9 335 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 336 } CONTROL_Type;
bogdanm 74:a842253909c9 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
bogdanm 74:a842253909c9 345 /*@} end of group CMSIS_CORE */
bogdanm 74:a842253909c9 346
bogdanm 74:a842253909c9 347
bogdanm 74:a842253909c9 348 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 74:a842253909c9 350 \brief Type definitions for the NVIC Registers
bogdanm 74:a842253909c9 351 @{
bogdanm 74:a842253909c9 352 */
bogdanm 74:a842253909c9 353
bogdanm 74:a842253909c9 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 74:a842253909c9 355 */
bogdanm 74:a842253909c9 356 typedef struct
bogdanm 74:a842253909c9 357 {
bogdanm 74:a842253909c9 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 74:a842253909c9 359 uint32_t RESERVED0[31];
bogdanm 74:a842253909c9 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 74:a842253909c9 361 uint32_t RSERVED1[31];
bogdanm 74:a842253909c9 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 74:a842253909c9 363 uint32_t RESERVED2[31];
bogdanm 74:a842253909c9 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 74:a842253909c9 365 uint32_t RESERVED3[31];
bogdanm 74:a842253909c9 366 uint32_t RESERVED4[64];
bogdanm 74:a842253909c9 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 74:a842253909c9 368 } NVIC_Type;
bogdanm 74:a842253909c9 369
bogdanm 74:a842253909c9 370 /*@} end of group CMSIS_NVIC */
bogdanm 74:a842253909c9 371
bogdanm 74:a842253909c9 372
bogdanm 74:a842253909c9 373 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 374 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 74:a842253909c9 375 \brief Type definitions for the System Control Block Registers
bogdanm 74:a842253909c9 376 @{
bogdanm 74:a842253909c9 377 */
bogdanm 74:a842253909c9 378
bogdanm 74:a842253909c9 379 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 74:a842253909c9 380 */
bogdanm 74:a842253909c9 381 typedef struct
bogdanm 74:a842253909c9 382 {
bogdanm 74:a842253909c9 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 74:a842253909c9 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 74:a842253909c9 385 #if (__VTOR_PRESENT == 1)
bogdanm 74:a842253909c9 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 74:a842253909c9 387 #else
bogdanm 74:a842253909c9 388 uint32_t RESERVED0;
bogdanm 74:a842253909c9 389 #endif
bogdanm 74:a842253909c9 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 74:a842253909c9 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 74:a842253909c9 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 74:a842253909c9 393 uint32_t RESERVED1;
bogdanm 74:a842253909c9 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 74:a842253909c9 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 74:a842253909c9 396 } SCB_Type;
bogdanm 74:a842253909c9 397
bogdanm 74:a842253909c9 398 /* SCB CPUID Register Definitions */
bogdanm 74:a842253909c9 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 74:a842253909c9 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 74:a842253909c9 401
bogdanm 74:a842253909c9 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 74:a842253909c9 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 74:a842253909c9 404
bogdanm 74:a842253909c9 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 74:a842253909c9 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 74:a842253909c9 407
bogdanm 74:a842253909c9 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 74:a842253909c9 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 74:a842253909c9 410
bogdanm 74:a842253909c9 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 74:a842253909c9 413
bogdanm 74:a842253909c9 414 /* SCB Interrupt Control State Register Definitions */
bogdanm 74:a842253909c9 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 74:a842253909c9 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 74:a842253909c9 417
bogdanm 74:a842253909c9 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 74:a842253909c9 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 74:a842253909c9 420
bogdanm 74:a842253909c9 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 74:a842253909c9 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 74:a842253909c9 423
bogdanm 74:a842253909c9 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 74:a842253909c9 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 74:a842253909c9 426
bogdanm 74:a842253909c9 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 74:a842253909c9 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 74:a842253909c9 429
bogdanm 74:a842253909c9 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 74:a842253909c9 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 74:a842253909c9 432
bogdanm 74:a842253909c9 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 74:a842253909c9 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 74:a842253909c9 435
bogdanm 74:a842253909c9 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 74:a842253909c9 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 74:a842253909c9 438
bogdanm 74:a842253909c9 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 74:a842253909c9 441
bogdanm 74:a842253909c9 442 #if (__VTOR_PRESENT == 1)
bogdanm 74:a842253909c9 443 /* SCB Interrupt Control State Register Definitions */
bogdanm 74:a842253909c9 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 74:a842253909c9 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 74:a842253909c9 446 #endif
bogdanm 74:a842253909c9 447
bogdanm 74:a842253909c9 448 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 74:a842253909c9 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 74:a842253909c9 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 74:a842253909c9 451
bogdanm 74:a842253909c9 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 74:a842253909c9 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 74:a842253909c9 454
bogdanm 74:a842253909c9 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 74:a842253909c9 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 74:a842253909c9 457
bogdanm 74:a842253909c9 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 74:a842253909c9 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 74:a842253909c9 460
bogdanm 74:a842253909c9 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 74:a842253909c9 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 74:a842253909c9 463
bogdanm 74:a842253909c9 464 /* SCB System Control Register Definitions */
bogdanm 74:a842253909c9 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 74:a842253909c9 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 74:a842253909c9 467
bogdanm 74:a842253909c9 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 74:a842253909c9 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 74:a842253909c9 470
bogdanm 74:a842253909c9 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 74:a842253909c9 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 74:a842253909c9 473
bogdanm 74:a842253909c9 474 /* SCB Configuration Control Register Definitions */
bogdanm 74:a842253909c9 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 74:a842253909c9 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 74:a842253909c9 477
bogdanm 74:a842253909c9 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 74:a842253909c9 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 74:a842253909c9 480
bogdanm 74:a842253909c9 481 /* SCB System Handler Control and State Register Definitions */
bogdanm 74:a842253909c9 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 74:a842253909c9 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 74:a842253909c9 484
bogdanm 74:a842253909c9 485 /*@} end of group CMSIS_SCB */
bogdanm 74:a842253909c9 486
bogdanm 74:a842253909c9 487
bogdanm 74:a842253909c9 488 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 74:a842253909c9 490 \brief Type definitions for the System Timer Registers.
bogdanm 74:a842253909c9 491 @{
bogdanm 74:a842253909c9 492 */
bogdanm 74:a842253909c9 493
bogdanm 74:a842253909c9 494 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 74:a842253909c9 495 */
bogdanm 74:a842253909c9 496 typedef struct
bogdanm 74:a842253909c9 497 {
bogdanm 74:a842253909c9 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 74:a842253909c9 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 74:a842253909c9 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 74:a842253909c9 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 74:a842253909c9 502 } SysTick_Type;
bogdanm 74:a842253909c9 503
bogdanm 74:a842253909c9 504 /* SysTick Control / Status Register Definitions */
bogdanm 74:a842253909c9 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 74:a842253909c9 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 74:a842253909c9 507
bogdanm 74:a842253909c9 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 74:a842253909c9 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 74:a842253909c9 510
bogdanm 74:a842253909c9 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 74:a842253909c9 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 74:a842253909c9 513
bogdanm 74:a842253909c9 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 74:a842253909c9 516
bogdanm 74:a842253909c9 517 /* SysTick Reload Register Definitions */
bogdanm 74:a842253909c9 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 74:a842253909c9 520
bogdanm 74:a842253909c9 521 /* SysTick Current Register Definitions */
bogdanm 74:a842253909c9 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 74:a842253909c9 524
bogdanm 74:a842253909c9 525 /* SysTick Calibration Register Definitions */
bogdanm 74:a842253909c9 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 74:a842253909c9 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 74:a842253909c9 528
bogdanm 74:a842253909c9 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 74:a842253909c9 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 74:a842253909c9 531
bogdanm 74:a842253909c9 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 74:a842253909c9 534
bogdanm 74:a842253909c9 535 /*@} end of group CMSIS_SysTick */
bogdanm 74:a842253909c9 536
bogdanm 74:a842253909c9 537 #if (__MPU_PRESENT == 1)
bogdanm 74:a842253909c9 538 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 74:a842253909c9 540 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 74:a842253909c9 541 @{
bogdanm 74:a842253909c9 542 */
bogdanm 74:a842253909c9 543
bogdanm 74:a842253909c9 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 74:a842253909c9 545 */
bogdanm 74:a842253909c9 546 typedef struct
bogdanm 74:a842253909c9 547 {
bogdanm 74:a842253909c9 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 74:a842253909c9 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 74:a842253909c9 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 74:a842253909c9 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 74:a842253909c9 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 74:a842253909c9 553 } MPU_Type;
bogdanm 74:a842253909c9 554
bogdanm 74:a842253909c9 555 /* MPU Type Register */
bogdanm 74:a842253909c9 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 74:a842253909c9 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 74:a842253909c9 558
bogdanm 74:a842253909c9 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 74:a842253909c9 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 74:a842253909c9 561
bogdanm 74:a842253909c9 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 74:a842253909c9 564
bogdanm 74:a842253909c9 565 /* MPU Control Register */
bogdanm 74:a842253909c9 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 74:a842253909c9 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 74:a842253909c9 568
bogdanm 74:a842253909c9 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 74:a842253909c9 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 74:a842253909c9 571
bogdanm 74:a842253909c9 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
bogdanm 74:a842253909c9 574
bogdanm 74:a842253909c9 575 /* MPU Region Number Register */
bogdanm 74:a842253909c9 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
bogdanm 74:a842253909c9 578
bogdanm 74:a842253909c9 579 /* MPU Region Base Address Register */
bogdanm 74:a842253909c9 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 74:a842253909c9 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 74:a842253909c9 582
bogdanm 74:a842253909c9 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 74:a842253909c9 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 74:a842253909c9 585
bogdanm 74:a842253909c9 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
bogdanm 74:a842253909c9 588
bogdanm 74:a842253909c9 589 /* MPU Region Attribute and Size Register */
bogdanm 74:a842253909c9 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 74:a842253909c9 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 74:a842253909c9 592
bogdanm 74:a842253909c9 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 74:a842253909c9 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 74:a842253909c9 595
bogdanm 74:a842253909c9 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 74:a842253909c9 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 74:a842253909c9 598
bogdanm 74:a842253909c9 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 74:a842253909c9 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 74:a842253909c9 601
bogdanm 74:a842253909c9 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 74:a842253909c9 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 74:a842253909c9 604
bogdanm 74:a842253909c9 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 74:a842253909c9 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 74:a842253909c9 607
bogdanm 74:a842253909c9 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 74:a842253909c9 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 74:a842253909c9 610
bogdanm 74:a842253909c9 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 74:a842253909c9 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 74:a842253909c9 613
bogdanm 74:a842253909c9 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 74:a842253909c9 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 74:a842253909c9 616
bogdanm 74:a842253909c9 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 74:a842253909c9 619
bogdanm 74:a842253909c9 620 /*@} end of group CMSIS_MPU */
bogdanm 74:a842253909c9 621 #endif
bogdanm 74:a842253909c9 622
bogdanm 74:a842253909c9 623
bogdanm 74:a842253909c9 624 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 74:a842253909c9 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 74:a842253909c9 627 are only accessible over DAP and not via processor. Therefore
bogdanm 74:a842253909c9 628 they are not covered by the Cortex-M0 header file.
bogdanm 74:a842253909c9 629 @{
bogdanm 74:a842253909c9 630 */
bogdanm 74:a842253909c9 631 /*@} end of group CMSIS_CoreDebug */
bogdanm 74:a842253909c9 632
bogdanm 74:a842253909c9 633
bogdanm 74:a842253909c9 634 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 635 \defgroup CMSIS_core_base Core Definitions
bogdanm 74:a842253909c9 636 \brief Definitions for base addresses, unions, and structures.
bogdanm 74:a842253909c9 637 @{
bogdanm 74:a842253909c9 638 */
bogdanm 74:a842253909c9 639
bogdanm 74:a842253909c9 640 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 74:a842253909c9 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 74:a842253909c9 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 74:a842253909c9 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 74:a842253909c9 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 74:a842253909c9 645
bogdanm 74:a842253909c9 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 74:a842253909c9 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 74:a842253909c9 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 74:a842253909c9 649
bogdanm 74:a842253909c9 650 #if (__MPU_PRESENT == 1)
bogdanm 74:a842253909c9 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 74:a842253909c9 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 74:a842253909c9 653 #endif
bogdanm 74:a842253909c9 654
bogdanm 74:a842253909c9 655 /*@} */
bogdanm 74:a842253909c9 656
bogdanm 74:a842253909c9 657
bogdanm 74:a842253909c9 658
bogdanm 74:a842253909c9 659 /*******************************************************************************
bogdanm 74:a842253909c9 660 * Hardware Abstraction Layer
bogdanm 74:a842253909c9 661 Core Function Interface contains:
bogdanm 74:a842253909c9 662 - Core NVIC Functions
bogdanm 74:a842253909c9 663 - Core SysTick Functions
bogdanm 74:a842253909c9 664 - Core Register Access Functions
bogdanm 74:a842253909c9 665 ******************************************************************************/
bogdanm 74:a842253909c9 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 74:a842253909c9 667 */
bogdanm 74:a842253909c9 668
bogdanm 74:a842253909c9 669
bogdanm 74:a842253909c9 670
bogdanm 74:a842253909c9 671 /* ########################## NVIC functions #################################### */
bogdanm 74:a842253909c9 672 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 74:a842253909c9 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 74:a842253909c9 674 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 74:a842253909c9 675 @{
bogdanm 74:a842253909c9 676 */
bogdanm 74:a842253909c9 677
bogdanm 74:a842253909c9 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 74:a842253909c9 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 74:a842253909c9 683
bogdanm 74:a842253909c9 684
bogdanm 74:a842253909c9 685 /** \brief Enable External Interrupt
bogdanm 74:a842253909c9 686
bogdanm 74:a842253909c9 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 74:a842253909c9 688
bogdanm 74:a842253909c9 689 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 74:a842253909c9 690 */
bogdanm 74:a842253909c9 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 74:a842253909c9 694 }
bogdanm 74:a842253909c9 695
bogdanm 74:a842253909c9 696
bogdanm 74:a842253909c9 697 /** \brief Disable External Interrupt
bogdanm 74:a842253909c9 698
bogdanm 74:a842253909c9 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 74:a842253909c9 700
bogdanm 74:a842253909c9 701 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 74:a842253909c9 702 */
bogdanm 74:a842253909c9 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
bogdanm 74:a842253909c9 708 }
bogdanm 74:a842253909c9 709
bogdanm 74:a842253909c9 710
bogdanm 74:a842253909c9 711 /** \brief Get Pending Interrupt
bogdanm 74:a842253909c9 712
bogdanm 74:a842253909c9 713 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 74:a842253909c9 714 for the specified interrupt.
bogdanm 74:a842253909c9 715
bogdanm 74:a842253909c9 716 \param [in] IRQn Interrupt number.
bogdanm 74:a842253909c9 717
bogdanm 74:a842253909c9 718 \return 0 Interrupt status is not pending.
bogdanm 74:a842253909c9 719 \return 1 Interrupt status is pending.
bogdanm 74:a842253909c9 720 */
bogdanm 74:a842253909c9 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 74:a842253909c9 724 }
bogdanm 74:a842253909c9 725
bogdanm 74:a842253909c9 726
bogdanm 74:a842253909c9 727 /** \brief Set Pending Interrupt
bogdanm 74:a842253909c9 728
bogdanm 74:a842253909c9 729 The function sets the pending bit of an external interrupt.
bogdanm 74:a842253909c9 730
bogdanm 74:a842253909c9 731 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 74:a842253909c9 732 */
bogdanm 74:a842253909c9 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 74:a842253909c9 736 }
bogdanm 74:a842253909c9 737
bogdanm 74:a842253909c9 738
bogdanm 74:a842253909c9 739 /** \brief Clear Pending Interrupt
bogdanm 74:a842253909c9 740
bogdanm 74:a842253909c9 741 The function clears the pending bit of an external interrupt.
bogdanm 74:a842253909c9 742
bogdanm 74:a842253909c9 743 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 74:a842253909c9 744 */
bogdanm 74:a842253909c9 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 74:a842253909c9 748 }
bogdanm 74:a842253909c9 749
bogdanm 74:a842253909c9 750
bogdanm 74:a842253909c9 751 /** \brief Set Interrupt Priority
bogdanm 74:a842253909c9 752
bogdanm 74:a842253909c9 753 The function sets the priority of an interrupt.
bogdanm 74:a842253909c9 754
bogdanm 74:a842253909c9 755 \note The priority cannot be set for every core interrupt.
bogdanm 74:a842253909c9 756
bogdanm 74:a842253909c9 757 \param [in] IRQn Interrupt number.
bogdanm 74:a842253909c9 758 \param [in] priority Priority to set.
bogdanm 74:a842253909c9 759 */
bogdanm 74:a842253909c9 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 74:a842253909c9 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
bogdanm 74:a842253909c9 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
bogdanm 74:a842253909c9 770 }
bogdanm 74:a842253909c9 771
bogdanm 74:a842253909c9 772
bogdanm 74:a842253909c9 773 /** \brief Get Interrupt Priority
bogdanm 74:a842253909c9 774
bogdanm 74:a842253909c9 775 The function reads the priority of an interrupt. The interrupt
bogdanm 74:a842253909c9 776 number can be positive to specify an external (device specific)
bogdanm 74:a842253909c9 777 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 74:a842253909c9 778
bogdanm 74:a842253909c9 779
bogdanm 74:a842253909c9 780 \param [in] IRQn Interrupt number.
bogdanm 74:a842253909c9 781 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 74:a842253909c9 782 priority bits of the microcontroller.
bogdanm 74:a842253909c9 783 */
bogdanm 74:a842253909c9 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 74:a842253909c9 785 {
bogdanm 74:a842253909c9 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
bogdanm 74:a842253909c9 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
bogdanm 74:a842253909c9 793 }
bogdanm 74:a842253909c9 794
bogdanm 74:a842253909c9 795
bogdanm 74:a842253909c9 796 /** \brief System Reset
bogdanm 74:a842253909c9 797
bogdanm 74:a842253909c9 798 The function initiates a system reset request to reset the MCU.
bogdanm 74:a842253909c9 799 */
bogdanm 74:a842253909c9 800 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 74:a842253909c9 801 {
bogdanm 74:a842253909c9 802 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 74:a842253909c9 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 74:a842253909c9 805 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 74:a842253909c9 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
bogdanm 74:a842253909c9 808 }
bogdanm 74:a842253909c9 809
bogdanm 74:a842253909c9 810 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 74:a842253909c9 811
bogdanm 74:a842253909c9 812
bogdanm 74:a842253909c9 813
bogdanm 74:a842253909c9 814 /* ################################## SysTick function ############################################ */
bogdanm 74:a842253909c9 815 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 74:a842253909c9 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 74:a842253909c9 817 \brief Functions that configure the System.
bogdanm 74:a842253909c9 818 @{
bogdanm 74:a842253909c9 819 */
bogdanm 74:a842253909c9 820
bogdanm 74:a842253909c9 821 #if (__Vendor_SysTickConfig == 0)
bogdanm 74:a842253909c9 822
bogdanm 74:a842253909c9 823 /** \brief System Tick Configuration
bogdanm 74:a842253909c9 824
bogdanm 74:a842253909c9 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 74:a842253909c9 826 Counter is in free running mode to generate periodic interrupts.
bogdanm 74:a842253909c9 827
bogdanm 74:a842253909c9 828 \param [in] ticks Number of ticks between two interrupts.
bogdanm 74:a842253909c9 829
bogdanm 74:a842253909c9 830 \return 0 Function succeeded.
bogdanm 74:a842253909c9 831 \return 1 Function failed.
bogdanm 74:a842253909c9 832
bogdanm 74:a842253909c9 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 74:a842253909c9 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 74:a842253909c9 835 must contain a vendor-specific implementation of this function.
bogdanm 74:a842253909c9 836
bogdanm 74:a842253909c9 837 */
bogdanm 74:a842253909c9 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 74:a842253909c9 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
bogdanm 74:a842253909c9 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 74:a842253909c9 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 74:a842253909c9 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
bogdanm 74:a842253909c9 849 }
bogdanm 74:a842253909c9 850
bogdanm 74:a842253909c9 851 #endif
bogdanm 74:a842253909c9 852
bogdanm 74:a842253909c9 853 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 74:a842253909c9 854
bogdanm 74:a842253909c9 855
bogdanm 74:a842253909c9 856
bogdanm 74:a842253909c9 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
bogdanm 74:a842253909c9 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 74:a842253909c9 863
bogdanm 74:a842253909c9 864 #endif /* __CMSIS_GENERIC */