mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_LPC11U35_401/core_cm0plus.h@74:a842253909c9, 2013-12-13 (annotated)

Committer:
bogdanm
Date:
Fri Dec 13 14:18:40 2013 +0200
Revision:
74:a842253909c9
Child:
110:165afa46840b
Release 74 of the mbed library



Main changes:



- added Embedded Artists LPC11U35 quick start board to the SDK

- fixes for LPC4088/NUCLEO_F103RB

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 74:a842253909c9 1 /**************************************************************************//**
bogdanm 74:a842253909c9 2 * @file core_cm0plus.h
bogdanm 74:a842253909c9 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
bogdanm 74:a842253909c9 4 * @version V3.20
bogdanm 74:a842253909c9 5 * @date 25. February 2013
bogdanm 74:a842253909c9 6 *
bogdanm 74:a842253909c9 7 * @note
bogdanm 74:a842253909c9 8 *
bogdanm 74:a842253909c9 9 ******************************************************************************/
bogdanm 74:a842253909c9 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 74:a842253909c9 11
bogdanm 74:a842253909c9 12 All rights reserved.
bogdanm 74:a842253909c9 13 Redistribution and use in source and binary forms, with or without
bogdanm 74:a842253909c9 14 modification, are permitted provided that the following conditions are met:
bogdanm 74:a842253909c9 15 - Redistributions of source code must retain the above copyright
bogdanm 74:a842253909c9 16 notice, this list of conditions and the following disclaimer.
bogdanm 74:a842253909c9 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 74:a842253909c9 18 notice, this list of conditions and the following disclaimer in the
bogdanm 74:a842253909c9 19 documentation and/or other materials provided with the distribution.
bogdanm 74:a842253909c9 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 74:a842253909c9 21 to endorse or promote products derived from this software without
bogdanm 74:a842253909c9 22 specific prior written permission.
bogdanm 74:a842253909c9 23 *
bogdanm 74:a842253909c9 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 74:a842253909c9 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 74:a842253909c9 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 74:a842253909c9 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 74:a842253909c9 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 74:a842253909c9 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 74:a842253909c9 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 74:a842253909c9 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 74:a842253909c9 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 74:a842253909c9 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 74:a842253909c9 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 74:a842253909c9 35 ---------------------------------------------------------------------------*/
bogdanm 74:a842253909c9 36
bogdanm 74:a842253909c9 37
bogdanm 74:a842253909c9 38 #if defined ( __ICCARM__ )
bogdanm 74:a842253909c9 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 74:a842253909c9 40 #endif
bogdanm 74:a842253909c9 41
bogdanm 74:a842253909c9 42 #ifdef __cplusplus
bogdanm 74:a842253909c9 43 extern "C" {
bogdanm 74:a842253909c9 44 #endif
bogdanm 74:a842253909c9 45
bogdanm 74:a842253909c9 46 #ifndef __CORE_CM0PLUS_H_GENERIC
bogdanm 74:a842253909c9 47 #define __CORE_CM0PLUS_H_GENERIC
bogdanm 74:a842253909c9 48
bogdanm 74:a842253909c9 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 74:a842253909c9 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 74:a842253909c9 51
bogdanm 74:a842253909c9 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 74:a842253909c9 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 74:a842253909c9 54
bogdanm 74:a842253909c9 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 74:a842253909c9 56 Unions are used for effective representation of core registers.
bogdanm 74:a842253909c9 57
bogdanm 74:a842253909c9 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 74:a842253909c9 59 Function-like macros are used to allow more efficient code.
bogdanm 74:a842253909c9 60 */
bogdanm 74:a842253909c9 61
bogdanm 74:a842253909c9 62
bogdanm 74:a842253909c9 63 /*******************************************************************************
bogdanm 74:a842253909c9 64 * CMSIS definitions
bogdanm 74:a842253909c9 65 ******************************************************************************/
bogdanm 74:a842253909c9 66 /** \ingroup Cortex-M0+
bogdanm 74:a842253909c9 67 @{
bogdanm 74:a842253909c9 68 */
bogdanm 74:a842253909c9 69
bogdanm 74:a842253909c9 70 /* CMSIS CM0P definitions */
bogdanm 74:a842253909c9 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 74:a842253909c9 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 74:a842253909c9 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 74:a842253909c9 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 74:a842253909c9 75
bogdanm 74:a842253909c9 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 74:a842253909c9 77
bogdanm 74:a842253909c9 78
bogdanm 74:a842253909c9 79 #if defined ( __CC_ARM )
bogdanm 74:a842253909c9 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 74:a842253909c9 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 74:a842253909c9 82 #define __STATIC_INLINE static __inline
bogdanm 74:a842253909c9 83
bogdanm 74:a842253909c9 84 #elif defined ( __ICCARM__ )
bogdanm 74:a842253909c9 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 74:a842253909c9 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 74:a842253909c9 87 #define __STATIC_INLINE static inline
bogdanm 74:a842253909c9 88
bogdanm 74:a842253909c9 89 #elif defined ( __GNUC__ )
bogdanm 74:a842253909c9 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 74:a842253909c9 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 74:a842253909c9 92 #define __STATIC_INLINE static inline
bogdanm 74:a842253909c9 93
bogdanm 74:a842253909c9 94 #elif defined ( __TASKING__ )
bogdanm 74:a842253909c9 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 74:a842253909c9 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 74:a842253909c9 97 #define __STATIC_INLINE static inline
bogdanm 74:a842253909c9 98
bogdanm 74:a842253909c9 99 #endif
bogdanm 74:a842253909c9 100
bogdanm 74:a842253909c9 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
bogdanm 74:a842253909c9 102 */
bogdanm 74:a842253909c9 103 #define __FPU_USED 0
bogdanm 74:a842253909c9 104
bogdanm 74:a842253909c9 105 #if defined ( __CC_ARM )
bogdanm 74:a842253909c9 106 #if defined __TARGET_FPU_VFP
bogdanm 74:a842253909c9 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 108 #endif
bogdanm 74:a842253909c9 109
bogdanm 74:a842253909c9 110 #elif defined ( __ICCARM__ )
bogdanm 74:a842253909c9 111 #if defined __ARMVFP__
bogdanm 74:a842253909c9 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 113 #endif
bogdanm 74:a842253909c9 114
bogdanm 74:a842253909c9 115 #elif defined ( __GNUC__ )
bogdanm 74:a842253909c9 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 74:a842253909c9 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 118 #endif
bogdanm 74:a842253909c9 119
bogdanm 74:a842253909c9 120 #elif defined ( __TASKING__ )
bogdanm 74:a842253909c9 121 #if defined __FPU_VFP__
bogdanm 74:a842253909c9 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 74:a842253909c9 123 #endif
bogdanm 74:a842253909c9 124 #endif
bogdanm 74:a842253909c9 125
bogdanm 74:a842253909c9 126 #include <stdint.h> /* standard types definitions */
bogdanm 74:a842253909c9 127 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 74:a842253909c9 128 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 74:a842253909c9 129
bogdanm 74:a842253909c9 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 74:a842253909c9 131
bogdanm 74:a842253909c9 132 #ifndef __CMSIS_GENERIC
bogdanm 74:a842253909c9 133
bogdanm 74:a842253909c9 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 74:a842253909c9 135 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 74:a842253909c9 136
bogdanm 74:a842253909c9 137 /* check device defines and use defaults */
bogdanm 74:a842253909c9 138 #if defined __CHECK_DEVICE_DEFINES
bogdanm 74:a842253909c9 139 #ifndef __CM0PLUS_REV
bogdanm 74:a842253909c9 140 #define __CM0PLUS_REV 0x0000
bogdanm 74:a842253909c9 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 74:a842253909c9 142 #endif
bogdanm 74:a842253909c9 143
bogdanm 74:a842253909c9 144 #ifndef __MPU_PRESENT
bogdanm 74:a842253909c9 145 #define __MPU_PRESENT 0
bogdanm 74:a842253909c9 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 74:a842253909c9 147 #endif
bogdanm 74:a842253909c9 148
bogdanm 74:a842253909c9 149 #ifndef __VTOR_PRESENT
bogdanm 74:a842253909c9 150 #define __VTOR_PRESENT 0
bogdanm 74:a842253909c9 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 74:a842253909c9 152 #endif
bogdanm 74:a842253909c9 153
bogdanm 74:a842253909c9 154 #ifndef __NVIC_PRIO_BITS
bogdanm 74:a842253909c9 155 #define __NVIC_PRIO_BITS 2
bogdanm 74:a842253909c9 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 74:a842253909c9 157 #endif
bogdanm 74:a842253909c9 158
bogdanm 74:a842253909c9 159 #ifndef __Vendor_SysTickConfig
bogdanm 74:a842253909c9 160 #define __Vendor_SysTickConfig 0
bogdanm 74:a842253909c9 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 74:a842253909c9 162 #endif
bogdanm 74:a842253909c9 163 #endif
bogdanm 74:a842253909c9 164
bogdanm 74:a842253909c9 165 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 74:a842253909c9 166 /**
bogdanm 74:a842253909c9 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 74:a842253909c9 168
bogdanm 74:a842253909c9 169 <strong>IO Type Qualifiers</strong> are used
bogdanm 74:a842253909c9 170 \li to specify the access to peripheral variables.
bogdanm 74:a842253909c9 171 \li for automatic generation of peripheral register debug information.
bogdanm 74:a842253909c9 172 */
bogdanm 74:a842253909c9 173 #ifdef __cplusplus
bogdanm 74:a842253909c9 174 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 74:a842253909c9 175 #else
bogdanm 74:a842253909c9 176 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 74:a842253909c9 177 #endif
bogdanm 74:a842253909c9 178 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 74:a842253909c9 179 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 74:a842253909c9 180
bogdanm 74:a842253909c9 181 /*@} end of group Cortex-M0+ */
bogdanm 74:a842253909c9 182
bogdanm 74:a842253909c9 183
bogdanm 74:a842253909c9 184
bogdanm 74:a842253909c9 185 /*******************************************************************************
bogdanm 74:a842253909c9 186 * Register Abstraction
bogdanm 74:a842253909c9 187 Core Register contain:
bogdanm 74:a842253909c9 188 - Core Register
bogdanm 74:a842253909c9 189 - Core NVIC Register
bogdanm 74:a842253909c9 190 - Core SCB Register
bogdanm 74:a842253909c9 191 - Core SysTick Register
bogdanm 74:a842253909c9 192 - Core MPU Register
bogdanm 74:a842253909c9 193 ******************************************************************************/
bogdanm 74:a842253909c9 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 74:a842253909c9 195 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 74:a842253909c9 196 */
bogdanm 74:a842253909c9 197
bogdanm 74:a842253909c9 198 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 199 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 74:a842253909c9 200 \brief Core Register type definitions.
bogdanm 74:a842253909c9 201 @{
bogdanm 74:a842253909c9 202 */
bogdanm 74:a842253909c9 203
bogdanm 74:a842253909c9 204 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 74:a842253909c9 205 */
bogdanm 74:a842253909c9 206 typedef union
bogdanm 74:a842253909c9 207 {
bogdanm 74:a842253909c9 208 struct
bogdanm 74:a842253909c9 209 {
bogdanm 74:a842253909c9 210 #if (__CORTEX_M != 0x04)
bogdanm 74:a842253909c9 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 74:a842253909c9 212 #else
bogdanm 74:a842253909c9 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 74:a842253909c9 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 74:a842253909c9 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 74:a842253909c9 216 #endif
bogdanm 74:a842253909c9 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 74:a842253909c9 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 74:a842253909c9 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 74:a842253909c9 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 74:a842253909c9 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 74:a842253909c9 222 } b; /*!< Structure used for bit access */
bogdanm 74:a842253909c9 223 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 224 } APSR_Type;
bogdanm 74:a842253909c9 225
bogdanm 74:a842253909c9 226
bogdanm 74:a842253909c9 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 74:a842253909c9 228 */
bogdanm 74:a842253909c9 229 typedef union
bogdanm 74:a842253909c9 230 {
bogdanm 74:a842253909c9 231 struct
bogdanm 74:a842253909c9 232 {
bogdanm 74:a842253909c9 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 74:a842253909c9 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 74:a842253909c9 235 } b; /*!< Structure used for bit access */
bogdanm 74:a842253909c9 236 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 237 } IPSR_Type;
bogdanm 74:a842253909c9 238
bogdanm 74:a842253909c9 239
bogdanm 74:a842253909c9 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 74:a842253909c9 241 */
bogdanm 74:a842253909c9 242 typedef union
bogdanm 74:a842253909c9 243 {
bogdanm 74:a842253909c9 244 struct
bogdanm 74:a842253909c9 245 {
bogdanm 74:a842253909c9 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 74:a842253909c9 247 #if (__CORTEX_M != 0x04)
bogdanm 74:a842253909c9 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 74:a842253909c9 249 #else
bogdanm 74:a842253909c9 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 74:a842253909c9 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 74:a842253909c9 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 74:a842253909c9 253 #endif
bogdanm 74:a842253909c9 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 74:a842253909c9 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 74:a842253909c9 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 74:a842253909c9 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 74:a842253909c9 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 74:a842253909c9 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 74:a842253909c9 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 74:a842253909c9 261 } b; /*!< Structure used for bit access */
bogdanm 74:a842253909c9 262 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 263 } xPSR_Type;
bogdanm 74:a842253909c9 264
bogdanm 74:a842253909c9 265
bogdanm 74:a842253909c9 266 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 74:a842253909c9 267 */
bogdanm 74:a842253909c9 268 typedef union
bogdanm 74:a842253909c9 269 {
bogdanm 74:a842253909c9 270 struct
bogdanm 74:a842253909c9 271 {
bogdanm 74:a842253909c9 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 74:a842253909c9 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 74:a842253909c9 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 74:a842253909c9 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 74:a842253909c9 276 } b; /*!< Structure used for bit access */
bogdanm 74:a842253909c9 277 uint32_t w; /*!< Type used for word access */
bogdanm 74:a842253909c9 278 } CONTROL_Type;
bogdanm 74:a842253909c9 279
bogdanm 74:a842253909c9 280 /*@} end of group CMSIS_CORE */
bogdanm 74:a842253909c9 281
bogdanm 74:a842253909c9 282
bogdanm 74:a842253909c9 283 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 74:a842253909c9 285 \brief Type definitions for the NVIC Registers
bogdanm 74:a842253909c9 286 @{
bogdanm 74:a842253909c9 287 */
bogdanm 74:a842253909c9 288
bogdanm 74:a842253909c9 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 74:a842253909c9 290 */
bogdanm 74:a842253909c9 291 typedef struct
bogdanm 74:a842253909c9 292 {
bogdanm 74:a842253909c9 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 74:a842253909c9 294 uint32_t RESERVED0[31];
bogdanm 74:a842253909c9 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 74:a842253909c9 296 uint32_t RSERVED1[31];
bogdanm 74:a842253909c9 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 74:a842253909c9 298 uint32_t RESERVED2[31];
bogdanm 74:a842253909c9 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 74:a842253909c9 300 uint32_t RESERVED3[31];
bogdanm 74:a842253909c9 301 uint32_t RESERVED4[64];
bogdanm 74:a842253909c9 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 74:a842253909c9 303 } NVIC_Type;
bogdanm 74:a842253909c9 304
bogdanm 74:a842253909c9 305 /*@} end of group CMSIS_NVIC */
bogdanm 74:a842253909c9 306
bogdanm 74:a842253909c9 307
bogdanm 74:a842253909c9 308 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 309 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 74:a842253909c9 310 \brief Type definitions for the System Control Block Registers
bogdanm 74:a842253909c9 311 @{
bogdanm 74:a842253909c9 312 */
bogdanm 74:a842253909c9 313
bogdanm 74:a842253909c9 314 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 74:a842253909c9 315 */
bogdanm 74:a842253909c9 316 typedef struct
bogdanm 74:a842253909c9 317 {
bogdanm 74:a842253909c9 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 74:a842253909c9 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 74:a842253909c9 320 #if (__VTOR_PRESENT == 1)
bogdanm 74:a842253909c9 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 74:a842253909c9 322 #else
bogdanm 74:a842253909c9 323 uint32_t RESERVED0;
bogdanm 74:a842253909c9 324 #endif
bogdanm 74:a842253909c9 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 74:a842253909c9 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 74:a842253909c9 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 74:a842253909c9 328 uint32_t RESERVED1;
bogdanm 74:a842253909c9 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 74:a842253909c9 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 74:a842253909c9 331 } SCB_Type;
bogdanm 74:a842253909c9 332
bogdanm 74:a842253909c9 333 /* SCB CPUID Register Definitions */
bogdanm 74:a842253909c9 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 74:a842253909c9 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 74:a842253909c9 336
bogdanm 74:a842253909c9 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 74:a842253909c9 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 74:a842253909c9 339
bogdanm 74:a842253909c9 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 74:a842253909c9 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 74:a842253909c9 342
bogdanm 74:a842253909c9 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 74:a842253909c9 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 74:a842253909c9 345
bogdanm 74:a842253909c9 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 74:a842253909c9 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 74:a842253909c9 348
bogdanm 74:a842253909c9 349 /* SCB Interrupt Control State Register Definitions */
bogdanm 74:a842253909c9 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 74:a842253909c9 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 74:a842253909c9 352
bogdanm 74:a842253909c9 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 74:a842253909c9 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 74:a842253909c9 355
bogdanm 74:a842253909c9 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 74:a842253909c9 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 74:a842253909c9 358
bogdanm 74:a842253909c9 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 74:a842253909c9 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 74:a842253909c9 361
bogdanm 74:a842253909c9 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 74:a842253909c9 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 74:a842253909c9 364
bogdanm 74:a842253909c9 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 74:a842253909c9 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 74:a842253909c9 367
bogdanm 74:a842253909c9 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 74:a842253909c9 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 74:a842253909c9 370
bogdanm 74:a842253909c9 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 74:a842253909c9 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 74:a842253909c9 373
bogdanm 74:a842253909c9 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 74:a842253909c9 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 74:a842253909c9 376
bogdanm 74:a842253909c9 377 #if (__VTOR_PRESENT == 1)
bogdanm 74:a842253909c9 378 /* SCB Interrupt Control State Register Definitions */
bogdanm 74:a842253909c9 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 74:a842253909c9 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 74:a842253909c9 381 #endif
bogdanm 74:a842253909c9 382
bogdanm 74:a842253909c9 383 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 74:a842253909c9 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 74:a842253909c9 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 74:a842253909c9 386
bogdanm 74:a842253909c9 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 74:a842253909c9 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 74:a842253909c9 389
bogdanm 74:a842253909c9 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 74:a842253909c9 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 74:a842253909c9 392
bogdanm 74:a842253909c9 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 74:a842253909c9 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 74:a842253909c9 395
bogdanm 74:a842253909c9 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 74:a842253909c9 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 74:a842253909c9 398
bogdanm 74:a842253909c9 399 /* SCB System Control Register Definitions */
bogdanm 74:a842253909c9 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 74:a842253909c9 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 74:a842253909c9 402
bogdanm 74:a842253909c9 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 74:a842253909c9 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 74:a842253909c9 405
bogdanm 74:a842253909c9 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 74:a842253909c9 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 74:a842253909c9 408
bogdanm 74:a842253909c9 409 /* SCB Configuration Control Register Definitions */
bogdanm 74:a842253909c9 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 74:a842253909c9 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 74:a842253909c9 412
bogdanm 74:a842253909c9 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 74:a842253909c9 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 74:a842253909c9 415
bogdanm 74:a842253909c9 416 /* SCB System Handler Control and State Register Definitions */
bogdanm 74:a842253909c9 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 74:a842253909c9 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 74:a842253909c9 419
bogdanm 74:a842253909c9 420 /*@} end of group CMSIS_SCB */
bogdanm 74:a842253909c9 421
bogdanm 74:a842253909c9 422
bogdanm 74:a842253909c9 423 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 74:a842253909c9 425 \brief Type definitions for the System Timer Registers.
bogdanm 74:a842253909c9 426 @{
bogdanm 74:a842253909c9 427 */
bogdanm 74:a842253909c9 428
bogdanm 74:a842253909c9 429 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 74:a842253909c9 430 */
bogdanm 74:a842253909c9 431 typedef struct
bogdanm 74:a842253909c9 432 {
bogdanm 74:a842253909c9 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 74:a842253909c9 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 74:a842253909c9 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 74:a842253909c9 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 74:a842253909c9 437 } SysTick_Type;
bogdanm 74:a842253909c9 438
bogdanm 74:a842253909c9 439 /* SysTick Control / Status Register Definitions */
bogdanm 74:a842253909c9 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 74:a842253909c9 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 74:a842253909c9 442
bogdanm 74:a842253909c9 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 74:a842253909c9 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 74:a842253909c9 445
bogdanm 74:a842253909c9 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 74:a842253909c9 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 74:a842253909c9 448
bogdanm 74:a842253909c9 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 74:a842253909c9 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 74:a842253909c9 451
bogdanm 74:a842253909c9 452 /* SysTick Reload Register Definitions */
bogdanm 74:a842253909c9 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 74:a842253909c9 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 74:a842253909c9 455
bogdanm 74:a842253909c9 456 /* SysTick Current Register Definitions */
bogdanm 74:a842253909c9 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 74:a842253909c9 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 74:a842253909c9 459
bogdanm 74:a842253909c9 460 /* SysTick Calibration Register Definitions */
bogdanm 74:a842253909c9 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 74:a842253909c9 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 74:a842253909c9 463
bogdanm 74:a842253909c9 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 74:a842253909c9 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 74:a842253909c9 466
bogdanm 74:a842253909c9 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 74:a842253909c9 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 74:a842253909c9 469
bogdanm 74:a842253909c9 470 /*@} end of group CMSIS_SysTick */
bogdanm 74:a842253909c9 471
bogdanm 74:a842253909c9 472 #if (__MPU_PRESENT == 1)
bogdanm 74:a842253909c9 473 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 74:a842253909c9 475 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 74:a842253909c9 476 @{
bogdanm 74:a842253909c9 477 */
bogdanm 74:a842253909c9 478
bogdanm 74:a842253909c9 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 74:a842253909c9 480 */
bogdanm 74:a842253909c9 481 typedef struct
bogdanm 74:a842253909c9 482 {
bogdanm 74:a842253909c9 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 74:a842253909c9 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 74:a842253909c9 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 74:a842253909c9 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 74:a842253909c9 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 74:a842253909c9 488 } MPU_Type;
bogdanm 74:a842253909c9 489
bogdanm 74:a842253909c9 490 /* MPU Type Register */
bogdanm 74:a842253909c9 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 74:a842253909c9 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 74:a842253909c9 493
bogdanm 74:a842253909c9 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 74:a842253909c9 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 74:a842253909c9 496
bogdanm 74:a842253909c9 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 74:a842253909c9 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 74:a842253909c9 499
bogdanm 74:a842253909c9 500 /* MPU Control Register */
bogdanm 74:a842253909c9 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 74:a842253909c9 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 74:a842253909c9 503
bogdanm 74:a842253909c9 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 74:a842253909c9 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 74:a842253909c9 506
bogdanm 74:a842253909c9 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 74:a842253909c9 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 74:a842253909c9 509
bogdanm 74:a842253909c9 510 /* MPU Region Number Register */
bogdanm 74:a842253909c9 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 74:a842253909c9 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 74:a842253909c9 513
bogdanm 74:a842253909c9 514 /* MPU Region Base Address Register */
bogdanm 74:a842253909c9 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 74:a842253909c9 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 74:a842253909c9 517
bogdanm 74:a842253909c9 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 74:a842253909c9 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 74:a842253909c9 520
bogdanm 74:a842253909c9 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 74:a842253909c9 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 74:a842253909c9 523
bogdanm 74:a842253909c9 524 /* MPU Region Attribute and Size Register */
bogdanm 74:a842253909c9 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 74:a842253909c9 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 74:a842253909c9 527
bogdanm 74:a842253909c9 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 74:a842253909c9 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 74:a842253909c9 530
bogdanm 74:a842253909c9 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 74:a842253909c9 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 74:a842253909c9 533
bogdanm 74:a842253909c9 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 74:a842253909c9 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 74:a842253909c9 536
bogdanm 74:a842253909c9 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 74:a842253909c9 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 74:a842253909c9 539
bogdanm 74:a842253909c9 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 74:a842253909c9 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 74:a842253909c9 542
bogdanm 74:a842253909c9 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 74:a842253909c9 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 74:a842253909c9 545
bogdanm 74:a842253909c9 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 74:a842253909c9 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 74:a842253909c9 548
bogdanm 74:a842253909c9 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 74:a842253909c9 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 74:a842253909c9 551
bogdanm 74:a842253909c9 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 74:a842253909c9 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 74:a842253909c9 554
bogdanm 74:a842253909c9 555 /*@} end of group CMSIS_MPU */
bogdanm 74:a842253909c9 556 #endif
bogdanm 74:a842253909c9 557
bogdanm 74:a842253909c9 558
bogdanm 74:a842253909c9 559 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 74:a842253909c9 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 74:a842253909c9 562 are only accessible over DAP and not via processor. Therefore
bogdanm 74:a842253909c9 563 they are not covered by the Cortex-M0 header file.
bogdanm 74:a842253909c9 564 @{
bogdanm 74:a842253909c9 565 */
bogdanm 74:a842253909c9 566 /*@} end of group CMSIS_CoreDebug */
bogdanm 74:a842253909c9 567
bogdanm 74:a842253909c9 568
bogdanm 74:a842253909c9 569 /** \ingroup CMSIS_core_register
bogdanm 74:a842253909c9 570 \defgroup CMSIS_core_base Core Definitions
bogdanm 74:a842253909c9 571 \brief Definitions for base addresses, unions, and structures.
bogdanm 74:a842253909c9 572 @{
bogdanm 74:a842253909c9 573 */
bogdanm 74:a842253909c9 574
bogdanm 74:a842253909c9 575 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 74:a842253909c9 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 74:a842253909c9 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 74:a842253909c9 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 74:a842253909c9 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 74:a842253909c9 580
bogdanm 74:a842253909c9 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 74:a842253909c9 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 74:a842253909c9 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 74:a842253909c9 584
bogdanm 74:a842253909c9 585 #if (__MPU_PRESENT == 1)
bogdanm 74:a842253909c9 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 74:a842253909c9 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 74:a842253909c9 588 #endif
bogdanm 74:a842253909c9 589
bogdanm 74:a842253909c9 590 /*@} */
bogdanm 74:a842253909c9 591
bogdanm 74:a842253909c9 592
bogdanm 74:a842253909c9 593
bogdanm 74:a842253909c9 594 /*******************************************************************************
bogdanm 74:a842253909c9 595 * Hardware Abstraction Layer
bogdanm 74:a842253909c9 596 Core Function Interface contains:
bogdanm 74:a842253909c9 597 - Core NVIC Functions
bogdanm 74:a842253909c9 598 - Core SysTick Functions
bogdanm 74:a842253909c9 599 - Core Register Access Functions
bogdanm 74:a842253909c9 600 ******************************************************************************/
bogdanm 74:a842253909c9 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 74:a842253909c9 602 */
bogdanm 74:a842253909c9 603
bogdanm 74:a842253909c9 604
bogdanm 74:a842253909c9 605
bogdanm 74:a842253909c9 606 /* ########################## NVIC functions #################################### */
bogdanm 74:a842253909c9 607 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 74:a842253909c9 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 74:a842253909c9 609 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 74:a842253909c9 610 @{
bogdanm 74:a842253909c9 611 */
bogdanm 74:a842253909c9 612
bogdanm 74:a842253909c9 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 74:a842253909c9 614 /* The following MACROS handle generation of the register offset and byte masks */
bogdanm 74:a842253909c9 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
bogdanm 74:a842253909c9 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
bogdanm 74:a842253909c9 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
bogdanm 74:a842253909c9 618
bogdanm 74:a842253909c9 619
bogdanm 74:a842253909c9 620 /** \brief Enable External Interrupt
bogdanm 74:a842253909c9 621
bogdanm 74:a842253909c9 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 74:a842253909c9 623
bogdanm 74:a842253909c9 624 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 74:a842253909c9 625 */
bogdanm 74:a842253909c9 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 627 {
bogdanm 74:a842253909c9 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 74:a842253909c9 629 }
bogdanm 74:a842253909c9 630
bogdanm 74:a842253909c9 631
bogdanm 74:a842253909c9 632 /** \brief Disable External Interrupt
bogdanm 74:a842253909c9 633
bogdanm 74:a842253909c9 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 74:a842253909c9 635
bogdanm 74:a842253909c9 636 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 74:a842253909c9 637 */
bogdanm 74:a842253909c9 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 639 {
bogdanm 74:a842253909c9 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 74:a842253909c9 641 }
bogdanm 74:a842253909c9 642
bogdanm 74:a842253909c9 643
bogdanm 74:a842253909c9 644 /** \brief Get Pending Interrupt
bogdanm 74:a842253909c9 645
bogdanm 74:a842253909c9 646 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 74:a842253909c9 647 for the specified interrupt.
bogdanm 74:a842253909c9 648
bogdanm 74:a842253909c9 649 \param [in] IRQn Interrupt number.
bogdanm 74:a842253909c9 650
bogdanm 74:a842253909c9 651 \return 0 Interrupt status is not pending.
bogdanm 74:a842253909c9 652 \return 1 Interrupt status is pending.
bogdanm 74:a842253909c9 653 */
bogdanm 74:a842253909c9 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 655 {
bogdanm 74:a842253909c9 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
bogdanm 74:a842253909c9 657 }
bogdanm 74:a842253909c9 658
bogdanm 74:a842253909c9 659
bogdanm 74:a842253909c9 660 /** \brief Set Pending Interrupt
bogdanm 74:a842253909c9 661
bogdanm 74:a842253909c9 662 The function sets the pending bit of an external interrupt.
bogdanm 74:a842253909c9 663
bogdanm 74:a842253909c9 664 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 74:a842253909c9 665 */
bogdanm 74:a842253909c9 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 667 {
bogdanm 74:a842253909c9 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 74:a842253909c9 669 }
bogdanm 74:a842253909c9 670
bogdanm 74:a842253909c9 671
bogdanm 74:a842253909c9 672 /** \brief Clear Pending Interrupt
bogdanm 74:a842253909c9 673
bogdanm 74:a842253909c9 674 The function clears the pending bit of an external interrupt.
bogdanm 74:a842253909c9 675
bogdanm 74:a842253909c9 676 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 74:a842253909c9 677 */
bogdanm 74:a842253909c9 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 74:a842253909c9 679 {
bogdanm 74:a842253909c9 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 74:a842253909c9 681 }
bogdanm 74:a842253909c9 682
bogdanm 74:a842253909c9 683
bogdanm 74:a842253909c9 684 /** \brief Set Interrupt Priority
bogdanm 74:a842253909c9 685
bogdanm 74:a842253909c9 686 The function sets the priority of an interrupt.
bogdanm 74:a842253909c9 687
bogdanm 74:a842253909c9 688 \note The priority cannot be set for every core interrupt.
bogdanm 74:a842253909c9 689
bogdanm 74:a842253909c9 690 \param [in] IRQn Interrupt number.
bogdanm 74:a842253909c9 691 \param [in] priority Priority to set.
bogdanm 74:a842253909c9 692 */
bogdanm 74:a842253909c9 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 74:a842253909c9 694 {
bogdanm 74:a842253909c9 695 if(IRQn < 0) {
bogdanm 74:a842253909c9 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 74:a842253909c9 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 74:a842253909c9 698 else {
bogdanm 74:a842253909c9 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 74:a842253909c9 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 74:a842253909c9 701 }
bogdanm 74:a842253909c9 702
bogdanm 74:a842253909c9 703
bogdanm 74:a842253909c9 704 /** \brief Get Interrupt Priority
bogdanm 74:a842253909c9 705
bogdanm 74:a842253909c9 706 The function reads the priority of an interrupt. The interrupt
bogdanm 74:a842253909c9 707 number can be positive to specify an external (device specific)
bogdanm 74:a842253909c9 708 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 74:a842253909c9 709
bogdanm 74:a842253909c9 710
bogdanm 74:a842253909c9 711 \param [in] IRQn Interrupt number.
bogdanm 74:a842253909c9 712 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 74:a842253909c9 713 priority bits of the microcontroller.
bogdanm 74:a842253909c9 714 */
bogdanm 74:a842253909c9 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 74:a842253909c9 716 {
bogdanm 74:a842253909c9 717
bogdanm 74:a842253909c9 718 if(IRQn < 0) {
bogdanm 74:a842253909c9 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
bogdanm 74:a842253909c9 720 else {
bogdanm 74:a842253909c9 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 74:a842253909c9 722 }
bogdanm 74:a842253909c9 723
bogdanm 74:a842253909c9 724
bogdanm 74:a842253909c9 725 /** \brief System Reset
bogdanm 74:a842253909c9 726
bogdanm 74:a842253909c9 727 The function initiates a system reset request to reset the MCU.
bogdanm 74:a842253909c9 728 */
bogdanm 74:a842253909c9 729 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 74:a842253909c9 730 {
bogdanm 74:a842253909c9 731 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 74:a842253909c9 732 buffered write are completed before reset */
bogdanm 74:a842253909c9 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 74:a842253909c9 734 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 74:a842253909c9 735 __DSB(); /* Ensure completion of memory access */
bogdanm 74:a842253909c9 736 while(1); /* wait until reset */
bogdanm 74:a842253909c9 737 }
bogdanm 74:a842253909c9 738
bogdanm 74:a842253909c9 739 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 74:a842253909c9 740
bogdanm 74:a842253909c9 741
bogdanm 74:a842253909c9 742
bogdanm 74:a842253909c9 743 /* ################################## SysTick function ############################################ */
bogdanm 74:a842253909c9 744 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 74:a842253909c9 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 74:a842253909c9 746 \brief Functions that configure the System.
bogdanm 74:a842253909c9 747 @{
bogdanm 74:a842253909c9 748 */
bogdanm 74:a842253909c9 749
bogdanm 74:a842253909c9 750 #if (__Vendor_SysTickConfig == 0)
bogdanm 74:a842253909c9 751
bogdanm 74:a842253909c9 752 /** \brief System Tick Configuration
bogdanm 74:a842253909c9 753
bogdanm 74:a842253909c9 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 74:a842253909c9 755 Counter is in free running mode to generate periodic interrupts.
bogdanm 74:a842253909c9 756
bogdanm 74:a842253909c9 757 \param [in] ticks Number of ticks between two interrupts.
bogdanm 74:a842253909c9 758
bogdanm 74:a842253909c9 759 \return 0 Function succeeded.
bogdanm 74:a842253909c9 760 \return 1 Function failed.
bogdanm 74:a842253909c9 761
bogdanm 74:a842253909c9 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 74:a842253909c9 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 74:a842253909c9 764 must contain a vendor-specific implementation of this function.
bogdanm 74:a842253909c9 765
bogdanm 74:a842253909c9 766 */
bogdanm 74:a842253909c9 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 74:a842253909c9 768 {
bogdanm 74:a842253909c9 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 74:a842253909c9 770
bogdanm 74:a842253909c9 771 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 74:a842253909c9 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 74:a842253909c9 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 74:a842253909c9 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 74:a842253909c9 775 SysTick_CTRL_TICKINT_Msk |
bogdanm 74:a842253909c9 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 74:a842253909c9 777 return (0); /* Function successful */
bogdanm 74:a842253909c9 778 }
bogdanm 74:a842253909c9 779
bogdanm 74:a842253909c9 780 #endif
bogdanm 74:a842253909c9 781
bogdanm 74:a842253909c9 782 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 74:a842253909c9 783
bogdanm 74:a842253909c9 784
bogdanm 74:a842253909c9 785
bogdanm 74:a842253909c9 786
bogdanm 74:a842253909c9 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 74:a842253909c9 788
bogdanm 74:a842253909c9 789 #endif /* __CMSIS_GENERIC */
bogdanm 74:a842253909c9 790
bogdanm 74:a842253909c9 791 #ifdef __cplusplus
bogdanm 74:a842253909c9 792 }
bogdanm 74:a842253909c9 793 #endif