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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_DISCO_L053C8/core_caFunc.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
130:d75b3fe1f5cb 
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /**************************************************************************//**
Kojto 99:dbbf35b96557 2 * @file core_caFunc.h
Kojto 99:dbbf35b96557 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 99:dbbf35b96557 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 99:dbbf35b96557 6 *
Kojto 99:dbbf35b96557 7 * @note
Kojto 99:dbbf35b96557 8 *
Kojto 99:dbbf35b96557 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 99:dbbf35b96557 11
Kojto 99:dbbf35b96557 12 All rights reserved.
Kojto 99:dbbf35b96557 13 Redistribution and use in source and binary forms, with or without
Kojto 99:dbbf35b96557 14 modification, are permitted provided that the following conditions are met:
Kojto 99:dbbf35b96557 15 - Redistributions of source code must retain the above copyright
Kojto 99:dbbf35b96557 16 notice, this list of conditions and the following disclaimer.
Kojto 99:dbbf35b96557 17 - Redistributions in binary form must reproduce the above copyright
Kojto 99:dbbf35b96557 18 notice, this list of conditions and the following disclaimer in the
Kojto 99:dbbf35b96557 19 documentation and/or other materials provided with the distribution.
Kojto 99:dbbf35b96557 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 99:dbbf35b96557 21 to endorse or promote products derived from this software without
Kojto 99:dbbf35b96557 22 specific prior written permission.
Kojto 99:dbbf35b96557 23 *
Kojto 99:dbbf35b96557 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 99:dbbf35b96557 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 99:dbbf35b96557 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 99:dbbf35b96557 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 99:dbbf35b96557 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 99:dbbf35b96557 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 99:dbbf35b96557 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 99:dbbf35b96557 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 99:dbbf35b96557 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 99:dbbf35b96557 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 99:dbbf35b96557 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 99:dbbf35b96557 35 ---------------------------------------------------------------------------*/
Kojto 99:dbbf35b96557 36
Kojto 99:dbbf35b96557 37
Kojto 99:dbbf35b96557 38 #ifndef __CORE_CAFUNC_H__
Kojto 99:dbbf35b96557 39 #define __CORE_CAFUNC_H__
Kojto 99:dbbf35b96557 40
Kojto 99:dbbf35b96557 41
Kojto 99:dbbf35b96557 42 /* ########################### Core Function Access ########################### */
Kojto 99:dbbf35b96557 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 99:dbbf35b96557 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 99:dbbf35b96557 45 @{
Kojto 99:dbbf35b96557 46 */
Kojto 99:dbbf35b96557 47
Kojto 99:dbbf35b96557 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 99:dbbf35b96557 49 /* ARM armcc specific functions */
Kojto 99:dbbf35b96557 50
Kojto 99:dbbf35b96557 51 #if (__ARMCC_VERSION < 400677)
Kojto 99:dbbf35b96557 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 99:dbbf35b96557 53 #endif
Kojto 99:dbbf35b96557 54
Kojto 99:dbbf35b96557 55 #define MODE_USR 0x10
Kojto 99:dbbf35b96557 56 #define MODE_FIQ 0x11
Kojto 99:dbbf35b96557 57 #define MODE_IRQ 0x12
Kojto 99:dbbf35b96557 58 #define MODE_SVC 0x13
Kojto 99:dbbf35b96557 59 #define MODE_MON 0x16
Kojto 99:dbbf35b96557 60 #define MODE_ABT 0x17
Kojto 99:dbbf35b96557 61 #define MODE_HYP 0x1A
Kojto 99:dbbf35b96557 62 #define MODE_UND 0x1B
Kojto 99:dbbf35b96557 63 #define MODE_SYS 0x1F
Kojto 99:dbbf35b96557 64
Kojto 99:dbbf35b96557 65 /** \brief Get APSR Register
Kojto 99:dbbf35b96557 66
Kojto 99:dbbf35b96557 67 This function returns the content of the APSR Register.
Kojto 99:dbbf35b96557 68
Kojto 99:dbbf35b96557 69 \return APSR Register value
Kojto 99:dbbf35b96557 70 */
Kojto 99:dbbf35b96557 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 99:dbbf35b96557 72 {
Kojto 99:dbbf35b96557 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 99:dbbf35b96557 74 return(__regAPSR);
Kojto 99:dbbf35b96557 75 }
Kojto 99:dbbf35b96557 76
Kojto 99:dbbf35b96557 77
Kojto 99:dbbf35b96557 78 /** \brief Get CPSR Register
Kojto 99:dbbf35b96557 79
Kojto 99:dbbf35b96557 80 This function returns the content of the CPSR Register.
Kojto 99:dbbf35b96557 81
Kojto 99:dbbf35b96557 82 \return CPSR Register value
Kojto 99:dbbf35b96557 83 */
Kojto 99:dbbf35b96557 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 99:dbbf35b96557 85 {
Kojto 99:dbbf35b96557 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 99:dbbf35b96557 87 return(__regCPSR);
Kojto 99:dbbf35b96557 88 }
Kojto 99:dbbf35b96557 89
Kojto 99:dbbf35b96557 90 /** \brief Set Stack Pointer
Kojto 99:dbbf35b96557 91
Kojto 99:dbbf35b96557 92 This function assigns the given value to the current stack pointer.
Kojto 99:dbbf35b96557 93
Kojto 99:dbbf35b96557 94 \param [in] topOfStack Stack Pointer value to set
Kojto 99:dbbf35b96557 95 */
Kojto 99:dbbf35b96557 96 register uint32_t __regSP __ASM("sp");
Kojto 99:dbbf35b96557 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 99:dbbf35b96557 98 {
Kojto 99:dbbf35b96557 99 __regSP = topOfStack;
Kojto 99:dbbf35b96557 100 }
Kojto 99:dbbf35b96557 101
Kojto 99:dbbf35b96557 102
Kojto 99:dbbf35b96557 103 /** \brief Get link register
Kojto 99:dbbf35b96557 104
Kojto 99:dbbf35b96557 105 This function returns the value of the link register
Kojto 99:dbbf35b96557 106
Kojto 99:dbbf35b96557 107 \return Value of link register
Kojto 99:dbbf35b96557 108 */
Kojto 99:dbbf35b96557 109 register uint32_t __reglr __ASM("lr");
Kojto 99:dbbf35b96557 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 99:dbbf35b96557 111 {
Kojto 99:dbbf35b96557 112 return(__reglr);
Kojto 99:dbbf35b96557 113 }
Kojto 99:dbbf35b96557 114
Kojto 99:dbbf35b96557 115 /** \brief Set link register
Kojto 99:dbbf35b96557 116
Kojto 99:dbbf35b96557 117 This function sets the value of the link register
Kojto 99:dbbf35b96557 118
Kojto 99:dbbf35b96557 119 \param [in] lr LR value to set
Kojto 99:dbbf35b96557 120 */
Kojto 99:dbbf35b96557 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 99:dbbf35b96557 122 {
Kojto 99:dbbf35b96557 123 __reglr = lr;
Kojto 99:dbbf35b96557 124 }
Kojto 99:dbbf35b96557 125
Kojto 99:dbbf35b96557 126 /** \brief Set Process Stack Pointer
Kojto 99:dbbf35b96557 127
Kojto 99:dbbf35b96557 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 99:dbbf35b96557 129
Kojto 99:dbbf35b96557 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 99:dbbf35b96557 131 */
Kojto 99:dbbf35b96557 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 99:dbbf35b96557 133 {
Kojto 99:dbbf35b96557 134 ARM
Kojto 99:dbbf35b96557 135 PRESERVE8
Kojto 99:dbbf35b96557 136
Kojto 99:dbbf35b96557 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 99:dbbf35b96557 138 MRS R1, CPSR
Kojto 99:dbbf35b96557 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 99:dbbf35b96557 140 MOV SP, R0
Kojto 99:dbbf35b96557 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 99:dbbf35b96557 142 ISB
Kojto 99:dbbf35b96557 143 BX LR
Kojto 99:dbbf35b96557 144
Kojto 99:dbbf35b96557 145 }
Kojto 99:dbbf35b96557 146
Kojto 99:dbbf35b96557 147 /** \brief Set User Mode
Kojto 99:dbbf35b96557 148
Kojto 99:dbbf35b96557 149 This function changes the processor state to User Mode
Kojto 99:dbbf35b96557 150 */
Kojto 99:dbbf35b96557 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 99:dbbf35b96557 152 {
Kojto 99:dbbf35b96557 153 ARM
Kojto 99:dbbf35b96557 154
Kojto 99:dbbf35b96557 155 CPS #MODE_USR
Kojto 99:dbbf35b96557 156 BX LR
Kojto 99:dbbf35b96557 157 }
Kojto 99:dbbf35b96557 158
Kojto 99:dbbf35b96557 159
Kojto 99:dbbf35b96557 160 /** \brief Enable FIQ
Kojto 99:dbbf35b96557 161
Kojto 99:dbbf35b96557 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 99:dbbf35b96557 163 Can only be executed in Privileged modes.
Kojto 99:dbbf35b96557 164 */
Kojto 99:dbbf35b96557 165 #define __enable_fault_irq __enable_fiq
Kojto 99:dbbf35b96557 166
Kojto 99:dbbf35b96557 167
Kojto 99:dbbf35b96557 168 /** \brief Disable FIQ
Kojto 99:dbbf35b96557 169
Kojto 99:dbbf35b96557 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 99:dbbf35b96557 171 Can only be executed in Privileged modes.
Kojto 99:dbbf35b96557 172 */
Kojto 99:dbbf35b96557 173 #define __disable_fault_irq __disable_fiq
Kojto 99:dbbf35b96557 174
Kojto 99:dbbf35b96557 175
Kojto 99:dbbf35b96557 176 /** \brief Get FPSCR
Kojto 99:dbbf35b96557 177
Kojto 99:dbbf35b96557 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 99:dbbf35b96557 179
Kojto 99:dbbf35b96557 180 \return Floating Point Status/Control register value
Kojto 99:dbbf35b96557 181 */
Kojto 99:dbbf35b96557 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 99:dbbf35b96557 183 {
Kojto 99:dbbf35b96557 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 99:dbbf35b96557 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 99:dbbf35b96557 186 return(__regfpscr);
Kojto 99:dbbf35b96557 187 #else
Kojto 99:dbbf35b96557 188 return(0);
Kojto 99:dbbf35b96557 189 #endif
Kojto 99:dbbf35b96557 190 }
Kojto 99:dbbf35b96557 191
Kojto 99:dbbf35b96557 192
Kojto 99:dbbf35b96557 193 /** \brief Set FPSCR
Kojto 99:dbbf35b96557 194
Kojto 99:dbbf35b96557 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 99:dbbf35b96557 196
Kojto 99:dbbf35b96557 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 99:dbbf35b96557 198 */
Kojto 99:dbbf35b96557 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 99:dbbf35b96557 200 {
Kojto 99:dbbf35b96557 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 99:dbbf35b96557 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 99:dbbf35b96557 203 __regfpscr = (fpscr);
Kojto 99:dbbf35b96557 204 #endif
Kojto 99:dbbf35b96557 205 }
Kojto 99:dbbf35b96557 206
Kojto 99:dbbf35b96557 207 /** \brief Get FPEXC
Kojto 99:dbbf35b96557 208
Kojto 99:dbbf35b96557 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 99:dbbf35b96557 210
Kojto 99:dbbf35b96557 211 \return Floating Point Exception Control register value
Kojto 99:dbbf35b96557 212 */
Kojto 99:dbbf35b96557 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 99:dbbf35b96557 214 {
Kojto 99:dbbf35b96557 215 #if (__FPU_PRESENT == 1)
Kojto 99:dbbf35b96557 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 99:dbbf35b96557 217 return(__regfpexc);
Kojto 99:dbbf35b96557 218 #else
Kojto 99:dbbf35b96557 219 return(0);
Kojto 99:dbbf35b96557 220 #endif
Kojto 99:dbbf35b96557 221 }
Kojto 99:dbbf35b96557 222
Kojto 99:dbbf35b96557 223
Kojto 99:dbbf35b96557 224 /** \brief Set FPEXC
Kojto 99:dbbf35b96557 225
Kojto 99:dbbf35b96557 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 99:dbbf35b96557 227
Kojto 99:dbbf35b96557 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 99:dbbf35b96557 229 */
Kojto 99:dbbf35b96557 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 99:dbbf35b96557 231 {
Kojto 99:dbbf35b96557 232 #if (__FPU_PRESENT == 1)
Kojto 99:dbbf35b96557 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 99:dbbf35b96557 234 __regfpexc = (fpexc);
Kojto 99:dbbf35b96557 235 #endif
Kojto 99:dbbf35b96557 236 }
Kojto 99:dbbf35b96557 237
Kojto 99:dbbf35b96557 238 /** \brief Get CPACR
Kojto 99:dbbf35b96557 239
Kojto 99:dbbf35b96557 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 99:dbbf35b96557 241
Kojto 99:dbbf35b96557 242 \return Coprocessor Access Control register value
Kojto 99:dbbf35b96557 243 */
Kojto 99:dbbf35b96557 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 99:dbbf35b96557 245 {
Kojto 99:dbbf35b96557 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 99:dbbf35b96557 247 return __regCPACR;
Kojto 99:dbbf35b96557 248 }
Kojto 99:dbbf35b96557 249
Kojto 99:dbbf35b96557 250 /** \brief Set CPACR
Kojto 99:dbbf35b96557 251
Kojto 99:dbbf35b96557 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 99:dbbf35b96557 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 99:dbbf35b96557 255 */
Kojto 99:dbbf35b96557 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 99:dbbf35b96557 257 {
Kojto 99:dbbf35b96557 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 99:dbbf35b96557 259 __regCPACR = cpacr;
Kojto 99:dbbf35b96557 260 __ISB();
Kojto 99:dbbf35b96557 261 }
Kojto 99:dbbf35b96557 262
Kojto 99:dbbf35b96557 263 /** \brief Get CBAR
Kojto 99:dbbf35b96557 264
Kojto 99:dbbf35b96557 265 This function returns the value of the Configuration Base Address register.
Kojto 99:dbbf35b96557 266
Kojto 99:dbbf35b96557 267 \return Configuration Base Address register value
Kojto 99:dbbf35b96557 268 */
Kojto 99:dbbf35b96557 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 99:dbbf35b96557 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 99:dbbf35b96557 271 return(__regCBAR);
Kojto 99:dbbf35b96557 272 }
Kojto 99:dbbf35b96557 273
Kojto 99:dbbf35b96557 274 /** \brief Get TTBR0
Kojto 99:dbbf35b96557 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 99:dbbf35b96557 277
Kojto 99:dbbf35b96557 278 \return Translation Table Base Register 0 value
Kojto 99:dbbf35b96557 279 */
Kojto 99:dbbf35b96557 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 99:dbbf35b96557 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 99:dbbf35b96557 282 return(__regTTBR0);
Kojto 99:dbbf35b96557 283 }
Kojto 99:dbbf35b96557 284
Kojto 99:dbbf35b96557 285 /** \brief Set TTBR0
Kojto 99:dbbf35b96557 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 99:dbbf35b96557 288
Kojto 99:dbbf35b96557 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 99:dbbf35b96557 290 */
Kojto 99:dbbf35b96557 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 99:dbbf35b96557 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 99:dbbf35b96557 293 __regTTBR0 = ttbr0;
Kojto 99:dbbf35b96557 294 __ISB();
Kojto 99:dbbf35b96557 295 }
Kojto 99:dbbf35b96557 296
Kojto 99:dbbf35b96557 297 /** \brief Get DACR
Kojto 99:dbbf35b96557 298
Kojto 99:dbbf35b96557 299 This function returns the value of the Domain Access Control Register.
Kojto 99:dbbf35b96557 300
Kojto 99:dbbf35b96557 301 \return Domain Access Control Register value
Kojto 99:dbbf35b96557 302 */
Kojto 99:dbbf35b96557 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 99:dbbf35b96557 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 99:dbbf35b96557 305 return(__regDACR);
Kojto 99:dbbf35b96557 306 }
Kojto 99:dbbf35b96557 307
Kojto 99:dbbf35b96557 308 /** \brief Set DACR
Kojto 99:dbbf35b96557 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 99:dbbf35b96557 311
Kojto 99:dbbf35b96557 312 \param [in] dacr Domain Access Control Register value to set
Kojto 99:dbbf35b96557 313 */
Kojto 99:dbbf35b96557 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 99:dbbf35b96557 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 99:dbbf35b96557 316 __regDACR = dacr;
Kojto 99:dbbf35b96557 317 __ISB();
Kojto 99:dbbf35b96557 318 }
Kojto 99:dbbf35b96557 319
Kojto 99:dbbf35b96557 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 99:dbbf35b96557 321
Kojto 99:dbbf35b96557 322 /** \brief Set SCTLR
Kojto 99:dbbf35b96557 323
Kojto 99:dbbf35b96557 324 This function assigns the given value to the System Control Register.
Kojto 99:dbbf35b96557 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 99:dbbf35b96557 327 */
Kojto 99:dbbf35b96557 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 99:dbbf35b96557 329 {
Kojto 99:dbbf35b96557 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 99:dbbf35b96557 331 __regSCTLR = sctlr;
Kojto 99:dbbf35b96557 332 }
Kojto 99:dbbf35b96557 333
Kojto 99:dbbf35b96557 334 /** \brief Get SCTLR
Kojto 99:dbbf35b96557 335
Kojto 99:dbbf35b96557 336 This function returns the value of the System Control Register.
Kojto 99:dbbf35b96557 337
Kojto 99:dbbf35b96557 338 \return System Control Register value
Kojto 99:dbbf35b96557 339 */
Kojto 99:dbbf35b96557 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 99:dbbf35b96557 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 99:dbbf35b96557 342 return(__regSCTLR);
Kojto 99:dbbf35b96557 343 }
Kojto 99:dbbf35b96557 344
Kojto 99:dbbf35b96557 345 /** \brief Enable Caches
Kojto 99:dbbf35b96557 346
Kojto 99:dbbf35b96557 347 Enable Caches
Kojto 99:dbbf35b96557 348 */
Kojto 99:dbbf35b96557 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 99:dbbf35b96557 350 // Set I bit 12 to enable I Cache
Kojto 99:dbbf35b96557 351 // Set C bit 2 to enable D Cache
Kojto 99:dbbf35b96557 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 99:dbbf35b96557 353 }
Kojto 99:dbbf35b96557 354
Kojto 99:dbbf35b96557 355 /** \brief Disable Caches
Kojto 99:dbbf35b96557 356
Kojto 99:dbbf35b96557 357 Disable Caches
Kojto 99:dbbf35b96557 358 */
Kojto 99:dbbf35b96557 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 99:dbbf35b96557 360 // Clear I bit 12 to disable I Cache
Kojto 99:dbbf35b96557 361 // Clear C bit 2 to disable D Cache
Kojto 99:dbbf35b96557 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 99:dbbf35b96557 363 __ISB();
Kojto 99:dbbf35b96557 364 }
Kojto 99:dbbf35b96557 365
Kojto 99:dbbf35b96557 366 /** \brief Enable BTAC
Kojto 99:dbbf35b96557 367
Kojto 99:dbbf35b96557 368 Enable BTAC
Kojto 99:dbbf35b96557 369 */
Kojto 99:dbbf35b96557 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 99:dbbf35b96557 371 // Set Z bit 11 to enable branch prediction
Kojto 99:dbbf35b96557 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 99:dbbf35b96557 373 __ISB();
Kojto 99:dbbf35b96557 374 }
Kojto 99:dbbf35b96557 375
Kojto 99:dbbf35b96557 376 /** \brief Disable BTAC
Kojto 99:dbbf35b96557 377
Kojto 99:dbbf35b96557 378 Disable BTAC
Kojto 99:dbbf35b96557 379 */
Kojto 99:dbbf35b96557 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 99:dbbf35b96557 381 // Clear Z bit 11 to disable branch prediction
Kojto 99:dbbf35b96557 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 99:dbbf35b96557 383 }
Kojto 99:dbbf35b96557 384
Kojto 99:dbbf35b96557 385
Kojto 99:dbbf35b96557 386 /** \brief Enable MMU
Kojto 99:dbbf35b96557 387
Kojto 99:dbbf35b96557 388 Enable MMU
Kojto 99:dbbf35b96557 389 */
Kojto 99:dbbf35b96557 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 99:dbbf35b96557 391 // Set M bit 0 to enable the MMU
Kojto 99:dbbf35b96557 392 // Set AFE bit to enable simplified access permissions model
Kojto 99:dbbf35b96557 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 99:dbbf35b96557 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 99:dbbf35b96557 395 __ISB();
Kojto 99:dbbf35b96557 396 }
Kojto 99:dbbf35b96557 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 99:dbbf35b96557 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 99:dbbf35b96557 401 */
Kojto 99:dbbf35b96557 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 99:dbbf35b96557 403 // Clear M bit 0 to disable the MMU
Kojto 99:dbbf35b96557 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 99:dbbf35b96557 405 __ISB();
Kojto 99:dbbf35b96557 406 }
Kojto 99:dbbf35b96557 407
Kojto 99:dbbf35b96557 408 /******************************** TLB maintenance operations ************************************************/
Kojto 99:dbbf35b96557 409 /** \brief Invalidate the whole tlb
Kojto 99:dbbf35b96557 410
Kojto 99:dbbf35b96557 411 TLBIALL. Invalidate the whole tlb
Kojto 99:dbbf35b96557 412 */
Kojto 99:dbbf35b96557 413
Kojto 99:dbbf35b96557 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 99:dbbf35b96557 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 99:dbbf35b96557 416 __TLBIALL = 0;
Kojto 99:dbbf35b96557 417 __DSB();
Kojto 99:dbbf35b96557 418 __ISB();
Kojto 99:dbbf35b96557 419 }
Kojto 99:dbbf35b96557 420
Kojto 99:dbbf35b96557 421 /******************************** BTB maintenance operations ************************************************/
Kojto 99:dbbf35b96557 422 /** \brief Invalidate entire branch predictor array
Kojto 99:dbbf35b96557 423
Kojto 99:dbbf35b96557 424 BPIALL. Branch Predictor Invalidate All.
Kojto 99:dbbf35b96557 425 */
Kojto 99:dbbf35b96557 426
Kojto 99:dbbf35b96557 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 99:dbbf35b96557 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 99:dbbf35b96557 429 __BPIALL = 0;
Kojto 99:dbbf35b96557 430 __DSB(); //ensure completion of the invalidation
Kojto 99:dbbf35b96557 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 99:dbbf35b96557 432 }
Kojto 99:dbbf35b96557 433
Kojto 99:dbbf35b96557 434
Kojto 99:dbbf35b96557 435 /******************************** L1 cache operations ******************************************************/
Kojto 99:dbbf35b96557 436
Kojto 99:dbbf35b96557 437 /** \brief Invalidate the whole I$
Kojto 99:dbbf35b96557 438
Kojto 99:dbbf35b96557 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 99:dbbf35b96557 440 */
Kojto 99:dbbf35b96557 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 99:dbbf35b96557 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 99:dbbf35b96557 443 __ICIALLU = 0;
Kojto 99:dbbf35b96557 444 __DSB(); //ensure completion of the invalidation
Kojto 99:dbbf35b96557 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 99:dbbf35b96557 446 }
Kojto 99:dbbf35b96557 447
Kojto 99:dbbf35b96557 448 /** \brief Clean D$ by MVA
Kojto 99:dbbf35b96557 449
Kojto 99:dbbf35b96557 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 99:dbbf35b96557 451 */
Kojto 99:dbbf35b96557 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 99:dbbf35b96557 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 99:dbbf35b96557 454 __DCCMVAC = (uint32_t)va;
Kojto 99:dbbf35b96557 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 99:dbbf35b96557 456 }
Kojto 99:dbbf35b96557 457
Kojto 99:dbbf35b96557 458 /** \brief Invalidate D$ by MVA
Kojto 99:dbbf35b96557 459
Kojto 99:dbbf35b96557 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 99:dbbf35b96557 461 */
Kojto 99:dbbf35b96557 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 99:dbbf35b96557 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 99:dbbf35b96557 464 __DCIMVAC = (uint32_t)va;
Kojto 99:dbbf35b96557 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 99:dbbf35b96557 466 }
Kojto 99:dbbf35b96557 467
Kojto 99:dbbf35b96557 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 99:dbbf35b96557 469
Kojto 99:dbbf35b96557 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 99:dbbf35b96557 471 */
Kojto 99:dbbf35b96557 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 99:dbbf35b96557 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 99:dbbf35b96557 474 __DCCIMVAC = (uint32_t)va;
Kojto 99:dbbf35b96557 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 99:dbbf35b96557 476 }
Kojto 99:dbbf35b96557 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 99:dbbf35b96557 481 */
Kojto 99:dbbf35b96557 482 #pragma push
Kojto 99:dbbf35b96557 483 #pragma arm
Kojto 99:dbbf35b96557 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 99:dbbf35b96557 485 ARM
Kojto 99:dbbf35b96557 486
Kojto 99:dbbf35b96557 487 PUSH {R4-R11}
Kojto 99:dbbf35b96557 488
Kojto 99:dbbf35b96557 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 99:dbbf35b96557 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 99:dbbf35b96557 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 99:dbbf35b96557 492 BEQ Finished // If 0, no need to clean
Kojto 99:dbbf35b96557 493
Kojto 99:dbbf35b96557 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 99:dbbf35b96557 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 99:dbbf35b96557 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 99:dbbf35b96557 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 99:dbbf35b96557 498 CMP R1, #2
Kojto 99:dbbf35b96557 499 BLT Skip // No cache or only instruction cache at this level
Kojto 99:dbbf35b96557 500
Kojto 99:dbbf35b96557 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 99:dbbf35b96557 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 99:dbbf35b96557 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 99:dbbf35b96557 504 AND R2, R1, #7 // Extract the line length field
Kojto 99:dbbf35b96557 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 99:dbbf35b96557 506 LDR R4, =0x3FF
Kojto 99:dbbf35b96557 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 99:dbbf35b96557 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 99:dbbf35b96557 509 LDR R7, =0x7FFF
Kojto 99:dbbf35b96557 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 99:dbbf35b96557 511
Kojto 99:dbbf35b96557 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 99:dbbf35b96557 513
Kojto 99:dbbf35b96557 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 99:dbbf35b96557 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 99:dbbf35b96557 516 CMP R0, #0
Kojto 99:dbbf35b96557 517 BNE Dccsw
Kojto 99:dbbf35b96557 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 99:dbbf35b96557 519 B cont
Kojto 99:dbbf35b96557 520 Dccsw CMP R0, #1
Kojto 99:dbbf35b96557 521 BNE Dccisw
Kojto 99:dbbf35b96557 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 99:dbbf35b96557 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 99:dbbf35b96557 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 99:dbbf35b96557 526 BGE Loop3
Kojto 99:dbbf35b96557 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 99:dbbf35b96557 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 99:dbbf35b96557 530 CMP R3, R10
Kojto 99:dbbf35b96557 531 BGT Loop1
Kojto 99:dbbf35b96557 532
Kojto 99:dbbf35b96557 533 Finished
Kojto 99:dbbf35b96557 534 DSB
Kojto 99:dbbf35b96557 535 POP {R4-R11}
Kojto 99:dbbf35b96557 536 BX lr
Kojto 99:dbbf35b96557 537
Kojto 99:dbbf35b96557 538 }
Kojto 99:dbbf35b96557 539 #pragma pop
Kojto 99:dbbf35b96557 540
Kojto 99:dbbf35b96557 541
Kojto 99:dbbf35b96557 542 /** \brief Invalidate the whole D$
Kojto 99:dbbf35b96557 543
Kojto 99:dbbf35b96557 544 DCISW. Invalidate by Set/Way
Kojto 99:dbbf35b96557 545 */
Kojto 99:dbbf35b96557 546
Kojto 99:dbbf35b96557 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 99:dbbf35b96557 548 __v7_all_cache(0);
Kojto 99:dbbf35b96557 549 }
Kojto 99:dbbf35b96557 550
Kojto 99:dbbf35b96557 551 /** \brief Clean the whole D$
Kojto 99:dbbf35b96557 552
Kojto 99:dbbf35b96557 553 DCCSW. Clean by Set/Way
Kojto 99:dbbf35b96557 554 */
Kojto 99:dbbf35b96557 555
Kojto 99:dbbf35b96557 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 99:dbbf35b96557 557 __v7_all_cache(1);
Kojto 99:dbbf35b96557 558 }
Kojto 99:dbbf35b96557 559
Kojto 99:dbbf35b96557 560 /** \brief Clean and invalidate the whole D$
Kojto 99:dbbf35b96557 561
Kojto 99:dbbf35b96557 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 99:dbbf35b96557 563 */
Kojto 99:dbbf35b96557 564
Kojto 99:dbbf35b96557 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 99:dbbf35b96557 566 __v7_all_cache(2);
Kojto 99:dbbf35b96557 567 }
Kojto 99:dbbf35b96557 568
Kojto 99:dbbf35b96557 569 #include "core_ca_mmu.h"
Kojto 99:dbbf35b96557 570
Kojto 99:dbbf35b96557 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 99:dbbf35b96557 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
<> 130:d75b3fe1f5cb 814 /** \brief Clean the whole D$
<> 130:d75b3fe1f5cb 815
<> 130:d75b3fe1f5cb 816 DCCSW. Clean by Set/Way
<> 130:d75b3fe1f5cb 817 */
<> 130:d75b3fe1f5cb 818
<> 130:d75b3fe1f5cb 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 130:d75b3fe1f5cb 820 __v7_all_cache(1);
<> 130:d75b3fe1f5cb 821 }
<> 130:d75b3fe1f5cb 822
<> 130:d75b3fe1f5cb 823 /** \brief Clean and invalidate the whole D$
<> 130:d75b3fe1f5cb 824
<> 130:d75b3fe1f5cb 825 DCCISW. Clean and Invalidate by Set/Way
<> 130:d75b3fe1f5cb 826 */
<> 130:d75b3fe1f5cb 827
<> 130:d75b3fe1f5cb 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 130:d75b3fe1f5cb 829 __v7_all_cache(2);
<> 130:d75b3fe1f5cb 830 }
Kojto 121:6c34061e7c34 831 /** \brief Clean and Invalidate D$ by MVA
Kojto 121:6c34061e7c34 832
Kojto 121:6c34061e7c34 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 121:6c34061e7c34 834 */
Kojto 121:6c34061e7c34 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 121:6c34061e7c34 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 121:6c34061e7c34 837 __DMB();
Kojto 121:6c34061e7c34 838 }
Kojto 121:6c34061e7c34 839
Kojto 115:87f2f5183dfb 840 #include "core_ca_mmu.h"
Kojto 99:dbbf35b96557 841
Kojto 99:dbbf35b96557 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 99:dbbf35b96557 843 /* GNU gcc specific functions */
Kojto 99:dbbf35b96557 844
Kojto 99:dbbf35b96557 845 #define MODE_USR 0x10
Kojto 99:dbbf35b96557 846 #define MODE_FIQ 0x11
Kojto 99:dbbf35b96557 847 #define MODE_IRQ 0x12
Kojto 99:dbbf35b96557 848 #define MODE_SVC 0x13
Kojto 99:dbbf35b96557 849 #define MODE_MON 0x16
Kojto 99:dbbf35b96557 850 #define MODE_ABT 0x17
Kojto 99:dbbf35b96557 851 #define MODE_HYP 0x1A
Kojto 99:dbbf35b96557 852 #define MODE_UND 0x1B
Kojto 99:dbbf35b96557 853 #define MODE_SYS 0x1F
Kojto 99:dbbf35b96557 854
Kojto 99:dbbf35b96557 855
Kojto 99:dbbf35b96557 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 99:dbbf35b96557 857 {
Kojto 99:dbbf35b96557 858 __ASM volatile ("cpsie i");
Kojto 99:dbbf35b96557 859 }
Kojto 99:dbbf35b96557 860
Kojto 99:dbbf35b96557 861 /** \brief Disable IRQ Interrupts
Kojto 99:dbbf35b96557 862
Kojto 99:dbbf35b96557 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 99:dbbf35b96557 864 Can only be executed in Privileged modes.
Kojto 99:dbbf35b96557 865 */
Kojto 99:dbbf35b96557 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 99:dbbf35b96557 867 {
Kojto 99:dbbf35b96557 868 uint32_t result;
Kojto 99:dbbf35b96557 869
Kojto 99:dbbf35b96557 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 99:dbbf35b96557 871 __ASM volatile ("cpsid i");
Kojto 99:dbbf35b96557 872 return(result & 0x80);
Kojto 99:dbbf35b96557 873 }
Kojto 99:dbbf35b96557 874
Kojto 99:dbbf35b96557 875
Kojto 99:dbbf35b96557 876 /** \brief Get APSR Register
Kojto 99:dbbf35b96557 877
Kojto 99:dbbf35b96557 878 This function returns the content of the APSR Register.
Kojto 99:dbbf35b96557 879
Kojto 99:dbbf35b96557 880 \return APSR Register value
Kojto 99:dbbf35b96557 881 */
Kojto 99:dbbf35b96557 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 99:dbbf35b96557 883 {
Kojto 99:dbbf35b96557 884 #if 1
Kojto 108:34e6b704fe68 885 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 99:dbbf35b96557 887 #else
Kojto 99:dbbf35b96557 888 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 889 #endif
Kojto 99:dbbf35b96557 890 return(__regAPSR);
Kojto 99:dbbf35b96557 891 }
Kojto 99:dbbf35b96557 892
Kojto 99:dbbf35b96557 893
Kojto 99:dbbf35b96557 894 /** \brief Get CPSR Register
Kojto 99:dbbf35b96557 895
Kojto 99:dbbf35b96557 896 This function returns the content of the CPSR Register.
Kojto 99:dbbf35b96557 897
Kojto 99:dbbf35b96557 898 \return CPSR Register value
Kojto 99:dbbf35b96557 899 */
Kojto 99:dbbf35b96557 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 99:dbbf35b96557 901 {
Kojto 99:dbbf35b96557 902 #if 1
Kojto 99:dbbf35b96557 903 register uint32_t __regCPSR;
Kojto 99:dbbf35b96557 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 99:dbbf35b96557 905 #else
Kojto 99:dbbf35b96557 906 register uint32_t __regCPSR __ASM("cpsr");
Kojto 99:dbbf35b96557 907 #endif
Kojto 99:dbbf35b96557 908 return(__regCPSR);
Kojto 99:dbbf35b96557 909 }
Kojto 99:dbbf35b96557 910
Kojto 99:dbbf35b96557 911 #if 0
Kojto 99:dbbf35b96557 912 /** \brief Set Stack Pointer
Kojto 99:dbbf35b96557 913
Kojto 99:dbbf35b96557 914 This function assigns the given value to the current stack pointer.
Kojto 99:dbbf35b96557 915
Kojto 99:dbbf35b96557 916 \param [in] topOfStack Stack Pointer value to set
Kojto 99:dbbf35b96557 917 */
Kojto 99:dbbf35b96557 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 99:dbbf35b96557 919 {
Kojto 99:dbbf35b96557 920 register uint32_t __regSP __ASM("sp");
Kojto 99:dbbf35b96557 921 __regSP = topOfStack;
Kojto 99:dbbf35b96557 922 }
Kojto 99:dbbf35b96557 923 #endif
Kojto 99:dbbf35b96557 924
Kojto 99:dbbf35b96557 925 /** \brief Get link register
Kojto 99:dbbf35b96557 926
Kojto 99:dbbf35b96557 927 This function returns the value of the link register
Kojto 99:dbbf35b96557 928
Kojto 99:dbbf35b96557 929 \return Value of link register
Kojto 99:dbbf35b96557 930 */
Kojto 99:dbbf35b96557 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 99:dbbf35b96557 932 {
Kojto 99:dbbf35b96557 933 register uint32_t __reglr __ASM("lr");
Kojto 99:dbbf35b96557 934 return(__reglr);
Kojto 99:dbbf35b96557 935 }
Kojto 99:dbbf35b96557 936
Kojto 99:dbbf35b96557 937 #if 0
Kojto 99:dbbf35b96557 938 /** \brief Set link register
Kojto 99:dbbf35b96557 939
Kojto 99:dbbf35b96557 940 This function sets the value of the link register
Kojto 99:dbbf35b96557 941
Kojto 99:dbbf35b96557 942 \param [in] lr LR value to set
Kojto 99:dbbf35b96557 943 */
Kojto 99:dbbf35b96557 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 99:dbbf35b96557 945 {
Kojto 99:dbbf35b96557 946 register uint32_t __reglr __ASM("lr");
Kojto 99:dbbf35b96557 947 __reglr = lr;
Kojto 99:dbbf35b96557 948 }
Kojto 99:dbbf35b96557 949 #endif
Kojto 99:dbbf35b96557 950
Kojto 99:dbbf35b96557 951 /** \brief Set Process Stack Pointer
Kojto 99:dbbf35b96557 952
Kojto 99:dbbf35b96557 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 99:dbbf35b96557 954
Kojto 99:dbbf35b96557 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 99:dbbf35b96557 956 */
Kojto 108:34e6b704fe68 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 958 {
Kojto 108:34e6b704fe68 959 __asm__ volatile (
Kojto 108:34e6b704fe68 960 ".ARM;"
Kojto 108:34e6b704fe68 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 962
Kojto 108:34e6b704fe68 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 964 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 965 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 966 "MOV SP, R0;"
Kojto 108:34e6b704fe68 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 968 "ISB;"
Kojto 108:34e6b704fe68 969 //"BX LR;"
Kojto 108:34e6b704fe68 970 :
Kojto 108:34e6b704fe68 971 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 972 : "r0", "r1");
Kojto 108:34e6b704fe68 973 return;
Kojto 108:34e6b704fe68 974 }
Kojto 99:dbbf35b96557 975
Kojto 99:dbbf35b96557 976 /** \brief Set User Mode
Kojto 99:dbbf35b96557 977
Kojto 99:dbbf35b96557 978 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 979 */
Kojto 108:34e6b704fe68 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 981 {
Kojto 108:34e6b704fe68 982 __asm__ volatile (
Kojto 108:34e6b704fe68 983 ".ARM;"
Kojto 99:dbbf35b96557 984
Kojto 108:34e6b704fe68 985 "CPS %0;"
Kojto 108:34e6b704fe68 986 //"BX LR;"
Kojto 108:34e6b704fe68 987 :
Kojto 108:34e6b704fe68 988 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 989 : );
Kojto 108:34e6b704fe68 990 return;
Kojto 108:34e6b704fe68 991 }
Kojto 108:34e6b704fe68 992
Kojto 99:dbbf35b96557 993
Kojto 99:dbbf35b96557 994 /** \brief Enable FIQ
Kojto 99:dbbf35b96557 995
Kojto 99:dbbf35b96557 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 99:dbbf35b96557 997 Can only be executed in Privileged modes.
Kojto 99:dbbf35b96557 998 */
Kojto 108:34e6b704fe68 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 99:dbbf35b96557 1000
Kojto 99:dbbf35b96557 1001
Kojto 99:dbbf35b96557 1002 /** \brief Disable FIQ
Kojto 99:dbbf35b96557 1003
Kojto 99:dbbf35b96557 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 99:dbbf35b96557 1005 Can only be executed in Privileged modes.
Kojto 99:dbbf35b96557 1006 */
Kojto 108:34e6b704fe68 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 99:dbbf35b96557 1008
Kojto 99:dbbf35b96557 1009
Kojto 99:dbbf35b96557 1010 /** \brief Get FPSCR
Kojto 99:dbbf35b96557 1011
Kojto 99:dbbf35b96557 1012 This function returns the current value of the Floating Point Status/Control register.
Kojto 99:dbbf35b96557 1013
Kojto 99:dbbf35b96557 1014 \return Floating Point Status/Control register value
Kojto 99:dbbf35b96557 1015 */
Kojto 99:dbbf35b96557 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 99:dbbf35b96557 1017 {
Kojto 99:dbbf35b96557 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 99:dbbf35b96557 1019 #if 1
Kojto 99:dbbf35b96557 1020 uint32_t result;
Kojto 99:dbbf35b96557 1021
Kojto 99:dbbf35b96557 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 99:dbbf35b96557 1023 return (result);
Kojto 99:dbbf35b96557 1024 #else
Kojto 99:dbbf35b96557 1025 register uint32_t __regfpscr __ASM("fpscr");
Kojto 99:dbbf35b96557 1026 return(__regfpscr);
Kojto 99:dbbf35b96557 1027 #endif
Kojto 99:dbbf35b96557 1028 #else
Kojto 99:dbbf35b96557 1029 return(0);
Kojto 99:dbbf35b96557 1030 #endif
Kojto 99:dbbf35b96557 1031 }
Kojto 99:dbbf35b96557 1032
Kojto 99:dbbf35b96557 1033
Kojto 99:dbbf35b96557 1034 /** \brief Set FPSCR
Kojto 99:dbbf35b96557 1035
Kojto 99:dbbf35b96557 1036 This function assigns the given value to the Floating Point Status/Control register.
Kojto 99:dbbf35b96557 1037
Kojto 99:dbbf35b96557 1038 \param [in] fpscr Floating Point Status/Control value to set
Kojto 99:dbbf35b96557 1039 */
Kojto 99:dbbf35b96557 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 99:dbbf35b96557 1041 {
Kojto 99:dbbf35b96557 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 99:dbbf35b96557 1043 #if 1
Kojto 99:dbbf35b96557 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 99:dbbf35b96557 1045 #else
Kojto 99:dbbf35b96557 1046 register uint32_t __regfpscr __ASM("fpscr");
Kojto 99:dbbf35b96557 1047 __regfpscr = (fpscr);
Kojto 99:dbbf35b96557 1048 #endif
Kojto 99:dbbf35b96557 1049 #endif
Kojto 99:dbbf35b96557 1050 }
Kojto 99:dbbf35b96557 1051
Kojto 99:dbbf35b96557 1052 /** \brief Get FPEXC
Kojto 99:dbbf35b96557 1053
Kojto 99:dbbf35b96557 1054 This function returns the current value of the Floating Point Exception Control register.
Kojto 99:dbbf35b96557 1055
Kojto 99:dbbf35b96557 1056 \return Floating Point Exception Control register value
Kojto 99:dbbf35b96557 1057 */
Kojto 99:dbbf35b96557 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 99:dbbf35b96557 1059 {
Kojto 99:dbbf35b96557 1060 #if (__FPU_PRESENT == 1)
Kojto 99:dbbf35b96557 1061 #if 1
Kojto 99:dbbf35b96557 1062 uint32_t result;
Kojto 99:dbbf35b96557 1063
Kojto 99:dbbf35b96557 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 99:dbbf35b96557 1065 return (result);
Kojto 99:dbbf35b96557 1066 #else
Kojto 99:dbbf35b96557 1067 register uint32_t __regfpexc __ASM("fpexc");
Kojto 99:dbbf35b96557 1068 return(__regfpexc);
Kojto 99:dbbf35b96557 1069 #endif
Kojto 99:dbbf35b96557 1070 #else
Kojto 99:dbbf35b96557 1071 return(0);
Kojto 99:dbbf35b96557 1072 #endif
Kojto 99:dbbf35b96557 1073 }
Kojto 99:dbbf35b96557 1074
Kojto 99:dbbf35b96557 1075
Kojto 99:dbbf35b96557 1076 /** \brief Set FPEXC
Kojto 99:dbbf35b96557 1077
Kojto 99:dbbf35b96557 1078 This function assigns the given value to the Floating Point Exception Control register.
Kojto 99:dbbf35b96557 1079
Kojto 99:dbbf35b96557 1080 \param [in] fpscr Floating Point Exception Control value to set
Kojto 99:dbbf35b96557 1081 */
Kojto 99:dbbf35b96557 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 99:dbbf35b96557 1083 {
Kojto 99:dbbf35b96557 1084 #if (__FPU_PRESENT == 1)
Kojto 99:dbbf35b96557 1085 #if 1
Kojto 99:dbbf35b96557 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 99:dbbf35b96557 1087 #else
Kojto 99:dbbf35b96557 1088 register uint32_t __regfpexc __ASM("fpexc");
Kojto 99:dbbf35b96557 1089 __regfpexc = (fpexc);
Kojto 99:dbbf35b96557 1090 #endif
Kojto 99:dbbf35b96557 1091 #endif
Kojto 99:dbbf35b96557 1092 }
Kojto 99:dbbf35b96557 1093
Kojto 99:dbbf35b96557 1094 /** \brief Get CPACR
Kojto 99:dbbf35b96557 1095
Kojto 99:dbbf35b96557 1096 This function returns the current value of the Coprocessor Access Control register.
Kojto 99:dbbf35b96557 1097
Kojto 99:dbbf35b96557 1098 \return Coprocessor Access Control register value
Kojto 99:dbbf35b96557 1099 */
Kojto 99:dbbf35b96557 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 99:dbbf35b96557 1101 {
Kojto 99:dbbf35b96557 1102 #if 1
Kojto 99:dbbf35b96557 1103 register uint32_t __regCPACR;
Kojto 99:dbbf35b96557 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 99:dbbf35b96557 1105 #else
Kojto 99:dbbf35b96557 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 99:dbbf35b96557 1107 #endif
Kojto 99:dbbf35b96557 1108 return __regCPACR;
Kojto 99:dbbf35b96557 1109 }
Kojto 99:dbbf35b96557 1110
Kojto 99:dbbf35b96557 1111 /** \brief Set CPACR
Kojto 99:dbbf35b96557 1112
Kojto 99:dbbf35b96557 1113 This function assigns the given value to the Coprocessor Access Control register.
Kojto 99:dbbf35b96557 1114
Kojto 108:34e6b704fe68 1115 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 99:dbbf35b96557 1116 */
Kojto 99:dbbf35b96557 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 99:dbbf35b96557 1118 {
Kojto 99:dbbf35b96557 1119 #if 1
Kojto 99:dbbf35b96557 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 99:dbbf35b96557 1121 #else
Kojto 99:dbbf35b96557 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 99:dbbf35b96557 1123 __regCPACR = cpacr;
Kojto 99:dbbf35b96557 1124 #endif
Kojto 99:dbbf35b96557 1125 __ISB();
Kojto 99:dbbf35b96557 1126 }
Kojto 99:dbbf35b96557 1127
Kojto 99:dbbf35b96557 1128 /** \brief Get CBAR
Kojto 99:dbbf35b96557 1129
Kojto 99:dbbf35b96557 1130 This function returns the value of the Configuration Base Address register.
Kojto 99:dbbf35b96557 1131
Kojto 99:dbbf35b96557 1132 \return Configuration Base Address register value
Kojto 99:dbbf35b96557 1133 */
Kojto 99:dbbf35b96557 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 99:dbbf35b96557 1135 #if 1
Kojto 99:dbbf35b96557 1136 register uint32_t __regCBAR;
Kojto 99:dbbf35b96557 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 99:dbbf35b96557 1138 #else
Kojto 99:dbbf35b96557 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 99:dbbf35b96557 1140 #endif
Kojto 99:dbbf35b96557 1141 return(__regCBAR);
Kojto 99:dbbf35b96557 1142 }
Kojto 99:dbbf35b96557 1143
Kojto 99:dbbf35b96557 1144 /** \brief Get TTBR0
Kojto 99:dbbf35b96557 1145
Kojto 108:34e6b704fe68 1146 This function returns the value of the Translation Table Base Register 0.
Kojto 99:dbbf35b96557 1147
Kojto 99:dbbf35b96557 1148 \return Translation Table Base Register 0 value
Kojto 99:dbbf35b96557 1149 */
Kojto 99:dbbf35b96557 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 99:dbbf35b96557 1151 #if 1
Kojto 99:dbbf35b96557 1152 register uint32_t __regTTBR0;
Kojto 99:dbbf35b96557 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 99:dbbf35b96557 1154 #else
Kojto 99:dbbf35b96557 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 99:dbbf35b96557 1156 #endif
Kojto 99:dbbf35b96557 1157 return(__regTTBR0);
Kojto 99:dbbf35b96557 1158 }
Kojto 99:dbbf35b96557 1159
Kojto 99:dbbf35b96557 1160 /** \brief Set TTBR0
Kojto 99:dbbf35b96557 1161
Kojto 108:34e6b704fe68 1162 This function assigns the given value to the Translation Table Base Register 0.
Kojto 99:dbbf35b96557 1163
Kojto 99:dbbf35b96557 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 99:dbbf35b96557 1165 */
Kojto 99:dbbf35b96557 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 99:dbbf35b96557 1167 #if 1
Kojto 99:dbbf35b96557 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 99:dbbf35b96557 1169 #else
Kojto 99:dbbf35b96557 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 99:dbbf35b96557 1171 __regTTBR0 = ttbr0;
Kojto 99:dbbf35b96557 1172 #endif
Kojto 99:dbbf35b96557 1173 __ISB();
Kojto 99:dbbf35b96557 1174 }
Kojto 99:dbbf35b96557 1175
Kojto 99:dbbf35b96557 1176 /** \brief Get DACR
Kojto 99:dbbf35b96557 1177
Kojto 99:dbbf35b96557 1178 This function returns the value of the Domain Access Control Register.
Kojto 99:dbbf35b96557 1179
Kojto 99:dbbf35b96557 1180 \return Domain Access Control Register value
Kojto 99:dbbf35b96557 1181 */
Kojto 99:dbbf35b96557 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 99:dbbf35b96557 1183 #if 1
Kojto 99:dbbf35b96557 1184 register uint32_t __regDACR;
Kojto 99:dbbf35b96557 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 99:dbbf35b96557 1186 #else
Kojto 99:dbbf35b96557 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 99:dbbf35b96557 1188 #endif
Kojto 99:dbbf35b96557 1189 return(__regDACR);
Kojto 99:dbbf35b96557 1190 }
Kojto 99:dbbf35b96557 1191
Kojto 99:dbbf35b96557 1192 /** \brief Set DACR
Kojto 99:dbbf35b96557 1193
Kojto 108:34e6b704fe68 1194 This function assigns the given value to the Domain Access Control Register.
Kojto 99:dbbf35b96557 1195
Kojto 99:dbbf35b96557 1196 \param [in] dacr Domain Access Control Register value to set
Kojto 99:dbbf35b96557 1197 */
Kojto 99:dbbf35b96557 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 99:dbbf35b96557 1199 #if 1
Kojto 99:dbbf35b96557 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 99:dbbf35b96557 1201 #else
Kojto 99:dbbf35b96557 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 99:dbbf35b96557 1203 __regDACR = dacr;
Kojto 99:dbbf35b96557 1204 #endif
Kojto 99:dbbf35b96557 1205 __ISB();
Kojto 99:dbbf35b96557 1206 }
Kojto 99:dbbf35b96557 1207
Kojto 99:dbbf35b96557 1208 /******************************** Cache and BTAC enable ****************************************************/
Kojto 99:dbbf35b96557 1209
Kojto 99:dbbf35b96557 1210 /** \brief Set SCTLR
Kojto 99:dbbf35b96557 1211
Kojto 99:dbbf35b96557 1212 This function assigns the given value to the System Control Register.
Kojto 99:dbbf35b96557 1213
Kojto 108:34e6b704fe68 1214 \param [in] sctlr System Control Register value to set
Kojto 99:dbbf35b96557 1215 */
Kojto 99:dbbf35b96557 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 99:dbbf35b96557 1217 {
Kojto 99:dbbf35b96557 1218 #if 1
Kojto 99:dbbf35b96557 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 99:dbbf35b96557 1220 #else
Kojto 99:dbbf35b96557 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 99:dbbf35b96557 1222 __regSCTLR = sctlr;
Kojto 99:dbbf35b96557 1223 #endif
Kojto 99:dbbf35b96557 1224 }
Kojto 99:dbbf35b96557 1225
Kojto 99:dbbf35b96557 1226 /** \brief Get SCTLR
Kojto 99:dbbf35b96557 1227
Kojto 99:dbbf35b96557 1228 This function returns the value of the System Control Register.
Kojto 99:dbbf35b96557 1229
Kojto 99:dbbf35b96557 1230 \return System Control Register value
Kojto 99:dbbf35b96557 1231 */
Kojto 99:dbbf35b96557 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 99:dbbf35b96557 1233 #if 1
Kojto 99:dbbf35b96557 1234 register uint32_t __regSCTLR;
Kojto 99:dbbf35b96557 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 99:dbbf35b96557 1236 #else
Kojto 99:dbbf35b96557 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 99:dbbf35b96557 1238 #endif
Kojto 99:dbbf35b96557 1239 return(__regSCTLR);
Kojto 99:dbbf35b96557 1240 }
Kojto 99:dbbf35b96557 1241
Kojto 99:dbbf35b96557 1242 /** \brief Enable Caches
Kojto 99:dbbf35b96557 1243
Kojto 99:dbbf35b96557 1244 Enable Caches
Kojto 99:dbbf35b96557 1245 */
Kojto 99:dbbf35b96557 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 99:dbbf35b96557 1247 // Set I bit 12 to enable I Cache
Kojto 99:dbbf35b96557 1248 // Set C bit 2 to enable D Cache
Kojto 99:dbbf35b96557 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 99:dbbf35b96557 1250 }
Kojto 99:dbbf35b96557 1251
Kojto 99:dbbf35b96557 1252 /** \brief Disable Caches
Kojto 99:dbbf35b96557 1253
Kojto 99:dbbf35b96557 1254 Disable Caches
Kojto 99:dbbf35b96557 1255 */
Kojto 99:dbbf35b96557 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 99:dbbf35b96557 1257 // Clear I bit 12 to disable I Cache
Kojto 99:dbbf35b96557 1258 // Clear C bit 2 to disable D Cache
Kojto 99:dbbf35b96557 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 99:dbbf35b96557 1260 __ISB();
Kojto 99:dbbf35b96557 1261 }
Kojto 99:dbbf35b96557 1262
Kojto 99:dbbf35b96557 1263 /** \brief Enable BTAC
Kojto 99:dbbf35b96557 1264
Kojto 99:dbbf35b96557 1265 Enable BTAC
Kojto 99:dbbf35b96557 1266 */
Kojto 99:dbbf35b96557 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 99:dbbf35b96557 1268 // Set Z bit 11 to enable branch prediction
Kojto 99:dbbf35b96557 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 99:dbbf35b96557 1270 __ISB();
Kojto 99:dbbf35b96557 1271 }
Kojto 99:dbbf35b96557 1272
Kojto 99:dbbf35b96557 1273 /** \brief Disable BTAC
Kojto 99:dbbf35b96557 1274
Kojto 99:dbbf35b96557 1275 Disable BTAC
Kojto 99:dbbf35b96557 1276 */
Kojto 99:dbbf35b96557 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 99:dbbf35b96557 1278 // Clear Z bit 11 to disable branch prediction
Kojto 99:dbbf35b96557 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 99:dbbf35b96557 1280 }
Kojto 99:dbbf35b96557 1281
Kojto 99:dbbf35b96557 1282
Kojto 99:dbbf35b96557 1283 /** \brief Enable MMU
Kojto 99:dbbf35b96557 1284
Kojto 99:dbbf35b96557 1285 Enable MMU
Kojto 99:dbbf35b96557 1286 */
Kojto 99:dbbf35b96557 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 99:dbbf35b96557 1288 // Set M bit 0 to enable the MMU
Kojto 99:dbbf35b96557 1289 // Set AFE bit to enable simplified access permissions model
Kojto 99:dbbf35b96557 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 99:dbbf35b96557 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 99:dbbf35b96557 1292 __ISB();
Kojto 99:dbbf35b96557 1293 }
Kojto 99:dbbf35b96557 1294
Kojto 108:34e6b704fe68 1295 /** \brief Disable MMU
Kojto 99:dbbf35b96557 1296
Kojto 108:34e6b704fe68 1297 Disable MMU
Kojto 99:dbbf35b96557 1298 */
Kojto 99:dbbf35b96557 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 99:dbbf35b96557 1300 // Clear M bit 0 to disable the MMU
Kojto 99:dbbf35b96557 1301 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 99:dbbf35b96557 1302 __ISB();
Kojto 99:dbbf35b96557 1303 }
Kojto 99:dbbf35b96557 1304
Kojto 99:dbbf35b96557 1305 /******************************** TLB maintenance operations ************************************************/
Kojto 99:dbbf35b96557 1306 /** \brief Invalidate the whole tlb
Kojto 99:dbbf35b96557 1307
Kojto 99:dbbf35b96557 1308 TLBIALL. Invalidate the whole tlb
Kojto 99:dbbf35b96557 1309 */
Kojto 99:dbbf35b96557 1310
Kojto 99:dbbf35b96557 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 99:dbbf35b96557 1312 #if 1
Kojto 99:dbbf35b96557 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 99:dbbf35b96557 1314 #else
Kojto 99:dbbf35b96557 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 99:dbbf35b96557 1316 __TLBIALL = 0;
Kojto 99:dbbf35b96557 1317 #endif
Kojto 99:dbbf35b96557 1318 __DSB();
Kojto 99:dbbf35b96557 1319 __ISB();
Kojto 99:dbbf35b96557 1320 }
Kojto 99:dbbf35b96557 1321
Kojto 99:dbbf35b96557 1322 /******************************** BTB maintenance operations ************************************************/
Kojto 99:dbbf35b96557 1323 /** \brief Invalidate entire branch predictor array
Kojto 99:dbbf35b96557 1324
Kojto 99:dbbf35b96557 1325 BPIALL. Branch Predictor Invalidate All.
Kojto 99:dbbf35b96557 1326 */
Kojto 99:dbbf35b96557 1327
Kojto 99:dbbf35b96557 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 99:dbbf35b96557 1329 #if 1
Kojto 99:dbbf35b96557 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 99:dbbf35b96557 1331 #else
Kojto 99:dbbf35b96557 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 99:dbbf35b96557 1333 __BPIALL = 0;
Kojto 99:dbbf35b96557 1334 #endif
Kojto 99:dbbf35b96557 1335 __DSB(); //ensure completion of the invalidation
Kojto 99:dbbf35b96557 1336 __ISB(); //ensure instruction fetch path sees new state
Kojto 99:dbbf35b96557 1337 }
Kojto 99:dbbf35b96557 1338
Kojto 99:dbbf35b96557 1339
Kojto 99:dbbf35b96557 1340 /******************************** L1 cache operations ******************************************************/
Kojto 99:dbbf35b96557 1341
Kojto 99:dbbf35b96557 1342 /** \brief Invalidate the whole I$
Kojto 99:dbbf35b96557 1343
Kojto 99:dbbf35b96557 1344 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 99:dbbf35b96557 1345 */
Kojto 99:dbbf35b96557 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 99:dbbf35b96557 1347 #if 1
Kojto 99:dbbf35b96557 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 99:dbbf35b96557 1349 #else
Kojto 99:dbbf35b96557 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 99:dbbf35b96557 1351 __ICIALLU = 0;
Kojto 99:dbbf35b96557 1352 #endif
Kojto 99:dbbf35b96557 1353 __DSB(); //ensure completion of the invalidation
Kojto 99:dbbf35b96557 1354 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 99:dbbf35b96557 1355 }
Kojto 99:dbbf35b96557 1356
Kojto 99:dbbf35b96557 1357 /** \brief Clean D$ by MVA
Kojto 99:dbbf35b96557 1358
Kojto 99:dbbf35b96557 1359 DCCMVAC. Data cache clean by MVA to PoC
Kojto 99:dbbf35b96557 1360 */
Kojto 99:dbbf35b96557 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 99:dbbf35b96557 1362 #if 1
Kojto 99:dbbf35b96557 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 99:dbbf35b96557 1364 #else
Kojto 99:dbbf35b96557 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 99:dbbf35b96557 1366 __DCCMVAC = (uint32_t)va;
Kojto 99:dbbf35b96557 1367 #endif
Kojto 99:dbbf35b96557 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 99:dbbf35b96557 1369 }
Kojto 99:dbbf35b96557 1370
Kojto 99:dbbf35b96557 1371 /** \brief Invalidate D$ by MVA
Kojto 99:dbbf35b96557 1372
Kojto 99:dbbf35b96557 1373 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 99:dbbf35b96557 1374 */
Kojto 99:dbbf35b96557 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 99:dbbf35b96557 1376 #if 1
Kojto 99:dbbf35b96557 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 99:dbbf35b96557 1378 #else
Kojto 99:dbbf35b96557 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 99:dbbf35b96557 1380 __DCIMVAC = (uint32_t)va;
Kojto 99:dbbf35b96557 1381 #endif
Kojto 99:dbbf35b96557 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 99:dbbf35b96557 1383 }
Kojto 99:dbbf35b96557 1384
Kojto 99:dbbf35b96557 1385 /** \brief Clean and Invalidate D$ by MVA
Kojto 99:dbbf35b96557 1386
Kojto 99:dbbf35b96557 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 99:dbbf35b96557 1388 */
Kojto 99:dbbf35b96557 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 99:dbbf35b96557 1390 #if 1
Kojto 99:dbbf35b96557 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 99:dbbf35b96557 1392 #else
Kojto 99:dbbf35b96557 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 99:dbbf35b96557 1394 __DCCIMVAC = (uint32_t)va;
Kojto 99:dbbf35b96557 1395 #endif
Kojto 99:dbbf35b96557 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 99:dbbf35b96557 1397 }
Kojto 99:dbbf35b96557 1398
Kojto 108:34e6b704fe68 1399 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 99:dbbf35b96557 1400
Kojto 108:34e6b704fe68 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 99:dbbf35b96557 1402 */
Kojto 99:dbbf35b96557 1403 extern void __v7_all_cache(uint32_t op);
Kojto 99:dbbf35b96557 1404
Kojto 99:dbbf35b96557 1405
Kojto 99:dbbf35b96557 1406 /** \brief Invalidate the whole D$
Kojto 99:dbbf35b96557 1407
Kojto 99:dbbf35b96557 1408 DCISW. Invalidate by Set/Way
Kojto 99:dbbf35b96557 1409 */
Kojto 99:dbbf35b96557 1410
Kojto 99:dbbf35b96557 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 99:dbbf35b96557 1412 __v7_all_cache(0);
Kojto 99:dbbf35b96557 1413 }
Kojto 99:dbbf35b96557 1414
Kojto 99:dbbf35b96557 1415 /** \brief Clean the whole D$
Kojto 99:dbbf35b96557 1416
Kojto 99:dbbf35b96557 1417 DCCSW. Clean by Set/Way
Kojto 99:dbbf35b96557 1418 */
Kojto 99:dbbf35b96557 1419
Kojto 99:dbbf35b96557 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 99:dbbf35b96557 1421 __v7_all_cache(1);
Kojto 99:dbbf35b96557 1422 }
Kojto 99:dbbf35b96557 1423
Kojto 99:dbbf35b96557 1424 /** \brief Clean and invalidate the whole D$
Kojto 99:dbbf35b96557 1425
Kojto 99:dbbf35b96557 1426 DCCISW. Clean and Invalidate by Set/Way
Kojto 99:dbbf35b96557 1427 */
Kojto 99:dbbf35b96557 1428
Kojto 99:dbbf35b96557 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 99:dbbf35b96557 1430 __v7_all_cache(2);
Kojto 99:dbbf35b96557 1431 }
Kojto 99:dbbf35b96557 1432
Kojto 99:dbbf35b96557 1433 #include "core_ca_mmu.h"
Kojto 99:dbbf35b96557 1434
Kojto 99:dbbf35b96557 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 99:dbbf35b96557 1436
Kojto 99:dbbf35b96557 1437 #error TASKING Compiler support not implemented for Cortex-A
Kojto 99:dbbf35b96557 1438
Kojto 99:dbbf35b96557 1439 #endif
Kojto 99:dbbf35b96557 1440
Kojto 99:dbbf35b96557 1441 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 99:dbbf35b96557 1442
Kojto 99:dbbf35b96557 1443
Kojto 99:dbbf35b96557 1444 #endif /* __CORE_CAFUNC_H__ */