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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_MPS2_M7/core_cm0plus.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 12:05:23 2017 +0000
Revision:
134:ad3be0349dc5
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 134 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 102:da0ca467f8b5 1 /**************************************************************************//**
Kojto 102:da0ca467f8b5 2 * @file core_cm0plus.h
Kojto 102:da0ca467f8b5 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 102:da0ca467f8b5 6 *
Kojto 102:da0ca467f8b5 7 * @note
Kojto 102:da0ca467f8b5 8 *
Kojto 102:da0ca467f8b5 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 102:da0ca467f8b5 11
Kojto 102:da0ca467f8b5 12 All rights reserved.
Kojto 102:da0ca467f8b5 13 Redistribution and use in source and binary forms, with or without
Kojto 102:da0ca467f8b5 14 modification, are permitted provided that the following conditions are met:
Kojto 102:da0ca467f8b5 15 - Redistributions of source code must retain the above copyright
Kojto 102:da0ca467f8b5 16 notice, this list of conditions and the following disclaimer.
Kojto 102:da0ca467f8b5 17 - Redistributions in binary form must reproduce the above copyright
Kojto 102:da0ca467f8b5 18 notice, this list of conditions and the following disclaimer in the
Kojto 102:da0ca467f8b5 19 documentation and/or other materials provided with the distribution.
Kojto 102:da0ca467f8b5 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 102:da0ca467f8b5 21 to endorse or promote products derived from this software without
Kojto 102:da0ca467f8b5 22 specific prior written permission.
Kojto 102:da0ca467f8b5 23 *
Kojto 102:da0ca467f8b5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 102:da0ca467f8b5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 102:da0ca467f8b5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 102:da0ca467f8b5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 102:da0ca467f8b5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 102:da0ca467f8b5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 102:da0ca467f8b5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 102:da0ca467f8b5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 102:da0ca467f8b5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 102:da0ca467f8b5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 102:da0ca467f8b5 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 102:da0ca467f8b5 35 ---------------------------------------------------------------------------*/
Kojto 102:da0ca467f8b5 36
Kojto 102:da0ca467f8b5 37
Kojto 102:da0ca467f8b5 38 #if defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 102:da0ca467f8b5 40 #endif
Kojto 102:da0ca467f8b5 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 102:da0ca467f8b5 45 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 46 extern "C" {
Kojto 102:da0ca467f8b5 47 #endif
Kojto 102:da0ca467f8b5 48
Kojto 102:da0ca467f8b5 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 102:da0ca467f8b5 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 102:da0ca467f8b5 51
Kojto 102:da0ca467f8b5 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 102:da0ca467f8b5 53 Function definitions in header files are used to allow 'inlining'.
Kojto 102:da0ca467f8b5 54
Kojto 102:da0ca467f8b5 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 102:da0ca467f8b5 56 Unions are used for effective representation of core registers.
Kojto 102:da0ca467f8b5 57
Kojto 102:da0ca467f8b5 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 102:da0ca467f8b5 59 Function-like macros are used to allow more efficient code.
Kojto 102:da0ca467f8b5 60 */
Kojto 102:da0ca467f8b5 61
Kojto 102:da0ca467f8b5 62
Kojto 102:da0ca467f8b5 63 /*******************************************************************************
Kojto 102:da0ca467f8b5 64 * CMSIS definitions
Kojto 102:da0ca467f8b5 65 ******************************************************************************/
Kojto 102:da0ca467f8b5 66 /** \ingroup Cortex-M0+
Kojto 102:da0ca467f8b5 67 @{
Kojto 102:da0ca467f8b5 68 */
Kojto 102:da0ca467f8b5 69
Kojto 102:da0ca467f8b5 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 102:da0ca467f8b5 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 102:da0ca467f8b5 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 102:da0ca467f8b5 75
Kojto 102:da0ca467f8b5 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 102:da0ca467f8b5 77
Kojto 102:da0ca467f8b5 78
Kojto 102:da0ca467f8b5 79 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 102:da0ca467f8b5 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 102:da0ca467f8b5 82 #define __STATIC_INLINE static __inline
Kojto 102:da0ca467f8b5 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 102:da0ca467f8b5 89 #elif defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 102:da0ca467f8b5 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 102:da0ca467f8b5 92 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 102:da0ca467f8b5 96 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 97
Kojto 102:da0ca467f8b5 98 #elif defined ( __TASKING__ )
Kojto 102:da0ca467f8b5 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 102:da0ca467f8b5 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 102:da0ca467f8b5 101 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 102:da0ca467f8b5 109 #endif
Kojto 102:da0ca467f8b5 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 102:da0ca467f8b5 113 */
Kojto 102:da0ca467f8b5 114 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 115
Kojto 102:da0ca467f8b5 116 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 117 #if defined __TARGET_FPU_VFP
Kojto 102:da0ca467f8b5 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 119 #endif
Kojto 102:da0ca467f8b5 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 102:da0ca467f8b5 126 #elif defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 127 #if defined __ARMVFP__
Kojto 102:da0ca467f8b5 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 129 #endif
Kojto 102:da0ca467f8b5 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 102:da0ca467f8b5 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 134 #endif
Kojto 102:da0ca467f8b5 135
Kojto 102:da0ca467f8b5 136 #elif defined ( __TASKING__ )
Kojto 102:da0ca467f8b5 137 #if defined __FPU_VFP__
Kojto 102:da0ca467f8b5 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 102:da0ca467f8b5 145 #endif
Kojto 102:da0ca467f8b5 146
Kojto 102:da0ca467f8b5 147 #include <stdint.h> /* standard types definitions */
Kojto 102:da0ca467f8b5 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 102:da0ca467f8b5 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 102:da0ca467f8b5 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 102:da0ca467f8b5 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 102:da0ca467f8b5 156
Kojto 102:da0ca467f8b5 157 #ifndef __CMSIS_GENERIC
Kojto 102:da0ca467f8b5 158
Kojto 102:da0ca467f8b5 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 102:da0ca467f8b5 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 102:da0ca467f8b5 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 102:da0ca467f8b5 166 /* check device defines and use defaults */
Kojto 102:da0ca467f8b5 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 102:da0ca467f8b5 168 #ifndef __CM0PLUS_REV
Kojto 102:da0ca467f8b5 169 #define __CM0PLUS_REV 0x0000
Kojto 102:da0ca467f8b5 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 171 #endif
Kojto 102:da0ca467f8b5 172
Kojto 102:da0ca467f8b5 173 #ifndef __MPU_PRESENT
Kojto 102:da0ca467f8b5 174 #define __MPU_PRESENT 0
Kojto 102:da0ca467f8b5 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 176 #endif
Kojto 102:da0ca467f8b5 177
Kojto 102:da0ca467f8b5 178 #ifndef __VTOR_PRESENT
Kojto 102:da0ca467f8b5 179 #define __VTOR_PRESENT 0
Kojto 102:da0ca467f8b5 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 181 #endif
Kojto 102:da0ca467f8b5 182
Kojto 102:da0ca467f8b5 183 #ifndef __NVIC_PRIO_BITS
Kojto 102:da0ca467f8b5 184 #define __NVIC_PRIO_BITS 2
Kojto 102:da0ca467f8b5 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 186 #endif
Kojto 102:da0ca467f8b5 187
Kojto 102:da0ca467f8b5 188 #ifndef __Vendor_SysTickConfig
Kojto 102:da0ca467f8b5 189 #define __Vendor_SysTickConfig 0
Kojto 102:da0ca467f8b5 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 191 #endif
Kojto 102:da0ca467f8b5 192 #endif
Kojto 102:da0ca467f8b5 193
Kojto 102:da0ca467f8b5 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 102:da0ca467f8b5 195 /**
Kojto 102:da0ca467f8b5 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 102:da0ca467f8b5 197
Kojto 102:da0ca467f8b5 198 <strong>IO Type Qualifiers</strong> are used
Kojto 102:da0ca467f8b5 199 \li to specify the access to peripheral variables.
Kojto 102:da0ca467f8b5 200 \li for automatic generation of peripheral register debug information.
Kojto 102:da0ca467f8b5 201 */
Kojto 102:da0ca467f8b5 202 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 102:da0ca467f8b5 204 #else
Kojto 102:da0ca467f8b5 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 102:da0ca467f8b5 206 #endif
Kojto 102:da0ca467f8b5 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 102:da0ca467f8b5 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 102:da0ca467f8b5 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
Kojto 102:da0ca467f8b5 218 /*@} end of group Cortex-M0+ */
Kojto 102:da0ca467f8b5 219
Kojto 102:da0ca467f8b5 220
Kojto 102:da0ca467f8b5 221
Kojto 102:da0ca467f8b5 222 /*******************************************************************************
Kojto 102:da0ca467f8b5 223 * Register Abstraction
Kojto 102:da0ca467f8b5 224 Core Register contain:
Kojto 102:da0ca467f8b5 225 - Core Register
Kojto 102:da0ca467f8b5 226 - Core NVIC Register
Kojto 102:da0ca467f8b5 227 - Core SCB Register
Kojto 102:da0ca467f8b5 228 - Core SysTick Register
Kojto 102:da0ca467f8b5 229 - Core MPU Register
Kojto 102:da0ca467f8b5 230 ******************************************************************************/
Kojto 102:da0ca467f8b5 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 102:da0ca467f8b5 232 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 102:da0ca467f8b5 233 */
Kojto 102:da0ca467f8b5 234
Kojto 102:da0ca467f8b5 235 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 236 \defgroup CMSIS_CORE Status and Control Registers
Kojto 102:da0ca467f8b5 237 \brief Core Register type definitions.
Kojto 102:da0ca467f8b5 238 @{
Kojto 102:da0ca467f8b5 239 */
Kojto 102:da0ca467f8b5 240
Kojto 102:da0ca467f8b5 241 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 102:da0ca467f8b5 242 */
Kojto 102:da0ca467f8b5 243 typedef union
Kojto 102:da0ca467f8b5 244 {
Kojto 102:da0ca467f8b5 245 struct
Kojto 102:da0ca467f8b5 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 102:da0ca467f8b5 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 102:da0ca467f8b5 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 102:da0ca467f8b5 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 102:da0ca467f8b5 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 102:da0ca467f8b5 252 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 253 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 254 } APSR_Type;
Kojto 102:da0ca467f8b5 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
Kojto 102:da0ca467f8b5 269
Kojto 102:da0ca467f8b5 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 102:da0ca467f8b5 271 */
Kojto 102:da0ca467f8b5 272 typedef union
Kojto 102:da0ca467f8b5 273 {
Kojto 102:da0ca467f8b5 274 struct
Kojto 102:da0ca467f8b5 275 {
Kojto 102:da0ca467f8b5 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 102:da0ca467f8b5 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 102:da0ca467f8b5 278 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 279 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 280 } IPSR_Type;
Kojto 102:da0ca467f8b5 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
Kojto 102:da0ca467f8b5 286
Kojto 102:da0ca467f8b5 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 102:da0ca467f8b5 288 */
Kojto 102:da0ca467f8b5 289 typedef union
Kojto 102:da0ca467f8b5 290 {
Kojto 102:da0ca467f8b5 291 struct
Kojto 102:da0ca467f8b5 292 {
Kojto 102:da0ca467f8b5 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 102:da0ca467f8b5 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 102:da0ca467f8b5 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 102:da0ca467f8b5 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 102:da0ca467f8b5 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 102:da0ca467f8b5 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 102:da0ca467f8b5 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 102:da0ca467f8b5 301 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 302 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 303 } xPSR_Type;
Kojto 102:da0ca467f8b5 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
Kojto 102:da0ca467f8b5 324
Kojto 102:da0ca467f8b5 325 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 102:da0ca467f8b5 326 */
Kojto 102:da0ca467f8b5 327 typedef union
Kojto 102:da0ca467f8b5 328 {
Kojto 102:da0ca467f8b5 329 struct
Kojto 102:da0ca467f8b5 330 {
Kojto 102:da0ca467f8b5 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 102:da0ca467f8b5 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 102:da0ca467f8b5 334 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 335 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 336 } CONTROL_Type;
Kojto 102:da0ca467f8b5 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
Kojto 102:da0ca467f8b5 345 /*@} end of group CMSIS_CORE */
Kojto 102:da0ca467f8b5 346
Kojto 102:da0ca467f8b5 347
Kojto 102:da0ca467f8b5 348 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 102:da0ca467f8b5 350 \brief Type definitions for the NVIC Registers
Kojto 102:da0ca467f8b5 351 @{
Kojto 102:da0ca467f8b5 352 */
Kojto 102:da0ca467f8b5 353
Kojto 102:da0ca467f8b5 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 102:da0ca467f8b5 355 */
Kojto 102:da0ca467f8b5 356 typedef struct
Kojto 102:da0ca467f8b5 357 {
Kojto 102:da0ca467f8b5 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 102:da0ca467f8b5 359 uint32_t RESERVED0[31];
Kojto 102:da0ca467f8b5 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 102:da0ca467f8b5 361 uint32_t RSERVED1[31];
Kojto 102:da0ca467f8b5 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 102:da0ca467f8b5 363 uint32_t RESERVED2[31];
Kojto 102:da0ca467f8b5 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 102:da0ca467f8b5 365 uint32_t RESERVED3[31];
Kojto 102:da0ca467f8b5 366 uint32_t RESERVED4[64];
Kojto 102:da0ca467f8b5 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 102:da0ca467f8b5 368 } NVIC_Type;
Kojto 102:da0ca467f8b5 369
Kojto 102:da0ca467f8b5 370 /*@} end of group CMSIS_NVIC */
Kojto 102:da0ca467f8b5 371
Kojto 102:da0ca467f8b5 372
Kojto 102:da0ca467f8b5 373 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 374 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 102:da0ca467f8b5 375 \brief Type definitions for the System Control Block Registers
Kojto 102:da0ca467f8b5 376 @{
Kojto 102:da0ca467f8b5 377 */
Kojto 102:da0ca467f8b5 378
Kojto 102:da0ca467f8b5 379 /** \brief Structure type to access the System Control Block (SCB).
Kojto 102:da0ca467f8b5 380 */
Kojto 102:da0ca467f8b5 381 typedef struct
Kojto 102:da0ca467f8b5 382 {
Kojto 102:da0ca467f8b5 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 102:da0ca467f8b5 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 102:da0ca467f8b5 385 #if (__VTOR_PRESENT == 1)
Kojto 102:da0ca467f8b5 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 102:da0ca467f8b5 387 #else
Kojto 102:da0ca467f8b5 388 uint32_t RESERVED0;
Kojto 102:da0ca467f8b5 389 #endif
Kojto 102:da0ca467f8b5 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 102:da0ca467f8b5 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 102:da0ca467f8b5 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 102:da0ca467f8b5 393 uint32_t RESERVED1;
Kojto 102:da0ca467f8b5 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 102:da0ca467f8b5 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 102:da0ca467f8b5 396 } SCB_Type;
Kojto 102:da0ca467f8b5 397
Kojto 102:da0ca467f8b5 398 /* SCB CPUID Register Definitions */
Kojto 102:da0ca467f8b5 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 102:da0ca467f8b5 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 102:da0ca467f8b5 401
Kojto 102:da0ca467f8b5 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 102:da0ca467f8b5 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 102:da0ca467f8b5 404
Kojto 102:da0ca467f8b5 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 102:da0ca467f8b5 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 102:da0ca467f8b5 407
Kojto 102:da0ca467f8b5 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 102:da0ca467f8b5 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 102:da0ca467f8b5 410
Kojto 102:da0ca467f8b5 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 102:da0ca467f8b5 413
Kojto 102:da0ca467f8b5 414 /* SCB Interrupt Control State Register Definitions */
Kojto 102:da0ca467f8b5 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 102:da0ca467f8b5 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 102:da0ca467f8b5 417
Kojto 102:da0ca467f8b5 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 102:da0ca467f8b5 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 102:da0ca467f8b5 420
Kojto 102:da0ca467f8b5 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 102:da0ca467f8b5 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 102:da0ca467f8b5 423
Kojto 102:da0ca467f8b5 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 102:da0ca467f8b5 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 102:da0ca467f8b5 426
Kojto 102:da0ca467f8b5 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 102:da0ca467f8b5 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 102:da0ca467f8b5 429
Kojto 102:da0ca467f8b5 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 102:da0ca467f8b5 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 102:da0ca467f8b5 432
Kojto 102:da0ca467f8b5 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 102:da0ca467f8b5 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 102:da0ca467f8b5 435
Kojto 102:da0ca467f8b5 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 102:da0ca467f8b5 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 102:da0ca467f8b5 438
Kojto 102:da0ca467f8b5 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 102:da0ca467f8b5 441
Kojto 102:da0ca467f8b5 442 #if (__VTOR_PRESENT == 1)
Kojto 102:da0ca467f8b5 443 /* SCB Interrupt Control State Register Definitions */
Kojto 102:da0ca467f8b5 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 102:da0ca467f8b5 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 102:da0ca467f8b5 446 #endif
Kojto 102:da0ca467f8b5 447
Kojto 102:da0ca467f8b5 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 102:da0ca467f8b5 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 102:da0ca467f8b5 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 102:da0ca467f8b5 451
Kojto 102:da0ca467f8b5 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 102:da0ca467f8b5 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 102:da0ca467f8b5 454
Kojto 102:da0ca467f8b5 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 102:da0ca467f8b5 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 102:da0ca467f8b5 457
Kojto 102:da0ca467f8b5 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 102:da0ca467f8b5 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 102:da0ca467f8b5 460
Kojto 102:da0ca467f8b5 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 102:da0ca467f8b5 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 102:da0ca467f8b5 463
Kojto 102:da0ca467f8b5 464 /* SCB System Control Register Definitions */
Kojto 102:da0ca467f8b5 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 102:da0ca467f8b5 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 102:da0ca467f8b5 467
Kojto 102:da0ca467f8b5 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 102:da0ca467f8b5 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 102:da0ca467f8b5 470
Kojto 102:da0ca467f8b5 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 102:da0ca467f8b5 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 102:da0ca467f8b5 473
Kojto 102:da0ca467f8b5 474 /* SCB Configuration Control Register Definitions */
Kojto 102:da0ca467f8b5 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 102:da0ca467f8b5 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 102:da0ca467f8b5 477
Kojto 102:da0ca467f8b5 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 102:da0ca467f8b5 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 102:da0ca467f8b5 480
Kojto 102:da0ca467f8b5 481 /* SCB System Handler Control and State Register Definitions */
Kojto 102:da0ca467f8b5 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 102:da0ca467f8b5 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 102:da0ca467f8b5 484
Kojto 102:da0ca467f8b5 485 /*@} end of group CMSIS_SCB */
Kojto 102:da0ca467f8b5 486
Kojto 102:da0ca467f8b5 487
Kojto 102:da0ca467f8b5 488 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 102:da0ca467f8b5 490 \brief Type definitions for the System Timer Registers.
Kojto 102:da0ca467f8b5 491 @{
Kojto 102:da0ca467f8b5 492 */
Kojto 102:da0ca467f8b5 493
Kojto 102:da0ca467f8b5 494 /** \brief Structure type to access the System Timer (SysTick).
Kojto 102:da0ca467f8b5 495 */
Kojto 102:da0ca467f8b5 496 typedef struct
Kojto 102:da0ca467f8b5 497 {
Kojto 102:da0ca467f8b5 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 102:da0ca467f8b5 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 102:da0ca467f8b5 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 102:da0ca467f8b5 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 102:da0ca467f8b5 502 } SysTick_Type;
Kojto 102:da0ca467f8b5 503
Kojto 102:da0ca467f8b5 504 /* SysTick Control / Status Register Definitions */
Kojto 102:da0ca467f8b5 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 102:da0ca467f8b5 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 102:da0ca467f8b5 507
Kojto 102:da0ca467f8b5 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 102:da0ca467f8b5 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 102:da0ca467f8b5 510
Kojto 102:da0ca467f8b5 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 102:da0ca467f8b5 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 102:da0ca467f8b5 513
Kojto 102:da0ca467f8b5 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 102:da0ca467f8b5 516
Kojto 102:da0ca467f8b5 517 /* SysTick Reload Register Definitions */
Kojto 102:da0ca467f8b5 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 102:da0ca467f8b5 520
Kojto 102:da0ca467f8b5 521 /* SysTick Current Register Definitions */
Kojto 102:da0ca467f8b5 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 102:da0ca467f8b5 524
Kojto 102:da0ca467f8b5 525 /* SysTick Calibration Register Definitions */
Kojto 102:da0ca467f8b5 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 102:da0ca467f8b5 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 102:da0ca467f8b5 528
Kojto 102:da0ca467f8b5 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 102:da0ca467f8b5 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 102:da0ca467f8b5 531
Kojto 102:da0ca467f8b5 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 102:da0ca467f8b5 534
Kojto 102:da0ca467f8b5 535 /*@} end of group CMSIS_SysTick */
Kojto 102:da0ca467f8b5 536
Kojto 102:da0ca467f8b5 537 #if (__MPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 538 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 102:da0ca467f8b5 540 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 102:da0ca467f8b5 541 @{
Kojto 102:da0ca467f8b5 542 */
Kojto 102:da0ca467f8b5 543
Kojto 102:da0ca467f8b5 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 102:da0ca467f8b5 545 */
Kojto 102:da0ca467f8b5 546 typedef struct
Kojto 102:da0ca467f8b5 547 {
Kojto 102:da0ca467f8b5 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 102:da0ca467f8b5 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 102:da0ca467f8b5 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 102:da0ca467f8b5 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 102:da0ca467f8b5 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 553 } MPU_Type;
Kojto 102:da0ca467f8b5 554
Kojto 102:da0ca467f8b5 555 /* MPU Type Register */
Kojto 102:da0ca467f8b5 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 102:da0ca467f8b5 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 102:da0ca467f8b5 558
Kojto 102:da0ca467f8b5 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 102:da0ca467f8b5 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 102:da0ca467f8b5 561
Kojto 102:da0ca467f8b5 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 102:da0ca467f8b5 564
Kojto 102:da0ca467f8b5 565 /* MPU Control Register */
Kojto 102:da0ca467f8b5 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 102:da0ca467f8b5 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 102:da0ca467f8b5 568
Kojto 102:da0ca467f8b5 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 102:da0ca467f8b5 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 102:da0ca467f8b5 571
Kojto 102:da0ca467f8b5 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 102:da0ca467f8b5 574
Kojto 102:da0ca467f8b5 575 /* MPU Region Number Register */
Kojto 102:da0ca467f8b5 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 102:da0ca467f8b5 578
Kojto 102:da0ca467f8b5 579 /* MPU Region Base Address Register */
Kojto 102:da0ca467f8b5 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 102:da0ca467f8b5 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 102:da0ca467f8b5 582
Kojto 102:da0ca467f8b5 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 102:da0ca467f8b5 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 102:da0ca467f8b5 585
Kojto 102:da0ca467f8b5 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 102:da0ca467f8b5 588
Kojto 102:da0ca467f8b5 589 /* MPU Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 102:da0ca467f8b5 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 102:da0ca467f8b5 592
Kojto 102:da0ca467f8b5 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 102:da0ca467f8b5 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 102:da0ca467f8b5 595
Kojto 102:da0ca467f8b5 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 102:da0ca467f8b5 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 102:da0ca467f8b5 598
Kojto 102:da0ca467f8b5 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 102:da0ca467f8b5 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 102:da0ca467f8b5 601
Kojto 102:da0ca467f8b5 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 102:da0ca467f8b5 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 102:da0ca467f8b5 604
Kojto 102:da0ca467f8b5 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 102:da0ca467f8b5 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 102:da0ca467f8b5 607
Kojto 102:da0ca467f8b5 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 102:da0ca467f8b5 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 102:da0ca467f8b5 610
Kojto 102:da0ca467f8b5 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 102:da0ca467f8b5 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 102:da0ca467f8b5 613
Kojto 102:da0ca467f8b5 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 102:da0ca467f8b5 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 102:da0ca467f8b5 616
Kojto 102:da0ca467f8b5 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 102:da0ca467f8b5 619
Kojto 102:da0ca467f8b5 620 /*@} end of group CMSIS_MPU */
Kojto 102:da0ca467f8b5 621 #endif
Kojto 102:da0ca467f8b5 622
Kojto 102:da0ca467f8b5 623
Kojto 102:da0ca467f8b5 624 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 102:da0ca467f8b5 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 102:da0ca467f8b5 627 are only accessible over DAP and not via processor. Therefore
Kojto 102:da0ca467f8b5 628 they are not covered by the Cortex-M0 header file.
Kojto 102:da0ca467f8b5 629 @{
Kojto 102:da0ca467f8b5 630 */
Kojto 102:da0ca467f8b5 631 /*@} end of group CMSIS_CoreDebug */
Kojto 102:da0ca467f8b5 632
Kojto 102:da0ca467f8b5 633
Kojto 102:da0ca467f8b5 634 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 635 \defgroup CMSIS_core_base Core Definitions
Kojto 102:da0ca467f8b5 636 \brief Definitions for base addresses, unions, and structures.
Kojto 102:da0ca467f8b5 637 @{
Kojto 102:da0ca467f8b5 638 */
Kojto 102:da0ca467f8b5 639
Kojto 102:da0ca467f8b5 640 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 102:da0ca467f8b5 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 102:da0ca467f8b5 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 102:da0ca467f8b5 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 102:da0ca467f8b5 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 102:da0ca467f8b5 645
Kojto 102:da0ca467f8b5 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 102:da0ca467f8b5 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 102:da0ca467f8b5 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 102:da0ca467f8b5 649
Kojto 102:da0ca467f8b5 650 #if (__MPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 102:da0ca467f8b5 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 102:da0ca467f8b5 653 #endif
Kojto 102:da0ca467f8b5 654
Kojto 102:da0ca467f8b5 655 /*@} */
Kojto 102:da0ca467f8b5 656
Kojto 102:da0ca467f8b5 657
Kojto 102:da0ca467f8b5 658
Kojto 102:da0ca467f8b5 659 /*******************************************************************************
Kojto 102:da0ca467f8b5 660 * Hardware Abstraction Layer
Kojto 102:da0ca467f8b5 661 Core Function Interface contains:
Kojto 102:da0ca467f8b5 662 - Core NVIC Functions
Kojto 102:da0ca467f8b5 663 - Core SysTick Functions
Kojto 102:da0ca467f8b5 664 - Core Register Access Functions
Kojto 102:da0ca467f8b5 665 ******************************************************************************/
Kojto 102:da0ca467f8b5 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 102:da0ca467f8b5 667 */
Kojto 102:da0ca467f8b5 668
Kojto 102:da0ca467f8b5 669
Kojto 102:da0ca467f8b5 670
Kojto 102:da0ca467f8b5 671 /* ########################## NVIC functions #################################### */
Kojto 102:da0ca467f8b5 672 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 102:da0ca467f8b5 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 102:da0ca467f8b5 675 @{
Kojto 102:da0ca467f8b5 676 */
Kojto 102:da0ca467f8b5 677
Kojto 102:da0ca467f8b5 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 102:da0ca467f8b5 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 102:da0ca467f8b5 683
Kojto 102:da0ca467f8b5 684
Kojto 102:da0ca467f8b5 685 /** \brief Enable External Interrupt
Kojto 102:da0ca467f8b5 686
Kojto 102:da0ca467f8b5 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 102:da0ca467f8b5 688
Kojto 102:da0ca467f8b5 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 690 */
Kojto 102:da0ca467f8b5 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 694 }
Kojto 102:da0ca467f8b5 695
Kojto 102:da0ca467f8b5 696
Kojto 102:da0ca467f8b5 697 /** \brief Disable External Interrupt
Kojto 102:da0ca467f8b5 698
Kojto 102:da0ca467f8b5 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 102:da0ca467f8b5 700
Kojto 102:da0ca467f8b5 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 702 */
Kojto 102:da0ca467f8b5 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
Kojto 102:da0ca467f8b5 708 }
Kojto 102:da0ca467f8b5 709
Kojto 102:da0ca467f8b5 710
Kojto 102:da0ca467f8b5 711 /** \brief Get Pending Interrupt
Kojto 102:da0ca467f8b5 712
Kojto 102:da0ca467f8b5 713 The function reads the pending register in the NVIC and returns the pending bit
Kojto 102:da0ca467f8b5 714 for the specified interrupt.
Kojto 102:da0ca467f8b5 715
Kojto 102:da0ca467f8b5 716 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 717
Kojto 102:da0ca467f8b5 718 \return 0 Interrupt status is not pending.
Kojto 102:da0ca467f8b5 719 \return 1 Interrupt status is pending.
Kojto 102:da0ca467f8b5 720 */
Kojto 102:da0ca467f8b5 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 102:da0ca467f8b5 724 }
Kojto 102:da0ca467f8b5 725
Kojto 102:da0ca467f8b5 726
Kojto 102:da0ca467f8b5 727 /** \brief Set Pending Interrupt
Kojto 102:da0ca467f8b5 728
Kojto 102:da0ca467f8b5 729 The function sets the pending bit of an external interrupt.
Kojto 102:da0ca467f8b5 730
Kojto 102:da0ca467f8b5 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 732 */
Kojto 102:da0ca467f8b5 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 736 }
Kojto 102:da0ca467f8b5 737
Kojto 102:da0ca467f8b5 738
Kojto 102:da0ca467f8b5 739 /** \brief Clear Pending Interrupt
Kojto 102:da0ca467f8b5 740
Kojto 102:da0ca467f8b5 741 The function clears the pending bit of an external interrupt.
Kojto 102:da0ca467f8b5 742
Kojto 102:da0ca467f8b5 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 744 */
Kojto 102:da0ca467f8b5 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 102:da0ca467f8b5 748 }
Kojto 102:da0ca467f8b5 749
Kojto 102:da0ca467f8b5 750
Kojto 102:da0ca467f8b5 751 /** \brief Set Interrupt Priority
Kojto 102:da0ca467f8b5 752
Kojto 102:da0ca467f8b5 753 The function sets the priority of an interrupt.
Kojto 102:da0ca467f8b5 754
Kojto 102:da0ca467f8b5 755 \note The priority cannot be set for every core interrupt.
Kojto 102:da0ca467f8b5 756
Kojto 102:da0ca467f8b5 757 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 758 \param [in] priority Priority to set.
Kojto 102:da0ca467f8b5 759 */
Kojto 102:da0ca467f8b5 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 102:da0ca467f8b5 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
Kojto 102:da0ca467f8b5 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
Kojto 102:da0ca467f8b5 770 }
Kojto 102:da0ca467f8b5 771
Kojto 102:da0ca467f8b5 772
Kojto 102:da0ca467f8b5 773 /** \brief Get Interrupt Priority
Kojto 102:da0ca467f8b5 774
Kojto 102:da0ca467f8b5 775 The function reads the priority of an interrupt. The interrupt
Kojto 102:da0ca467f8b5 776 number can be positive to specify an external (device specific)
Kojto 102:da0ca467f8b5 777 interrupt, or negative to specify an internal (core) interrupt.
Kojto 102:da0ca467f8b5 778
Kojto 102:da0ca467f8b5 779
Kojto 102:da0ca467f8b5 780 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 102:da0ca467f8b5 782 priority bits of the microcontroller.
Kojto 102:da0ca467f8b5 783 */
Kojto 102:da0ca467f8b5 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 785 {
Kojto 102:da0ca467f8b5 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
Kojto 102:da0ca467f8b5 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
Kojto 102:da0ca467f8b5 793 }
Kojto 102:da0ca467f8b5 794
Kojto 102:da0ca467f8b5 795
Kojto 102:da0ca467f8b5 796 /** \brief System Reset
Kojto 102:da0ca467f8b5 797
Kojto 102:da0ca467f8b5 798 The function initiates a system reset request to reset the MCU.
Kojto 102:da0ca467f8b5 799 */
Kojto 102:da0ca467f8b5 800 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 102:da0ca467f8b5 801 {
Kojto 102:da0ca467f8b5 802 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 102:da0ca467f8b5 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 102:da0ca467f8b5 805 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 102:da0ca467f8b5 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
Kojto 102:da0ca467f8b5 808 }
Kojto 102:da0ca467f8b5 809
Kojto 102:da0ca467f8b5 810 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 102:da0ca467f8b5 811
Kojto 102:da0ca467f8b5 812
Kojto 102:da0ca467f8b5 813
Kojto 102:da0ca467f8b5 814 /* ################################## SysTick function ############################################ */
Kojto 102:da0ca467f8b5 815 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 102:da0ca467f8b5 817 \brief Functions that configure the System.
Kojto 102:da0ca467f8b5 818 @{
Kojto 102:da0ca467f8b5 819 */
Kojto 102:da0ca467f8b5 820
Kojto 102:da0ca467f8b5 821 #if (__Vendor_SysTickConfig == 0)
Kojto 102:da0ca467f8b5 822
Kojto 102:da0ca467f8b5 823 /** \brief System Tick Configuration
Kojto 102:da0ca467f8b5 824
Kojto 102:da0ca467f8b5 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 102:da0ca467f8b5 826 Counter is in free running mode to generate periodic interrupts.
Kojto 102:da0ca467f8b5 827
Kojto 102:da0ca467f8b5 828 \param [in] ticks Number of ticks between two interrupts.
Kojto 102:da0ca467f8b5 829
Kojto 102:da0ca467f8b5 830 \return 0 Function succeeded.
Kojto 102:da0ca467f8b5 831 \return 1 Function failed.
Kojto 102:da0ca467f8b5 832
Kojto 102:da0ca467f8b5 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 102:da0ca467f8b5 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 102:da0ca467f8b5 835 must contain a vendor-specific implementation of this function.
Kojto 102:da0ca467f8b5 836
Kojto 102:da0ca467f8b5 837 */
Kojto 102:da0ca467f8b5 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 102:da0ca467f8b5 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 102:da0ca467f8b5 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 102:da0ca467f8b5 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 102:da0ca467f8b5 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
Kojto 102:da0ca467f8b5 849 }
Kojto 102:da0ca467f8b5 850
Kojto 102:da0ca467f8b5 851 #endif
Kojto 102:da0ca467f8b5 852
Kojto 102:da0ca467f8b5 853 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 102:da0ca467f8b5 854
Kojto 102:da0ca467f8b5 855
Kojto 102:da0ca467f8b5 856
Kojto 102:da0ca467f8b5 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
Kojto 102:da0ca467f8b5 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 102:da0ca467f8b5 863
Kojto 102:da0ca467f8b5 864 #endif /* __CMSIS_GENERIC */