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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_MPS2_M7/core_cm0plus.h@102:da0ca467f8b5, 2015-07-08 (annotated)

Committer:
Kojto
Date:
Wed Jul 08 11:22:30 2015 +0100
Revision:
102:da0ca467f8b5
Child:
110:165afa46840b
Release 102 of the mbed library



Changes:

- new platform: MPS2

- K64f - mac address fix

- Freescale Kinetis - Serial NC handling fix

- Asynch constnes fixes

- startup files .s - change extension to .S

- APPNEARME_MICRONFCBOARD rename to MICRONFCBOARD

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 102:da0ca467f8b5 1 /**************************************************************************//**
Kojto 102:da0ca467f8b5 2 * @file core_cm0plus.h
Kojto 102:da0ca467f8b5 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 102:da0ca467f8b5 4 * @version V3.20
Kojto 102:da0ca467f8b5 5 * @date 25. February 2013
Kojto 102:da0ca467f8b5 6 *
Kojto 102:da0ca467f8b5 7 * @note
Kojto 102:da0ca467f8b5 8 *
Kojto 102:da0ca467f8b5 9 ******************************************************************************/
Kojto 102:da0ca467f8b5 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 102:da0ca467f8b5 11
Kojto 102:da0ca467f8b5 12 All rights reserved.
Kojto 102:da0ca467f8b5 13 Redistribution and use in source and binary forms, with or without
Kojto 102:da0ca467f8b5 14 modification, are permitted provided that the following conditions are met:
Kojto 102:da0ca467f8b5 15 - Redistributions of source code must retain the above copyright
Kojto 102:da0ca467f8b5 16 notice, this list of conditions and the following disclaimer.
Kojto 102:da0ca467f8b5 17 - Redistributions in binary form must reproduce the above copyright
Kojto 102:da0ca467f8b5 18 notice, this list of conditions and the following disclaimer in the
Kojto 102:da0ca467f8b5 19 documentation and/or other materials provided with the distribution.
Kojto 102:da0ca467f8b5 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 102:da0ca467f8b5 21 to endorse or promote products derived from this software without
Kojto 102:da0ca467f8b5 22 specific prior written permission.
Kojto 102:da0ca467f8b5 23 *
Kojto 102:da0ca467f8b5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 102:da0ca467f8b5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 102:da0ca467f8b5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 102:da0ca467f8b5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 102:da0ca467f8b5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 102:da0ca467f8b5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 102:da0ca467f8b5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 102:da0ca467f8b5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 102:da0ca467f8b5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 102:da0ca467f8b5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 102:da0ca467f8b5 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 102:da0ca467f8b5 35 ---------------------------------------------------------------------------*/
Kojto 102:da0ca467f8b5 36
Kojto 102:da0ca467f8b5 37
Kojto 102:da0ca467f8b5 38 #if defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 102:da0ca467f8b5 40 #endif
Kojto 102:da0ca467f8b5 41
Kojto 102:da0ca467f8b5 42 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 43 extern "C" {
Kojto 102:da0ca467f8b5 44 #endif
Kojto 102:da0ca467f8b5 45
Kojto 102:da0ca467f8b5 46 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 102:da0ca467f8b5 47 #define __CORE_CM0PLUS_H_GENERIC
Kojto 102:da0ca467f8b5 48
Kojto 102:da0ca467f8b5 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 102:da0ca467f8b5 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 102:da0ca467f8b5 51
Kojto 102:da0ca467f8b5 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 102:da0ca467f8b5 53 Function definitions in header files are used to allow 'inlining'.
Kojto 102:da0ca467f8b5 54
Kojto 102:da0ca467f8b5 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 102:da0ca467f8b5 56 Unions are used for effective representation of core registers.
Kojto 102:da0ca467f8b5 57
Kojto 102:da0ca467f8b5 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 102:da0ca467f8b5 59 Function-like macros are used to allow more efficient code.
Kojto 102:da0ca467f8b5 60 */
Kojto 102:da0ca467f8b5 61
Kojto 102:da0ca467f8b5 62
Kojto 102:da0ca467f8b5 63 /*******************************************************************************
Kojto 102:da0ca467f8b5 64 * CMSIS definitions
Kojto 102:da0ca467f8b5 65 ******************************************************************************/
Kojto 102:da0ca467f8b5 66 /** \ingroup Cortex-M0+
Kojto 102:da0ca467f8b5 67 @{
Kojto 102:da0ca467f8b5 68 */
Kojto 102:da0ca467f8b5 69
Kojto 102:da0ca467f8b5 70 /* CMSIS CM0P definitions */
Kojto 102:da0ca467f8b5 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 102:da0ca467f8b5 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 102:da0ca467f8b5 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 102:da0ca467f8b5 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 102:da0ca467f8b5 75
Kojto 102:da0ca467f8b5 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 102:da0ca467f8b5 77
Kojto 102:da0ca467f8b5 78
Kojto 102:da0ca467f8b5 79 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 102:da0ca467f8b5 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 102:da0ca467f8b5 82 #define __STATIC_INLINE static __inline
Kojto 102:da0ca467f8b5 83
Kojto 102:da0ca467f8b5 84 #elif defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 102:da0ca467f8b5 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 102:da0ca467f8b5 87 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 88
Kojto 102:da0ca467f8b5 89 #elif defined ( __GNUC__ )
Kojto 102:da0ca467f8b5 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 102:da0ca467f8b5 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 102:da0ca467f8b5 92 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 93
Kojto 102:da0ca467f8b5 94 #elif defined ( __TASKING__ )
Kojto 102:da0ca467f8b5 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 102:da0ca467f8b5 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 102:da0ca467f8b5 97 #define __STATIC_INLINE static inline
Kojto 102:da0ca467f8b5 98
Kojto 102:da0ca467f8b5 99 #endif
Kojto 102:da0ca467f8b5 100
Kojto 102:da0ca467f8b5 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 102:da0ca467f8b5 102 */
Kojto 102:da0ca467f8b5 103 #define __FPU_USED 0
Kojto 102:da0ca467f8b5 104
Kojto 102:da0ca467f8b5 105 #if defined ( __CC_ARM )
Kojto 102:da0ca467f8b5 106 #if defined __TARGET_FPU_VFP
Kojto 102:da0ca467f8b5 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 108 #endif
Kojto 102:da0ca467f8b5 109
Kojto 102:da0ca467f8b5 110 #elif defined ( __ICCARM__ )
Kojto 102:da0ca467f8b5 111 #if defined __ARMVFP__
Kojto 102:da0ca467f8b5 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 113 #endif
Kojto 102:da0ca467f8b5 114
Kojto 102:da0ca467f8b5 115 #elif defined ( __GNUC__ )
Kojto 102:da0ca467f8b5 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 102:da0ca467f8b5 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 118 #endif
Kojto 102:da0ca467f8b5 119
Kojto 102:da0ca467f8b5 120 #elif defined ( __TASKING__ )
Kojto 102:da0ca467f8b5 121 #if defined __FPU_VFP__
Kojto 102:da0ca467f8b5 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 102:da0ca467f8b5 123 #endif
Kojto 102:da0ca467f8b5 124 #endif
Kojto 102:da0ca467f8b5 125
Kojto 102:da0ca467f8b5 126 #include <stdint.h> /* standard types definitions */
Kojto 102:da0ca467f8b5 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 102:da0ca467f8b5 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 102:da0ca467f8b5 129
Kojto 102:da0ca467f8b5 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 102:da0ca467f8b5 131
Kojto 102:da0ca467f8b5 132 #ifndef __CMSIS_GENERIC
Kojto 102:da0ca467f8b5 133
Kojto 102:da0ca467f8b5 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 102:da0ca467f8b5 135 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 102:da0ca467f8b5 136
Kojto 102:da0ca467f8b5 137 /* check device defines and use defaults */
Kojto 102:da0ca467f8b5 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 102:da0ca467f8b5 139 #ifndef __CM0PLUS_REV
Kojto 102:da0ca467f8b5 140 #define __CM0PLUS_REV 0x0000
Kojto 102:da0ca467f8b5 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 142 #endif
Kojto 102:da0ca467f8b5 143
Kojto 102:da0ca467f8b5 144 #ifndef __MPU_PRESENT
Kojto 102:da0ca467f8b5 145 #define __MPU_PRESENT 0
Kojto 102:da0ca467f8b5 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 147 #endif
Kojto 102:da0ca467f8b5 148
Kojto 102:da0ca467f8b5 149 #ifndef __VTOR_PRESENT
Kojto 102:da0ca467f8b5 150 #define __VTOR_PRESENT 0
Kojto 102:da0ca467f8b5 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 152 #endif
Kojto 102:da0ca467f8b5 153
Kojto 102:da0ca467f8b5 154 #ifndef __NVIC_PRIO_BITS
Kojto 102:da0ca467f8b5 155 #define __NVIC_PRIO_BITS 2
Kojto 102:da0ca467f8b5 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 157 #endif
Kojto 102:da0ca467f8b5 158
Kojto 102:da0ca467f8b5 159 #ifndef __Vendor_SysTickConfig
Kojto 102:da0ca467f8b5 160 #define __Vendor_SysTickConfig 0
Kojto 102:da0ca467f8b5 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 102:da0ca467f8b5 162 #endif
Kojto 102:da0ca467f8b5 163 #endif
Kojto 102:da0ca467f8b5 164
Kojto 102:da0ca467f8b5 165 /* IO definitions (access restrictions to peripheral registers) */
Kojto 102:da0ca467f8b5 166 /**
Kojto 102:da0ca467f8b5 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 102:da0ca467f8b5 168
Kojto 102:da0ca467f8b5 169 <strong>IO Type Qualifiers</strong> are used
Kojto 102:da0ca467f8b5 170 \li to specify the access to peripheral variables.
Kojto 102:da0ca467f8b5 171 \li for automatic generation of peripheral register debug information.
Kojto 102:da0ca467f8b5 172 */
Kojto 102:da0ca467f8b5 173 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 174 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 102:da0ca467f8b5 175 #else
Kojto 102:da0ca467f8b5 176 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 102:da0ca467f8b5 177 #endif
Kojto 102:da0ca467f8b5 178 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 102:da0ca467f8b5 179 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 102:da0ca467f8b5 180
Kojto 102:da0ca467f8b5 181 /*@} end of group Cortex-M0+ */
Kojto 102:da0ca467f8b5 182
Kojto 102:da0ca467f8b5 183
Kojto 102:da0ca467f8b5 184
Kojto 102:da0ca467f8b5 185 /*******************************************************************************
Kojto 102:da0ca467f8b5 186 * Register Abstraction
Kojto 102:da0ca467f8b5 187 Core Register contain:
Kojto 102:da0ca467f8b5 188 - Core Register
Kojto 102:da0ca467f8b5 189 - Core NVIC Register
Kojto 102:da0ca467f8b5 190 - Core SCB Register
Kojto 102:da0ca467f8b5 191 - Core SysTick Register
Kojto 102:da0ca467f8b5 192 - Core MPU Register
Kojto 102:da0ca467f8b5 193 ******************************************************************************/
Kojto 102:da0ca467f8b5 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 102:da0ca467f8b5 195 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 102:da0ca467f8b5 196 */
Kojto 102:da0ca467f8b5 197
Kojto 102:da0ca467f8b5 198 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 199 \defgroup CMSIS_CORE Status and Control Registers
Kojto 102:da0ca467f8b5 200 \brief Core Register type definitions.
Kojto 102:da0ca467f8b5 201 @{
Kojto 102:da0ca467f8b5 202 */
Kojto 102:da0ca467f8b5 203
Kojto 102:da0ca467f8b5 204 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 102:da0ca467f8b5 205 */
Kojto 102:da0ca467f8b5 206 typedef union
Kojto 102:da0ca467f8b5 207 {
Kojto 102:da0ca467f8b5 208 struct
Kojto 102:da0ca467f8b5 209 {
Kojto 102:da0ca467f8b5 210 #if (__CORTEX_M != 0x04)
Kojto 102:da0ca467f8b5 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 102:da0ca467f8b5 212 #else
Kojto 102:da0ca467f8b5 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 102:da0ca467f8b5 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 102:da0ca467f8b5 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 102:da0ca467f8b5 216 #endif
Kojto 102:da0ca467f8b5 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 102:da0ca467f8b5 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 102:da0ca467f8b5 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 102:da0ca467f8b5 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 102:da0ca467f8b5 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 102:da0ca467f8b5 222 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 223 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 224 } APSR_Type;
Kojto 102:da0ca467f8b5 225
Kojto 102:da0ca467f8b5 226
Kojto 102:da0ca467f8b5 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 102:da0ca467f8b5 228 */
Kojto 102:da0ca467f8b5 229 typedef union
Kojto 102:da0ca467f8b5 230 {
Kojto 102:da0ca467f8b5 231 struct
Kojto 102:da0ca467f8b5 232 {
Kojto 102:da0ca467f8b5 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 102:da0ca467f8b5 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 102:da0ca467f8b5 235 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 236 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 237 } IPSR_Type;
Kojto 102:da0ca467f8b5 238
Kojto 102:da0ca467f8b5 239
Kojto 102:da0ca467f8b5 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 102:da0ca467f8b5 241 */
Kojto 102:da0ca467f8b5 242 typedef union
Kojto 102:da0ca467f8b5 243 {
Kojto 102:da0ca467f8b5 244 struct
Kojto 102:da0ca467f8b5 245 {
Kojto 102:da0ca467f8b5 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 102:da0ca467f8b5 247 #if (__CORTEX_M != 0x04)
Kojto 102:da0ca467f8b5 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 102:da0ca467f8b5 249 #else
Kojto 102:da0ca467f8b5 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 102:da0ca467f8b5 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 102:da0ca467f8b5 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 102:da0ca467f8b5 253 #endif
Kojto 102:da0ca467f8b5 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 102:da0ca467f8b5 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 102:da0ca467f8b5 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 102:da0ca467f8b5 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 102:da0ca467f8b5 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 102:da0ca467f8b5 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 102:da0ca467f8b5 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 102:da0ca467f8b5 261 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 262 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 263 } xPSR_Type;
Kojto 102:da0ca467f8b5 264
Kojto 102:da0ca467f8b5 265
Kojto 102:da0ca467f8b5 266 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 102:da0ca467f8b5 267 */
Kojto 102:da0ca467f8b5 268 typedef union
Kojto 102:da0ca467f8b5 269 {
Kojto 102:da0ca467f8b5 270 struct
Kojto 102:da0ca467f8b5 271 {
Kojto 102:da0ca467f8b5 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 102:da0ca467f8b5 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 102:da0ca467f8b5 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 102:da0ca467f8b5 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 102:da0ca467f8b5 276 } b; /*!< Structure used for bit access */
Kojto 102:da0ca467f8b5 277 uint32_t w; /*!< Type used for word access */
Kojto 102:da0ca467f8b5 278 } CONTROL_Type;
Kojto 102:da0ca467f8b5 279
Kojto 102:da0ca467f8b5 280 /*@} end of group CMSIS_CORE */
Kojto 102:da0ca467f8b5 281
Kojto 102:da0ca467f8b5 282
Kojto 102:da0ca467f8b5 283 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 102:da0ca467f8b5 285 \brief Type definitions for the NVIC Registers
Kojto 102:da0ca467f8b5 286 @{
Kojto 102:da0ca467f8b5 287 */
Kojto 102:da0ca467f8b5 288
Kojto 102:da0ca467f8b5 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 102:da0ca467f8b5 290 */
Kojto 102:da0ca467f8b5 291 typedef struct
Kojto 102:da0ca467f8b5 292 {
Kojto 102:da0ca467f8b5 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 102:da0ca467f8b5 294 uint32_t RESERVED0[31];
Kojto 102:da0ca467f8b5 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 102:da0ca467f8b5 296 uint32_t RSERVED1[31];
Kojto 102:da0ca467f8b5 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 102:da0ca467f8b5 298 uint32_t RESERVED2[31];
Kojto 102:da0ca467f8b5 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 102:da0ca467f8b5 300 uint32_t RESERVED3[31];
Kojto 102:da0ca467f8b5 301 uint32_t RESERVED4[64];
Kojto 102:da0ca467f8b5 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 102:da0ca467f8b5 303 } NVIC_Type;
Kojto 102:da0ca467f8b5 304
Kojto 102:da0ca467f8b5 305 /*@} end of group CMSIS_NVIC */
Kojto 102:da0ca467f8b5 306
Kojto 102:da0ca467f8b5 307
Kojto 102:da0ca467f8b5 308 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 309 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 102:da0ca467f8b5 310 \brief Type definitions for the System Control Block Registers
Kojto 102:da0ca467f8b5 311 @{
Kojto 102:da0ca467f8b5 312 */
Kojto 102:da0ca467f8b5 313
Kojto 102:da0ca467f8b5 314 /** \brief Structure type to access the System Control Block (SCB).
Kojto 102:da0ca467f8b5 315 */
Kojto 102:da0ca467f8b5 316 typedef struct
Kojto 102:da0ca467f8b5 317 {
Kojto 102:da0ca467f8b5 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 102:da0ca467f8b5 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 102:da0ca467f8b5 320 #if (__VTOR_PRESENT == 1)
Kojto 102:da0ca467f8b5 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 102:da0ca467f8b5 322 #else
Kojto 102:da0ca467f8b5 323 uint32_t RESERVED0;
Kojto 102:da0ca467f8b5 324 #endif
Kojto 102:da0ca467f8b5 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 102:da0ca467f8b5 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 102:da0ca467f8b5 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 102:da0ca467f8b5 328 uint32_t RESERVED1;
Kojto 102:da0ca467f8b5 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 102:da0ca467f8b5 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 102:da0ca467f8b5 331 } SCB_Type;
Kojto 102:da0ca467f8b5 332
Kojto 102:da0ca467f8b5 333 /* SCB CPUID Register Definitions */
Kojto 102:da0ca467f8b5 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 102:da0ca467f8b5 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 102:da0ca467f8b5 336
Kojto 102:da0ca467f8b5 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 102:da0ca467f8b5 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 102:da0ca467f8b5 339
Kojto 102:da0ca467f8b5 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 102:da0ca467f8b5 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 102:da0ca467f8b5 342
Kojto 102:da0ca467f8b5 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 102:da0ca467f8b5 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 102:da0ca467f8b5 345
Kojto 102:da0ca467f8b5 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 102:da0ca467f8b5 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 102:da0ca467f8b5 348
Kojto 102:da0ca467f8b5 349 /* SCB Interrupt Control State Register Definitions */
Kojto 102:da0ca467f8b5 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 102:da0ca467f8b5 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 102:da0ca467f8b5 352
Kojto 102:da0ca467f8b5 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 102:da0ca467f8b5 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 102:da0ca467f8b5 355
Kojto 102:da0ca467f8b5 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 102:da0ca467f8b5 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 102:da0ca467f8b5 358
Kojto 102:da0ca467f8b5 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 102:da0ca467f8b5 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 102:da0ca467f8b5 361
Kojto 102:da0ca467f8b5 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 102:da0ca467f8b5 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 102:da0ca467f8b5 364
Kojto 102:da0ca467f8b5 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 102:da0ca467f8b5 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 102:da0ca467f8b5 367
Kojto 102:da0ca467f8b5 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 102:da0ca467f8b5 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 102:da0ca467f8b5 370
Kojto 102:da0ca467f8b5 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 102:da0ca467f8b5 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 102:da0ca467f8b5 373
Kojto 102:da0ca467f8b5 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 102:da0ca467f8b5 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 102:da0ca467f8b5 376
Kojto 102:da0ca467f8b5 377 #if (__VTOR_PRESENT == 1)
Kojto 102:da0ca467f8b5 378 /* SCB Interrupt Control State Register Definitions */
Kojto 102:da0ca467f8b5 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 102:da0ca467f8b5 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 102:da0ca467f8b5 381 #endif
Kojto 102:da0ca467f8b5 382
Kojto 102:da0ca467f8b5 383 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 102:da0ca467f8b5 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 102:da0ca467f8b5 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 102:da0ca467f8b5 386
Kojto 102:da0ca467f8b5 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 102:da0ca467f8b5 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 102:da0ca467f8b5 389
Kojto 102:da0ca467f8b5 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 102:da0ca467f8b5 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 102:da0ca467f8b5 392
Kojto 102:da0ca467f8b5 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 102:da0ca467f8b5 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 102:da0ca467f8b5 395
Kojto 102:da0ca467f8b5 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 102:da0ca467f8b5 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 102:da0ca467f8b5 398
Kojto 102:da0ca467f8b5 399 /* SCB System Control Register Definitions */
Kojto 102:da0ca467f8b5 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 102:da0ca467f8b5 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 102:da0ca467f8b5 402
Kojto 102:da0ca467f8b5 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 102:da0ca467f8b5 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 102:da0ca467f8b5 405
Kojto 102:da0ca467f8b5 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 102:da0ca467f8b5 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 102:da0ca467f8b5 408
Kojto 102:da0ca467f8b5 409 /* SCB Configuration Control Register Definitions */
Kojto 102:da0ca467f8b5 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 102:da0ca467f8b5 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 102:da0ca467f8b5 412
Kojto 102:da0ca467f8b5 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 102:da0ca467f8b5 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 102:da0ca467f8b5 415
Kojto 102:da0ca467f8b5 416 /* SCB System Handler Control and State Register Definitions */
Kojto 102:da0ca467f8b5 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 102:da0ca467f8b5 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 102:da0ca467f8b5 419
Kojto 102:da0ca467f8b5 420 /*@} end of group CMSIS_SCB */
Kojto 102:da0ca467f8b5 421
Kojto 102:da0ca467f8b5 422
Kojto 102:da0ca467f8b5 423 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 102:da0ca467f8b5 425 \brief Type definitions for the System Timer Registers.
Kojto 102:da0ca467f8b5 426 @{
Kojto 102:da0ca467f8b5 427 */
Kojto 102:da0ca467f8b5 428
Kojto 102:da0ca467f8b5 429 /** \brief Structure type to access the System Timer (SysTick).
Kojto 102:da0ca467f8b5 430 */
Kojto 102:da0ca467f8b5 431 typedef struct
Kojto 102:da0ca467f8b5 432 {
Kojto 102:da0ca467f8b5 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 102:da0ca467f8b5 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 102:da0ca467f8b5 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 102:da0ca467f8b5 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 102:da0ca467f8b5 437 } SysTick_Type;
Kojto 102:da0ca467f8b5 438
Kojto 102:da0ca467f8b5 439 /* SysTick Control / Status Register Definitions */
Kojto 102:da0ca467f8b5 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 102:da0ca467f8b5 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 102:da0ca467f8b5 442
Kojto 102:da0ca467f8b5 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 102:da0ca467f8b5 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 102:da0ca467f8b5 445
Kojto 102:da0ca467f8b5 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 102:da0ca467f8b5 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 102:da0ca467f8b5 448
Kojto 102:da0ca467f8b5 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 102:da0ca467f8b5 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 102:da0ca467f8b5 451
Kojto 102:da0ca467f8b5 452 /* SysTick Reload Register Definitions */
Kojto 102:da0ca467f8b5 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 102:da0ca467f8b5 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 102:da0ca467f8b5 455
Kojto 102:da0ca467f8b5 456 /* SysTick Current Register Definitions */
Kojto 102:da0ca467f8b5 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 102:da0ca467f8b5 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 102:da0ca467f8b5 459
Kojto 102:da0ca467f8b5 460 /* SysTick Calibration Register Definitions */
Kojto 102:da0ca467f8b5 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 102:da0ca467f8b5 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 102:da0ca467f8b5 463
Kojto 102:da0ca467f8b5 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 102:da0ca467f8b5 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 102:da0ca467f8b5 466
Kojto 102:da0ca467f8b5 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 102:da0ca467f8b5 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 102:da0ca467f8b5 469
Kojto 102:da0ca467f8b5 470 /*@} end of group CMSIS_SysTick */
Kojto 102:da0ca467f8b5 471
Kojto 102:da0ca467f8b5 472 #if (__MPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 473 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 102:da0ca467f8b5 475 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 102:da0ca467f8b5 476 @{
Kojto 102:da0ca467f8b5 477 */
Kojto 102:da0ca467f8b5 478
Kojto 102:da0ca467f8b5 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 102:da0ca467f8b5 480 */
Kojto 102:da0ca467f8b5 481 typedef struct
Kojto 102:da0ca467f8b5 482 {
Kojto 102:da0ca467f8b5 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 102:da0ca467f8b5 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 102:da0ca467f8b5 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 102:da0ca467f8b5 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 102:da0ca467f8b5 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 488 } MPU_Type;
Kojto 102:da0ca467f8b5 489
Kojto 102:da0ca467f8b5 490 /* MPU Type Register */
Kojto 102:da0ca467f8b5 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 102:da0ca467f8b5 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 102:da0ca467f8b5 493
Kojto 102:da0ca467f8b5 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 102:da0ca467f8b5 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 102:da0ca467f8b5 496
Kojto 102:da0ca467f8b5 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 102:da0ca467f8b5 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Kojto 102:da0ca467f8b5 499
Kojto 102:da0ca467f8b5 500 /* MPU Control Register */
Kojto 102:da0ca467f8b5 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 102:da0ca467f8b5 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 102:da0ca467f8b5 503
Kojto 102:da0ca467f8b5 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 102:da0ca467f8b5 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 102:da0ca467f8b5 506
Kojto 102:da0ca467f8b5 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 102:da0ca467f8b5 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Kojto 102:da0ca467f8b5 509
Kojto 102:da0ca467f8b5 510 /* MPU Region Number Register */
Kojto 102:da0ca467f8b5 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 102:da0ca467f8b5 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Kojto 102:da0ca467f8b5 513
Kojto 102:da0ca467f8b5 514 /* MPU Region Base Address Register */
Kojto 102:da0ca467f8b5 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 102:da0ca467f8b5 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 102:da0ca467f8b5 517
Kojto 102:da0ca467f8b5 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 102:da0ca467f8b5 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 102:da0ca467f8b5 520
Kojto 102:da0ca467f8b5 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 102:da0ca467f8b5 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Kojto 102:da0ca467f8b5 523
Kojto 102:da0ca467f8b5 524 /* MPU Region Attribute and Size Register */
Kojto 102:da0ca467f8b5 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 102:da0ca467f8b5 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 102:da0ca467f8b5 527
Kojto 102:da0ca467f8b5 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 102:da0ca467f8b5 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 102:da0ca467f8b5 530
Kojto 102:da0ca467f8b5 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 102:da0ca467f8b5 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 102:da0ca467f8b5 533
Kojto 102:da0ca467f8b5 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 102:da0ca467f8b5 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 102:da0ca467f8b5 536
Kojto 102:da0ca467f8b5 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 102:da0ca467f8b5 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 102:da0ca467f8b5 539
Kojto 102:da0ca467f8b5 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 102:da0ca467f8b5 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 102:da0ca467f8b5 542
Kojto 102:da0ca467f8b5 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 102:da0ca467f8b5 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 102:da0ca467f8b5 545
Kojto 102:da0ca467f8b5 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 102:da0ca467f8b5 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 102:da0ca467f8b5 548
Kojto 102:da0ca467f8b5 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 102:da0ca467f8b5 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 102:da0ca467f8b5 551
Kojto 102:da0ca467f8b5 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 102:da0ca467f8b5 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 102:da0ca467f8b5 554
Kojto 102:da0ca467f8b5 555 /*@} end of group CMSIS_MPU */
Kojto 102:da0ca467f8b5 556 #endif
Kojto 102:da0ca467f8b5 557
Kojto 102:da0ca467f8b5 558
Kojto 102:da0ca467f8b5 559 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 102:da0ca467f8b5 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 102:da0ca467f8b5 562 are only accessible over DAP and not via processor. Therefore
Kojto 102:da0ca467f8b5 563 they are not covered by the Cortex-M0 header file.
Kojto 102:da0ca467f8b5 564 @{
Kojto 102:da0ca467f8b5 565 */
Kojto 102:da0ca467f8b5 566 /*@} end of group CMSIS_CoreDebug */
Kojto 102:da0ca467f8b5 567
Kojto 102:da0ca467f8b5 568
Kojto 102:da0ca467f8b5 569 /** \ingroup CMSIS_core_register
Kojto 102:da0ca467f8b5 570 \defgroup CMSIS_core_base Core Definitions
Kojto 102:da0ca467f8b5 571 \brief Definitions for base addresses, unions, and structures.
Kojto 102:da0ca467f8b5 572 @{
Kojto 102:da0ca467f8b5 573 */
Kojto 102:da0ca467f8b5 574
Kojto 102:da0ca467f8b5 575 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 102:da0ca467f8b5 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 102:da0ca467f8b5 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 102:da0ca467f8b5 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 102:da0ca467f8b5 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 102:da0ca467f8b5 580
Kojto 102:da0ca467f8b5 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 102:da0ca467f8b5 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 102:da0ca467f8b5 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 102:da0ca467f8b5 584
Kojto 102:da0ca467f8b5 585 #if (__MPU_PRESENT == 1)
Kojto 102:da0ca467f8b5 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 102:da0ca467f8b5 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 102:da0ca467f8b5 588 #endif
Kojto 102:da0ca467f8b5 589
Kojto 102:da0ca467f8b5 590 /*@} */
Kojto 102:da0ca467f8b5 591
Kojto 102:da0ca467f8b5 592
Kojto 102:da0ca467f8b5 593
Kojto 102:da0ca467f8b5 594 /*******************************************************************************
Kojto 102:da0ca467f8b5 595 * Hardware Abstraction Layer
Kojto 102:da0ca467f8b5 596 Core Function Interface contains:
Kojto 102:da0ca467f8b5 597 - Core NVIC Functions
Kojto 102:da0ca467f8b5 598 - Core SysTick Functions
Kojto 102:da0ca467f8b5 599 - Core Register Access Functions
Kojto 102:da0ca467f8b5 600 ******************************************************************************/
Kojto 102:da0ca467f8b5 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 102:da0ca467f8b5 602 */
Kojto 102:da0ca467f8b5 603
Kojto 102:da0ca467f8b5 604
Kojto 102:da0ca467f8b5 605
Kojto 102:da0ca467f8b5 606 /* ########################## NVIC functions #################################### */
Kojto 102:da0ca467f8b5 607 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 102:da0ca467f8b5 609 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 102:da0ca467f8b5 610 @{
Kojto 102:da0ca467f8b5 611 */
Kojto 102:da0ca467f8b5 612
Kojto 102:da0ca467f8b5 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 102:da0ca467f8b5 614 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 102:da0ca467f8b5 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 102:da0ca467f8b5 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 102:da0ca467f8b5 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 102:da0ca467f8b5 618
Kojto 102:da0ca467f8b5 619
Kojto 102:da0ca467f8b5 620 /** \brief Enable External Interrupt
Kojto 102:da0ca467f8b5 621
Kojto 102:da0ca467f8b5 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 102:da0ca467f8b5 623
Kojto 102:da0ca467f8b5 624 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 625 */
Kojto 102:da0ca467f8b5 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 627 {
Kojto 102:da0ca467f8b5 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 102:da0ca467f8b5 629 }
Kojto 102:da0ca467f8b5 630
Kojto 102:da0ca467f8b5 631
Kojto 102:da0ca467f8b5 632 /** \brief Disable External Interrupt
Kojto 102:da0ca467f8b5 633
Kojto 102:da0ca467f8b5 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 102:da0ca467f8b5 635
Kojto 102:da0ca467f8b5 636 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 637 */
Kojto 102:da0ca467f8b5 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 639 {
Kojto 102:da0ca467f8b5 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 102:da0ca467f8b5 641 }
Kojto 102:da0ca467f8b5 642
Kojto 102:da0ca467f8b5 643
Kojto 102:da0ca467f8b5 644 /** \brief Get Pending Interrupt
Kojto 102:da0ca467f8b5 645
Kojto 102:da0ca467f8b5 646 The function reads the pending register in the NVIC and returns the pending bit
Kojto 102:da0ca467f8b5 647 for the specified interrupt.
Kojto 102:da0ca467f8b5 648
Kojto 102:da0ca467f8b5 649 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 650
Kojto 102:da0ca467f8b5 651 \return 0 Interrupt status is not pending.
Kojto 102:da0ca467f8b5 652 \return 1 Interrupt status is pending.
Kojto 102:da0ca467f8b5 653 */
Kojto 102:da0ca467f8b5 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 655 {
Kojto 102:da0ca467f8b5 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 102:da0ca467f8b5 657 }
Kojto 102:da0ca467f8b5 658
Kojto 102:da0ca467f8b5 659
Kojto 102:da0ca467f8b5 660 /** \brief Set Pending Interrupt
Kojto 102:da0ca467f8b5 661
Kojto 102:da0ca467f8b5 662 The function sets the pending bit of an external interrupt.
Kojto 102:da0ca467f8b5 663
Kojto 102:da0ca467f8b5 664 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 665 */
Kojto 102:da0ca467f8b5 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 667 {
Kojto 102:da0ca467f8b5 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 102:da0ca467f8b5 669 }
Kojto 102:da0ca467f8b5 670
Kojto 102:da0ca467f8b5 671
Kojto 102:da0ca467f8b5 672 /** \brief Clear Pending Interrupt
Kojto 102:da0ca467f8b5 673
Kojto 102:da0ca467f8b5 674 The function clears the pending bit of an external interrupt.
Kojto 102:da0ca467f8b5 675
Kojto 102:da0ca467f8b5 676 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 102:da0ca467f8b5 677 */
Kojto 102:da0ca467f8b5 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 679 {
Kojto 102:da0ca467f8b5 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 102:da0ca467f8b5 681 }
Kojto 102:da0ca467f8b5 682
Kojto 102:da0ca467f8b5 683
Kojto 102:da0ca467f8b5 684 /** \brief Set Interrupt Priority
Kojto 102:da0ca467f8b5 685
Kojto 102:da0ca467f8b5 686 The function sets the priority of an interrupt.
Kojto 102:da0ca467f8b5 687
Kojto 102:da0ca467f8b5 688 \note The priority cannot be set for every core interrupt.
Kojto 102:da0ca467f8b5 689
Kojto 102:da0ca467f8b5 690 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 691 \param [in] priority Priority to set.
Kojto 102:da0ca467f8b5 692 */
Kojto 102:da0ca467f8b5 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 102:da0ca467f8b5 694 {
Kojto 102:da0ca467f8b5 695 if(IRQn < 0) {
Kojto 102:da0ca467f8b5 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 102:da0ca467f8b5 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 102:da0ca467f8b5 698 else {
Kojto 102:da0ca467f8b5 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 102:da0ca467f8b5 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 102:da0ca467f8b5 701 }
Kojto 102:da0ca467f8b5 702
Kojto 102:da0ca467f8b5 703
Kojto 102:da0ca467f8b5 704 /** \brief Get Interrupt Priority
Kojto 102:da0ca467f8b5 705
Kojto 102:da0ca467f8b5 706 The function reads the priority of an interrupt. The interrupt
Kojto 102:da0ca467f8b5 707 number can be positive to specify an external (device specific)
Kojto 102:da0ca467f8b5 708 interrupt, or negative to specify an internal (core) interrupt.
Kojto 102:da0ca467f8b5 709
Kojto 102:da0ca467f8b5 710
Kojto 102:da0ca467f8b5 711 \param [in] IRQn Interrupt number.
Kojto 102:da0ca467f8b5 712 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 102:da0ca467f8b5 713 priority bits of the microcontroller.
Kojto 102:da0ca467f8b5 714 */
Kojto 102:da0ca467f8b5 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 102:da0ca467f8b5 716 {
Kojto 102:da0ca467f8b5 717
Kojto 102:da0ca467f8b5 718 if(IRQn < 0) {
Kojto 102:da0ca467f8b5 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 102:da0ca467f8b5 720 else {
Kojto 102:da0ca467f8b5 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 102:da0ca467f8b5 722 }
Kojto 102:da0ca467f8b5 723
Kojto 102:da0ca467f8b5 724
Kojto 102:da0ca467f8b5 725 /** \brief System Reset
Kojto 102:da0ca467f8b5 726
Kojto 102:da0ca467f8b5 727 The function initiates a system reset request to reset the MCU.
Kojto 102:da0ca467f8b5 728 */
Kojto 102:da0ca467f8b5 729 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 102:da0ca467f8b5 730 {
Kojto 102:da0ca467f8b5 731 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 102:da0ca467f8b5 732 buffered write are completed before reset */
Kojto 102:da0ca467f8b5 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 102:da0ca467f8b5 734 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 102:da0ca467f8b5 735 __DSB(); /* Ensure completion of memory access */
Kojto 102:da0ca467f8b5 736 while(1); /* wait until reset */
Kojto 102:da0ca467f8b5 737 }
Kojto 102:da0ca467f8b5 738
Kojto 102:da0ca467f8b5 739 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 102:da0ca467f8b5 740
Kojto 102:da0ca467f8b5 741
Kojto 102:da0ca467f8b5 742
Kojto 102:da0ca467f8b5 743 /* ################################## SysTick function ############################################ */
Kojto 102:da0ca467f8b5 744 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 102:da0ca467f8b5 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 102:da0ca467f8b5 746 \brief Functions that configure the System.
Kojto 102:da0ca467f8b5 747 @{
Kojto 102:da0ca467f8b5 748 */
Kojto 102:da0ca467f8b5 749
Kojto 102:da0ca467f8b5 750 #if (__Vendor_SysTickConfig == 0)
Kojto 102:da0ca467f8b5 751
Kojto 102:da0ca467f8b5 752 /** \brief System Tick Configuration
Kojto 102:da0ca467f8b5 753
Kojto 102:da0ca467f8b5 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 102:da0ca467f8b5 755 Counter is in free running mode to generate periodic interrupts.
Kojto 102:da0ca467f8b5 756
Kojto 102:da0ca467f8b5 757 \param [in] ticks Number of ticks between two interrupts.
Kojto 102:da0ca467f8b5 758
Kojto 102:da0ca467f8b5 759 \return 0 Function succeeded.
Kojto 102:da0ca467f8b5 760 \return 1 Function failed.
Kojto 102:da0ca467f8b5 761
Kojto 102:da0ca467f8b5 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 102:da0ca467f8b5 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 102:da0ca467f8b5 764 must contain a vendor-specific implementation of this function.
Kojto 102:da0ca467f8b5 765
Kojto 102:da0ca467f8b5 766 */
Kojto 102:da0ca467f8b5 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 102:da0ca467f8b5 768 {
Kojto 102:da0ca467f8b5 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 102:da0ca467f8b5 770
Kojto 102:da0ca467f8b5 771 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 102:da0ca467f8b5 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 102:da0ca467f8b5 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 102:da0ca467f8b5 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 102:da0ca467f8b5 775 SysTick_CTRL_TICKINT_Msk |
Kojto 102:da0ca467f8b5 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 102:da0ca467f8b5 777 return (0); /* Function successful */
Kojto 102:da0ca467f8b5 778 }
Kojto 102:da0ca467f8b5 779
Kojto 102:da0ca467f8b5 780 #endif
Kojto 102:da0ca467f8b5 781
Kojto 102:da0ca467f8b5 782 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 102:da0ca467f8b5 783
Kojto 102:da0ca467f8b5 784
Kojto 102:da0ca467f8b5 785
Kojto 102:da0ca467f8b5 786
Kojto 102:da0ca467f8b5 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 102:da0ca467f8b5 788
Kojto 102:da0ca467f8b5 789 #endif /* __CMSIS_GENERIC */
Kojto 102:da0ca467f8b5 790
Kojto 102:da0ca467f8b5 791 #ifdef __cplusplus
Kojto 102:da0ca467f8b5 792 }
Kojto 102:da0ca467f8b5 793 #endif