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TARGET_NRF52840_DK/core_cm0plus.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
145:64910690c574 
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 140:97feb9bacc10 1 /**************************************************************************//**
<> 140:97feb9bacc10 2 * @file core_cm0plus.h
<> 140:97feb9bacc10 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
AnnaBridge 145:64910690c574 4 * @version V5.0.2
AnnaBridge 145:64910690c574 5 * @date 13. February 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
<> 140:97feb9bacc10 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
<> 140:97feb9bacc10 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
<> 140:97feb9bacc10 24
AnnaBridge 145:64910690c574 25 #if defined ( __ICCARM__ )
AnnaBridge 145:64910690c574 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 145:64910690c574 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 28 #pragma clang system_header /* treat file as system include file */
<> 140:97feb9bacc10 29 #endif
<> 140:97feb9bacc10 30
<> 140:97feb9bacc10 31 #ifndef __CORE_CM0PLUS_H_GENERIC
<> 140:97feb9bacc10 32 #define __CORE_CM0PLUS_H_GENERIC
<> 140:97feb9bacc10 33
AnnaBridge 145:64910690c574 34 #include <stdint.h>
AnnaBridge 145:64910690c574 35
<> 140:97feb9bacc10 36 #ifdef __cplusplus
<> 140:97feb9bacc10 37 extern "C" {
<> 140:97feb9bacc10 38 #endif
<> 140:97feb9bacc10 39
AnnaBridge 145:64910690c574 40 /**
AnnaBridge 145:64910690c574 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 140:97feb9bacc10 42 CMSIS violates the following MISRA-C:2004 rules:
<> 140:97feb9bacc10 43
<> 140:97feb9bacc10 44 \li Required Rule 8.5, object/function definition in header file.<br>
<> 140:97feb9bacc10 45 Function definitions in header files are used to allow 'inlining'.
<> 140:97feb9bacc10 46
<> 140:97feb9bacc10 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 140:97feb9bacc10 48 Unions are used for effective representation of core registers.
<> 140:97feb9bacc10 49
<> 140:97feb9bacc10 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 140:97feb9bacc10 51 Function-like macros are used to allow more efficient code.
<> 140:97feb9bacc10 52 */
<> 140:97feb9bacc10 53
<> 140:97feb9bacc10 54
<> 140:97feb9bacc10 55 /*******************************************************************************
<> 140:97feb9bacc10 56 * CMSIS definitions
<> 140:97feb9bacc10 57 ******************************************************************************/
AnnaBridge 145:64910690c574 58 /**
AnnaBridge 145:64910690c574 59 \ingroup Cortex-M0+
<> 140:97feb9bacc10 60 @{
<> 140:97feb9bacc10 61 */
<> 140:97feb9bacc10 62
AnnaBridge 145:64910690c574 63 /* CMSIS CM0+ definitions */
AnnaBridge 145:64910690c574 64 #define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 145:64910690c574 65 #define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 145:64910690c574 66 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 145:64910690c574 67 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 140:97feb9bacc10 68
AnnaBridge 145:64910690c574 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
<> 140:97feb9bacc10 70
<> 140:97feb9bacc10 71 /** __FPU_USED indicates whether an FPU is used or not.
<> 140:97feb9bacc10 72 This core does not support an FPU at all
<> 140:97feb9bacc10 73 */
AnnaBridge 145:64910690c574 74 #define __FPU_USED 0U
<> 140:97feb9bacc10 75
<> 140:97feb9bacc10 76 #if defined ( __CC_ARM )
<> 140:97feb9bacc10 77 #if defined __TARGET_FPU_VFP
AnnaBridge 145:64910690c574 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 79 #endif
AnnaBridge 145:64910690c574 80
AnnaBridge 145:64910690c574 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 82 #if defined __ARM_PCS_VFP
AnnaBridge 145:64910690c574 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 84 #endif
<> 140:97feb9bacc10 85
<> 140:97feb9bacc10 86 #elif defined ( __GNUC__ )
<> 140:97feb9bacc10 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 145:64910690c574 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 89 #endif
<> 140:97feb9bacc10 90
<> 140:97feb9bacc10 91 #elif defined ( __ICCARM__ )
<> 140:97feb9bacc10 92 #if defined __ARMVFP__
AnnaBridge 145:64910690c574 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 94 #endif
<> 140:97feb9bacc10 95
AnnaBridge 145:64910690c574 96 #elif defined ( __TI_ARM__ )
AnnaBridge 145:64910690c574 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 145:64910690c574 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 99 #endif
<> 140:97feb9bacc10 100
<> 140:97feb9bacc10 101 #elif defined ( __TASKING__ )
<> 140:97feb9bacc10 102 #if defined __FPU_VFP__
<> 140:97feb9bacc10 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 104 #endif
<> 140:97feb9bacc10 105
AnnaBridge 145:64910690c574 106 #elif defined ( __CSMC__ )
AnnaBridge 145:64910690c574 107 #if ( __CSMC__ & 0x400U)
<> 140:97feb9bacc10 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 109 #endif
AnnaBridge 145:64910690c574 110
<> 140:97feb9bacc10 111 #endif
<> 140:97feb9bacc10 112
AnnaBridge 145:64910690c574 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 114
<> 140:97feb9bacc10 115
<> 140:97feb9bacc10 116 #ifdef __cplusplus
<> 140:97feb9bacc10 117 }
<> 140:97feb9bacc10 118 #endif
<> 140:97feb9bacc10 119
<> 140:97feb9bacc10 120 #endif /* __CORE_CM0PLUS_H_GENERIC */
<> 140:97feb9bacc10 121
<> 140:97feb9bacc10 122 #ifndef __CMSIS_GENERIC
<> 140:97feb9bacc10 123
<> 140:97feb9bacc10 124 #ifndef __CORE_CM0PLUS_H_DEPENDANT
<> 140:97feb9bacc10 125 #define __CORE_CM0PLUS_H_DEPENDANT
<> 140:97feb9bacc10 126
<> 140:97feb9bacc10 127 #ifdef __cplusplus
<> 140:97feb9bacc10 128 extern "C" {
<> 140:97feb9bacc10 129 #endif
<> 140:97feb9bacc10 130
<> 140:97feb9bacc10 131 /* check device defines and use defaults */
<> 140:97feb9bacc10 132 #if defined __CHECK_DEVICE_DEFINES
<> 140:97feb9bacc10 133 #ifndef __CM0PLUS_REV
AnnaBridge 145:64910690c574 134 #define __CM0PLUS_REV 0x0000U
<> 140:97feb9bacc10 135 #warning "__CM0PLUS_REV not defined in device header file; using default!"
<> 140:97feb9bacc10 136 #endif
<> 140:97feb9bacc10 137
<> 140:97feb9bacc10 138 #ifndef __MPU_PRESENT
AnnaBridge 145:64910690c574 139 #define __MPU_PRESENT 0U
<> 140:97feb9bacc10 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 141 #endif
<> 140:97feb9bacc10 142
<> 140:97feb9bacc10 143 #ifndef __VTOR_PRESENT
AnnaBridge 145:64910690c574 144 #define __VTOR_PRESENT 0U
<> 140:97feb9bacc10 145 #warning "__VTOR_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 146 #endif
<> 140:97feb9bacc10 147
<> 140:97feb9bacc10 148 #ifndef __NVIC_PRIO_BITS
AnnaBridge 145:64910690c574 149 #define __NVIC_PRIO_BITS 2U
<> 140:97feb9bacc10 150 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 140:97feb9bacc10 151 #endif
<> 140:97feb9bacc10 152
<> 140:97feb9bacc10 153 #ifndef __Vendor_SysTickConfig
AnnaBridge 145:64910690c574 154 #define __Vendor_SysTickConfig 0U
<> 140:97feb9bacc10 155 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 140:97feb9bacc10 156 #endif
<> 140:97feb9bacc10 157 #endif
<> 140:97feb9bacc10 158
<> 140:97feb9bacc10 159 /* IO definitions (access restrictions to peripheral registers) */
<> 140:97feb9bacc10 160 /**
<> 140:97feb9bacc10 161 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 140:97feb9bacc10 162
<> 140:97feb9bacc10 163 <strong>IO Type Qualifiers</strong> are used
<> 140:97feb9bacc10 164 \li to specify the access to peripheral variables.
<> 140:97feb9bacc10 165 \li for automatic generation of peripheral register debug information.
<> 140:97feb9bacc10 166 */
<> 140:97feb9bacc10 167 #ifdef __cplusplus
AnnaBridge 145:64910690c574 168 #define __I volatile /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 169 #else
AnnaBridge 145:64910690c574 170 #define __I volatile const /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 171 #endif
AnnaBridge 145:64910690c574 172 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 145:64910690c574 173 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 140:97feb9bacc10 174
AnnaBridge 145:64910690c574 175 /* following defines should be used for structure members */
AnnaBridge 145:64910690c574 176 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 145:64910690c574 177 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 145:64910690c574 178 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
<> 140:97feb9bacc10 179
<> 140:97feb9bacc10 180 /*@} end of group Cortex-M0+ */
<> 140:97feb9bacc10 181
<> 140:97feb9bacc10 182
<> 140:97feb9bacc10 183
<> 140:97feb9bacc10 184 /*******************************************************************************
<> 140:97feb9bacc10 185 * Register Abstraction
<> 140:97feb9bacc10 186 Core Register contain:
<> 140:97feb9bacc10 187 - Core Register
<> 140:97feb9bacc10 188 - Core NVIC Register
<> 140:97feb9bacc10 189 - Core SCB Register
<> 140:97feb9bacc10 190 - Core SysTick Register
<> 140:97feb9bacc10 191 - Core MPU Register
<> 140:97feb9bacc10 192 ******************************************************************************/
AnnaBridge 145:64910690c574 193 /**
AnnaBridge 145:64910690c574 194 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 145:64910690c574 195 \brief Type definitions and defines for Cortex-M processor based devices.
<> 140:97feb9bacc10 196 */
<> 140:97feb9bacc10 197
AnnaBridge 145:64910690c574 198 /**
AnnaBridge 145:64910690c574 199 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 200 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 145:64910690c574 201 \brief Core Register type definitions.
<> 140:97feb9bacc10 202 @{
<> 140:97feb9bacc10 203 */
<> 140:97feb9bacc10 204
AnnaBridge 145:64910690c574 205 /**
AnnaBridge 145:64910690c574 206 \brief Union type to access the Application Program Status Register (APSR).
<> 140:97feb9bacc10 207 */
<> 140:97feb9bacc10 208 typedef union
<> 140:97feb9bacc10 209 {
<> 140:97feb9bacc10 210 struct
<> 140:97feb9bacc10 211 {
AnnaBridge 145:64910690c574 212 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 145:64910690c574 213 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 214 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 215 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 216 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 217 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 218 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 219 } APSR_Type;
<> 140:97feb9bacc10 220
<> 140:97feb9bacc10 221 /* APSR Register Definitions */
AnnaBridge 145:64910690c574 222 #define APSR_N_Pos 31U /*!< APSR: N Position */
<> 140:97feb9bacc10 223 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 140:97feb9bacc10 224
AnnaBridge 145:64910690c574 225 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
<> 140:97feb9bacc10 226 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 140:97feb9bacc10 227
AnnaBridge 145:64910690c574 228 #define APSR_C_Pos 29U /*!< APSR: C Position */
<> 140:97feb9bacc10 229 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 140:97feb9bacc10 230
AnnaBridge 145:64910690c574 231 #define APSR_V_Pos 28U /*!< APSR: V Position */
<> 140:97feb9bacc10 232 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 140:97feb9bacc10 233
<> 140:97feb9bacc10 234
AnnaBridge 145:64910690c574 235 /**
AnnaBridge 145:64910690c574 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 140:97feb9bacc10 237 */
<> 140:97feb9bacc10 238 typedef union
<> 140:97feb9bacc10 239 {
<> 140:97feb9bacc10 240 struct
<> 140:97feb9bacc10 241 {
AnnaBridge 145:64910690c574 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 145:64910690c574 244 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 245 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 246 } IPSR_Type;
<> 140:97feb9bacc10 247
<> 140:97feb9bacc10 248 /* IPSR Register Definitions */
AnnaBridge 145:64910690c574 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
<> 140:97feb9bacc10 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 140:97feb9bacc10 251
<> 140:97feb9bacc10 252
AnnaBridge 145:64910690c574 253 /**
AnnaBridge 145:64910690c574 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 140:97feb9bacc10 255 */
<> 140:97feb9bacc10 256 typedef union
<> 140:97feb9bacc10 257 {
<> 140:97feb9bacc10 258 struct
<> 140:97feb9bacc10 259 {
AnnaBridge 145:64910690c574 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 261 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 145:64910690c574 262 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 145:64910690c574 263 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 145:64910690c574 264 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 265 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 266 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 267 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 268 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 269 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 270 } xPSR_Type;
<> 140:97feb9bacc10 271
<> 140:97feb9bacc10 272 /* xPSR Register Definitions */
AnnaBridge 145:64910690c574 273 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
<> 140:97feb9bacc10 274 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 140:97feb9bacc10 275
AnnaBridge 145:64910690c574 276 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
<> 140:97feb9bacc10 277 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 140:97feb9bacc10 278
AnnaBridge 145:64910690c574 279 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
<> 140:97feb9bacc10 280 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 140:97feb9bacc10 281
AnnaBridge 145:64910690c574 282 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
<> 140:97feb9bacc10 283 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 140:97feb9bacc10 284
AnnaBridge 145:64910690c574 285 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
<> 140:97feb9bacc10 286 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 140:97feb9bacc10 287
AnnaBridge 145:64910690c574 288 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
<> 140:97feb9bacc10 289 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 140:97feb9bacc10 290
<> 140:97feb9bacc10 291
AnnaBridge 145:64910690c574 292 /**
AnnaBridge 145:64910690c574 293 \brief Union type to access the Control Registers (CONTROL).
<> 140:97feb9bacc10 294 */
<> 140:97feb9bacc10 295 typedef union
<> 140:97feb9bacc10 296 {
<> 140:97feb9bacc10 297 struct
<> 140:97feb9bacc10 298 {
<> 140:97feb9bacc10 299 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 145:64910690c574 300 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 145:64910690c574 301 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 145:64910690c574 302 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 303 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 304 } CONTROL_Type;
<> 140:97feb9bacc10 305
<> 140:97feb9bacc10 306 /* CONTROL Register Definitions */
AnnaBridge 145:64910690c574 307 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
<> 140:97feb9bacc10 308 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 140:97feb9bacc10 309
AnnaBridge 145:64910690c574 310 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
<> 140:97feb9bacc10 311 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 140:97feb9bacc10 312
<> 140:97feb9bacc10 313 /*@} end of group CMSIS_CORE */
<> 140:97feb9bacc10 314
<> 140:97feb9bacc10 315
AnnaBridge 145:64910690c574 316 /**
AnnaBridge 145:64910690c574 317 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 318 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 145:64910690c574 319 \brief Type definitions for the NVIC Registers
<> 140:97feb9bacc10 320 @{
<> 140:97feb9bacc10 321 */
<> 140:97feb9bacc10 322
AnnaBridge 145:64910690c574 323 /**
AnnaBridge 145:64910690c574 324 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 140:97feb9bacc10 325 */
<> 140:97feb9bacc10 326 typedef struct
<> 140:97feb9bacc10 327 {
AnnaBridge 145:64910690c574 328 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 145:64910690c574 329 uint32_t RESERVED0[31U];
AnnaBridge 145:64910690c574 330 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 145:64910690c574 331 uint32_t RSERVED1[31U];
AnnaBridge 145:64910690c574 332 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 145:64910690c574 333 uint32_t RESERVED2[31U];
AnnaBridge 145:64910690c574 334 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 145:64910690c574 335 uint32_t RESERVED3[31U];
AnnaBridge 145:64910690c574 336 uint32_t RESERVED4[64U];
AnnaBridge 145:64910690c574 337 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 140:97feb9bacc10 338 } NVIC_Type;
<> 140:97feb9bacc10 339
<> 140:97feb9bacc10 340 /*@} end of group CMSIS_NVIC */
<> 140:97feb9bacc10 341
<> 140:97feb9bacc10 342
AnnaBridge 145:64910690c574 343 /**
AnnaBridge 145:64910690c574 344 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 345 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 145:64910690c574 346 \brief Type definitions for the System Control Block Registers
<> 140:97feb9bacc10 347 @{
<> 140:97feb9bacc10 348 */
<> 140:97feb9bacc10 349
AnnaBridge 145:64910690c574 350 /**
AnnaBridge 145:64910690c574 351 \brief Structure type to access the System Control Block (SCB).
<> 140:97feb9bacc10 352 */
<> 140:97feb9bacc10 353 typedef struct
<> 140:97feb9bacc10 354 {
AnnaBridge 145:64910690c574 355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 145:64910690c574 356 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 145:64910690c574 357 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 145:64910690c574 358 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 140:97feb9bacc10 359 #else
AnnaBridge 145:64910690c574 360 uint32_t RESERVED0;
<> 140:97feb9bacc10 361 #endif
AnnaBridge 145:64910690c574 362 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 145:64910690c574 363 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 145:64910690c574 364 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 145:64910690c574 365 uint32_t RESERVED1;
AnnaBridge 145:64910690c574 366 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 145:64910690c574 367 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 140:97feb9bacc10 368 } SCB_Type;
<> 140:97feb9bacc10 369
<> 140:97feb9bacc10 370 /* SCB CPUID Register Definitions */
AnnaBridge 145:64910690c574 371 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
<> 140:97feb9bacc10 372 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 140:97feb9bacc10 373
AnnaBridge 145:64910690c574 374 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
<> 140:97feb9bacc10 375 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 140:97feb9bacc10 376
AnnaBridge 145:64910690c574 377 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
<> 140:97feb9bacc10 378 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 140:97feb9bacc10 379
AnnaBridge 145:64910690c574 380 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
<> 140:97feb9bacc10 381 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 140:97feb9bacc10 382
AnnaBridge 145:64910690c574 383 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
<> 140:97feb9bacc10 384 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 140:97feb9bacc10 385
<> 140:97feb9bacc10 386 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 387 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
<> 140:97feb9bacc10 388 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 140:97feb9bacc10 389
AnnaBridge 145:64910690c574 390 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
<> 140:97feb9bacc10 391 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 140:97feb9bacc10 392
AnnaBridge 145:64910690c574 393 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
<> 140:97feb9bacc10 394 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 140:97feb9bacc10 395
AnnaBridge 145:64910690c574 396 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
<> 140:97feb9bacc10 397 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 140:97feb9bacc10 398
AnnaBridge 145:64910690c574 399 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
<> 140:97feb9bacc10 400 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 140:97feb9bacc10 401
AnnaBridge 145:64910690c574 402 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
<> 140:97feb9bacc10 403 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 140:97feb9bacc10 404
AnnaBridge 145:64910690c574 405 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
<> 140:97feb9bacc10 406 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 140:97feb9bacc10 407
AnnaBridge 145:64910690c574 408 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
<> 140:97feb9bacc10 409 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 140:97feb9bacc10 410
AnnaBridge 145:64910690c574 411 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
<> 140:97feb9bacc10 412 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 140:97feb9bacc10 413
AnnaBridge 145:64910690c574 414 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
<> 140:97feb9bacc10 415 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 416 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
<> 140:97feb9bacc10 417 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 140:97feb9bacc10 418 #endif
<> 140:97feb9bacc10 419
<> 140:97feb9bacc10 420 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 145:64910690c574 421 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
<> 140:97feb9bacc10 422 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 140:97feb9bacc10 423
AnnaBridge 145:64910690c574 424 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 140:97feb9bacc10 425 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 140:97feb9bacc10 426
AnnaBridge 145:64910690c574 427 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
<> 140:97feb9bacc10 428 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 140:97feb9bacc10 429
AnnaBridge 145:64910690c574 430 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
<> 140:97feb9bacc10 431 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 140:97feb9bacc10 432
AnnaBridge 145:64910690c574 433 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 140:97feb9bacc10 434 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 140:97feb9bacc10 435
<> 140:97feb9bacc10 436 /* SCB System Control Register Definitions */
AnnaBridge 145:64910690c574 437 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
<> 140:97feb9bacc10 438 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 140:97feb9bacc10 439
AnnaBridge 145:64910690c574 440 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
<> 140:97feb9bacc10 441 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 140:97feb9bacc10 442
AnnaBridge 145:64910690c574 443 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
<> 140:97feb9bacc10 444 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 140:97feb9bacc10 445
<> 140:97feb9bacc10 446 /* SCB Configuration Control Register Definitions */
AnnaBridge 145:64910690c574 447 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
<> 140:97feb9bacc10 448 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 140:97feb9bacc10 449
AnnaBridge 145:64910690c574 450 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
<> 140:97feb9bacc10 451 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 140:97feb9bacc10 452
<> 140:97feb9bacc10 453 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 145:64910690c574 454 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
<> 140:97feb9bacc10 455 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 140:97feb9bacc10 456
<> 140:97feb9bacc10 457 /*@} end of group CMSIS_SCB */
<> 140:97feb9bacc10 458
<> 140:97feb9bacc10 459
AnnaBridge 145:64910690c574 460 /**
AnnaBridge 145:64910690c574 461 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 462 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 145:64910690c574 463 \brief Type definitions for the System Timer Registers.
<> 140:97feb9bacc10 464 @{
<> 140:97feb9bacc10 465 */
<> 140:97feb9bacc10 466
AnnaBridge 145:64910690c574 467 /**
AnnaBridge 145:64910690c574 468 \brief Structure type to access the System Timer (SysTick).
<> 140:97feb9bacc10 469 */
<> 140:97feb9bacc10 470 typedef struct
<> 140:97feb9bacc10 471 {
AnnaBridge 145:64910690c574 472 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 145:64910690c574 473 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 145:64910690c574 474 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 145:64910690c574 475 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 140:97feb9bacc10 476 } SysTick_Type;
<> 140:97feb9bacc10 477
<> 140:97feb9bacc10 478 /* SysTick Control / Status Register Definitions */
AnnaBridge 145:64910690c574 479 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
<> 140:97feb9bacc10 480 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 140:97feb9bacc10 481
AnnaBridge 145:64910690c574 482 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
<> 140:97feb9bacc10 483 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 140:97feb9bacc10 484
AnnaBridge 145:64910690c574 485 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
<> 140:97feb9bacc10 486 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 140:97feb9bacc10 487
AnnaBridge 145:64910690c574 488 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
<> 140:97feb9bacc10 489 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 140:97feb9bacc10 490
<> 140:97feb9bacc10 491 /* SysTick Reload Register Definitions */
AnnaBridge 145:64910690c574 492 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
<> 140:97feb9bacc10 493 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 140:97feb9bacc10 494
<> 140:97feb9bacc10 495 /* SysTick Current Register Definitions */
AnnaBridge 145:64910690c574 496 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
<> 140:97feb9bacc10 497 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 140:97feb9bacc10 498
<> 140:97feb9bacc10 499 /* SysTick Calibration Register Definitions */
AnnaBridge 145:64910690c574 500 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
<> 140:97feb9bacc10 501 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 140:97feb9bacc10 502
AnnaBridge 145:64910690c574 503 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
<> 140:97feb9bacc10 504 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 140:97feb9bacc10 505
AnnaBridge 145:64910690c574 506 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
<> 140:97feb9bacc10 507 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 140:97feb9bacc10 508
<> 140:97feb9bacc10 509 /*@} end of group CMSIS_SysTick */
<> 140:97feb9bacc10 510
AnnaBridge 145:64910690c574 511 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 512 /**
AnnaBridge 145:64910690c574 513 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 514 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 145:64910690c574 515 \brief Type definitions for the Memory Protection Unit (MPU)
<> 140:97feb9bacc10 516 @{
<> 140:97feb9bacc10 517 */
<> 140:97feb9bacc10 518
AnnaBridge 145:64910690c574 519 /**
AnnaBridge 145:64910690c574 520 \brief Structure type to access the Memory Protection Unit (MPU).
<> 140:97feb9bacc10 521 */
<> 140:97feb9bacc10 522 typedef struct
<> 140:97feb9bacc10 523 {
AnnaBridge 145:64910690c574 524 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 145:64910690c574 525 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 145:64910690c574 526 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 145:64910690c574 527 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 145:64910690c574 528 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 140:97feb9bacc10 529 } MPU_Type;
<> 140:97feb9bacc10 530
AnnaBridge 145:64910690c574 531 /* MPU Type Register Definitions */
AnnaBridge 145:64910690c574 532 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
<> 140:97feb9bacc10 533 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 140:97feb9bacc10 534
AnnaBridge 145:64910690c574 535 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
<> 140:97feb9bacc10 536 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 140:97feb9bacc10 537
AnnaBridge 145:64910690c574 538 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
<> 140:97feb9bacc10 539 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 140:97feb9bacc10 540
AnnaBridge 145:64910690c574 541 /* MPU Control Register Definitions */
AnnaBridge 145:64910690c574 542 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
<> 140:97feb9bacc10 543 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 140:97feb9bacc10 544
AnnaBridge 145:64910690c574 545 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
<> 140:97feb9bacc10 546 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 140:97feb9bacc10 547
AnnaBridge 145:64910690c574 548 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
<> 140:97feb9bacc10 549 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 140:97feb9bacc10 550
AnnaBridge 145:64910690c574 551 /* MPU Region Number Register Definitions */
AnnaBridge 145:64910690c574 552 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
<> 140:97feb9bacc10 553 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 140:97feb9bacc10 554
AnnaBridge 145:64910690c574 555 /* MPU Region Base Address Register Definitions */
AnnaBridge 145:64910690c574 556 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
<> 140:97feb9bacc10 557 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 140:97feb9bacc10 558
AnnaBridge 145:64910690c574 559 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
<> 140:97feb9bacc10 560 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 140:97feb9bacc10 561
AnnaBridge 145:64910690c574 562 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
<> 140:97feb9bacc10 563 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 140:97feb9bacc10 564
AnnaBridge 145:64910690c574 565 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 145:64910690c574 566 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
<> 140:97feb9bacc10 567 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 140:97feb9bacc10 568
AnnaBridge 145:64910690c574 569 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
<> 140:97feb9bacc10 570 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 140:97feb9bacc10 571
AnnaBridge 145:64910690c574 572 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
<> 140:97feb9bacc10 573 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 140:97feb9bacc10 574
AnnaBridge 145:64910690c574 575 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
<> 140:97feb9bacc10 576 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 140:97feb9bacc10 577
AnnaBridge 145:64910690c574 578 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
<> 140:97feb9bacc10 579 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 140:97feb9bacc10 580
AnnaBridge 145:64910690c574 581 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
<> 140:97feb9bacc10 582 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 140:97feb9bacc10 583
AnnaBridge 145:64910690c574 584 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
<> 140:97feb9bacc10 585 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 140:97feb9bacc10 586
AnnaBridge 145:64910690c574 587 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
<> 140:97feb9bacc10 588 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 140:97feb9bacc10 589
AnnaBridge 145:64910690c574 590 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
<> 140:97feb9bacc10 591 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 140:97feb9bacc10 592
AnnaBridge 145:64910690c574 593 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
<> 140:97feb9bacc10 594 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 140:97feb9bacc10 595
<> 140:97feb9bacc10 596 /*@} end of group CMSIS_MPU */
<> 140:97feb9bacc10 597 #endif
<> 140:97feb9bacc10 598
<> 140:97feb9bacc10 599
AnnaBridge 145:64910690c574 600 /**
AnnaBridge 145:64910690c574 601 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 602 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 145:64910690c574 603 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 145:64910690c574 604 Therefore they are not covered by the Cortex-M0+ header file.
<> 140:97feb9bacc10 605 @{
<> 140:97feb9bacc10 606 */
<> 140:97feb9bacc10 607 /*@} end of group CMSIS_CoreDebug */
<> 140:97feb9bacc10 608
<> 140:97feb9bacc10 609
AnnaBridge 145:64910690c574 610 /**
AnnaBridge 145:64910690c574 611 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 612 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 145:64910690c574 613 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
<> 140:97feb9bacc10 614 @{
<> 140:97feb9bacc10 615 */
<> 140:97feb9bacc10 616
AnnaBridge 145:64910690c574 617 /**
AnnaBridge 145:64910690c574 618 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 145:64910690c574 619 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 620 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 621 \return Masked and shifted value.
AnnaBridge 145:64910690c574 622 */
AnnaBridge 145:64910690c574 623 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 145:64910690c574 624
AnnaBridge 145:64910690c574 625 /**
AnnaBridge 145:64910690c574 626 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 145:64910690c574 627 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 628 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 629 \return Masked and shifted bit field value.
AnnaBridge 145:64910690c574 630 */
AnnaBridge 145:64910690c574 631 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 145:64910690c574 632
AnnaBridge 145:64910690c574 633 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 145:64910690c574 634
AnnaBridge 145:64910690c574 635
AnnaBridge 145:64910690c574 636 /**
AnnaBridge 145:64910690c574 637 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 638 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 145:64910690c574 639 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 145:64910690c574 640 @{
AnnaBridge 145:64910690c574 641 */
AnnaBridge 145:64910690c574 642
AnnaBridge 145:64910690c574 643 /* Memory mapping of Core Hardware */
<> 140:97feb9bacc10 644 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 145:64910690c574 645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 145:64910690c574 646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 140:97feb9bacc10 647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 140:97feb9bacc10 648
AnnaBridge 145:64910690c574 649 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 145:64910690c574 650 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 145:64910690c574 651 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 140:97feb9bacc10 652
AnnaBridge 145:64910690c574 653 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 654 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 145:64910690c574 655 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 140:97feb9bacc10 656 #endif
<> 140:97feb9bacc10 657
<> 140:97feb9bacc10 658 /*@} */
<> 140:97feb9bacc10 659
<> 140:97feb9bacc10 660
<> 140:97feb9bacc10 661
<> 140:97feb9bacc10 662 /*******************************************************************************
<> 140:97feb9bacc10 663 * Hardware Abstraction Layer
<> 140:97feb9bacc10 664 Core Function Interface contains:
<> 140:97feb9bacc10 665 - Core NVIC Functions
<> 140:97feb9bacc10 666 - Core SysTick Functions
<> 140:97feb9bacc10 667 - Core Register Access Functions
<> 140:97feb9bacc10 668 ******************************************************************************/
AnnaBridge 145:64910690c574 669 /**
AnnaBridge 145:64910690c574 670 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 140:97feb9bacc10 671 */
<> 140:97feb9bacc10 672
<> 140:97feb9bacc10 673
<> 140:97feb9bacc10 674
<> 140:97feb9bacc10 675 /* ########################## NVIC functions #################################### */
AnnaBridge 145:64910690c574 676 /**
AnnaBridge 145:64910690c574 677 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 678 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 145:64910690c574 679 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 145:64910690c574 680 @{
<> 140:97feb9bacc10 681 */
<> 140:97feb9bacc10 682
AnnaBridge 145:64910690c574 683 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 145:64910690c574 684 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 685 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 145:64910690c574 686 #endif
AnnaBridge 145:64910690c574 687 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 688 #else
AnnaBridge 145:64910690c574 689 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
AnnaBridge 145:64910690c574 690 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
AnnaBridge 145:64910690c574 691 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 145:64910690c574 692 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 145:64910690c574 693 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 145:64910690c574 694 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 145:64910690c574 695 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 145:64910690c574 696 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 145:64910690c574 697 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
AnnaBridge 145:64910690c574 698 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 145:64910690c574 699 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 145:64910690c574 700 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 145:64910690c574 701 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 145:64910690c574 702
AnnaBridge 145:64910690c574 703 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 145:64910690c574 704 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 705 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 145:64910690c574 706 #endif
AnnaBridge 145:64910690c574 707 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 708 #else
AnnaBridge 145:64910690c574 709 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 145:64910690c574 710 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 145:64910690c574 711 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 145:64910690c574 712
AnnaBridge 145:64910690c574 713 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 145:64910690c574 714
AnnaBridge 145:64910690c574 715
<> 140:97feb9bacc10 716 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 140:97feb9bacc10 717 /* The following MACROS handle generation of the register offset and byte masks */
<> 140:97feb9bacc10 718 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 140:97feb9bacc10 719 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 140:97feb9bacc10 720 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 140:97feb9bacc10 721
<> 140:97feb9bacc10 722
AnnaBridge 145:64910690c574 723 /**
AnnaBridge 145:64910690c574 724 \brief Enable Interrupt
AnnaBridge 145:64910690c574 725 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 726 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 727 \note IRQn must not be negative.
<> 140:97feb9bacc10 728 */
AnnaBridge 145:64910690c574 729 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 730 {
AnnaBridge 145:64910690c574 731 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 732 {
AnnaBridge 145:64910690c574 733 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 734 }
<> 140:97feb9bacc10 735 }
<> 140:97feb9bacc10 736
<> 140:97feb9bacc10 737
AnnaBridge 145:64910690c574 738 /**
AnnaBridge 145:64910690c574 739 \brief Get Interrupt Enable status
AnnaBridge 145:64910690c574 740 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 145:64910690c574 741 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 742 \return 0 Interrupt is not enabled.
AnnaBridge 145:64910690c574 743 \return 1 Interrupt is enabled.
AnnaBridge 145:64910690c574 744 \note IRQn must not be negative.
<> 140:97feb9bacc10 745 */
AnnaBridge 145:64910690c574 746 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 747 {
AnnaBridge 145:64910690c574 748 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 749 {
AnnaBridge 145:64910690c574 750 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 751 }
AnnaBridge 145:64910690c574 752 else
AnnaBridge 145:64910690c574 753 {
AnnaBridge 145:64910690c574 754 return(0U);
AnnaBridge 145:64910690c574 755 }
<> 140:97feb9bacc10 756 }
<> 140:97feb9bacc10 757
<> 140:97feb9bacc10 758
AnnaBridge 145:64910690c574 759 /**
AnnaBridge 145:64910690c574 760 \brief Disable Interrupt
AnnaBridge 145:64910690c574 761 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 762 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 763 \note IRQn must not be negative.
<> 140:97feb9bacc10 764 */
AnnaBridge 145:64910690c574 765 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 766 {
AnnaBridge 145:64910690c574 767 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 768 {
AnnaBridge 145:64910690c574 769 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 770 __DSB();
AnnaBridge 145:64910690c574 771 __ISB();
AnnaBridge 145:64910690c574 772 }
<> 140:97feb9bacc10 773 }
<> 140:97feb9bacc10 774
<> 140:97feb9bacc10 775
AnnaBridge 145:64910690c574 776 /**
AnnaBridge 145:64910690c574 777 \brief Get Pending Interrupt
AnnaBridge 145:64910690c574 778 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 145:64910690c574 779 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 780 \return 0 Interrupt status is not pending.
AnnaBridge 145:64910690c574 781 \return 1 Interrupt status is pending.
AnnaBridge 145:64910690c574 782 \note IRQn must not be negative.
<> 140:97feb9bacc10 783 */
AnnaBridge 145:64910690c574 784 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 785 {
AnnaBridge 145:64910690c574 786 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 787 {
AnnaBridge 145:64910690c574 788 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 789 }
AnnaBridge 145:64910690c574 790 else
AnnaBridge 145:64910690c574 791 {
AnnaBridge 145:64910690c574 792 return(0U);
AnnaBridge 145:64910690c574 793 }
<> 140:97feb9bacc10 794 }
<> 140:97feb9bacc10 795
<> 140:97feb9bacc10 796
AnnaBridge 145:64910690c574 797 /**
AnnaBridge 145:64910690c574 798 \brief Set Pending Interrupt
AnnaBridge 145:64910690c574 799 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 800 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 801 \note IRQn must not be negative.
<> 140:97feb9bacc10 802 */
AnnaBridge 145:64910690c574 803 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 804 {
AnnaBridge 145:64910690c574 805 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 806 {
AnnaBridge 145:64910690c574 807 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 808 }
AnnaBridge 145:64910690c574 809 }
AnnaBridge 145:64910690c574 810
AnnaBridge 145:64910690c574 811
AnnaBridge 145:64910690c574 812 /**
AnnaBridge 145:64910690c574 813 \brief Clear Pending Interrupt
AnnaBridge 145:64910690c574 814 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 815 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 816 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 817 */
AnnaBridge 145:64910690c574 818 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 819 {
AnnaBridge 145:64910690c574 820 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 821 {
AnnaBridge 145:64910690c574 822 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 823 }
<> 140:97feb9bacc10 824 }
<> 140:97feb9bacc10 825
<> 140:97feb9bacc10 826
AnnaBridge 145:64910690c574 827 /**
AnnaBridge 145:64910690c574 828 \brief Set Interrupt Priority
AnnaBridge 145:64910690c574 829 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 830 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 831 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 832 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 833 \param [in] priority Priority to set.
AnnaBridge 145:64910690c574 834 \note The priority cannot be set for every processor exception.
AnnaBridge 145:64910690c574 835 */
AnnaBridge 145:64910690c574 836 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 145:64910690c574 837 {
AnnaBridge 145:64910690c574 838 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 839 {
AnnaBridge 145:64910690c574 840 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 841 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 145:64910690c574 842 }
AnnaBridge 145:64910690c574 843 else
AnnaBridge 145:64910690c574 844 {
AnnaBridge 145:64910690c574 845 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 846 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 145:64910690c574 847 }
AnnaBridge 145:64910690c574 848 }
<> 140:97feb9bacc10 849
<> 140:97feb9bacc10 850
AnnaBridge 145:64910690c574 851 /**
AnnaBridge 145:64910690c574 852 \brief Get Interrupt Priority
AnnaBridge 145:64910690c574 853 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 854 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 855 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 856 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 857 \return Interrupt Priority.
AnnaBridge 145:64910690c574 858 Value is aligned automatically to the implemented priority bits of the microcontroller.
<> 140:97feb9bacc10 859 */
AnnaBridge 145:64910690c574 860 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
<> 140:97feb9bacc10 861 {
<> 140:97feb9bacc10 862
AnnaBridge 145:64910690c574 863 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 864 {
AnnaBridge 145:64910690c574 865 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
<> 140:97feb9bacc10 866 }
AnnaBridge 145:64910690c574 867 else
AnnaBridge 145:64910690c574 868 {
AnnaBridge 145:64910690c574 869 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
<> 140:97feb9bacc10 870 }
<> 140:97feb9bacc10 871 }
<> 140:97feb9bacc10 872
<> 140:97feb9bacc10 873
AnnaBridge 145:64910690c574 874 /**
AnnaBridge 145:64910690c574 875 \brief Set Interrupt Vector
AnnaBridge 145:64910690c574 876 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 145:64910690c574 877 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 878 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 879 VTOR must been relocated to SRAM before.
AnnaBridge 145:64910690c574 880 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 145:64910690c574 881 \param [in] IRQn Interrupt number
AnnaBridge 145:64910690c574 882 \param [in] vector Address of interrupt handler function
<> 140:97feb9bacc10 883 */
AnnaBridge 145:64910690c574 884 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
<> 140:97feb9bacc10 885 {
AnnaBridge 145:64910690c574 886 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 145:64910690c574 887 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 888 #else
AnnaBridge 145:64910690c574 889 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 145:64910690c574 890 #endif
AnnaBridge 145:64910690c574 891 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 145:64910690c574 892 }
AnnaBridge 145:64910690c574 893
AnnaBridge 145:64910690c574 894
AnnaBridge 145:64910690c574 895 /**
AnnaBridge 145:64910690c574 896 \brief Get Interrupt Vector
AnnaBridge 145:64910690c574 897 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 145:64910690c574 898 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 899 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 900 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 901 \return Address of interrupt handler function
AnnaBridge 145:64910690c574 902 */
AnnaBridge 145:64910690c574 903 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 904 {
AnnaBridge 145:64910690c574 905 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 145:64910690c574 906 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 907 #else
AnnaBridge 145:64910690c574 908 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 145:64910690c574 909 #endif
AnnaBridge 145:64910690c574 910 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 145:64910690c574 911
AnnaBridge 145:64910690c574 912 }
AnnaBridge 145:64910690c574 913
AnnaBridge 145:64910690c574 914
AnnaBridge 145:64910690c574 915 /**
AnnaBridge 145:64910690c574 916 \brief System Reset
AnnaBridge 145:64910690c574 917 \details Initiates a system reset request to reset the MCU.
AnnaBridge 145:64910690c574 918 */
AnnaBridge 145:64910690c574 919 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 145:64910690c574 920 {
AnnaBridge 145:64910690c574 921 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 145:64910690c574 922 buffered write are completed before reset */
<> 140:97feb9bacc10 923 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 140:97feb9bacc10 924 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 145:64910690c574 925 __DSB(); /* Ensure completion of memory access */
AnnaBridge 145:64910690c574 926
AnnaBridge 145:64910690c574 927 for(;;) /* wait until reset */
AnnaBridge 145:64910690c574 928 {
AnnaBridge 145:64910690c574 929 __NOP();
AnnaBridge 145:64910690c574 930 }
<> 140:97feb9bacc10 931 }
<> 140:97feb9bacc10 932
<> 140:97feb9bacc10 933 /*@} end of CMSIS_Core_NVICFunctions */
<> 140:97feb9bacc10 934
<> 140:97feb9bacc10 935
AnnaBridge 145:64910690c574 936 /* ########################## FPU functions #################################### */
AnnaBridge 145:64910690c574 937 /**
AnnaBridge 145:64910690c574 938 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 939 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 145:64910690c574 940 \brief Function that provides FPU type.
<> 140:97feb9bacc10 941 @{
<> 140:97feb9bacc10 942 */
<> 140:97feb9bacc10 943
AnnaBridge 145:64910690c574 944 /**
AnnaBridge 145:64910690c574 945 \brief get FPU type
AnnaBridge 145:64910690c574 946 \details returns the FPU type
AnnaBridge 145:64910690c574 947 \returns
AnnaBridge 145:64910690c574 948 - \b 0: No FPU
AnnaBridge 145:64910690c574 949 - \b 1: Single precision FPU
AnnaBridge 145:64910690c574 950 - \b 2: Double + Single precision FPU
AnnaBridge 145:64910690c574 951 */
AnnaBridge 145:64910690c574 952 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 145:64910690c574 953 {
AnnaBridge 145:64910690c574 954 return 0U; /* No FPU */
AnnaBridge 145:64910690c574 955 }
<> 140:97feb9bacc10 956
<> 140:97feb9bacc10 957
AnnaBridge 145:64910690c574 958 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 145:64910690c574 959
AnnaBridge 145:64910690c574 960
<> 140:97feb9bacc10 961
AnnaBridge 145:64910690c574 962 /* ################################## SysTick function ############################################ */
AnnaBridge 145:64910690c574 963 /**
AnnaBridge 145:64910690c574 964 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 965 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 145:64910690c574 966 \brief Functions that configure the System.
AnnaBridge 145:64910690c574 967 @{
AnnaBridge 145:64910690c574 968 */
<> 140:97feb9bacc10 969
AnnaBridge 145:64910690c574 970 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
<> 140:97feb9bacc10 971
AnnaBridge 145:64910690c574 972 /**
AnnaBridge 145:64910690c574 973 \brief System Tick Configuration
AnnaBridge 145:64910690c574 974 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 145:64910690c574 975 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 145:64910690c574 976 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 145:64910690c574 977 \return 0 Function succeeded.
AnnaBridge 145:64910690c574 978 \return 1 Function failed.
AnnaBridge 145:64910690c574 979 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 145:64910690c574 980 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 145:64910690c574 981 must contain a vendor-specific implementation of this function.
<> 140:97feb9bacc10 982 */
<> 140:97feb9bacc10 983 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 140:97feb9bacc10 984 {
AnnaBridge 145:64910690c574 985 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 145:64910690c574 986 {
AnnaBridge 145:64910690c574 987 return (1UL); /* Reload value impossible */
AnnaBridge 145:64910690c574 988 }
<> 140:97feb9bacc10 989
<> 140:97feb9bacc10 990 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 140:97feb9bacc10 991 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 140:97feb9bacc10 992 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 140:97feb9bacc10 993 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 140:97feb9bacc10 994 SysTick_CTRL_TICKINT_Msk |
<> 140:97feb9bacc10 995 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 140:97feb9bacc10 996 return (0UL); /* Function successful */
<> 140:97feb9bacc10 997 }
<> 140:97feb9bacc10 998
<> 140:97feb9bacc10 999 #endif
<> 140:97feb9bacc10 1000
<> 140:97feb9bacc10 1001 /*@} end of CMSIS_Core_SysTickFunctions */
<> 140:97feb9bacc10 1002
<> 140:97feb9bacc10 1003
<> 140:97feb9bacc10 1004
<> 140:97feb9bacc10 1005
<> 140:97feb9bacc10 1006 #ifdef __cplusplus
<> 140:97feb9bacc10 1007 }
<> 140:97feb9bacc10 1008 #endif
<> 140:97feb9bacc10 1009
<> 140:97feb9bacc10 1010 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
<> 140:97feb9bacc10 1011
<> 140:97feb9bacc10 1012 #endif /* __CMSIS_GENERIC */