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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF52840_DK/core_cm0plus.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 140:97feb9bacc10 1 /**************************************************************************//**
<> 140:97feb9bacc10 2 * @file core_cm0plus.h
<> 140:97feb9bacc10 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
<> 140:97feb9bacc10 4 * @version V4.10
<> 140:97feb9bacc10 5 * @date 18. March 2015
<> 140:97feb9bacc10 6 *
<> 140:97feb9bacc10 7 * @note
<> 140:97feb9bacc10 8 *
<> 140:97feb9bacc10 9 ******************************************************************************/
<> 140:97feb9bacc10 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 140:97feb9bacc10 11
<> 140:97feb9bacc10 12 All rights reserved.
<> 140:97feb9bacc10 13 Redistribution and use in source and binary forms, with or without
<> 140:97feb9bacc10 14 modification, are permitted provided that the following conditions are met:
<> 140:97feb9bacc10 15 - Redistributions of source code must retain the above copyright
<> 140:97feb9bacc10 16 notice, this list of conditions and the following disclaimer.
<> 140:97feb9bacc10 17 - Redistributions in binary form must reproduce the above copyright
<> 140:97feb9bacc10 18 notice, this list of conditions and the following disclaimer in the
<> 140:97feb9bacc10 19 documentation and/or other materials provided with the distribution.
<> 140:97feb9bacc10 20 - Neither the name of ARM nor the names of its contributors may be used
<> 140:97feb9bacc10 21 to endorse or promote products derived from this software without
<> 140:97feb9bacc10 22 specific prior written permission.
<> 140:97feb9bacc10 23 *
<> 140:97feb9bacc10 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 140:97feb9bacc10 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 140:97feb9bacc10 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 140:97feb9bacc10 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 140:97feb9bacc10 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 140:97feb9bacc10 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 140:97feb9bacc10 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 140:97feb9bacc10 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 140:97feb9bacc10 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 140:97feb9bacc10 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 140:97feb9bacc10 34 POSSIBILITY OF SUCH DAMAGE.
<> 140:97feb9bacc10 35 ---------------------------------------------------------------------------*/
<> 140:97feb9bacc10 36
<> 140:97feb9bacc10 37
<> 140:97feb9bacc10 38 #if defined ( __ICCARM__ )
<> 140:97feb9bacc10 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 140:97feb9bacc10 40 #endif
<> 140:97feb9bacc10 41
<> 140:97feb9bacc10 42 #ifndef __CORE_CM0PLUS_H_GENERIC
<> 140:97feb9bacc10 43 #define __CORE_CM0PLUS_H_GENERIC
<> 140:97feb9bacc10 44
<> 140:97feb9bacc10 45 #ifdef __cplusplus
<> 140:97feb9bacc10 46 extern "C" {
<> 140:97feb9bacc10 47 #endif
<> 140:97feb9bacc10 48
<> 140:97feb9bacc10 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 140:97feb9bacc10 50 CMSIS violates the following MISRA-C:2004 rules:
<> 140:97feb9bacc10 51
<> 140:97feb9bacc10 52 \li Required Rule 8.5, object/function definition in header file.<br>
<> 140:97feb9bacc10 53 Function definitions in header files are used to allow 'inlining'.
<> 140:97feb9bacc10 54
<> 140:97feb9bacc10 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 140:97feb9bacc10 56 Unions are used for effective representation of core registers.
<> 140:97feb9bacc10 57
<> 140:97feb9bacc10 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 140:97feb9bacc10 59 Function-like macros are used to allow more efficient code.
<> 140:97feb9bacc10 60 */
<> 140:97feb9bacc10 61
<> 140:97feb9bacc10 62
<> 140:97feb9bacc10 63 /*******************************************************************************
<> 140:97feb9bacc10 64 * CMSIS definitions
<> 140:97feb9bacc10 65 ******************************************************************************/
<> 140:97feb9bacc10 66 /** \ingroup Cortex-M0+
<> 140:97feb9bacc10 67 @{
<> 140:97feb9bacc10 68 */
<> 140:97feb9bacc10 69
<> 140:97feb9bacc10 70 /* CMSIS CM0P definitions */
<> 140:97feb9bacc10 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
<> 140:97feb9bacc10 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
<> 140:97feb9bacc10 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
<> 140:97feb9bacc10 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
<> 140:97feb9bacc10 75
<> 140:97feb9bacc10 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
<> 140:97feb9bacc10 77
<> 140:97feb9bacc10 78
<> 140:97feb9bacc10 79 #if defined ( __CC_ARM )
<> 140:97feb9bacc10 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 140:97feb9bacc10 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 140:97feb9bacc10 82 #define __STATIC_INLINE static __inline
<> 140:97feb9bacc10 83
<> 140:97feb9bacc10 84 #elif defined ( __GNUC__ )
<> 140:97feb9bacc10 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 140:97feb9bacc10 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 140:97feb9bacc10 87 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 88
<> 140:97feb9bacc10 89 #elif defined ( __ICCARM__ )
<> 140:97feb9bacc10 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 140:97feb9bacc10 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 140:97feb9bacc10 92 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 93
<> 140:97feb9bacc10 94 #elif defined ( __TMS470__ )
<> 140:97feb9bacc10 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 140:97feb9bacc10 96 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 97
<> 140:97feb9bacc10 98 #elif defined ( __TASKING__ )
<> 140:97feb9bacc10 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 140:97feb9bacc10 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 140:97feb9bacc10 101 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 102
<> 140:97feb9bacc10 103 #elif defined ( __CSMC__ )
<> 140:97feb9bacc10 104 #define __packed
<> 140:97feb9bacc10 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
<> 140:97feb9bacc10 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
<> 140:97feb9bacc10 107 #define __STATIC_INLINE static inline
<> 140:97feb9bacc10 108
<> 140:97feb9bacc10 109 #endif
<> 140:97feb9bacc10 110
<> 140:97feb9bacc10 111 /** __FPU_USED indicates whether an FPU is used or not.
<> 140:97feb9bacc10 112 This core does not support an FPU at all
<> 140:97feb9bacc10 113 */
<> 140:97feb9bacc10 114 #define __FPU_USED 0
<> 140:97feb9bacc10 115
<> 140:97feb9bacc10 116 #if defined ( __CC_ARM )
<> 140:97feb9bacc10 117 #if defined __TARGET_FPU_VFP
<> 140:97feb9bacc10 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 119 #endif
<> 140:97feb9bacc10 120
<> 140:97feb9bacc10 121 #elif defined ( __GNUC__ )
<> 140:97feb9bacc10 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 140:97feb9bacc10 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 124 #endif
<> 140:97feb9bacc10 125
<> 140:97feb9bacc10 126 #elif defined ( __ICCARM__ )
<> 140:97feb9bacc10 127 #if defined __ARMVFP__
<> 140:97feb9bacc10 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 129 #endif
<> 140:97feb9bacc10 130
<> 140:97feb9bacc10 131 #elif defined ( __TMS470__ )
<> 140:97feb9bacc10 132 #if defined __TI__VFP_SUPPORT____
<> 140:97feb9bacc10 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 134 #endif
<> 140:97feb9bacc10 135
<> 140:97feb9bacc10 136 #elif defined ( __TASKING__ )
<> 140:97feb9bacc10 137 #if defined __FPU_VFP__
<> 140:97feb9bacc10 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 139 #endif
<> 140:97feb9bacc10 140
<> 140:97feb9bacc10 141 #elif defined ( __CSMC__ ) /* Cosmic */
<> 140:97feb9bacc10 142 #if ( __CSMC__ & 0x400) // FPU present for parser
<> 140:97feb9bacc10 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 140:97feb9bacc10 144 #endif
<> 140:97feb9bacc10 145 #endif
<> 140:97feb9bacc10 146
<> 140:97feb9bacc10 147 #include <stdint.h> /* standard types definitions */
<> 140:97feb9bacc10 148 #include <core_cmInstr.h> /* Core Instruction Access */
<> 140:97feb9bacc10 149 #include <core_cmFunc.h> /* Core Function Access */
<> 140:97feb9bacc10 150
<> 140:97feb9bacc10 151 #ifdef __cplusplus
<> 140:97feb9bacc10 152 }
<> 140:97feb9bacc10 153 #endif
<> 140:97feb9bacc10 154
<> 140:97feb9bacc10 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
<> 140:97feb9bacc10 156
<> 140:97feb9bacc10 157 #ifndef __CMSIS_GENERIC
<> 140:97feb9bacc10 158
<> 140:97feb9bacc10 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
<> 140:97feb9bacc10 160 #define __CORE_CM0PLUS_H_DEPENDANT
<> 140:97feb9bacc10 161
<> 140:97feb9bacc10 162 #ifdef __cplusplus
<> 140:97feb9bacc10 163 extern "C" {
<> 140:97feb9bacc10 164 #endif
<> 140:97feb9bacc10 165
<> 140:97feb9bacc10 166 /* check device defines and use defaults */
<> 140:97feb9bacc10 167 #if defined __CHECK_DEVICE_DEFINES
<> 140:97feb9bacc10 168 #ifndef __CM0PLUS_REV
<> 140:97feb9bacc10 169 #define __CM0PLUS_REV 0x0000
<> 140:97feb9bacc10 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
<> 140:97feb9bacc10 171 #endif
<> 140:97feb9bacc10 172
<> 140:97feb9bacc10 173 #ifndef __MPU_PRESENT
<> 140:97feb9bacc10 174 #define __MPU_PRESENT 0
<> 140:97feb9bacc10 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 176 #endif
<> 140:97feb9bacc10 177
<> 140:97feb9bacc10 178 #ifndef __VTOR_PRESENT
<> 140:97feb9bacc10 179 #define __VTOR_PRESENT 0
<> 140:97feb9bacc10 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
<> 140:97feb9bacc10 181 #endif
<> 140:97feb9bacc10 182
<> 140:97feb9bacc10 183 #ifndef __NVIC_PRIO_BITS
<> 140:97feb9bacc10 184 #define __NVIC_PRIO_BITS 2
<> 140:97feb9bacc10 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
<> 140:97feb9bacc10 186 #endif
<> 140:97feb9bacc10 187
<> 140:97feb9bacc10 188 #ifndef __Vendor_SysTickConfig
<> 140:97feb9bacc10 189 #define __Vendor_SysTickConfig 0
<> 140:97feb9bacc10 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
<> 140:97feb9bacc10 191 #endif
<> 140:97feb9bacc10 192 #endif
<> 140:97feb9bacc10 193
<> 140:97feb9bacc10 194 /* IO definitions (access restrictions to peripheral registers) */
<> 140:97feb9bacc10 195 /**
<> 140:97feb9bacc10 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 140:97feb9bacc10 197
<> 140:97feb9bacc10 198 <strong>IO Type Qualifiers</strong> are used
<> 140:97feb9bacc10 199 \li to specify the access to peripheral variables.
<> 140:97feb9bacc10 200 \li for automatic generation of peripheral register debug information.
<> 140:97feb9bacc10 201 */
<> 140:97feb9bacc10 202 #ifdef __cplusplus
<> 140:97feb9bacc10 203 #define __I volatile /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 204 #else
<> 140:97feb9bacc10 205 #define __I volatile const /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 206 #endif
<> 140:97feb9bacc10 207 #define __O volatile /*!< Defines 'write only' permissions */
<> 140:97feb9bacc10 208 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 140:97feb9bacc10 209
<> 140:97feb9bacc10 210 #ifdef __cplusplus
<> 140:97feb9bacc10 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 212 #else
<> 140:97feb9bacc10 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 140:97feb9bacc10 214 #endif
<> 140:97feb9bacc10 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 140:97feb9bacc10 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 140:97feb9bacc10 217
<> 140:97feb9bacc10 218 /*@} end of group Cortex-M0+ */
<> 140:97feb9bacc10 219
<> 140:97feb9bacc10 220
<> 140:97feb9bacc10 221
<> 140:97feb9bacc10 222 /*******************************************************************************
<> 140:97feb9bacc10 223 * Register Abstraction
<> 140:97feb9bacc10 224 Core Register contain:
<> 140:97feb9bacc10 225 - Core Register
<> 140:97feb9bacc10 226 - Core NVIC Register
<> 140:97feb9bacc10 227 - Core SCB Register
<> 140:97feb9bacc10 228 - Core SysTick Register
<> 140:97feb9bacc10 229 - Core MPU Register
<> 140:97feb9bacc10 230 ******************************************************************************/
<> 140:97feb9bacc10 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 140:97feb9bacc10 232 \brief Type definitions and defines for Cortex-M processor based devices.
<> 140:97feb9bacc10 233 */
<> 140:97feb9bacc10 234
<> 140:97feb9bacc10 235 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 236 \defgroup CMSIS_CORE Status and Control Registers
<> 140:97feb9bacc10 237 \brief Core Register type definitions.
<> 140:97feb9bacc10 238 @{
<> 140:97feb9bacc10 239 */
<> 140:97feb9bacc10 240
<> 140:97feb9bacc10 241 /** \brief Union type to access the Application Program Status Register (APSR).
<> 140:97feb9bacc10 242 */
<> 140:97feb9bacc10 243 typedef union
<> 140:97feb9bacc10 244 {
<> 140:97feb9bacc10 245 struct
<> 140:97feb9bacc10 246 {
<> 140:97feb9bacc10 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
<> 140:97feb9bacc10 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 140:97feb9bacc10 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 140:97feb9bacc10 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 140:97feb9bacc10 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 140:97feb9bacc10 252 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 253 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 254 } APSR_Type;
<> 140:97feb9bacc10 255
<> 140:97feb9bacc10 256 /* APSR Register Definitions */
<> 140:97feb9bacc10 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
<> 140:97feb9bacc10 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
<> 140:97feb9bacc10 259
<> 140:97feb9bacc10 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
<> 140:97feb9bacc10 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
<> 140:97feb9bacc10 262
<> 140:97feb9bacc10 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
<> 140:97feb9bacc10 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
<> 140:97feb9bacc10 265
<> 140:97feb9bacc10 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
<> 140:97feb9bacc10 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
<> 140:97feb9bacc10 268
<> 140:97feb9bacc10 269
<> 140:97feb9bacc10 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
<> 140:97feb9bacc10 271 */
<> 140:97feb9bacc10 272 typedef union
<> 140:97feb9bacc10 273 {
<> 140:97feb9bacc10 274 struct
<> 140:97feb9bacc10 275 {
<> 140:97feb9bacc10 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 140:97feb9bacc10 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
<> 140:97feb9bacc10 278 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 279 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 280 } IPSR_Type;
<> 140:97feb9bacc10 281
<> 140:97feb9bacc10 282 /* IPSR Register Definitions */
<> 140:97feb9bacc10 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
<> 140:97feb9bacc10 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
<> 140:97feb9bacc10 285
<> 140:97feb9bacc10 286
<> 140:97feb9bacc10 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
<> 140:97feb9bacc10 288 */
<> 140:97feb9bacc10 289 typedef union
<> 140:97feb9bacc10 290 {
<> 140:97feb9bacc10 291 struct
<> 140:97feb9bacc10 292 {
<> 140:97feb9bacc10 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
<> 140:97feb9bacc10 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
<> 140:97feb9bacc10 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
<> 140:97feb9bacc10 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
<> 140:97feb9bacc10 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 140:97feb9bacc10 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 140:97feb9bacc10 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 140:97feb9bacc10 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 140:97feb9bacc10 301 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 302 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 303 } xPSR_Type;
<> 140:97feb9bacc10 304
<> 140:97feb9bacc10 305 /* xPSR Register Definitions */
<> 140:97feb9bacc10 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
<> 140:97feb9bacc10 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
<> 140:97feb9bacc10 308
<> 140:97feb9bacc10 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
<> 140:97feb9bacc10 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
<> 140:97feb9bacc10 311
<> 140:97feb9bacc10 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
<> 140:97feb9bacc10 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
<> 140:97feb9bacc10 314
<> 140:97feb9bacc10 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
<> 140:97feb9bacc10 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
<> 140:97feb9bacc10 317
<> 140:97feb9bacc10 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
<> 140:97feb9bacc10 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
<> 140:97feb9bacc10 320
<> 140:97feb9bacc10 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
<> 140:97feb9bacc10 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
<> 140:97feb9bacc10 323
<> 140:97feb9bacc10 324
<> 140:97feb9bacc10 325 /** \brief Union type to access the Control Registers (CONTROL).
<> 140:97feb9bacc10 326 */
<> 140:97feb9bacc10 327 typedef union
<> 140:97feb9bacc10 328 {
<> 140:97feb9bacc10 329 struct
<> 140:97feb9bacc10 330 {
<> 140:97feb9bacc10 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
<> 140:97feb9bacc10 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
<> 140:97feb9bacc10 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
<> 140:97feb9bacc10 334 } b; /*!< Structure used for bit access */
<> 140:97feb9bacc10 335 uint32_t w; /*!< Type used for word access */
<> 140:97feb9bacc10 336 } CONTROL_Type;
<> 140:97feb9bacc10 337
<> 140:97feb9bacc10 338 /* CONTROL Register Definitions */
<> 140:97feb9bacc10 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
<> 140:97feb9bacc10 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
<> 140:97feb9bacc10 341
<> 140:97feb9bacc10 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
<> 140:97feb9bacc10 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
<> 140:97feb9bacc10 344
<> 140:97feb9bacc10 345 /*@} end of group CMSIS_CORE */
<> 140:97feb9bacc10 346
<> 140:97feb9bacc10 347
<> 140:97feb9bacc10 348 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
<> 140:97feb9bacc10 350 \brief Type definitions for the NVIC Registers
<> 140:97feb9bacc10 351 @{
<> 140:97feb9bacc10 352 */
<> 140:97feb9bacc10 353
<> 140:97feb9bacc10 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
<> 140:97feb9bacc10 355 */
<> 140:97feb9bacc10 356 typedef struct
<> 140:97feb9bacc10 357 {
<> 140:97feb9bacc10 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
<> 140:97feb9bacc10 359 uint32_t RESERVED0[31];
<> 140:97feb9bacc10 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
<> 140:97feb9bacc10 361 uint32_t RSERVED1[31];
<> 140:97feb9bacc10 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
<> 140:97feb9bacc10 363 uint32_t RESERVED2[31];
<> 140:97feb9bacc10 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
<> 140:97feb9bacc10 365 uint32_t RESERVED3[31];
<> 140:97feb9bacc10 366 uint32_t RESERVED4[64];
<> 140:97feb9bacc10 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
<> 140:97feb9bacc10 368 } NVIC_Type;
<> 140:97feb9bacc10 369
<> 140:97feb9bacc10 370 /*@} end of group CMSIS_NVIC */
<> 140:97feb9bacc10 371
<> 140:97feb9bacc10 372
<> 140:97feb9bacc10 373 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 374 \defgroup CMSIS_SCB System Control Block (SCB)
<> 140:97feb9bacc10 375 \brief Type definitions for the System Control Block Registers
<> 140:97feb9bacc10 376 @{
<> 140:97feb9bacc10 377 */
<> 140:97feb9bacc10 378
<> 140:97feb9bacc10 379 /** \brief Structure type to access the System Control Block (SCB).
<> 140:97feb9bacc10 380 */
<> 140:97feb9bacc10 381 typedef struct
<> 140:97feb9bacc10 382 {
<> 140:97feb9bacc10 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
<> 140:97feb9bacc10 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
<> 140:97feb9bacc10 385 #if (__VTOR_PRESENT == 1)
<> 140:97feb9bacc10 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
<> 140:97feb9bacc10 387 #else
<> 140:97feb9bacc10 388 uint32_t RESERVED0;
<> 140:97feb9bacc10 389 #endif
<> 140:97feb9bacc10 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
<> 140:97feb9bacc10 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
<> 140:97feb9bacc10 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
<> 140:97feb9bacc10 393 uint32_t RESERVED1;
<> 140:97feb9bacc10 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
<> 140:97feb9bacc10 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
<> 140:97feb9bacc10 396 } SCB_Type;
<> 140:97feb9bacc10 397
<> 140:97feb9bacc10 398 /* SCB CPUID Register Definitions */
<> 140:97feb9bacc10 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
<> 140:97feb9bacc10 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
<> 140:97feb9bacc10 401
<> 140:97feb9bacc10 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
<> 140:97feb9bacc10 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
<> 140:97feb9bacc10 404
<> 140:97feb9bacc10 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
<> 140:97feb9bacc10 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
<> 140:97feb9bacc10 407
<> 140:97feb9bacc10 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
<> 140:97feb9bacc10 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
<> 140:97feb9bacc10 410
<> 140:97feb9bacc10 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
<> 140:97feb9bacc10 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
<> 140:97feb9bacc10 413
<> 140:97feb9bacc10 414 /* SCB Interrupt Control State Register Definitions */
<> 140:97feb9bacc10 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
<> 140:97feb9bacc10 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
<> 140:97feb9bacc10 417
<> 140:97feb9bacc10 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
<> 140:97feb9bacc10 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
<> 140:97feb9bacc10 420
<> 140:97feb9bacc10 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
<> 140:97feb9bacc10 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
<> 140:97feb9bacc10 423
<> 140:97feb9bacc10 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
<> 140:97feb9bacc10 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
<> 140:97feb9bacc10 426
<> 140:97feb9bacc10 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
<> 140:97feb9bacc10 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
<> 140:97feb9bacc10 429
<> 140:97feb9bacc10 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
<> 140:97feb9bacc10 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
<> 140:97feb9bacc10 432
<> 140:97feb9bacc10 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
<> 140:97feb9bacc10 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
<> 140:97feb9bacc10 435
<> 140:97feb9bacc10 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
<> 140:97feb9bacc10 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
<> 140:97feb9bacc10 438
<> 140:97feb9bacc10 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
<> 140:97feb9bacc10 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
<> 140:97feb9bacc10 441
<> 140:97feb9bacc10 442 #if (__VTOR_PRESENT == 1)
<> 140:97feb9bacc10 443 /* SCB Interrupt Control State Register Definitions */
<> 140:97feb9bacc10 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
<> 140:97feb9bacc10 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
<> 140:97feb9bacc10 446 #endif
<> 140:97feb9bacc10 447
<> 140:97feb9bacc10 448 /* SCB Application Interrupt and Reset Control Register Definitions */
<> 140:97feb9bacc10 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
<> 140:97feb9bacc10 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
<> 140:97feb9bacc10 451
<> 140:97feb9bacc10 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
<> 140:97feb9bacc10 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
<> 140:97feb9bacc10 454
<> 140:97feb9bacc10 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
<> 140:97feb9bacc10 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
<> 140:97feb9bacc10 457
<> 140:97feb9bacc10 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
<> 140:97feb9bacc10 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
<> 140:97feb9bacc10 460
<> 140:97feb9bacc10 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
<> 140:97feb9bacc10 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
<> 140:97feb9bacc10 463
<> 140:97feb9bacc10 464 /* SCB System Control Register Definitions */
<> 140:97feb9bacc10 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
<> 140:97feb9bacc10 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
<> 140:97feb9bacc10 467
<> 140:97feb9bacc10 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
<> 140:97feb9bacc10 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
<> 140:97feb9bacc10 470
<> 140:97feb9bacc10 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
<> 140:97feb9bacc10 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
<> 140:97feb9bacc10 473
<> 140:97feb9bacc10 474 /* SCB Configuration Control Register Definitions */
<> 140:97feb9bacc10 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
<> 140:97feb9bacc10 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
<> 140:97feb9bacc10 477
<> 140:97feb9bacc10 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
<> 140:97feb9bacc10 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
<> 140:97feb9bacc10 480
<> 140:97feb9bacc10 481 /* SCB System Handler Control and State Register Definitions */
<> 140:97feb9bacc10 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
<> 140:97feb9bacc10 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
<> 140:97feb9bacc10 484
<> 140:97feb9bacc10 485 /*@} end of group CMSIS_SCB */
<> 140:97feb9bacc10 486
<> 140:97feb9bacc10 487
<> 140:97feb9bacc10 488 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
<> 140:97feb9bacc10 490 \brief Type definitions for the System Timer Registers.
<> 140:97feb9bacc10 491 @{
<> 140:97feb9bacc10 492 */
<> 140:97feb9bacc10 493
<> 140:97feb9bacc10 494 /** \brief Structure type to access the System Timer (SysTick).
<> 140:97feb9bacc10 495 */
<> 140:97feb9bacc10 496 typedef struct
<> 140:97feb9bacc10 497 {
<> 140:97feb9bacc10 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
<> 140:97feb9bacc10 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
<> 140:97feb9bacc10 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
<> 140:97feb9bacc10 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
<> 140:97feb9bacc10 502 } SysTick_Type;
<> 140:97feb9bacc10 503
<> 140:97feb9bacc10 504 /* SysTick Control / Status Register Definitions */
<> 140:97feb9bacc10 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
<> 140:97feb9bacc10 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
<> 140:97feb9bacc10 507
<> 140:97feb9bacc10 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
<> 140:97feb9bacc10 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
<> 140:97feb9bacc10 510
<> 140:97feb9bacc10 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
<> 140:97feb9bacc10 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
<> 140:97feb9bacc10 513
<> 140:97feb9bacc10 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
<> 140:97feb9bacc10 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
<> 140:97feb9bacc10 516
<> 140:97feb9bacc10 517 /* SysTick Reload Register Definitions */
<> 140:97feb9bacc10 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
<> 140:97feb9bacc10 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
<> 140:97feb9bacc10 520
<> 140:97feb9bacc10 521 /* SysTick Current Register Definitions */
<> 140:97feb9bacc10 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
<> 140:97feb9bacc10 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
<> 140:97feb9bacc10 524
<> 140:97feb9bacc10 525 /* SysTick Calibration Register Definitions */
<> 140:97feb9bacc10 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
<> 140:97feb9bacc10 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
<> 140:97feb9bacc10 528
<> 140:97feb9bacc10 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
<> 140:97feb9bacc10 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
<> 140:97feb9bacc10 531
<> 140:97feb9bacc10 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
<> 140:97feb9bacc10 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
<> 140:97feb9bacc10 534
<> 140:97feb9bacc10 535 /*@} end of group CMSIS_SysTick */
<> 140:97feb9bacc10 536
<> 140:97feb9bacc10 537 #if (__MPU_PRESENT == 1)
<> 140:97feb9bacc10 538 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
<> 140:97feb9bacc10 540 \brief Type definitions for the Memory Protection Unit (MPU)
<> 140:97feb9bacc10 541 @{
<> 140:97feb9bacc10 542 */
<> 140:97feb9bacc10 543
<> 140:97feb9bacc10 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
<> 140:97feb9bacc10 545 */
<> 140:97feb9bacc10 546 typedef struct
<> 140:97feb9bacc10 547 {
<> 140:97feb9bacc10 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
<> 140:97feb9bacc10 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
<> 140:97feb9bacc10 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
<> 140:97feb9bacc10 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
<> 140:97feb9bacc10 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
<> 140:97feb9bacc10 553 } MPU_Type;
<> 140:97feb9bacc10 554
<> 140:97feb9bacc10 555 /* MPU Type Register */
<> 140:97feb9bacc10 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
<> 140:97feb9bacc10 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
<> 140:97feb9bacc10 558
<> 140:97feb9bacc10 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
<> 140:97feb9bacc10 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
<> 140:97feb9bacc10 561
<> 140:97feb9bacc10 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
<> 140:97feb9bacc10 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
<> 140:97feb9bacc10 564
<> 140:97feb9bacc10 565 /* MPU Control Register */
<> 140:97feb9bacc10 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
<> 140:97feb9bacc10 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
<> 140:97feb9bacc10 568
<> 140:97feb9bacc10 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
<> 140:97feb9bacc10 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
<> 140:97feb9bacc10 571
<> 140:97feb9bacc10 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
<> 140:97feb9bacc10 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
<> 140:97feb9bacc10 574
<> 140:97feb9bacc10 575 /* MPU Region Number Register */
<> 140:97feb9bacc10 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
<> 140:97feb9bacc10 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
<> 140:97feb9bacc10 578
<> 140:97feb9bacc10 579 /* MPU Region Base Address Register */
<> 140:97feb9bacc10 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
<> 140:97feb9bacc10 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
<> 140:97feb9bacc10 582
<> 140:97feb9bacc10 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
<> 140:97feb9bacc10 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
<> 140:97feb9bacc10 585
<> 140:97feb9bacc10 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
<> 140:97feb9bacc10 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
<> 140:97feb9bacc10 588
<> 140:97feb9bacc10 589 /* MPU Region Attribute and Size Register */
<> 140:97feb9bacc10 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
<> 140:97feb9bacc10 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
<> 140:97feb9bacc10 592
<> 140:97feb9bacc10 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
<> 140:97feb9bacc10 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
<> 140:97feb9bacc10 595
<> 140:97feb9bacc10 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
<> 140:97feb9bacc10 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
<> 140:97feb9bacc10 598
<> 140:97feb9bacc10 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
<> 140:97feb9bacc10 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
<> 140:97feb9bacc10 601
<> 140:97feb9bacc10 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
<> 140:97feb9bacc10 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
<> 140:97feb9bacc10 604
<> 140:97feb9bacc10 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
<> 140:97feb9bacc10 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
<> 140:97feb9bacc10 607
<> 140:97feb9bacc10 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
<> 140:97feb9bacc10 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
<> 140:97feb9bacc10 610
<> 140:97feb9bacc10 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
<> 140:97feb9bacc10 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
<> 140:97feb9bacc10 613
<> 140:97feb9bacc10 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
<> 140:97feb9bacc10 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
<> 140:97feb9bacc10 616
<> 140:97feb9bacc10 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
<> 140:97feb9bacc10 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
<> 140:97feb9bacc10 619
<> 140:97feb9bacc10 620 /*@} end of group CMSIS_MPU */
<> 140:97feb9bacc10 621 #endif
<> 140:97feb9bacc10 622
<> 140:97feb9bacc10 623
<> 140:97feb9bacc10 624 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
<> 140:97feb9bacc10 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
<> 140:97feb9bacc10 627 are only accessible over DAP and not via processor. Therefore
<> 140:97feb9bacc10 628 they are not covered by the Cortex-M0 header file.
<> 140:97feb9bacc10 629 @{
<> 140:97feb9bacc10 630 */
<> 140:97feb9bacc10 631 /*@} end of group CMSIS_CoreDebug */
<> 140:97feb9bacc10 632
<> 140:97feb9bacc10 633
<> 140:97feb9bacc10 634 /** \ingroup CMSIS_core_register
<> 140:97feb9bacc10 635 \defgroup CMSIS_core_base Core Definitions
<> 140:97feb9bacc10 636 \brief Definitions for base addresses, unions, and structures.
<> 140:97feb9bacc10 637 @{
<> 140:97feb9bacc10 638 */
<> 140:97feb9bacc10 639
<> 140:97feb9bacc10 640 /* Memory mapping of Cortex-M0+ Hardware */
<> 140:97feb9bacc10 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
<> 140:97feb9bacc10 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
<> 140:97feb9bacc10 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
<> 140:97feb9bacc10 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
<> 140:97feb9bacc10 645
<> 140:97feb9bacc10 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
<> 140:97feb9bacc10 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
<> 140:97feb9bacc10 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
<> 140:97feb9bacc10 649
<> 140:97feb9bacc10 650 #if (__MPU_PRESENT == 1)
<> 140:97feb9bacc10 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
<> 140:97feb9bacc10 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
<> 140:97feb9bacc10 653 #endif
<> 140:97feb9bacc10 654
<> 140:97feb9bacc10 655 /*@} */
<> 140:97feb9bacc10 656
<> 140:97feb9bacc10 657
<> 140:97feb9bacc10 658
<> 140:97feb9bacc10 659 /*******************************************************************************
<> 140:97feb9bacc10 660 * Hardware Abstraction Layer
<> 140:97feb9bacc10 661 Core Function Interface contains:
<> 140:97feb9bacc10 662 - Core NVIC Functions
<> 140:97feb9bacc10 663 - Core SysTick Functions
<> 140:97feb9bacc10 664 - Core Register Access Functions
<> 140:97feb9bacc10 665 ******************************************************************************/
<> 140:97feb9bacc10 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
<> 140:97feb9bacc10 667 */
<> 140:97feb9bacc10 668
<> 140:97feb9bacc10 669
<> 140:97feb9bacc10 670
<> 140:97feb9bacc10 671 /* ########################## NVIC functions #################################### */
<> 140:97feb9bacc10 672 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
<> 140:97feb9bacc10 674 \brief Functions that manage interrupts and exceptions via the NVIC.
<> 140:97feb9bacc10 675 @{
<> 140:97feb9bacc10 676 */
<> 140:97feb9bacc10 677
<> 140:97feb9bacc10 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
<> 140:97feb9bacc10 679 /* The following MACROS handle generation of the register offset and byte masks */
<> 140:97feb9bacc10 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
<> 140:97feb9bacc10 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
<> 140:97feb9bacc10 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
<> 140:97feb9bacc10 683
<> 140:97feb9bacc10 684
<> 140:97feb9bacc10 685 /** \brief Enable External Interrupt
<> 140:97feb9bacc10 686
<> 140:97feb9bacc10 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
<> 140:97feb9bacc10 688
<> 140:97feb9bacc10 689 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 690 */
<> 140:97feb9bacc10 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 692 {
<> 140:97feb9bacc10 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 694 }
<> 140:97feb9bacc10 695
<> 140:97feb9bacc10 696
<> 140:97feb9bacc10 697 /** \brief Disable External Interrupt
<> 140:97feb9bacc10 698
<> 140:97feb9bacc10 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
<> 140:97feb9bacc10 700
<> 140:97feb9bacc10 701 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 702 */
<> 140:97feb9bacc10 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 704 {
<> 140:97feb9bacc10 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 706 __DSB();
<> 140:97feb9bacc10 707 __ISB();
<> 140:97feb9bacc10 708 }
<> 140:97feb9bacc10 709
<> 140:97feb9bacc10 710
<> 140:97feb9bacc10 711 /** \brief Get Pending Interrupt
<> 140:97feb9bacc10 712
<> 140:97feb9bacc10 713 The function reads the pending register in the NVIC and returns the pending bit
<> 140:97feb9bacc10 714 for the specified interrupt.
<> 140:97feb9bacc10 715
<> 140:97feb9bacc10 716 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 717
<> 140:97feb9bacc10 718 \return 0 Interrupt status is not pending.
<> 140:97feb9bacc10 719 \return 1 Interrupt status is pending.
<> 140:97feb9bacc10 720 */
<> 140:97feb9bacc10 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 722 {
<> 140:97feb9bacc10 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
<> 140:97feb9bacc10 724 }
<> 140:97feb9bacc10 725
<> 140:97feb9bacc10 726
<> 140:97feb9bacc10 727 /** \brief Set Pending Interrupt
<> 140:97feb9bacc10 728
<> 140:97feb9bacc10 729 The function sets the pending bit of an external interrupt.
<> 140:97feb9bacc10 730
<> 140:97feb9bacc10 731 \param [in] IRQn Interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 732 */
<> 140:97feb9bacc10 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 734 {
<> 140:97feb9bacc10 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 736 }
<> 140:97feb9bacc10 737
<> 140:97feb9bacc10 738
<> 140:97feb9bacc10 739 /** \brief Clear Pending Interrupt
<> 140:97feb9bacc10 740
<> 140:97feb9bacc10 741 The function clears the pending bit of an external interrupt.
<> 140:97feb9bacc10 742
<> 140:97feb9bacc10 743 \param [in] IRQn External interrupt number. Value cannot be negative.
<> 140:97feb9bacc10 744 */
<> 140:97feb9bacc10 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 140:97feb9bacc10 746 {
<> 140:97feb9bacc10 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 140:97feb9bacc10 748 }
<> 140:97feb9bacc10 749
<> 140:97feb9bacc10 750
<> 140:97feb9bacc10 751 /** \brief Set Interrupt Priority
<> 140:97feb9bacc10 752
<> 140:97feb9bacc10 753 The function sets the priority of an interrupt.
<> 140:97feb9bacc10 754
<> 140:97feb9bacc10 755 \note The priority cannot be set for every core interrupt.
<> 140:97feb9bacc10 756
<> 140:97feb9bacc10 757 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 758 \param [in] priority Priority to set.
<> 140:97feb9bacc10 759 */
<> 140:97feb9bacc10 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
<> 140:97feb9bacc10 761 {
<> 140:97feb9bacc10 762 if((int32_t)(IRQn) < 0) {
<> 140:97feb9bacc10 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 140:97feb9bacc10 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 140:97feb9bacc10 765 }
<> 140:97feb9bacc10 766 else {
<> 140:97feb9bacc10 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
<> 140:97feb9bacc10 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
<> 140:97feb9bacc10 769 }
<> 140:97feb9bacc10 770 }
<> 140:97feb9bacc10 771
<> 140:97feb9bacc10 772
<> 140:97feb9bacc10 773 /** \brief Get Interrupt Priority
<> 140:97feb9bacc10 774
<> 140:97feb9bacc10 775 The function reads the priority of an interrupt. The interrupt
<> 140:97feb9bacc10 776 number can be positive to specify an external (device specific)
<> 140:97feb9bacc10 777 interrupt, or negative to specify an internal (core) interrupt.
<> 140:97feb9bacc10 778
<> 140:97feb9bacc10 779
<> 140:97feb9bacc10 780 \param [in] IRQn Interrupt number.
<> 140:97feb9bacc10 781 \return Interrupt Priority. Value is aligned automatically to the implemented
<> 140:97feb9bacc10 782 priority bits of the microcontroller.
<> 140:97feb9bacc10 783 */
<> 140:97feb9bacc10 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
<> 140:97feb9bacc10 785 {
<> 140:97feb9bacc10 786
<> 140:97feb9bacc10 787 if((int32_t)(IRQn) < 0) {
<> 140:97feb9bacc10 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 140:97feb9bacc10 789 }
<> 140:97feb9bacc10 790 else {
<> 140:97feb9bacc10 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
<> 140:97feb9bacc10 792 }
<> 140:97feb9bacc10 793 }
<> 140:97feb9bacc10 794
<> 140:97feb9bacc10 795
<> 140:97feb9bacc10 796 /** \brief System Reset
<> 140:97feb9bacc10 797
<> 140:97feb9bacc10 798 The function initiates a system reset request to reset the MCU.
<> 140:97feb9bacc10 799 */
<> 140:97feb9bacc10 800 __STATIC_INLINE void NVIC_SystemReset(void)
<> 140:97feb9bacc10 801 {
<> 140:97feb9bacc10 802 __DSB(); /* Ensure all outstanding memory accesses included
<> 140:97feb9bacc10 803 buffered write are completed before reset */
<> 140:97feb9bacc10 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
<> 140:97feb9bacc10 805 SCB_AIRCR_SYSRESETREQ_Msk);
<> 140:97feb9bacc10 806 __DSB(); /* Ensure completion of memory access */
<> 140:97feb9bacc10 807 while(1) { __NOP(); } /* wait until reset */
<> 140:97feb9bacc10 808 }
<> 140:97feb9bacc10 809
<> 140:97feb9bacc10 810 /*@} end of CMSIS_Core_NVICFunctions */
<> 140:97feb9bacc10 811
<> 140:97feb9bacc10 812
<> 140:97feb9bacc10 813
<> 140:97feb9bacc10 814 /* ################################## SysTick function ############################################ */
<> 140:97feb9bacc10 815 /** \ingroup CMSIS_Core_FunctionInterface
<> 140:97feb9bacc10 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
<> 140:97feb9bacc10 817 \brief Functions that configure the System.
<> 140:97feb9bacc10 818 @{
<> 140:97feb9bacc10 819 */
<> 140:97feb9bacc10 820
<> 140:97feb9bacc10 821 #if (__Vendor_SysTickConfig == 0)
<> 140:97feb9bacc10 822
<> 140:97feb9bacc10 823 /** \brief System Tick Configuration
<> 140:97feb9bacc10 824
<> 140:97feb9bacc10 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 140:97feb9bacc10 826 Counter is in free running mode to generate periodic interrupts.
<> 140:97feb9bacc10 827
<> 140:97feb9bacc10 828 \param [in] ticks Number of ticks between two interrupts.
<> 140:97feb9bacc10 829
<> 140:97feb9bacc10 830 \return 0 Function succeeded.
<> 140:97feb9bacc10 831 \return 1 Function failed.
<> 140:97feb9bacc10 832
<> 140:97feb9bacc10 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
<> 140:97feb9bacc10 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
<> 140:97feb9bacc10 835 must contain a vendor-specific implementation of this function.
<> 140:97feb9bacc10 836
<> 140:97feb9bacc10 837 */
<> 140:97feb9bacc10 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
<> 140:97feb9bacc10 839 {
<> 140:97feb9bacc10 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
<> 140:97feb9bacc10 841
<> 140:97feb9bacc10 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
<> 140:97feb9bacc10 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
<> 140:97feb9bacc10 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
<> 140:97feb9bacc10 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
<> 140:97feb9bacc10 846 SysTick_CTRL_TICKINT_Msk |
<> 140:97feb9bacc10 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
<> 140:97feb9bacc10 848 return (0UL); /* Function successful */
<> 140:97feb9bacc10 849 }
<> 140:97feb9bacc10 850
<> 140:97feb9bacc10 851 #endif
<> 140:97feb9bacc10 852
<> 140:97feb9bacc10 853 /*@} end of CMSIS_Core_SysTickFunctions */
<> 140:97feb9bacc10 854
<> 140:97feb9bacc10 855
<> 140:97feb9bacc10 856
<> 140:97feb9bacc10 857
<> 140:97feb9bacc10 858 #ifdef __cplusplus
<> 140:97feb9bacc10 859 }
<> 140:97feb9bacc10 860 #endif
<> 140:97feb9bacc10 861
<> 140:97feb9bacc10 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
<> 140:97feb9bacc10 863
<> 140:97feb9bacc10 864 #endif /* __CMSIS_GENERIC */