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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_MPS2_M4/core_cm0plus.h@140:97feb9bacc10, 2017-04-12 (annotated)

Committer:
<>
Date:
Wed Apr 12 16:07:08 2017 +0100
Revision:
140:97feb9bacc10
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 140 of the mbed library



Ports for Upcoming Targets



3841: Add nRf52840 target https://github.com/ARMmbed/mbed-os/pull/3841

3992: Introducing UBLOX_C030 platform. https://github.com/ARMmbed/mbed-os/pull/3992



Fixes and Changes



3951: [NUCLEO_F303ZE] Correct ARDUINO pin https://github.com/ARMmbed/mbed-os/pull/3951

4021: Fixing a macro to detect when RTOS was in use for the NRF52840_DK https://github.com/ARMmbed/mbed-os/pull/4021

3979: KW24D: Add missing SPI defines and Arduino connector definitions https://github.com/ARMmbed/mbed-os/pull/3979

3990: UBLOX_C027: construct a ticker-based wait, rather than calling wait_ms(), in the  https://github.com/ARMmbed/mbed-os/pull/3990

4003: Fixed OBOE in async serial tx for NRF52 target, fixes #4002 https://github.com/ARMmbed/mbed-os/pull/4003

4012: STM32: Correct I2C master error handling https://github.com/ARMmbed/mbed-os/pull/4012

4020: NUCLEO_L011K4 remove unsupported tool chain files https://github.com/ARMmbed/mbed-os/pull/4020

4065: K66F: Move bss section to m_data_2 Section https://github.com/ARMmbed/mbed-os/pull/4065

4014: Issue 3763: Reduce heap allocation in the GCC linker file https://github.com/ARMmbed/mbed-os/pull/4014

4030: [STM32L0] reduce IAR heap and stack size for small targets https://github.com/ARMmbed/mbed-os/pull/4030

4109: NUCLEO_L476RG : minor serial pin update https://github.com/ARMmbed/mbed-os/pull/4109

3982: Ticker - kl25z bugfix for handling events in the past https://github.com/ARMmbed/mbed-os/pull/3982

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**************************************************************************//**
Kojto 101:7cff1c4259d7 2 * @file core_cm0plus.h
Kojto 101:7cff1c4259d7 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 101:7cff1c4259d7 6 *
Kojto 101:7cff1c4259d7 7 * @note
Kojto 101:7cff1c4259d7 8 *
Kojto 101:7cff1c4259d7 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 101:7cff1c4259d7 11
Kojto 101:7cff1c4259d7 12 All rights reserved.
Kojto 101:7cff1c4259d7 13 Redistribution and use in source and binary forms, with or without
Kojto 101:7cff1c4259d7 14 modification, are permitted provided that the following conditions are met:
Kojto 101:7cff1c4259d7 15 - Redistributions of source code must retain the above copyright
Kojto 101:7cff1c4259d7 16 notice, this list of conditions and the following disclaimer.
Kojto 101:7cff1c4259d7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 101:7cff1c4259d7 18 notice, this list of conditions and the following disclaimer in the
Kojto 101:7cff1c4259d7 19 documentation and/or other materials provided with the distribution.
Kojto 101:7cff1c4259d7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 101:7cff1c4259d7 21 to endorse or promote products derived from this software without
Kojto 101:7cff1c4259d7 22 specific prior written permission.
Kojto 101:7cff1c4259d7 23 *
Kojto 101:7cff1c4259d7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 101:7cff1c4259d7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 101:7cff1c4259d7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 101:7cff1c4259d7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 101:7cff1c4259d7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 101:7cff1c4259d7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 101:7cff1c4259d7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 101:7cff1c4259d7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 101:7cff1c4259d7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 101:7cff1c4259d7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 101:7cff1c4259d7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 101:7cff1c4259d7 35 ---------------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 #if defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 101:7cff1c4259d7 40 #endif
Kojto 101:7cff1c4259d7 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 101:7cff1c4259d7 45 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 46 extern "C" {
Kojto 101:7cff1c4259d7 47 #endif
Kojto 101:7cff1c4259d7 48
Kojto 101:7cff1c4259d7 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 101:7cff1c4259d7 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 101:7cff1c4259d7 51
Kojto 101:7cff1c4259d7 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 101:7cff1c4259d7 53 Function definitions in header files are used to allow 'inlining'.
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 101:7cff1c4259d7 56 Unions are used for effective representation of core registers.
Kojto 101:7cff1c4259d7 57
Kojto 101:7cff1c4259d7 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 101:7cff1c4259d7 59 Function-like macros are used to allow more efficient code.
Kojto 101:7cff1c4259d7 60 */
Kojto 101:7cff1c4259d7 61
Kojto 101:7cff1c4259d7 62
Kojto 101:7cff1c4259d7 63 /*******************************************************************************
Kojto 101:7cff1c4259d7 64 * CMSIS definitions
Kojto 101:7cff1c4259d7 65 ******************************************************************************/
Kojto 101:7cff1c4259d7 66 /** \ingroup Cortex-M0+
Kojto 101:7cff1c4259d7 67 @{
Kojto 101:7cff1c4259d7 68 */
Kojto 101:7cff1c4259d7 69
Kojto 101:7cff1c4259d7 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 101:7cff1c4259d7 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 101:7cff1c4259d7 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 101:7cff1c4259d7 75
Kojto 101:7cff1c4259d7 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 101:7cff1c4259d7 77
Kojto 101:7cff1c4259d7 78
Kojto 101:7cff1c4259d7 79 #if defined ( __CC_ARM )
Kojto 101:7cff1c4259d7 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 101:7cff1c4259d7 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 101:7cff1c4259d7 82 #define __STATIC_INLINE static __inline
Kojto 101:7cff1c4259d7 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 101:7cff1c4259d7 89 #elif defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 101:7cff1c4259d7 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 101:7cff1c4259d7 92 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 101:7cff1c4259d7 96 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 97
Kojto 101:7cff1c4259d7 98 #elif defined ( __TASKING__ )
Kojto 101:7cff1c4259d7 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 101:7cff1c4259d7 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 101:7cff1c4259d7 101 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 101:7cff1c4259d7 109 #endif
Kojto 101:7cff1c4259d7 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 101:7cff1c4259d7 113 */
Kojto 101:7cff1c4259d7 114 #define __FPU_USED 0
Kojto 101:7cff1c4259d7 115
Kojto 101:7cff1c4259d7 116 #if defined ( __CC_ARM )
Kojto 101:7cff1c4259d7 117 #if defined __TARGET_FPU_VFP
Kojto 101:7cff1c4259d7 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 119 #endif
Kojto 101:7cff1c4259d7 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 101:7cff1c4259d7 126 #elif defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 127 #if defined __ARMVFP__
Kojto 101:7cff1c4259d7 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 129 #endif
Kojto 101:7cff1c4259d7 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 101:7cff1c4259d7 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 134 #endif
Kojto 101:7cff1c4259d7 135
Kojto 101:7cff1c4259d7 136 #elif defined ( __TASKING__ )
Kojto 101:7cff1c4259d7 137 #if defined __FPU_VFP__
Kojto 101:7cff1c4259d7 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 101:7cff1c4259d7 145 #endif
Kojto 101:7cff1c4259d7 146
Kojto 101:7cff1c4259d7 147 #include <stdint.h> /* standard types definitions */
Kojto 101:7cff1c4259d7 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 101:7cff1c4259d7 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 101:7cff1c4259d7 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 101:7cff1c4259d7 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 101:7cff1c4259d7 156
Kojto 101:7cff1c4259d7 157 #ifndef __CMSIS_GENERIC
Kojto 101:7cff1c4259d7 158
Kojto 101:7cff1c4259d7 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 101:7cff1c4259d7 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 101:7cff1c4259d7 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 101:7cff1c4259d7 166 /* check device defines and use defaults */
Kojto 101:7cff1c4259d7 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 101:7cff1c4259d7 168 #ifndef __CM0PLUS_REV
Kojto 101:7cff1c4259d7 169 #define __CM0PLUS_REV 0x0000
Kojto 101:7cff1c4259d7 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 171 #endif
Kojto 101:7cff1c4259d7 172
Kojto 101:7cff1c4259d7 173 #ifndef __MPU_PRESENT
Kojto 101:7cff1c4259d7 174 #define __MPU_PRESENT 0
Kojto 101:7cff1c4259d7 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 176 #endif
Kojto 101:7cff1c4259d7 177
Kojto 101:7cff1c4259d7 178 #ifndef __VTOR_PRESENT
Kojto 101:7cff1c4259d7 179 #define __VTOR_PRESENT 0
Kojto 101:7cff1c4259d7 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 181 #endif
Kojto 101:7cff1c4259d7 182
Kojto 101:7cff1c4259d7 183 #ifndef __NVIC_PRIO_BITS
Kojto 101:7cff1c4259d7 184 #define __NVIC_PRIO_BITS 2
Kojto 101:7cff1c4259d7 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 186 #endif
Kojto 101:7cff1c4259d7 187
Kojto 101:7cff1c4259d7 188 #ifndef __Vendor_SysTickConfig
Kojto 101:7cff1c4259d7 189 #define __Vendor_SysTickConfig 0
Kojto 101:7cff1c4259d7 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 191 #endif
Kojto 101:7cff1c4259d7 192 #endif
Kojto 101:7cff1c4259d7 193
Kojto 101:7cff1c4259d7 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 101:7cff1c4259d7 195 /**
Kojto 101:7cff1c4259d7 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 101:7cff1c4259d7 197
Kojto 101:7cff1c4259d7 198 <strong>IO Type Qualifiers</strong> are used
Kojto 101:7cff1c4259d7 199 \li to specify the access to peripheral variables.
Kojto 101:7cff1c4259d7 200 \li for automatic generation of peripheral register debug information.
Kojto 101:7cff1c4259d7 201 */
Kojto 101:7cff1c4259d7 202 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 101:7cff1c4259d7 204 #else
Kojto 101:7cff1c4259d7 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 101:7cff1c4259d7 206 #endif
Kojto 101:7cff1c4259d7 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 101:7cff1c4259d7 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 101:7cff1c4259d7 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
Kojto 101:7cff1c4259d7 218 /*@} end of group Cortex-M0+ */
Kojto 101:7cff1c4259d7 219
Kojto 101:7cff1c4259d7 220
Kojto 101:7cff1c4259d7 221
Kojto 101:7cff1c4259d7 222 /*******************************************************************************
Kojto 101:7cff1c4259d7 223 * Register Abstraction
Kojto 101:7cff1c4259d7 224 Core Register contain:
Kojto 101:7cff1c4259d7 225 - Core Register
Kojto 101:7cff1c4259d7 226 - Core NVIC Register
Kojto 101:7cff1c4259d7 227 - Core SCB Register
Kojto 101:7cff1c4259d7 228 - Core SysTick Register
Kojto 101:7cff1c4259d7 229 - Core MPU Register
Kojto 101:7cff1c4259d7 230 ******************************************************************************/
Kojto 101:7cff1c4259d7 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 101:7cff1c4259d7 232 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 101:7cff1c4259d7 233 */
Kojto 101:7cff1c4259d7 234
Kojto 101:7cff1c4259d7 235 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 236 \defgroup CMSIS_CORE Status and Control Registers
Kojto 101:7cff1c4259d7 237 \brief Core Register type definitions.
Kojto 101:7cff1c4259d7 238 @{
Kojto 101:7cff1c4259d7 239 */
Kojto 101:7cff1c4259d7 240
Kojto 101:7cff1c4259d7 241 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 101:7cff1c4259d7 242 */
Kojto 101:7cff1c4259d7 243 typedef union
Kojto 101:7cff1c4259d7 244 {
Kojto 101:7cff1c4259d7 245 struct
Kojto 101:7cff1c4259d7 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 101:7cff1c4259d7 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 101:7cff1c4259d7 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 101:7cff1c4259d7 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 101:7cff1c4259d7 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 101:7cff1c4259d7 252 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 253 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 254 } APSR_Type;
Kojto 101:7cff1c4259d7 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
Kojto 101:7cff1c4259d7 269
Kojto 101:7cff1c4259d7 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 101:7cff1c4259d7 271 */
Kojto 101:7cff1c4259d7 272 typedef union
Kojto 101:7cff1c4259d7 273 {
Kojto 101:7cff1c4259d7 274 struct
Kojto 101:7cff1c4259d7 275 {
Kojto 101:7cff1c4259d7 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 101:7cff1c4259d7 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 101:7cff1c4259d7 278 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 279 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 280 } IPSR_Type;
Kojto 101:7cff1c4259d7 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
Kojto 101:7cff1c4259d7 286
Kojto 101:7cff1c4259d7 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 101:7cff1c4259d7 288 */
Kojto 101:7cff1c4259d7 289 typedef union
Kojto 101:7cff1c4259d7 290 {
Kojto 101:7cff1c4259d7 291 struct
Kojto 101:7cff1c4259d7 292 {
Kojto 101:7cff1c4259d7 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 101:7cff1c4259d7 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 101:7cff1c4259d7 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 101:7cff1c4259d7 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 101:7cff1c4259d7 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 101:7cff1c4259d7 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 101:7cff1c4259d7 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 101:7cff1c4259d7 301 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 302 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 303 } xPSR_Type;
Kojto 101:7cff1c4259d7 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
Kojto 101:7cff1c4259d7 324
Kojto 101:7cff1c4259d7 325 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 101:7cff1c4259d7 326 */
Kojto 101:7cff1c4259d7 327 typedef union
Kojto 101:7cff1c4259d7 328 {
Kojto 101:7cff1c4259d7 329 struct
Kojto 101:7cff1c4259d7 330 {
Kojto 101:7cff1c4259d7 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 101:7cff1c4259d7 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 101:7cff1c4259d7 334 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 335 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 336 } CONTROL_Type;
Kojto 101:7cff1c4259d7 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
Kojto 101:7cff1c4259d7 345 /*@} end of group CMSIS_CORE */
Kojto 101:7cff1c4259d7 346
Kojto 101:7cff1c4259d7 347
Kojto 101:7cff1c4259d7 348 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 101:7cff1c4259d7 350 \brief Type definitions for the NVIC Registers
Kojto 101:7cff1c4259d7 351 @{
Kojto 101:7cff1c4259d7 352 */
Kojto 101:7cff1c4259d7 353
Kojto 101:7cff1c4259d7 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 101:7cff1c4259d7 355 */
Kojto 101:7cff1c4259d7 356 typedef struct
Kojto 101:7cff1c4259d7 357 {
Kojto 101:7cff1c4259d7 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 101:7cff1c4259d7 359 uint32_t RESERVED0[31];
Kojto 101:7cff1c4259d7 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 101:7cff1c4259d7 361 uint32_t RSERVED1[31];
Kojto 101:7cff1c4259d7 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 101:7cff1c4259d7 363 uint32_t RESERVED2[31];
Kojto 101:7cff1c4259d7 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 101:7cff1c4259d7 365 uint32_t RESERVED3[31];
Kojto 101:7cff1c4259d7 366 uint32_t RESERVED4[64];
Kojto 101:7cff1c4259d7 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 101:7cff1c4259d7 368 } NVIC_Type;
Kojto 101:7cff1c4259d7 369
Kojto 101:7cff1c4259d7 370 /*@} end of group CMSIS_NVIC */
Kojto 101:7cff1c4259d7 371
Kojto 101:7cff1c4259d7 372
Kojto 101:7cff1c4259d7 373 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 374 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 101:7cff1c4259d7 375 \brief Type definitions for the System Control Block Registers
Kojto 101:7cff1c4259d7 376 @{
Kojto 101:7cff1c4259d7 377 */
Kojto 101:7cff1c4259d7 378
Kojto 101:7cff1c4259d7 379 /** \brief Structure type to access the System Control Block (SCB).
Kojto 101:7cff1c4259d7 380 */
Kojto 101:7cff1c4259d7 381 typedef struct
Kojto 101:7cff1c4259d7 382 {
Kojto 101:7cff1c4259d7 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 101:7cff1c4259d7 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 101:7cff1c4259d7 385 #if (__VTOR_PRESENT == 1)
Kojto 101:7cff1c4259d7 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 101:7cff1c4259d7 387 #else
Kojto 101:7cff1c4259d7 388 uint32_t RESERVED0;
Kojto 101:7cff1c4259d7 389 #endif
Kojto 101:7cff1c4259d7 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 101:7cff1c4259d7 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 101:7cff1c4259d7 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 101:7cff1c4259d7 393 uint32_t RESERVED1;
Kojto 101:7cff1c4259d7 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 101:7cff1c4259d7 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 101:7cff1c4259d7 396 } SCB_Type;
Kojto 101:7cff1c4259d7 397
Kojto 101:7cff1c4259d7 398 /* SCB CPUID Register Definitions */
Kojto 101:7cff1c4259d7 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 101:7cff1c4259d7 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 101:7cff1c4259d7 401
Kojto 101:7cff1c4259d7 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 101:7cff1c4259d7 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 101:7cff1c4259d7 404
Kojto 101:7cff1c4259d7 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 101:7cff1c4259d7 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 101:7cff1c4259d7 407
Kojto 101:7cff1c4259d7 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 101:7cff1c4259d7 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 101:7cff1c4259d7 410
Kojto 101:7cff1c4259d7 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 101:7cff1c4259d7 413
Kojto 101:7cff1c4259d7 414 /* SCB Interrupt Control State Register Definitions */
Kojto 101:7cff1c4259d7 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 101:7cff1c4259d7 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 101:7cff1c4259d7 417
Kojto 101:7cff1c4259d7 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 101:7cff1c4259d7 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 101:7cff1c4259d7 420
Kojto 101:7cff1c4259d7 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 101:7cff1c4259d7 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 101:7cff1c4259d7 423
Kojto 101:7cff1c4259d7 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 101:7cff1c4259d7 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 101:7cff1c4259d7 426
Kojto 101:7cff1c4259d7 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 101:7cff1c4259d7 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 101:7cff1c4259d7 429
Kojto 101:7cff1c4259d7 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 101:7cff1c4259d7 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 101:7cff1c4259d7 432
Kojto 101:7cff1c4259d7 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 101:7cff1c4259d7 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 101:7cff1c4259d7 435
Kojto 101:7cff1c4259d7 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 101:7cff1c4259d7 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 101:7cff1c4259d7 438
Kojto 101:7cff1c4259d7 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 101:7cff1c4259d7 441
Kojto 101:7cff1c4259d7 442 #if (__VTOR_PRESENT == 1)
Kojto 101:7cff1c4259d7 443 /* SCB Interrupt Control State Register Definitions */
Kojto 101:7cff1c4259d7 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 101:7cff1c4259d7 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 101:7cff1c4259d7 446 #endif
Kojto 101:7cff1c4259d7 447
Kojto 101:7cff1c4259d7 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 101:7cff1c4259d7 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 101:7cff1c4259d7 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 101:7cff1c4259d7 451
Kojto 101:7cff1c4259d7 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 101:7cff1c4259d7 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 101:7cff1c4259d7 454
Kojto 101:7cff1c4259d7 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 101:7cff1c4259d7 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 101:7cff1c4259d7 457
Kojto 101:7cff1c4259d7 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 101:7cff1c4259d7 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 101:7cff1c4259d7 460
Kojto 101:7cff1c4259d7 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 101:7cff1c4259d7 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 101:7cff1c4259d7 463
Kojto 101:7cff1c4259d7 464 /* SCB System Control Register Definitions */
Kojto 101:7cff1c4259d7 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 101:7cff1c4259d7 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 101:7cff1c4259d7 467
Kojto 101:7cff1c4259d7 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 101:7cff1c4259d7 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 101:7cff1c4259d7 470
Kojto 101:7cff1c4259d7 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 101:7cff1c4259d7 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 101:7cff1c4259d7 473
Kojto 101:7cff1c4259d7 474 /* SCB Configuration Control Register Definitions */
Kojto 101:7cff1c4259d7 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 101:7cff1c4259d7 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 101:7cff1c4259d7 477
Kojto 101:7cff1c4259d7 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 101:7cff1c4259d7 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 101:7cff1c4259d7 480
Kojto 101:7cff1c4259d7 481 /* SCB System Handler Control and State Register Definitions */
Kojto 101:7cff1c4259d7 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 101:7cff1c4259d7 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 101:7cff1c4259d7 484
Kojto 101:7cff1c4259d7 485 /*@} end of group CMSIS_SCB */
Kojto 101:7cff1c4259d7 486
Kojto 101:7cff1c4259d7 487
Kojto 101:7cff1c4259d7 488 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 101:7cff1c4259d7 490 \brief Type definitions for the System Timer Registers.
Kojto 101:7cff1c4259d7 491 @{
Kojto 101:7cff1c4259d7 492 */
Kojto 101:7cff1c4259d7 493
Kojto 101:7cff1c4259d7 494 /** \brief Structure type to access the System Timer (SysTick).
Kojto 101:7cff1c4259d7 495 */
Kojto 101:7cff1c4259d7 496 typedef struct
Kojto 101:7cff1c4259d7 497 {
Kojto 101:7cff1c4259d7 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 101:7cff1c4259d7 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 101:7cff1c4259d7 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 101:7cff1c4259d7 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 101:7cff1c4259d7 502 } SysTick_Type;
Kojto 101:7cff1c4259d7 503
Kojto 101:7cff1c4259d7 504 /* SysTick Control / Status Register Definitions */
Kojto 101:7cff1c4259d7 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 101:7cff1c4259d7 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 101:7cff1c4259d7 507
Kojto 101:7cff1c4259d7 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 101:7cff1c4259d7 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 101:7cff1c4259d7 510
Kojto 101:7cff1c4259d7 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 101:7cff1c4259d7 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 101:7cff1c4259d7 513
Kojto 101:7cff1c4259d7 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 101:7cff1c4259d7 516
Kojto 101:7cff1c4259d7 517 /* SysTick Reload Register Definitions */
Kojto 101:7cff1c4259d7 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 101:7cff1c4259d7 520
Kojto 101:7cff1c4259d7 521 /* SysTick Current Register Definitions */
Kojto 101:7cff1c4259d7 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 101:7cff1c4259d7 524
Kojto 101:7cff1c4259d7 525 /* SysTick Calibration Register Definitions */
Kojto 101:7cff1c4259d7 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 101:7cff1c4259d7 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 101:7cff1c4259d7 528
Kojto 101:7cff1c4259d7 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 101:7cff1c4259d7 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 101:7cff1c4259d7 531
Kojto 101:7cff1c4259d7 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 101:7cff1c4259d7 534
Kojto 101:7cff1c4259d7 535 /*@} end of group CMSIS_SysTick */
Kojto 101:7cff1c4259d7 536
Kojto 101:7cff1c4259d7 537 #if (__MPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 538 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 101:7cff1c4259d7 540 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 101:7cff1c4259d7 541 @{
Kojto 101:7cff1c4259d7 542 */
Kojto 101:7cff1c4259d7 543
Kojto 101:7cff1c4259d7 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 101:7cff1c4259d7 545 */
Kojto 101:7cff1c4259d7 546 typedef struct
Kojto 101:7cff1c4259d7 547 {
Kojto 101:7cff1c4259d7 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 101:7cff1c4259d7 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 101:7cff1c4259d7 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 101:7cff1c4259d7 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 101:7cff1c4259d7 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 101:7cff1c4259d7 553 } MPU_Type;
Kojto 101:7cff1c4259d7 554
Kojto 101:7cff1c4259d7 555 /* MPU Type Register */
Kojto 101:7cff1c4259d7 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 101:7cff1c4259d7 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 101:7cff1c4259d7 558
Kojto 101:7cff1c4259d7 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 101:7cff1c4259d7 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 101:7cff1c4259d7 561
Kojto 101:7cff1c4259d7 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 101:7cff1c4259d7 564
Kojto 101:7cff1c4259d7 565 /* MPU Control Register */
Kojto 101:7cff1c4259d7 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 101:7cff1c4259d7 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 101:7cff1c4259d7 568
Kojto 101:7cff1c4259d7 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 101:7cff1c4259d7 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 101:7cff1c4259d7 571
Kojto 101:7cff1c4259d7 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 101:7cff1c4259d7 574
Kojto 101:7cff1c4259d7 575 /* MPU Region Number Register */
Kojto 101:7cff1c4259d7 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 101:7cff1c4259d7 578
Kojto 101:7cff1c4259d7 579 /* MPU Region Base Address Register */
Kojto 101:7cff1c4259d7 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 101:7cff1c4259d7 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 101:7cff1c4259d7 582
Kojto 101:7cff1c4259d7 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 101:7cff1c4259d7 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 101:7cff1c4259d7 585
Kojto 101:7cff1c4259d7 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 101:7cff1c4259d7 588
Kojto 101:7cff1c4259d7 589 /* MPU Region Attribute and Size Register */
Kojto 101:7cff1c4259d7 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 101:7cff1c4259d7 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 101:7cff1c4259d7 592
Kojto 101:7cff1c4259d7 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 101:7cff1c4259d7 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 101:7cff1c4259d7 595
Kojto 101:7cff1c4259d7 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 101:7cff1c4259d7 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 101:7cff1c4259d7 598
Kojto 101:7cff1c4259d7 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 101:7cff1c4259d7 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 101:7cff1c4259d7 601
Kojto 101:7cff1c4259d7 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 101:7cff1c4259d7 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 101:7cff1c4259d7 604
Kojto 101:7cff1c4259d7 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 101:7cff1c4259d7 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 101:7cff1c4259d7 607
Kojto 101:7cff1c4259d7 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 101:7cff1c4259d7 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 101:7cff1c4259d7 610
Kojto 101:7cff1c4259d7 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 101:7cff1c4259d7 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 101:7cff1c4259d7 613
Kojto 101:7cff1c4259d7 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 101:7cff1c4259d7 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 101:7cff1c4259d7 616
Kojto 101:7cff1c4259d7 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 101:7cff1c4259d7 619
Kojto 101:7cff1c4259d7 620 /*@} end of group CMSIS_MPU */
Kojto 101:7cff1c4259d7 621 #endif
Kojto 101:7cff1c4259d7 622
Kojto 101:7cff1c4259d7 623
Kojto 101:7cff1c4259d7 624 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 101:7cff1c4259d7 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 101:7cff1c4259d7 627 are only accessible over DAP and not via processor. Therefore
Kojto 101:7cff1c4259d7 628 they are not covered by the Cortex-M0 header file.
Kojto 101:7cff1c4259d7 629 @{
Kojto 101:7cff1c4259d7 630 */
Kojto 101:7cff1c4259d7 631 /*@} end of group CMSIS_CoreDebug */
Kojto 101:7cff1c4259d7 632
Kojto 101:7cff1c4259d7 633
Kojto 101:7cff1c4259d7 634 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 635 \defgroup CMSIS_core_base Core Definitions
Kojto 101:7cff1c4259d7 636 \brief Definitions for base addresses, unions, and structures.
Kojto 101:7cff1c4259d7 637 @{
Kojto 101:7cff1c4259d7 638 */
Kojto 101:7cff1c4259d7 639
Kojto 101:7cff1c4259d7 640 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 101:7cff1c4259d7 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 101:7cff1c4259d7 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 101:7cff1c4259d7 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 101:7cff1c4259d7 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 101:7cff1c4259d7 645
Kojto 101:7cff1c4259d7 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 101:7cff1c4259d7 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 101:7cff1c4259d7 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 101:7cff1c4259d7 649
Kojto 101:7cff1c4259d7 650 #if (__MPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 101:7cff1c4259d7 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 101:7cff1c4259d7 653 #endif
Kojto 101:7cff1c4259d7 654
Kojto 101:7cff1c4259d7 655 /*@} */
Kojto 101:7cff1c4259d7 656
Kojto 101:7cff1c4259d7 657
Kojto 101:7cff1c4259d7 658
Kojto 101:7cff1c4259d7 659 /*******************************************************************************
Kojto 101:7cff1c4259d7 660 * Hardware Abstraction Layer
Kojto 101:7cff1c4259d7 661 Core Function Interface contains:
Kojto 101:7cff1c4259d7 662 - Core NVIC Functions
Kojto 101:7cff1c4259d7 663 - Core SysTick Functions
Kojto 101:7cff1c4259d7 664 - Core Register Access Functions
Kojto 101:7cff1c4259d7 665 ******************************************************************************/
Kojto 101:7cff1c4259d7 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 101:7cff1c4259d7 667 */
Kojto 101:7cff1c4259d7 668
Kojto 101:7cff1c4259d7 669
Kojto 101:7cff1c4259d7 670
Kojto 101:7cff1c4259d7 671 /* ########################## NVIC functions #################################### */
Kojto 101:7cff1c4259d7 672 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 101:7cff1c4259d7 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 101:7cff1c4259d7 675 @{
Kojto 101:7cff1c4259d7 676 */
Kojto 101:7cff1c4259d7 677
Kojto 101:7cff1c4259d7 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 101:7cff1c4259d7 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 101:7cff1c4259d7 683
Kojto 101:7cff1c4259d7 684
Kojto 101:7cff1c4259d7 685 /** \brief Enable External Interrupt
Kojto 101:7cff1c4259d7 686
Kojto 101:7cff1c4259d7 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 101:7cff1c4259d7 688
Kojto 101:7cff1c4259d7 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 690 */
Kojto 101:7cff1c4259d7 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 101:7cff1c4259d7 694 }
Kojto 101:7cff1c4259d7 695
Kojto 101:7cff1c4259d7 696
Kojto 101:7cff1c4259d7 697 /** \brief Disable External Interrupt
Kojto 101:7cff1c4259d7 698
Kojto 101:7cff1c4259d7 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 101:7cff1c4259d7 700
Kojto 101:7cff1c4259d7 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 702 */
Kojto 101:7cff1c4259d7 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
Kojto 101:7cff1c4259d7 708 }
Kojto 101:7cff1c4259d7 709
Kojto 101:7cff1c4259d7 710
Kojto 101:7cff1c4259d7 711 /** \brief Get Pending Interrupt
Kojto 101:7cff1c4259d7 712
Kojto 101:7cff1c4259d7 713 The function reads the pending register in the NVIC and returns the pending bit
Kojto 101:7cff1c4259d7 714 for the specified interrupt.
Kojto 101:7cff1c4259d7 715
Kojto 101:7cff1c4259d7 716 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 717
Kojto 101:7cff1c4259d7 718 \return 0 Interrupt status is not pending.
Kojto 101:7cff1c4259d7 719 \return 1 Interrupt status is pending.
Kojto 101:7cff1c4259d7 720 */
Kojto 101:7cff1c4259d7 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 101:7cff1c4259d7 724 }
Kojto 101:7cff1c4259d7 725
Kojto 101:7cff1c4259d7 726
Kojto 101:7cff1c4259d7 727 /** \brief Set Pending Interrupt
Kojto 101:7cff1c4259d7 728
Kojto 101:7cff1c4259d7 729 The function sets the pending bit of an external interrupt.
Kojto 101:7cff1c4259d7 730
Kojto 101:7cff1c4259d7 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 732 */
Kojto 101:7cff1c4259d7 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 101:7cff1c4259d7 736 }
Kojto 101:7cff1c4259d7 737
Kojto 101:7cff1c4259d7 738
Kojto 101:7cff1c4259d7 739 /** \brief Clear Pending Interrupt
Kojto 101:7cff1c4259d7 740
Kojto 101:7cff1c4259d7 741 The function clears the pending bit of an external interrupt.
Kojto 101:7cff1c4259d7 742
Kojto 101:7cff1c4259d7 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 744 */
Kojto 101:7cff1c4259d7 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 101:7cff1c4259d7 748 }
Kojto 101:7cff1c4259d7 749
Kojto 101:7cff1c4259d7 750
Kojto 101:7cff1c4259d7 751 /** \brief Set Interrupt Priority
Kojto 101:7cff1c4259d7 752
Kojto 101:7cff1c4259d7 753 The function sets the priority of an interrupt.
Kojto 101:7cff1c4259d7 754
Kojto 101:7cff1c4259d7 755 \note The priority cannot be set for every core interrupt.
Kojto 101:7cff1c4259d7 756
Kojto 101:7cff1c4259d7 757 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 758 \param [in] priority Priority to set.
Kojto 101:7cff1c4259d7 759 */
Kojto 101:7cff1c4259d7 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 101:7cff1c4259d7 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
Kojto 101:7cff1c4259d7 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
Kojto 101:7cff1c4259d7 770 }
Kojto 101:7cff1c4259d7 771
Kojto 101:7cff1c4259d7 772
Kojto 101:7cff1c4259d7 773 /** \brief Get Interrupt Priority
Kojto 101:7cff1c4259d7 774
Kojto 101:7cff1c4259d7 775 The function reads the priority of an interrupt. The interrupt
Kojto 101:7cff1c4259d7 776 number can be positive to specify an external (device specific)
Kojto 101:7cff1c4259d7 777 interrupt, or negative to specify an internal (core) interrupt.
Kojto 101:7cff1c4259d7 778
Kojto 101:7cff1c4259d7 779
Kojto 101:7cff1c4259d7 780 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 101:7cff1c4259d7 782 priority bits of the microcontroller.
Kojto 101:7cff1c4259d7 783 */
Kojto 101:7cff1c4259d7 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 785 {
Kojto 101:7cff1c4259d7 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
Kojto 101:7cff1c4259d7 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
Kojto 101:7cff1c4259d7 793 }
Kojto 101:7cff1c4259d7 794
Kojto 101:7cff1c4259d7 795
Kojto 101:7cff1c4259d7 796 /** \brief System Reset
Kojto 101:7cff1c4259d7 797
Kojto 101:7cff1c4259d7 798 The function initiates a system reset request to reset the MCU.
Kojto 101:7cff1c4259d7 799 */
Kojto 101:7cff1c4259d7 800 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 101:7cff1c4259d7 801 {
Kojto 101:7cff1c4259d7 802 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 101:7cff1c4259d7 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 101:7cff1c4259d7 805 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 101:7cff1c4259d7 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
Kojto 101:7cff1c4259d7 808 }
Kojto 101:7cff1c4259d7 809
Kojto 101:7cff1c4259d7 810 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 101:7cff1c4259d7 811
Kojto 101:7cff1c4259d7 812
Kojto 101:7cff1c4259d7 813
Kojto 101:7cff1c4259d7 814 /* ################################## SysTick function ############################################ */
Kojto 101:7cff1c4259d7 815 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 101:7cff1c4259d7 817 \brief Functions that configure the System.
Kojto 101:7cff1c4259d7 818 @{
Kojto 101:7cff1c4259d7 819 */
Kojto 101:7cff1c4259d7 820
Kojto 101:7cff1c4259d7 821 #if (__Vendor_SysTickConfig == 0)
Kojto 101:7cff1c4259d7 822
Kojto 101:7cff1c4259d7 823 /** \brief System Tick Configuration
Kojto 101:7cff1c4259d7 824
Kojto 101:7cff1c4259d7 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 101:7cff1c4259d7 826 Counter is in free running mode to generate periodic interrupts.
Kojto 101:7cff1c4259d7 827
Kojto 101:7cff1c4259d7 828 \param [in] ticks Number of ticks between two interrupts.
Kojto 101:7cff1c4259d7 829
Kojto 101:7cff1c4259d7 830 \return 0 Function succeeded.
Kojto 101:7cff1c4259d7 831 \return 1 Function failed.
Kojto 101:7cff1c4259d7 832
Kojto 101:7cff1c4259d7 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 101:7cff1c4259d7 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 101:7cff1c4259d7 835 must contain a vendor-specific implementation of this function.
Kojto 101:7cff1c4259d7 836
Kojto 101:7cff1c4259d7 837 */
Kojto 101:7cff1c4259d7 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 101:7cff1c4259d7 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 101:7cff1c4259d7 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 101:7cff1c4259d7 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 101:7cff1c4259d7 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
Kojto 101:7cff1c4259d7 849 }
Kojto 101:7cff1c4259d7 850
Kojto 101:7cff1c4259d7 851 #endif
Kojto 101:7cff1c4259d7 852
Kojto 101:7cff1c4259d7 853 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 101:7cff1c4259d7 854
Kojto 101:7cff1c4259d7 855
Kojto 101:7cff1c4259d7 856
Kojto 101:7cff1c4259d7 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
Kojto 101:7cff1c4259d7 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 101:7cff1c4259d7 863
Kojto 101:7cff1c4259d7 864 #endif /* __CMSIS_GENERIC */