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TARGET_APPNEARME_MICRONFCBOARD/core_cm0plus.h@101:7cff1c4259d7, 2015-06-09 (annotated)

Committer:
Kojto
Date:
Tue Jun 09 14:29:26 2015 +0100
Revision:
101:7cff1c4259d7
Release 101 of the mbed library



Changes:

- new platform: APPNEARME_MICRONFCBOARD, MTS_DRAGONFLY_F411RE, MAX32600MBED, WIZwiki_W7500

- Silabs memory optimization in gpio, pwm fixes

- SPI  - ssel documentation fixes and its use

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**************************************************************************//**
Kojto 101:7cff1c4259d7 2 * @file core_cm0plus.h
Kojto 101:7cff1c4259d7 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 101:7cff1c4259d7 4 * @version V3.20
Kojto 101:7cff1c4259d7 5 * @date 25. February 2013
Kojto 101:7cff1c4259d7 6 *
Kojto 101:7cff1c4259d7 7 * @note
Kojto 101:7cff1c4259d7 8 *
Kojto 101:7cff1c4259d7 9 ******************************************************************************/
Kojto 101:7cff1c4259d7 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 101:7cff1c4259d7 11
Kojto 101:7cff1c4259d7 12 All rights reserved.
Kojto 101:7cff1c4259d7 13 Redistribution and use in source and binary forms, with or without
Kojto 101:7cff1c4259d7 14 modification, are permitted provided that the following conditions are met:
Kojto 101:7cff1c4259d7 15 - Redistributions of source code must retain the above copyright
Kojto 101:7cff1c4259d7 16 notice, this list of conditions and the following disclaimer.
Kojto 101:7cff1c4259d7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 101:7cff1c4259d7 18 notice, this list of conditions and the following disclaimer in the
Kojto 101:7cff1c4259d7 19 documentation and/or other materials provided with the distribution.
Kojto 101:7cff1c4259d7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 101:7cff1c4259d7 21 to endorse or promote products derived from this software without
Kojto 101:7cff1c4259d7 22 specific prior written permission.
Kojto 101:7cff1c4259d7 23 *
Kojto 101:7cff1c4259d7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 101:7cff1c4259d7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 101:7cff1c4259d7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 101:7cff1c4259d7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 101:7cff1c4259d7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 101:7cff1c4259d7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 101:7cff1c4259d7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 101:7cff1c4259d7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 101:7cff1c4259d7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 101:7cff1c4259d7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 101:7cff1c4259d7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 101:7cff1c4259d7 35 ---------------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 #if defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 101:7cff1c4259d7 40 #endif
Kojto 101:7cff1c4259d7 41
Kojto 101:7cff1c4259d7 42 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 43 extern "C" {
Kojto 101:7cff1c4259d7 44 #endif
Kojto 101:7cff1c4259d7 45
Kojto 101:7cff1c4259d7 46 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 101:7cff1c4259d7 47 #define __CORE_CM0PLUS_H_GENERIC
Kojto 101:7cff1c4259d7 48
Kojto 101:7cff1c4259d7 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 101:7cff1c4259d7 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 101:7cff1c4259d7 51
Kojto 101:7cff1c4259d7 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 101:7cff1c4259d7 53 Function definitions in header files are used to allow 'inlining'.
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 101:7cff1c4259d7 56 Unions are used for effective representation of core registers.
Kojto 101:7cff1c4259d7 57
Kojto 101:7cff1c4259d7 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 101:7cff1c4259d7 59 Function-like macros are used to allow more efficient code.
Kojto 101:7cff1c4259d7 60 */
Kojto 101:7cff1c4259d7 61
Kojto 101:7cff1c4259d7 62
Kojto 101:7cff1c4259d7 63 /*******************************************************************************
Kojto 101:7cff1c4259d7 64 * CMSIS definitions
Kojto 101:7cff1c4259d7 65 ******************************************************************************/
Kojto 101:7cff1c4259d7 66 /** \ingroup Cortex-M0+
Kojto 101:7cff1c4259d7 67 @{
Kojto 101:7cff1c4259d7 68 */
Kojto 101:7cff1c4259d7 69
Kojto 101:7cff1c4259d7 70 /* CMSIS CM0P definitions */
Kojto 101:7cff1c4259d7 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 101:7cff1c4259d7 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 101:7cff1c4259d7 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 101:7cff1c4259d7 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 101:7cff1c4259d7 75
Kojto 101:7cff1c4259d7 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 101:7cff1c4259d7 77
Kojto 101:7cff1c4259d7 78
Kojto 101:7cff1c4259d7 79 #if defined ( __CC_ARM )
Kojto 101:7cff1c4259d7 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 101:7cff1c4259d7 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 101:7cff1c4259d7 82 #define __STATIC_INLINE static __inline
Kojto 101:7cff1c4259d7 83
Kojto 101:7cff1c4259d7 84 #elif defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 101:7cff1c4259d7 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 101:7cff1c4259d7 87 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 88
Kojto 101:7cff1c4259d7 89 #elif defined ( __GNUC__ )
Kojto 101:7cff1c4259d7 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 101:7cff1c4259d7 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 101:7cff1c4259d7 92 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 93
Kojto 101:7cff1c4259d7 94 #elif defined ( __TASKING__ )
Kojto 101:7cff1c4259d7 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 101:7cff1c4259d7 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 101:7cff1c4259d7 97 #define __STATIC_INLINE static inline
Kojto 101:7cff1c4259d7 98
Kojto 101:7cff1c4259d7 99 #endif
Kojto 101:7cff1c4259d7 100
Kojto 101:7cff1c4259d7 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 101:7cff1c4259d7 102 */
Kojto 101:7cff1c4259d7 103 #define __FPU_USED 0
Kojto 101:7cff1c4259d7 104
Kojto 101:7cff1c4259d7 105 #if defined ( __CC_ARM )
Kojto 101:7cff1c4259d7 106 #if defined __TARGET_FPU_VFP
Kojto 101:7cff1c4259d7 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 108 #endif
Kojto 101:7cff1c4259d7 109
Kojto 101:7cff1c4259d7 110 #elif defined ( __ICCARM__ )
Kojto 101:7cff1c4259d7 111 #if defined __ARMVFP__
Kojto 101:7cff1c4259d7 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 113 #endif
Kojto 101:7cff1c4259d7 114
Kojto 101:7cff1c4259d7 115 #elif defined ( __GNUC__ )
Kojto 101:7cff1c4259d7 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 101:7cff1c4259d7 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 118 #endif
Kojto 101:7cff1c4259d7 119
Kojto 101:7cff1c4259d7 120 #elif defined ( __TASKING__ )
Kojto 101:7cff1c4259d7 121 #if defined __FPU_VFP__
Kojto 101:7cff1c4259d7 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 101:7cff1c4259d7 123 #endif
Kojto 101:7cff1c4259d7 124 #endif
Kojto 101:7cff1c4259d7 125
Kojto 101:7cff1c4259d7 126 #include <stdint.h> /* standard types definitions */
Kojto 101:7cff1c4259d7 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 101:7cff1c4259d7 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 101:7cff1c4259d7 129
Kojto 101:7cff1c4259d7 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 101:7cff1c4259d7 131
Kojto 101:7cff1c4259d7 132 #ifndef __CMSIS_GENERIC
Kojto 101:7cff1c4259d7 133
Kojto 101:7cff1c4259d7 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 101:7cff1c4259d7 135 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 101:7cff1c4259d7 136
Kojto 101:7cff1c4259d7 137 /* check device defines and use defaults */
Kojto 101:7cff1c4259d7 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 101:7cff1c4259d7 139 #ifndef __CM0PLUS_REV
Kojto 101:7cff1c4259d7 140 #define __CM0PLUS_REV 0x0000
Kojto 101:7cff1c4259d7 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 142 #endif
Kojto 101:7cff1c4259d7 143
Kojto 101:7cff1c4259d7 144 #ifndef __MPU_PRESENT
Kojto 101:7cff1c4259d7 145 #define __MPU_PRESENT 0
Kojto 101:7cff1c4259d7 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 147 #endif
Kojto 101:7cff1c4259d7 148
Kojto 101:7cff1c4259d7 149 #ifndef __VTOR_PRESENT
Kojto 101:7cff1c4259d7 150 #define __VTOR_PRESENT 0
Kojto 101:7cff1c4259d7 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 152 #endif
Kojto 101:7cff1c4259d7 153
Kojto 101:7cff1c4259d7 154 #ifndef __NVIC_PRIO_BITS
Kojto 101:7cff1c4259d7 155 #define __NVIC_PRIO_BITS 2
Kojto 101:7cff1c4259d7 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 157 #endif
Kojto 101:7cff1c4259d7 158
Kojto 101:7cff1c4259d7 159 #ifndef __Vendor_SysTickConfig
Kojto 101:7cff1c4259d7 160 #define __Vendor_SysTickConfig 0
Kojto 101:7cff1c4259d7 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 101:7cff1c4259d7 162 #endif
Kojto 101:7cff1c4259d7 163 #endif
Kojto 101:7cff1c4259d7 164
Kojto 101:7cff1c4259d7 165 /* IO definitions (access restrictions to peripheral registers) */
Kojto 101:7cff1c4259d7 166 /**
Kojto 101:7cff1c4259d7 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 101:7cff1c4259d7 168
Kojto 101:7cff1c4259d7 169 <strong>IO Type Qualifiers</strong> are used
Kojto 101:7cff1c4259d7 170 \li to specify the access to peripheral variables.
Kojto 101:7cff1c4259d7 171 \li for automatic generation of peripheral register debug information.
Kojto 101:7cff1c4259d7 172 */
Kojto 101:7cff1c4259d7 173 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 174 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 101:7cff1c4259d7 175 #else
Kojto 101:7cff1c4259d7 176 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 101:7cff1c4259d7 177 #endif
Kojto 101:7cff1c4259d7 178 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 101:7cff1c4259d7 179 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 101:7cff1c4259d7 180
Kojto 101:7cff1c4259d7 181 /*@} end of group Cortex-M0+ */
Kojto 101:7cff1c4259d7 182
Kojto 101:7cff1c4259d7 183
Kojto 101:7cff1c4259d7 184
Kojto 101:7cff1c4259d7 185 /*******************************************************************************
Kojto 101:7cff1c4259d7 186 * Register Abstraction
Kojto 101:7cff1c4259d7 187 Core Register contain:
Kojto 101:7cff1c4259d7 188 - Core Register
Kojto 101:7cff1c4259d7 189 - Core NVIC Register
Kojto 101:7cff1c4259d7 190 - Core SCB Register
Kojto 101:7cff1c4259d7 191 - Core SysTick Register
Kojto 101:7cff1c4259d7 192 - Core MPU Register
Kojto 101:7cff1c4259d7 193 ******************************************************************************/
Kojto 101:7cff1c4259d7 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 101:7cff1c4259d7 195 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 101:7cff1c4259d7 196 */
Kojto 101:7cff1c4259d7 197
Kojto 101:7cff1c4259d7 198 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 199 \defgroup CMSIS_CORE Status and Control Registers
Kojto 101:7cff1c4259d7 200 \brief Core Register type definitions.
Kojto 101:7cff1c4259d7 201 @{
Kojto 101:7cff1c4259d7 202 */
Kojto 101:7cff1c4259d7 203
Kojto 101:7cff1c4259d7 204 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 101:7cff1c4259d7 205 */
Kojto 101:7cff1c4259d7 206 typedef union
Kojto 101:7cff1c4259d7 207 {
Kojto 101:7cff1c4259d7 208 struct
Kojto 101:7cff1c4259d7 209 {
Kojto 101:7cff1c4259d7 210 #if (__CORTEX_M != 0x04)
Kojto 101:7cff1c4259d7 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 101:7cff1c4259d7 212 #else
Kojto 101:7cff1c4259d7 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 101:7cff1c4259d7 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 101:7cff1c4259d7 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 101:7cff1c4259d7 216 #endif
Kojto 101:7cff1c4259d7 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 101:7cff1c4259d7 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 101:7cff1c4259d7 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 101:7cff1c4259d7 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 101:7cff1c4259d7 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 101:7cff1c4259d7 222 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 223 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 224 } APSR_Type;
Kojto 101:7cff1c4259d7 225
Kojto 101:7cff1c4259d7 226
Kojto 101:7cff1c4259d7 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 101:7cff1c4259d7 228 */
Kojto 101:7cff1c4259d7 229 typedef union
Kojto 101:7cff1c4259d7 230 {
Kojto 101:7cff1c4259d7 231 struct
Kojto 101:7cff1c4259d7 232 {
Kojto 101:7cff1c4259d7 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 101:7cff1c4259d7 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 101:7cff1c4259d7 235 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 236 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 237 } IPSR_Type;
Kojto 101:7cff1c4259d7 238
Kojto 101:7cff1c4259d7 239
Kojto 101:7cff1c4259d7 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 101:7cff1c4259d7 241 */
Kojto 101:7cff1c4259d7 242 typedef union
Kojto 101:7cff1c4259d7 243 {
Kojto 101:7cff1c4259d7 244 struct
Kojto 101:7cff1c4259d7 245 {
Kojto 101:7cff1c4259d7 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 101:7cff1c4259d7 247 #if (__CORTEX_M != 0x04)
Kojto 101:7cff1c4259d7 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 101:7cff1c4259d7 249 #else
Kojto 101:7cff1c4259d7 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 101:7cff1c4259d7 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 101:7cff1c4259d7 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 101:7cff1c4259d7 253 #endif
Kojto 101:7cff1c4259d7 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 101:7cff1c4259d7 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 101:7cff1c4259d7 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 101:7cff1c4259d7 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 101:7cff1c4259d7 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 101:7cff1c4259d7 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 101:7cff1c4259d7 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 101:7cff1c4259d7 261 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 262 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 263 } xPSR_Type;
Kojto 101:7cff1c4259d7 264
Kojto 101:7cff1c4259d7 265
Kojto 101:7cff1c4259d7 266 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 101:7cff1c4259d7 267 */
Kojto 101:7cff1c4259d7 268 typedef union
Kojto 101:7cff1c4259d7 269 {
Kojto 101:7cff1c4259d7 270 struct
Kojto 101:7cff1c4259d7 271 {
Kojto 101:7cff1c4259d7 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 101:7cff1c4259d7 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 101:7cff1c4259d7 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 101:7cff1c4259d7 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 101:7cff1c4259d7 276 } b; /*!< Structure used for bit access */
Kojto 101:7cff1c4259d7 277 uint32_t w; /*!< Type used for word access */
Kojto 101:7cff1c4259d7 278 } CONTROL_Type;
Kojto 101:7cff1c4259d7 279
Kojto 101:7cff1c4259d7 280 /*@} end of group CMSIS_CORE */
Kojto 101:7cff1c4259d7 281
Kojto 101:7cff1c4259d7 282
Kojto 101:7cff1c4259d7 283 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 101:7cff1c4259d7 285 \brief Type definitions for the NVIC Registers
Kojto 101:7cff1c4259d7 286 @{
Kojto 101:7cff1c4259d7 287 */
Kojto 101:7cff1c4259d7 288
Kojto 101:7cff1c4259d7 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 101:7cff1c4259d7 290 */
Kojto 101:7cff1c4259d7 291 typedef struct
Kojto 101:7cff1c4259d7 292 {
Kojto 101:7cff1c4259d7 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 101:7cff1c4259d7 294 uint32_t RESERVED0[31];
Kojto 101:7cff1c4259d7 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 101:7cff1c4259d7 296 uint32_t RSERVED1[31];
Kojto 101:7cff1c4259d7 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 101:7cff1c4259d7 298 uint32_t RESERVED2[31];
Kojto 101:7cff1c4259d7 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 101:7cff1c4259d7 300 uint32_t RESERVED3[31];
Kojto 101:7cff1c4259d7 301 uint32_t RESERVED4[64];
Kojto 101:7cff1c4259d7 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 101:7cff1c4259d7 303 } NVIC_Type;
Kojto 101:7cff1c4259d7 304
Kojto 101:7cff1c4259d7 305 /*@} end of group CMSIS_NVIC */
Kojto 101:7cff1c4259d7 306
Kojto 101:7cff1c4259d7 307
Kojto 101:7cff1c4259d7 308 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 309 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 101:7cff1c4259d7 310 \brief Type definitions for the System Control Block Registers
Kojto 101:7cff1c4259d7 311 @{
Kojto 101:7cff1c4259d7 312 */
Kojto 101:7cff1c4259d7 313
Kojto 101:7cff1c4259d7 314 /** \brief Structure type to access the System Control Block (SCB).
Kojto 101:7cff1c4259d7 315 */
Kojto 101:7cff1c4259d7 316 typedef struct
Kojto 101:7cff1c4259d7 317 {
Kojto 101:7cff1c4259d7 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 101:7cff1c4259d7 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 101:7cff1c4259d7 320 #if (__VTOR_PRESENT == 1)
Kojto 101:7cff1c4259d7 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 101:7cff1c4259d7 322 #else
Kojto 101:7cff1c4259d7 323 uint32_t RESERVED0;
Kojto 101:7cff1c4259d7 324 #endif
Kojto 101:7cff1c4259d7 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 101:7cff1c4259d7 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 101:7cff1c4259d7 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 101:7cff1c4259d7 328 uint32_t RESERVED1;
Kojto 101:7cff1c4259d7 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 101:7cff1c4259d7 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 101:7cff1c4259d7 331 } SCB_Type;
Kojto 101:7cff1c4259d7 332
Kojto 101:7cff1c4259d7 333 /* SCB CPUID Register Definitions */
Kojto 101:7cff1c4259d7 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 101:7cff1c4259d7 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 101:7cff1c4259d7 336
Kojto 101:7cff1c4259d7 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 101:7cff1c4259d7 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 101:7cff1c4259d7 339
Kojto 101:7cff1c4259d7 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 101:7cff1c4259d7 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 101:7cff1c4259d7 342
Kojto 101:7cff1c4259d7 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 101:7cff1c4259d7 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 101:7cff1c4259d7 345
Kojto 101:7cff1c4259d7 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 101:7cff1c4259d7 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 101:7cff1c4259d7 348
Kojto 101:7cff1c4259d7 349 /* SCB Interrupt Control State Register Definitions */
Kojto 101:7cff1c4259d7 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 101:7cff1c4259d7 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 101:7cff1c4259d7 352
Kojto 101:7cff1c4259d7 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 101:7cff1c4259d7 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 101:7cff1c4259d7 355
Kojto 101:7cff1c4259d7 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 101:7cff1c4259d7 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 101:7cff1c4259d7 358
Kojto 101:7cff1c4259d7 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 101:7cff1c4259d7 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 101:7cff1c4259d7 361
Kojto 101:7cff1c4259d7 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 101:7cff1c4259d7 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 101:7cff1c4259d7 364
Kojto 101:7cff1c4259d7 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 101:7cff1c4259d7 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 101:7cff1c4259d7 367
Kojto 101:7cff1c4259d7 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 101:7cff1c4259d7 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 101:7cff1c4259d7 370
Kojto 101:7cff1c4259d7 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 101:7cff1c4259d7 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 101:7cff1c4259d7 373
Kojto 101:7cff1c4259d7 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 101:7cff1c4259d7 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 101:7cff1c4259d7 376
Kojto 101:7cff1c4259d7 377 #if (__VTOR_PRESENT == 1)
Kojto 101:7cff1c4259d7 378 /* SCB Interrupt Control State Register Definitions */
Kojto 101:7cff1c4259d7 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 101:7cff1c4259d7 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 101:7cff1c4259d7 381 #endif
Kojto 101:7cff1c4259d7 382
Kojto 101:7cff1c4259d7 383 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 101:7cff1c4259d7 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 101:7cff1c4259d7 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 101:7cff1c4259d7 386
Kojto 101:7cff1c4259d7 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 101:7cff1c4259d7 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 101:7cff1c4259d7 389
Kojto 101:7cff1c4259d7 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 101:7cff1c4259d7 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 101:7cff1c4259d7 392
Kojto 101:7cff1c4259d7 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 101:7cff1c4259d7 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 101:7cff1c4259d7 395
Kojto 101:7cff1c4259d7 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 101:7cff1c4259d7 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 101:7cff1c4259d7 398
Kojto 101:7cff1c4259d7 399 /* SCB System Control Register Definitions */
Kojto 101:7cff1c4259d7 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 101:7cff1c4259d7 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 101:7cff1c4259d7 402
Kojto 101:7cff1c4259d7 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 101:7cff1c4259d7 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 101:7cff1c4259d7 405
Kojto 101:7cff1c4259d7 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 101:7cff1c4259d7 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 101:7cff1c4259d7 408
Kojto 101:7cff1c4259d7 409 /* SCB Configuration Control Register Definitions */
Kojto 101:7cff1c4259d7 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 101:7cff1c4259d7 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 101:7cff1c4259d7 412
Kojto 101:7cff1c4259d7 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 101:7cff1c4259d7 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 101:7cff1c4259d7 415
Kojto 101:7cff1c4259d7 416 /* SCB System Handler Control and State Register Definitions */
Kojto 101:7cff1c4259d7 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 101:7cff1c4259d7 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 101:7cff1c4259d7 419
Kojto 101:7cff1c4259d7 420 /*@} end of group CMSIS_SCB */
Kojto 101:7cff1c4259d7 421
Kojto 101:7cff1c4259d7 422
Kojto 101:7cff1c4259d7 423 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 101:7cff1c4259d7 425 \brief Type definitions for the System Timer Registers.
Kojto 101:7cff1c4259d7 426 @{
Kojto 101:7cff1c4259d7 427 */
Kojto 101:7cff1c4259d7 428
Kojto 101:7cff1c4259d7 429 /** \brief Structure type to access the System Timer (SysTick).
Kojto 101:7cff1c4259d7 430 */
Kojto 101:7cff1c4259d7 431 typedef struct
Kojto 101:7cff1c4259d7 432 {
Kojto 101:7cff1c4259d7 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 101:7cff1c4259d7 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 101:7cff1c4259d7 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 101:7cff1c4259d7 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 101:7cff1c4259d7 437 } SysTick_Type;
Kojto 101:7cff1c4259d7 438
Kojto 101:7cff1c4259d7 439 /* SysTick Control / Status Register Definitions */
Kojto 101:7cff1c4259d7 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 101:7cff1c4259d7 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 101:7cff1c4259d7 442
Kojto 101:7cff1c4259d7 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 101:7cff1c4259d7 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 101:7cff1c4259d7 445
Kojto 101:7cff1c4259d7 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 101:7cff1c4259d7 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 101:7cff1c4259d7 448
Kojto 101:7cff1c4259d7 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 101:7cff1c4259d7 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 101:7cff1c4259d7 451
Kojto 101:7cff1c4259d7 452 /* SysTick Reload Register Definitions */
Kojto 101:7cff1c4259d7 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 101:7cff1c4259d7 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 101:7cff1c4259d7 455
Kojto 101:7cff1c4259d7 456 /* SysTick Current Register Definitions */
Kojto 101:7cff1c4259d7 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 101:7cff1c4259d7 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 101:7cff1c4259d7 459
Kojto 101:7cff1c4259d7 460 /* SysTick Calibration Register Definitions */
Kojto 101:7cff1c4259d7 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 101:7cff1c4259d7 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 101:7cff1c4259d7 463
Kojto 101:7cff1c4259d7 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 101:7cff1c4259d7 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 101:7cff1c4259d7 466
Kojto 101:7cff1c4259d7 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 101:7cff1c4259d7 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 101:7cff1c4259d7 469
Kojto 101:7cff1c4259d7 470 /*@} end of group CMSIS_SysTick */
Kojto 101:7cff1c4259d7 471
Kojto 101:7cff1c4259d7 472 #if (__MPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 473 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 101:7cff1c4259d7 475 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 101:7cff1c4259d7 476 @{
Kojto 101:7cff1c4259d7 477 */
Kojto 101:7cff1c4259d7 478
Kojto 101:7cff1c4259d7 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 101:7cff1c4259d7 480 */
Kojto 101:7cff1c4259d7 481 typedef struct
Kojto 101:7cff1c4259d7 482 {
Kojto 101:7cff1c4259d7 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 101:7cff1c4259d7 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 101:7cff1c4259d7 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 101:7cff1c4259d7 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 101:7cff1c4259d7 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 101:7cff1c4259d7 488 } MPU_Type;
Kojto 101:7cff1c4259d7 489
Kojto 101:7cff1c4259d7 490 /* MPU Type Register */
Kojto 101:7cff1c4259d7 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 101:7cff1c4259d7 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 101:7cff1c4259d7 493
Kojto 101:7cff1c4259d7 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 101:7cff1c4259d7 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 101:7cff1c4259d7 496
Kojto 101:7cff1c4259d7 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 101:7cff1c4259d7 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Kojto 101:7cff1c4259d7 499
Kojto 101:7cff1c4259d7 500 /* MPU Control Register */
Kojto 101:7cff1c4259d7 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 101:7cff1c4259d7 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 101:7cff1c4259d7 503
Kojto 101:7cff1c4259d7 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 101:7cff1c4259d7 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 101:7cff1c4259d7 506
Kojto 101:7cff1c4259d7 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 101:7cff1c4259d7 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Kojto 101:7cff1c4259d7 509
Kojto 101:7cff1c4259d7 510 /* MPU Region Number Register */
Kojto 101:7cff1c4259d7 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 101:7cff1c4259d7 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Kojto 101:7cff1c4259d7 513
Kojto 101:7cff1c4259d7 514 /* MPU Region Base Address Register */
Kojto 101:7cff1c4259d7 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 101:7cff1c4259d7 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 101:7cff1c4259d7 517
Kojto 101:7cff1c4259d7 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 101:7cff1c4259d7 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 101:7cff1c4259d7 520
Kojto 101:7cff1c4259d7 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 101:7cff1c4259d7 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Kojto 101:7cff1c4259d7 523
Kojto 101:7cff1c4259d7 524 /* MPU Region Attribute and Size Register */
Kojto 101:7cff1c4259d7 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 101:7cff1c4259d7 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 101:7cff1c4259d7 527
Kojto 101:7cff1c4259d7 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 101:7cff1c4259d7 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 101:7cff1c4259d7 530
Kojto 101:7cff1c4259d7 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 101:7cff1c4259d7 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 101:7cff1c4259d7 533
Kojto 101:7cff1c4259d7 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 101:7cff1c4259d7 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 101:7cff1c4259d7 536
Kojto 101:7cff1c4259d7 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 101:7cff1c4259d7 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 101:7cff1c4259d7 539
Kojto 101:7cff1c4259d7 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 101:7cff1c4259d7 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 101:7cff1c4259d7 542
Kojto 101:7cff1c4259d7 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 101:7cff1c4259d7 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 101:7cff1c4259d7 545
Kojto 101:7cff1c4259d7 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 101:7cff1c4259d7 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 101:7cff1c4259d7 548
Kojto 101:7cff1c4259d7 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 101:7cff1c4259d7 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 101:7cff1c4259d7 551
Kojto 101:7cff1c4259d7 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 101:7cff1c4259d7 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 101:7cff1c4259d7 554
Kojto 101:7cff1c4259d7 555 /*@} end of group CMSIS_MPU */
Kojto 101:7cff1c4259d7 556 #endif
Kojto 101:7cff1c4259d7 557
Kojto 101:7cff1c4259d7 558
Kojto 101:7cff1c4259d7 559 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 101:7cff1c4259d7 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 101:7cff1c4259d7 562 are only accessible over DAP and not via processor. Therefore
Kojto 101:7cff1c4259d7 563 they are not covered by the Cortex-M0 header file.
Kojto 101:7cff1c4259d7 564 @{
Kojto 101:7cff1c4259d7 565 */
Kojto 101:7cff1c4259d7 566 /*@} end of group CMSIS_CoreDebug */
Kojto 101:7cff1c4259d7 567
Kojto 101:7cff1c4259d7 568
Kojto 101:7cff1c4259d7 569 /** \ingroup CMSIS_core_register
Kojto 101:7cff1c4259d7 570 \defgroup CMSIS_core_base Core Definitions
Kojto 101:7cff1c4259d7 571 \brief Definitions for base addresses, unions, and structures.
Kojto 101:7cff1c4259d7 572 @{
Kojto 101:7cff1c4259d7 573 */
Kojto 101:7cff1c4259d7 574
Kojto 101:7cff1c4259d7 575 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 101:7cff1c4259d7 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 101:7cff1c4259d7 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 101:7cff1c4259d7 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 101:7cff1c4259d7 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 101:7cff1c4259d7 580
Kojto 101:7cff1c4259d7 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 101:7cff1c4259d7 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 101:7cff1c4259d7 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 101:7cff1c4259d7 584
Kojto 101:7cff1c4259d7 585 #if (__MPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 101:7cff1c4259d7 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 101:7cff1c4259d7 588 #endif
Kojto 101:7cff1c4259d7 589
Kojto 101:7cff1c4259d7 590 /*@} */
Kojto 101:7cff1c4259d7 591
Kojto 101:7cff1c4259d7 592
Kojto 101:7cff1c4259d7 593
Kojto 101:7cff1c4259d7 594 /*******************************************************************************
Kojto 101:7cff1c4259d7 595 * Hardware Abstraction Layer
Kojto 101:7cff1c4259d7 596 Core Function Interface contains:
Kojto 101:7cff1c4259d7 597 - Core NVIC Functions
Kojto 101:7cff1c4259d7 598 - Core SysTick Functions
Kojto 101:7cff1c4259d7 599 - Core Register Access Functions
Kojto 101:7cff1c4259d7 600 ******************************************************************************/
Kojto 101:7cff1c4259d7 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 101:7cff1c4259d7 602 */
Kojto 101:7cff1c4259d7 603
Kojto 101:7cff1c4259d7 604
Kojto 101:7cff1c4259d7 605
Kojto 101:7cff1c4259d7 606 /* ########################## NVIC functions #################################### */
Kojto 101:7cff1c4259d7 607 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 101:7cff1c4259d7 609 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 101:7cff1c4259d7 610 @{
Kojto 101:7cff1c4259d7 611 */
Kojto 101:7cff1c4259d7 612
Kojto 101:7cff1c4259d7 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 101:7cff1c4259d7 614 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 101:7cff1c4259d7 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 101:7cff1c4259d7 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 101:7cff1c4259d7 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 101:7cff1c4259d7 618
Kojto 101:7cff1c4259d7 619
Kojto 101:7cff1c4259d7 620 /** \brief Enable External Interrupt
Kojto 101:7cff1c4259d7 621
Kojto 101:7cff1c4259d7 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 101:7cff1c4259d7 623
Kojto 101:7cff1c4259d7 624 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 625 */
Kojto 101:7cff1c4259d7 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 627 {
Kojto 101:7cff1c4259d7 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 101:7cff1c4259d7 629 }
Kojto 101:7cff1c4259d7 630
Kojto 101:7cff1c4259d7 631
Kojto 101:7cff1c4259d7 632 /** \brief Disable External Interrupt
Kojto 101:7cff1c4259d7 633
Kojto 101:7cff1c4259d7 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 101:7cff1c4259d7 635
Kojto 101:7cff1c4259d7 636 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 637 */
Kojto 101:7cff1c4259d7 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 639 {
Kojto 101:7cff1c4259d7 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 101:7cff1c4259d7 641 }
Kojto 101:7cff1c4259d7 642
Kojto 101:7cff1c4259d7 643
Kojto 101:7cff1c4259d7 644 /** \brief Get Pending Interrupt
Kojto 101:7cff1c4259d7 645
Kojto 101:7cff1c4259d7 646 The function reads the pending register in the NVIC and returns the pending bit
Kojto 101:7cff1c4259d7 647 for the specified interrupt.
Kojto 101:7cff1c4259d7 648
Kojto 101:7cff1c4259d7 649 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 650
Kojto 101:7cff1c4259d7 651 \return 0 Interrupt status is not pending.
Kojto 101:7cff1c4259d7 652 \return 1 Interrupt status is pending.
Kojto 101:7cff1c4259d7 653 */
Kojto 101:7cff1c4259d7 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 655 {
Kojto 101:7cff1c4259d7 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 101:7cff1c4259d7 657 }
Kojto 101:7cff1c4259d7 658
Kojto 101:7cff1c4259d7 659
Kojto 101:7cff1c4259d7 660 /** \brief Set Pending Interrupt
Kojto 101:7cff1c4259d7 661
Kojto 101:7cff1c4259d7 662 The function sets the pending bit of an external interrupt.
Kojto 101:7cff1c4259d7 663
Kojto 101:7cff1c4259d7 664 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 665 */
Kojto 101:7cff1c4259d7 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 667 {
Kojto 101:7cff1c4259d7 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 101:7cff1c4259d7 669 }
Kojto 101:7cff1c4259d7 670
Kojto 101:7cff1c4259d7 671
Kojto 101:7cff1c4259d7 672 /** \brief Clear Pending Interrupt
Kojto 101:7cff1c4259d7 673
Kojto 101:7cff1c4259d7 674 The function clears the pending bit of an external interrupt.
Kojto 101:7cff1c4259d7 675
Kojto 101:7cff1c4259d7 676 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 101:7cff1c4259d7 677 */
Kojto 101:7cff1c4259d7 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 679 {
Kojto 101:7cff1c4259d7 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 101:7cff1c4259d7 681 }
Kojto 101:7cff1c4259d7 682
Kojto 101:7cff1c4259d7 683
Kojto 101:7cff1c4259d7 684 /** \brief Set Interrupt Priority
Kojto 101:7cff1c4259d7 685
Kojto 101:7cff1c4259d7 686 The function sets the priority of an interrupt.
Kojto 101:7cff1c4259d7 687
Kojto 101:7cff1c4259d7 688 \note The priority cannot be set for every core interrupt.
Kojto 101:7cff1c4259d7 689
Kojto 101:7cff1c4259d7 690 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 691 \param [in] priority Priority to set.
Kojto 101:7cff1c4259d7 692 */
Kojto 101:7cff1c4259d7 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 101:7cff1c4259d7 694 {
Kojto 101:7cff1c4259d7 695 if(IRQn < 0) {
Kojto 101:7cff1c4259d7 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 101:7cff1c4259d7 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 101:7cff1c4259d7 698 else {
Kojto 101:7cff1c4259d7 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 101:7cff1c4259d7 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 101:7cff1c4259d7 701 }
Kojto 101:7cff1c4259d7 702
Kojto 101:7cff1c4259d7 703
Kojto 101:7cff1c4259d7 704 /** \brief Get Interrupt Priority
Kojto 101:7cff1c4259d7 705
Kojto 101:7cff1c4259d7 706 The function reads the priority of an interrupt. The interrupt
Kojto 101:7cff1c4259d7 707 number can be positive to specify an external (device specific)
Kojto 101:7cff1c4259d7 708 interrupt, or negative to specify an internal (core) interrupt.
Kojto 101:7cff1c4259d7 709
Kojto 101:7cff1c4259d7 710
Kojto 101:7cff1c4259d7 711 \param [in] IRQn Interrupt number.
Kojto 101:7cff1c4259d7 712 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 101:7cff1c4259d7 713 priority bits of the microcontroller.
Kojto 101:7cff1c4259d7 714 */
Kojto 101:7cff1c4259d7 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 101:7cff1c4259d7 716 {
Kojto 101:7cff1c4259d7 717
Kojto 101:7cff1c4259d7 718 if(IRQn < 0) {
Kojto 101:7cff1c4259d7 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 101:7cff1c4259d7 720 else {
Kojto 101:7cff1c4259d7 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 101:7cff1c4259d7 722 }
Kojto 101:7cff1c4259d7 723
Kojto 101:7cff1c4259d7 724
Kojto 101:7cff1c4259d7 725 /** \brief System Reset
Kojto 101:7cff1c4259d7 726
Kojto 101:7cff1c4259d7 727 The function initiates a system reset request to reset the MCU.
Kojto 101:7cff1c4259d7 728 */
Kojto 101:7cff1c4259d7 729 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 101:7cff1c4259d7 730 {
Kojto 101:7cff1c4259d7 731 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 101:7cff1c4259d7 732 buffered write are completed before reset */
Kojto 101:7cff1c4259d7 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 101:7cff1c4259d7 734 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 101:7cff1c4259d7 735 __DSB(); /* Ensure completion of memory access */
Kojto 101:7cff1c4259d7 736 while(1); /* wait until reset */
Kojto 101:7cff1c4259d7 737 }
Kojto 101:7cff1c4259d7 738
Kojto 101:7cff1c4259d7 739 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 101:7cff1c4259d7 740
Kojto 101:7cff1c4259d7 741
Kojto 101:7cff1c4259d7 742
Kojto 101:7cff1c4259d7 743 /* ################################## SysTick function ############################################ */
Kojto 101:7cff1c4259d7 744 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 101:7cff1c4259d7 746 \brief Functions that configure the System.
Kojto 101:7cff1c4259d7 747 @{
Kojto 101:7cff1c4259d7 748 */
Kojto 101:7cff1c4259d7 749
Kojto 101:7cff1c4259d7 750 #if (__Vendor_SysTickConfig == 0)
Kojto 101:7cff1c4259d7 751
Kojto 101:7cff1c4259d7 752 /** \brief System Tick Configuration
Kojto 101:7cff1c4259d7 753
Kojto 101:7cff1c4259d7 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 101:7cff1c4259d7 755 Counter is in free running mode to generate periodic interrupts.
Kojto 101:7cff1c4259d7 756
Kojto 101:7cff1c4259d7 757 \param [in] ticks Number of ticks between two interrupts.
Kojto 101:7cff1c4259d7 758
Kojto 101:7cff1c4259d7 759 \return 0 Function succeeded.
Kojto 101:7cff1c4259d7 760 \return 1 Function failed.
Kojto 101:7cff1c4259d7 761
Kojto 101:7cff1c4259d7 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 101:7cff1c4259d7 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 101:7cff1c4259d7 764 must contain a vendor-specific implementation of this function.
Kojto 101:7cff1c4259d7 765
Kojto 101:7cff1c4259d7 766 */
Kojto 101:7cff1c4259d7 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 101:7cff1c4259d7 768 {
Kojto 101:7cff1c4259d7 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 101:7cff1c4259d7 770
Kojto 101:7cff1c4259d7 771 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 101:7cff1c4259d7 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 101:7cff1c4259d7 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 101:7cff1c4259d7 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 101:7cff1c4259d7 775 SysTick_CTRL_TICKINT_Msk |
Kojto 101:7cff1c4259d7 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 101:7cff1c4259d7 777 return (0); /* Function successful */
Kojto 101:7cff1c4259d7 778 }
Kojto 101:7cff1c4259d7 779
Kojto 101:7cff1c4259d7 780 #endif
Kojto 101:7cff1c4259d7 781
Kojto 101:7cff1c4259d7 782 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 101:7cff1c4259d7 783
Kojto 101:7cff1c4259d7 784
Kojto 101:7cff1c4259d7 785
Kojto 101:7cff1c4259d7 786
Kojto 101:7cff1c4259d7 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 101:7cff1c4259d7 788
Kojto 101:7cff1c4259d7 789 #endif /* __CMSIS_GENERIC */
Kojto 101:7cff1c4259d7 790
Kojto 101:7cff1c4259d7 791 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 792 }
Kojto 101:7cff1c4259d7 793 #endif