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This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32600MBED/core_caFunc.h@121:6c34061e7c34, 2016-05-25 (annotated)

Committer:
Kojto
Date:
Wed May 25 16:44:06 2016 +0100
Revision:
121:6c34061e7c34
Parent:
115:87f2f5183dfb
Child:
130:d75b3fe1f5cb
Release 121 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - F7 - analogin conversion fix

     - F1, F4 - serial flushed prior init fix

     - CAN added for F042K6,F072RB,F091RC

     - NUCLE_L053R8/F030R8/F070RB,F103RB - ticker 16bit counter fix

- NXP - LPC812 PWMOut conflict issue fix

      - KSDK - PWMout fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**************************************************************************//**
Kojto 101:7cff1c4259d7 2 * @file core_caFunc.h
Kojto 101:7cff1c4259d7 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 101:7cff1c4259d7 4 * @version V3.10
Kojto 108:34e6b704fe68 5 * @date 30 Oct 2013
Kojto 101:7cff1c4259d7 6 *
Kojto 101:7cff1c4259d7 7 * @note
Kojto 101:7cff1c4259d7 8 *
Kojto 101:7cff1c4259d7 9 ******************************************************************************/
Kojto 108:34e6b704fe68 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 101:7cff1c4259d7 11
Kojto 101:7cff1c4259d7 12 All rights reserved.
Kojto 101:7cff1c4259d7 13 Redistribution and use in source and binary forms, with or without
Kojto 101:7cff1c4259d7 14 modification, are permitted provided that the following conditions are met:
Kojto 101:7cff1c4259d7 15 - Redistributions of source code must retain the above copyright
Kojto 101:7cff1c4259d7 16 notice, this list of conditions and the following disclaimer.
Kojto 101:7cff1c4259d7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 101:7cff1c4259d7 18 notice, this list of conditions and the following disclaimer in the
Kojto 101:7cff1c4259d7 19 documentation and/or other materials provided with the distribution.
Kojto 101:7cff1c4259d7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 101:7cff1c4259d7 21 to endorse or promote products derived from this software without
Kojto 101:7cff1c4259d7 22 specific prior written permission.
Kojto 101:7cff1c4259d7 23 *
Kojto 101:7cff1c4259d7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 101:7cff1c4259d7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 101:7cff1c4259d7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 101:7cff1c4259d7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 101:7cff1c4259d7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 101:7cff1c4259d7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 101:7cff1c4259d7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 101:7cff1c4259d7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 101:7cff1c4259d7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 101:7cff1c4259d7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 101:7cff1c4259d7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 101:7cff1c4259d7 35 ---------------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 #ifndef __CORE_CAFUNC_H__
Kojto 101:7cff1c4259d7 39 #define __CORE_CAFUNC_H__
Kojto 101:7cff1c4259d7 40
Kojto 101:7cff1c4259d7 41
Kojto 101:7cff1c4259d7 42 /* ########################### Core Function Access ########################### */
Kojto 101:7cff1c4259d7 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 101:7cff1c4259d7 45 @{
Kojto 101:7cff1c4259d7 46 */
Kojto 101:7cff1c4259d7 47
Kojto 101:7cff1c4259d7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 101:7cff1c4259d7 49 /* ARM armcc specific functions */
Kojto 101:7cff1c4259d7 50
Kojto 101:7cff1c4259d7 51 #if (__ARMCC_VERSION < 400677)
Kojto 101:7cff1c4259d7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 101:7cff1c4259d7 53 #endif
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 #define MODE_USR 0x10
Kojto 101:7cff1c4259d7 56 #define MODE_FIQ 0x11
Kojto 101:7cff1c4259d7 57 #define MODE_IRQ 0x12
Kojto 101:7cff1c4259d7 58 #define MODE_SVC 0x13
Kojto 101:7cff1c4259d7 59 #define MODE_MON 0x16
Kojto 101:7cff1c4259d7 60 #define MODE_ABT 0x17
Kojto 101:7cff1c4259d7 61 #define MODE_HYP 0x1A
Kojto 101:7cff1c4259d7 62 #define MODE_UND 0x1B
Kojto 101:7cff1c4259d7 63 #define MODE_SYS 0x1F
Kojto 101:7cff1c4259d7 64
Kojto 101:7cff1c4259d7 65 /** \brief Get APSR Register
Kojto 101:7cff1c4259d7 66
Kojto 101:7cff1c4259d7 67 This function returns the content of the APSR Register.
Kojto 101:7cff1c4259d7 68
Kojto 101:7cff1c4259d7 69 \return APSR Register value
Kojto 101:7cff1c4259d7 70 */
Kojto 101:7cff1c4259d7 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 101:7cff1c4259d7 72 {
Kojto 101:7cff1c4259d7 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 101:7cff1c4259d7 74 return(__regAPSR);
Kojto 101:7cff1c4259d7 75 }
Kojto 101:7cff1c4259d7 76
Kojto 101:7cff1c4259d7 77
Kojto 101:7cff1c4259d7 78 /** \brief Get CPSR Register
Kojto 101:7cff1c4259d7 79
Kojto 101:7cff1c4259d7 80 This function returns the content of the CPSR Register.
Kojto 101:7cff1c4259d7 81
Kojto 101:7cff1c4259d7 82 \return CPSR Register value
Kojto 101:7cff1c4259d7 83 */
Kojto 101:7cff1c4259d7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 101:7cff1c4259d7 85 {
Kojto 101:7cff1c4259d7 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 101:7cff1c4259d7 87 return(__regCPSR);
Kojto 101:7cff1c4259d7 88 }
Kojto 101:7cff1c4259d7 89
Kojto 101:7cff1c4259d7 90 /** \brief Set Stack Pointer
Kojto 101:7cff1c4259d7 91
Kojto 101:7cff1c4259d7 92 This function assigns the given value to the current stack pointer.
Kojto 101:7cff1c4259d7 93
Kojto 101:7cff1c4259d7 94 \param [in] topOfStack Stack Pointer value to set
Kojto 101:7cff1c4259d7 95 */
Kojto 101:7cff1c4259d7 96 register uint32_t __regSP __ASM("sp");
Kojto 101:7cff1c4259d7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 101:7cff1c4259d7 98 {
Kojto 101:7cff1c4259d7 99 __regSP = topOfStack;
Kojto 101:7cff1c4259d7 100 }
Kojto 101:7cff1c4259d7 101
Kojto 101:7cff1c4259d7 102
Kojto 101:7cff1c4259d7 103 /** \brief Get link register
Kojto 101:7cff1c4259d7 104
Kojto 101:7cff1c4259d7 105 This function returns the value of the link register
Kojto 101:7cff1c4259d7 106
Kojto 101:7cff1c4259d7 107 \return Value of link register
Kojto 101:7cff1c4259d7 108 */
Kojto 101:7cff1c4259d7 109 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 101:7cff1c4259d7 111 {
Kojto 101:7cff1c4259d7 112 return(__reglr);
Kojto 101:7cff1c4259d7 113 }
Kojto 101:7cff1c4259d7 114
Kojto 101:7cff1c4259d7 115 /** \brief Set link register
Kojto 101:7cff1c4259d7 116
Kojto 101:7cff1c4259d7 117 This function sets the value of the link register
Kojto 101:7cff1c4259d7 118
Kojto 101:7cff1c4259d7 119 \param [in] lr LR value to set
Kojto 101:7cff1c4259d7 120 */
Kojto 101:7cff1c4259d7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 101:7cff1c4259d7 122 {
Kojto 101:7cff1c4259d7 123 __reglr = lr;
Kojto 101:7cff1c4259d7 124 }
Kojto 101:7cff1c4259d7 125
Kojto 101:7cff1c4259d7 126 /** \brief Set Process Stack Pointer
Kojto 101:7cff1c4259d7 127
Kojto 101:7cff1c4259d7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 101:7cff1c4259d7 129
Kojto 101:7cff1c4259d7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 101:7cff1c4259d7 131 */
Kojto 101:7cff1c4259d7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 101:7cff1c4259d7 133 {
Kojto 101:7cff1c4259d7 134 ARM
Kojto 101:7cff1c4259d7 135 PRESERVE8
Kojto 101:7cff1c4259d7 136
Kojto 101:7cff1c4259d7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 101:7cff1c4259d7 138 MRS R1, CPSR
Kojto 101:7cff1c4259d7 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 101:7cff1c4259d7 140 MOV SP, R0
Kojto 101:7cff1c4259d7 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 101:7cff1c4259d7 142 ISB
Kojto 101:7cff1c4259d7 143 BX LR
Kojto 101:7cff1c4259d7 144
Kojto 101:7cff1c4259d7 145 }
Kojto 101:7cff1c4259d7 146
Kojto 101:7cff1c4259d7 147 /** \brief Set User Mode
Kojto 101:7cff1c4259d7 148
Kojto 101:7cff1c4259d7 149 This function changes the processor state to User Mode
Kojto 101:7cff1c4259d7 150 */
Kojto 101:7cff1c4259d7 151 __STATIC_ASM void __set_CPS_USR(void)
Kojto 101:7cff1c4259d7 152 {
Kojto 101:7cff1c4259d7 153 ARM
Kojto 101:7cff1c4259d7 154
Kojto 101:7cff1c4259d7 155 CPS #MODE_USR
Kojto 101:7cff1c4259d7 156 BX LR
Kojto 101:7cff1c4259d7 157 }
Kojto 101:7cff1c4259d7 158
Kojto 101:7cff1c4259d7 159
Kojto 101:7cff1c4259d7 160 /** \brief Enable FIQ
Kojto 101:7cff1c4259d7 161
Kojto 101:7cff1c4259d7 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 163 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 164 */
Kojto 101:7cff1c4259d7 165 #define __enable_fault_irq __enable_fiq
Kojto 101:7cff1c4259d7 166
Kojto 101:7cff1c4259d7 167
Kojto 101:7cff1c4259d7 168 /** \brief Disable FIQ
Kojto 101:7cff1c4259d7 169
Kojto 101:7cff1c4259d7 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 171 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 172 */
Kojto 101:7cff1c4259d7 173 #define __disable_fault_irq __disable_fiq
Kojto 101:7cff1c4259d7 174
Kojto 101:7cff1c4259d7 175
Kojto 101:7cff1c4259d7 176 /** \brief Get FPSCR
Kojto 101:7cff1c4259d7 177
Kojto 101:7cff1c4259d7 178 This function returns the current value of the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 179
Kojto 101:7cff1c4259d7 180 \return Floating Point Status/Control register value
Kojto 101:7cff1c4259d7 181 */
Kojto 101:7cff1c4259d7 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 101:7cff1c4259d7 183 {
Kojto 101:7cff1c4259d7 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 185 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 186 return(__regfpscr);
Kojto 101:7cff1c4259d7 187 #else
Kojto 101:7cff1c4259d7 188 return(0);
Kojto 101:7cff1c4259d7 189 #endif
Kojto 101:7cff1c4259d7 190 }
Kojto 101:7cff1c4259d7 191
Kojto 101:7cff1c4259d7 192
Kojto 101:7cff1c4259d7 193 /** \brief Set FPSCR
Kojto 101:7cff1c4259d7 194
Kojto 101:7cff1c4259d7 195 This function assigns the given value to the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 196
Kojto 101:7cff1c4259d7 197 \param [in] fpscr Floating Point Status/Control value to set
Kojto 101:7cff1c4259d7 198 */
Kojto 101:7cff1c4259d7 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 101:7cff1c4259d7 200 {
Kojto 101:7cff1c4259d7 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 202 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 203 __regfpscr = (fpscr);
Kojto 101:7cff1c4259d7 204 #endif
Kojto 101:7cff1c4259d7 205 }
Kojto 101:7cff1c4259d7 206
Kojto 101:7cff1c4259d7 207 /** \brief Get FPEXC
Kojto 101:7cff1c4259d7 208
Kojto 101:7cff1c4259d7 209 This function returns the current value of the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 210
Kojto 101:7cff1c4259d7 211 \return Floating Point Exception Control register value
Kojto 101:7cff1c4259d7 212 */
Kojto 101:7cff1c4259d7 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 101:7cff1c4259d7 214 {
Kojto 101:7cff1c4259d7 215 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 216 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 217 return(__regfpexc);
Kojto 101:7cff1c4259d7 218 #else
Kojto 101:7cff1c4259d7 219 return(0);
Kojto 101:7cff1c4259d7 220 #endif
Kojto 101:7cff1c4259d7 221 }
Kojto 101:7cff1c4259d7 222
Kojto 101:7cff1c4259d7 223
Kojto 101:7cff1c4259d7 224 /** \brief Set FPEXC
Kojto 101:7cff1c4259d7 225
Kojto 101:7cff1c4259d7 226 This function assigns the given value to the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 227
Kojto 101:7cff1c4259d7 228 \param [in] fpscr Floating Point Exception Control value to set
Kojto 101:7cff1c4259d7 229 */
Kojto 101:7cff1c4259d7 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 101:7cff1c4259d7 231 {
Kojto 101:7cff1c4259d7 232 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 233 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 234 __regfpexc = (fpexc);
Kojto 101:7cff1c4259d7 235 #endif
Kojto 101:7cff1c4259d7 236 }
Kojto 101:7cff1c4259d7 237
Kojto 101:7cff1c4259d7 238 /** \brief Get CPACR
Kojto 101:7cff1c4259d7 239
Kojto 101:7cff1c4259d7 240 This function returns the current value of the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 241
Kojto 101:7cff1c4259d7 242 \return Coprocessor Access Control register value
Kojto 101:7cff1c4259d7 243 */
Kojto 101:7cff1c4259d7 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 101:7cff1c4259d7 245 {
Kojto 101:7cff1c4259d7 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 247 return __regCPACR;
Kojto 101:7cff1c4259d7 248 }
Kojto 101:7cff1c4259d7 249
Kojto 101:7cff1c4259d7 250 /** \brief Set CPACR
Kojto 101:7cff1c4259d7 251
Kojto 101:7cff1c4259d7 252 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 253
Kojto 108:34e6b704fe68 254 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 101:7cff1c4259d7 255 */
Kojto 101:7cff1c4259d7 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 101:7cff1c4259d7 257 {
Kojto 101:7cff1c4259d7 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 259 __regCPACR = cpacr;
Kojto 101:7cff1c4259d7 260 __ISB();
Kojto 101:7cff1c4259d7 261 }
Kojto 101:7cff1c4259d7 262
Kojto 101:7cff1c4259d7 263 /** \brief Get CBAR
Kojto 101:7cff1c4259d7 264
Kojto 101:7cff1c4259d7 265 This function returns the value of the Configuration Base Address register.
Kojto 101:7cff1c4259d7 266
Kojto 101:7cff1c4259d7 267 \return Configuration Base Address register value
Kojto 101:7cff1c4259d7 268 */
Kojto 101:7cff1c4259d7 269 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 101:7cff1c4259d7 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 101:7cff1c4259d7 271 return(__regCBAR);
Kojto 101:7cff1c4259d7 272 }
Kojto 101:7cff1c4259d7 273
Kojto 101:7cff1c4259d7 274 /** \brief Get TTBR0
Kojto 101:7cff1c4259d7 275
Kojto 108:34e6b704fe68 276 This function returns the value of the Translation Table Base Register 0.
Kojto 101:7cff1c4259d7 277
Kojto 101:7cff1c4259d7 278 \return Translation Table Base Register 0 value
Kojto 101:7cff1c4259d7 279 */
Kojto 101:7cff1c4259d7 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 101:7cff1c4259d7 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 282 return(__regTTBR0);
Kojto 101:7cff1c4259d7 283 }
Kojto 101:7cff1c4259d7 284
Kojto 101:7cff1c4259d7 285 /** \brief Set TTBR0
Kojto 101:7cff1c4259d7 286
Kojto 108:34e6b704fe68 287 This function assigns the given value to the Translation Table Base Register 0.
Kojto 101:7cff1c4259d7 288
Kojto 101:7cff1c4259d7 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 101:7cff1c4259d7 290 */
Kojto 101:7cff1c4259d7 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 101:7cff1c4259d7 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 293 __regTTBR0 = ttbr0;
Kojto 101:7cff1c4259d7 294 __ISB();
Kojto 101:7cff1c4259d7 295 }
Kojto 101:7cff1c4259d7 296
Kojto 101:7cff1c4259d7 297 /** \brief Get DACR
Kojto 101:7cff1c4259d7 298
Kojto 101:7cff1c4259d7 299 This function returns the value of the Domain Access Control Register.
Kojto 101:7cff1c4259d7 300
Kojto 101:7cff1c4259d7 301 \return Domain Access Control Register value
Kojto 101:7cff1c4259d7 302 */
Kojto 101:7cff1c4259d7 303 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 101:7cff1c4259d7 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 305 return(__regDACR);
Kojto 101:7cff1c4259d7 306 }
Kojto 101:7cff1c4259d7 307
Kojto 101:7cff1c4259d7 308 /** \brief Set DACR
Kojto 101:7cff1c4259d7 309
Kojto 108:34e6b704fe68 310 This function assigns the given value to the Domain Access Control Register.
Kojto 101:7cff1c4259d7 311
Kojto 101:7cff1c4259d7 312 \param [in] dacr Domain Access Control Register value to set
Kojto 101:7cff1c4259d7 313 */
Kojto 101:7cff1c4259d7 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 101:7cff1c4259d7 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 316 __regDACR = dacr;
Kojto 101:7cff1c4259d7 317 __ISB();
Kojto 101:7cff1c4259d7 318 }
Kojto 101:7cff1c4259d7 319
Kojto 101:7cff1c4259d7 320 /******************************** Cache and BTAC enable ****************************************************/
Kojto 101:7cff1c4259d7 321
Kojto 101:7cff1c4259d7 322 /** \brief Set SCTLR
Kojto 101:7cff1c4259d7 323
Kojto 101:7cff1c4259d7 324 This function assigns the given value to the System Control Register.
Kojto 101:7cff1c4259d7 325
Kojto 108:34e6b704fe68 326 \param [in] sctlr System Control Register value to set
Kojto 101:7cff1c4259d7 327 */
Kojto 101:7cff1c4259d7 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 101:7cff1c4259d7 329 {
Kojto 101:7cff1c4259d7 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 331 __regSCTLR = sctlr;
Kojto 101:7cff1c4259d7 332 }
Kojto 101:7cff1c4259d7 333
Kojto 101:7cff1c4259d7 334 /** \brief Get SCTLR
Kojto 101:7cff1c4259d7 335
Kojto 101:7cff1c4259d7 336 This function returns the value of the System Control Register.
Kojto 101:7cff1c4259d7 337
Kojto 101:7cff1c4259d7 338 \return System Control Register value
Kojto 101:7cff1c4259d7 339 */
Kojto 101:7cff1c4259d7 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 101:7cff1c4259d7 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 342 return(__regSCTLR);
Kojto 101:7cff1c4259d7 343 }
Kojto 101:7cff1c4259d7 344
Kojto 101:7cff1c4259d7 345 /** \brief Enable Caches
Kojto 101:7cff1c4259d7 346
Kojto 101:7cff1c4259d7 347 Enable Caches
Kojto 101:7cff1c4259d7 348 */
Kojto 101:7cff1c4259d7 349 __STATIC_INLINE void __enable_caches(void) {
Kojto 101:7cff1c4259d7 350 // Set I bit 12 to enable I Cache
Kojto 101:7cff1c4259d7 351 // Set C bit 2 to enable D Cache
Kojto 101:7cff1c4259d7 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 101:7cff1c4259d7 353 }
Kojto 101:7cff1c4259d7 354
Kojto 101:7cff1c4259d7 355 /** \brief Disable Caches
Kojto 101:7cff1c4259d7 356
Kojto 101:7cff1c4259d7 357 Disable Caches
Kojto 101:7cff1c4259d7 358 */
Kojto 101:7cff1c4259d7 359 __STATIC_INLINE void __disable_caches(void) {
Kojto 101:7cff1c4259d7 360 // Clear I bit 12 to disable I Cache
Kojto 101:7cff1c4259d7 361 // Clear C bit 2 to disable D Cache
Kojto 101:7cff1c4259d7 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 101:7cff1c4259d7 363 __ISB();
Kojto 101:7cff1c4259d7 364 }
Kojto 101:7cff1c4259d7 365
Kojto 101:7cff1c4259d7 366 /** \brief Enable BTAC
Kojto 101:7cff1c4259d7 367
Kojto 101:7cff1c4259d7 368 Enable BTAC
Kojto 101:7cff1c4259d7 369 */
Kojto 101:7cff1c4259d7 370 __STATIC_INLINE void __enable_btac(void) {
Kojto 101:7cff1c4259d7 371 // Set Z bit 11 to enable branch prediction
Kojto 101:7cff1c4259d7 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 101:7cff1c4259d7 373 __ISB();
Kojto 101:7cff1c4259d7 374 }
Kojto 101:7cff1c4259d7 375
Kojto 101:7cff1c4259d7 376 /** \brief Disable BTAC
Kojto 101:7cff1c4259d7 377
Kojto 101:7cff1c4259d7 378 Disable BTAC
Kojto 101:7cff1c4259d7 379 */
Kojto 101:7cff1c4259d7 380 __STATIC_INLINE void __disable_btac(void) {
Kojto 101:7cff1c4259d7 381 // Clear Z bit 11 to disable branch prediction
Kojto 101:7cff1c4259d7 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 101:7cff1c4259d7 383 }
Kojto 101:7cff1c4259d7 384
Kojto 101:7cff1c4259d7 385
Kojto 101:7cff1c4259d7 386 /** \brief Enable MMU
Kojto 101:7cff1c4259d7 387
Kojto 101:7cff1c4259d7 388 Enable MMU
Kojto 101:7cff1c4259d7 389 */
Kojto 101:7cff1c4259d7 390 __STATIC_INLINE void __enable_mmu(void) {
Kojto 101:7cff1c4259d7 391 // Set M bit 0 to enable the MMU
Kojto 101:7cff1c4259d7 392 // Set AFE bit to enable simplified access permissions model
Kojto 101:7cff1c4259d7 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 101:7cff1c4259d7 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 101:7cff1c4259d7 395 __ISB();
Kojto 101:7cff1c4259d7 396 }
Kojto 101:7cff1c4259d7 397
Kojto 108:34e6b704fe68 398 /** \brief Disable MMU
Kojto 101:7cff1c4259d7 399
Kojto 108:34e6b704fe68 400 Disable MMU
Kojto 101:7cff1c4259d7 401 */
Kojto 101:7cff1c4259d7 402 __STATIC_INLINE void __disable_mmu(void) {
Kojto 101:7cff1c4259d7 403 // Clear M bit 0 to disable the MMU
Kojto 101:7cff1c4259d7 404 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 101:7cff1c4259d7 405 __ISB();
Kojto 101:7cff1c4259d7 406 }
Kojto 101:7cff1c4259d7 407
Kojto 101:7cff1c4259d7 408 /******************************** TLB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 409 /** \brief Invalidate the whole tlb
Kojto 101:7cff1c4259d7 410
Kojto 101:7cff1c4259d7 411 TLBIALL. Invalidate the whole tlb
Kojto 101:7cff1c4259d7 412 */
Kojto 101:7cff1c4259d7 413
Kojto 101:7cff1c4259d7 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 101:7cff1c4259d7 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 101:7cff1c4259d7 416 __TLBIALL = 0;
Kojto 101:7cff1c4259d7 417 __DSB();
Kojto 101:7cff1c4259d7 418 __ISB();
Kojto 101:7cff1c4259d7 419 }
Kojto 101:7cff1c4259d7 420
Kojto 101:7cff1c4259d7 421 /******************************** BTB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 422 /** \brief Invalidate entire branch predictor array
Kojto 101:7cff1c4259d7 423
Kojto 101:7cff1c4259d7 424 BPIALL. Branch Predictor Invalidate All.
Kojto 101:7cff1c4259d7 425 */
Kojto 101:7cff1c4259d7 426
Kojto 101:7cff1c4259d7 427 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 101:7cff1c4259d7 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 101:7cff1c4259d7 429 __BPIALL = 0;
Kojto 101:7cff1c4259d7 430 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 431 __ISB(); //ensure instruction fetch path sees new state
Kojto 101:7cff1c4259d7 432 }
Kojto 101:7cff1c4259d7 433
Kojto 101:7cff1c4259d7 434
Kojto 101:7cff1c4259d7 435 /******************************** L1 cache operations ******************************************************/
Kojto 101:7cff1c4259d7 436
Kojto 101:7cff1c4259d7 437 /** \brief Invalidate the whole I$
Kojto 101:7cff1c4259d7 438
Kojto 101:7cff1c4259d7 439 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 101:7cff1c4259d7 440 */
Kojto 101:7cff1c4259d7 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 101:7cff1c4259d7 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 101:7cff1c4259d7 443 __ICIALLU = 0;
Kojto 101:7cff1c4259d7 444 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 445 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 101:7cff1c4259d7 446 }
Kojto 101:7cff1c4259d7 447
Kojto 101:7cff1c4259d7 448 /** \brief Clean D$ by MVA
Kojto 101:7cff1c4259d7 449
Kojto 101:7cff1c4259d7 450 DCCMVAC. Data cache clean by MVA to PoC
Kojto 101:7cff1c4259d7 451 */
Kojto 101:7cff1c4259d7 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 101:7cff1c4259d7 454 __DCCMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 456 }
Kojto 101:7cff1c4259d7 457
Kojto 101:7cff1c4259d7 458 /** \brief Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 459
Kojto 101:7cff1c4259d7 460 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 461 */
Kojto 101:7cff1c4259d7 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 101:7cff1c4259d7 464 __DCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 466 }
Kojto 101:7cff1c4259d7 467
Kojto 101:7cff1c4259d7 468 /** \brief Clean and Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 469
Kojto 101:7cff1c4259d7 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 471 */
Kojto 101:7cff1c4259d7 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 101:7cff1c4259d7 474 __DCCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 476 }
Kojto 101:7cff1c4259d7 477
Kojto 108:34e6b704fe68 478 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 108:34e6b704fe68 479
Kojto 108:34e6b704fe68 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 101:7cff1c4259d7 481 */
Kojto 101:7cff1c4259d7 482 #pragma push
Kojto 101:7cff1c4259d7 483 #pragma arm
Kojto 101:7cff1c4259d7 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 101:7cff1c4259d7 485 ARM
Kojto 101:7cff1c4259d7 486
Kojto 101:7cff1c4259d7 487 PUSH {R4-R11}
Kojto 101:7cff1c4259d7 488
Kojto 101:7cff1c4259d7 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 101:7cff1c4259d7 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 101:7cff1c4259d7 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 101:7cff1c4259d7 492 BEQ Finished // If 0, no need to clean
Kojto 101:7cff1c4259d7 493
Kojto 101:7cff1c4259d7 494 MOV R10, #0 // R10 holds current cache level << 1
Kojto 101:7cff1c4259d7 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 101:7cff1c4259d7 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 101:7cff1c4259d7 497 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 101:7cff1c4259d7 498 CMP R1, #2
Kojto 101:7cff1c4259d7 499 BLT Skip // No cache or only instruction cache at this level
Kojto 101:7cff1c4259d7 500
Kojto 101:7cff1c4259d7 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 101:7cff1c4259d7 502 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 101:7cff1c4259d7 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 101:7cff1c4259d7 504 AND R2, R1, #7 // Extract the line length field
Kojto 101:7cff1c4259d7 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 101:7cff1c4259d7 506 LDR R4, =0x3FF
Kojto 101:7cff1c4259d7 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 101:7cff1c4259d7 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 101:7cff1c4259d7 509 LDR R7, =0x7FFF
Kojto 101:7cff1c4259d7 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 101:7cff1c4259d7 511
Kojto 101:7cff1c4259d7 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 101:7cff1c4259d7 513
Kojto 101:7cff1c4259d7 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 101:7cff1c4259d7 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 101:7cff1c4259d7 516 CMP R0, #0
Kojto 101:7cff1c4259d7 517 BNE Dccsw
Kojto 101:7cff1c4259d7 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 519 B cont
Kojto 101:7cff1c4259d7 520 Dccsw CMP R0, #1
Kojto 101:7cff1c4259d7 521 BNE Dccisw
Kojto 101:7cff1c4259d7 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 523 B cont
Kojto 108:34e6b704fe68 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 525 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 101:7cff1c4259d7 526 BGE Loop3
Kojto 101:7cff1c4259d7 527 SUBS R7, R7, #1 // Decrement the Set number
Kojto 101:7cff1c4259d7 528 BGE Loop2
Kojto 108:34e6b704fe68 529 Skip ADD R10, R10, #2 // Increment the cache number
Kojto 101:7cff1c4259d7 530 CMP R3, R10
Kojto 101:7cff1c4259d7 531 BGT Loop1
Kojto 101:7cff1c4259d7 532
Kojto 101:7cff1c4259d7 533 Finished
Kojto 101:7cff1c4259d7 534 DSB
Kojto 101:7cff1c4259d7 535 POP {R4-R11}
Kojto 101:7cff1c4259d7 536 BX lr
Kojto 101:7cff1c4259d7 537
Kojto 101:7cff1c4259d7 538 }
Kojto 101:7cff1c4259d7 539 #pragma pop
Kojto 101:7cff1c4259d7 540
Kojto 101:7cff1c4259d7 541
Kojto 101:7cff1c4259d7 542 /** \brief Invalidate the whole D$
Kojto 101:7cff1c4259d7 543
Kojto 101:7cff1c4259d7 544 DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 545 */
Kojto 101:7cff1c4259d7 546
Kojto 101:7cff1c4259d7 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 548 __v7_all_cache(0);
Kojto 101:7cff1c4259d7 549 }
Kojto 101:7cff1c4259d7 550
Kojto 101:7cff1c4259d7 551 /** \brief Clean the whole D$
Kojto 101:7cff1c4259d7 552
Kojto 101:7cff1c4259d7 553 DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 554 */
Kojto 101:7cff1c4259d7 555
Kojto 101:7cff1c4259d7 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 101:7cff1c4259d7 557 __v7_all_cache(1);
Kojto 101:7cff1c4259d7 558 }
Kojto 101:7cff1c4259d7 559
Kojto 101:7cff1c4259d7 560 /** \brief Clean and invalidate the whole D$
Kojto 101:7cff1c4259d7 561
Kojto 101:7cff1c4259d7 562 DCCISW. Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 563 */
Kojto 101:7cff1c4259d7 564
Kojto 101:7cff1c4259d7 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 566 __v7_all_cache(2);
Kojto 101:7cff1c4259d7 567 }
Kojto 101:7cff1c4259d7 568
Kojto 101:7cff1c4259d7 569 #include "core_ca_mmu.h"
Kojto 101:7cff1c4259d7 570
Kojto 101:7cff1c4259d7 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 101:7cff1c4259d7 572
Kojto 115:87f2f5183dfb 573 #define __inline inline
Kojto 115:87f2f5183dfb 574
Kojto 115:87f2f5183dfb 575 inline static uint32_t __disable_irq_iar() {
Kojto 115:87f2f5183dfb 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
Kojto 115:87f2f5183dfb 577 __disable_irq();
Kojto 115:87f2f5183dfb 578 return irq_dis;
Kojto 115:87f2f5183dfb 579 }
Kojto 115:87f2f5183dfb 580
Kojto 115:87f2f5183dfb 581 #define MODE_USR 0x10
Kojto 115:87f2f5183dfb 582 #define MODE_FIQ 0x11
Kojto 115:87f2f5183dfb 583 #define MODE_IRQ 0x12
Kojto 115:87f2f5183dfb 584 #define MODE_SVC 0x13
Kojto 115:87f2f5183dfb 585 #define MODE_MON 0x16
Kojto 115:87f2f5183dfb 586 #define MODE_ABT 0x17
Kojto 115:87f2f5183dfb 587 #define MODE_HYP 0x1A
Kojto 115:87f2f5183dfb 588 #define MODE_UND 0x1B
Kojto 115:87f2f5183dfb 589 #define MODE_SYS 0x1F
Kojto 115:87f2f5183dfb 590
Kojto 115:87f2f5183dfb 591 /** \brief Set Process Stack Pointer
Kojto 115:87f2f5183dfb 592
Kojto 115:87f2f5183dfb 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 115:87f2f5183dfb 594
Kojto 115:87f2f5183dfb 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 115:87f2f5183dfb 596 */
Kojto 115:87f2f5183dfb 597 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
Kojto 115:87f2f5183dfb 599 __asm(
Kojto 115:87f2f5183dfb 600 " ARM\n"
Kojto 115:87f2f5183dfb 601 // " PRESERVE8\n"
Kojto 115:87f2f5183dfb 602
Kojto 115:87f2f5183dfb 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
Kojto 115:87f2f5183dfb 604 " MRS R1, CPSR \n"
Kojto 115:87f2f5183dfb 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
Kojto 115:87f2f5183dfb 606 " MOV SP, R0 \n"
Kojto 115:87f2f5183dfb 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
Kojto 115:87f2f5183dfb 608 " ISB \n"
Kojto 115:87f2f5183dfb 609 " BX LR \n");
Kojto 115:87f2f5183dfb 610 }
Kojto 115:87f2f5183dfb 611
Kojto 115:87f2f5183dfb 612 /** \brief Set User Mode
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 This function changes the processor state to User Mode
Kojto 115:87f2f5183dfb 615 */
Kojto 115:87f2f5183dfb 616 // from rt_CMSIS.c
Kojto 115:87f2f5183dfb 617 __arm static inline void __set_CPS_USR(void) {
Kojto 115:87f2f5183dfb 618 __asm(
Kojto 115:87f2f5183dfb 619 " ARM \n"
Kojto 115:87f2f5183dfb 620
Kojto 115:87f2f5183dfb 621 " CPS #0x10 \n" // MODE_USR
Kojto 115:87f2f5183dfb 622 " BX LR\n");
Kojto 115:87f2f5183dfb 623 }
Kojto 115:87f2f5183dfb 624
Kojto 115:87f2f5183dfb 625 /** \brief Set TTBR0
Kojto 115:87f2f5183dfb 626
Kojto 115:87f2f5183dfb 627 This function assigns the given value to the Translation Table Base Register 0.
Kojto 115:87f2f5183dfb 628
Kojto 115:87f2f5183dfb 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 115:87f2f5183dfb 630 */
Kojto 115:87f2f5183dfb 631 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 115:87f2f5183dfb 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 634 __ISB();
Kojto 115:87f2f5183dfb 635 }
Kojto 115:87f2f5183dfb 636
Kojto 115:87f2f5183dfb 637 /** \brief Set DACR
Kojto 115:87f2f5183dfb 638
Kojto 115:87f2f5183dfb 639 This function assigns the given value to the Domain Access Control Register.
Kojto 115:87f2f5183dfb 640
Kojto 115:87f2f5183dfb 641 \param [in] dacr Domain Access Control Register value to set
Kojto 115:87f2f5183dfb 642 */
Kojto 115:87f2f5183dfb 643 // from mmu_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 115:87f2f5183dfb 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 646 __ISB();
Kojto 115:87f2f5183dfb 647 }
Kojto 115:87f2f5183dfb 648
Kojto 115:87f2f5183dfb 649
Kojto 115:87f2f5183dfb 650 /******************************** Cache and BTAC enable ****************************************************/
Kojto 115:87f2f5183dfb 651 /** \brief Set SCTLR
Kojto 115:87f2f5183dfb 652
Kojto 115:87f2f5183dfb 653 This function assigns the given value to the System Control Register.
Kojto 115:87f2f5183dfb 654
Kojto 115:87f2f5183dfb 655 \param [in] sctlr System Control Register value to set
Kojto 115:87f2f5183dfb 656 */
Kojto 115:87f2f5183dfb 657 // from __enable_mmu()
Kojto 115:87f2f5183dfb 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
Kojto 115:87f2f5183dfb 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
Kojto 115:87f2f5183dfb 660 }
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 /** \brief Get SCTLR
Kojto 115:87f2f5183dfb 663
Kojto 115:87f2f5183dfb 664 This function returns the value of the System Control Register.
Kojto 115:87f2f5183dfb 665
Kojto 115:87f2f5183dfb 666 \return System Control Register value
Kojto 115:87f2f5183dfb 667 */
Kojto 115:87f2f5183dfb 668 // from __enable_mmu()
Kojto 115:87f2f5183dfb 669 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 115:87f2f5183dfb 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
Kojto 115:87f2f5183dfb 671 return __regSCTLR;
Kojto 115:87f2f5183dfb 672 }
Kojto 115:87f2f5183dfb 673
Kojto 115:87f2f5183dfb 674 /** \brief Enable Caches
Kojto 115:87f2f5183dfb 675
Kojto 115:87f2f5183dfb 676 Enable Caches
Kojto 115:87f2f5183dfb 677 */
Kojto 115:87f2f5183dfb 678 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 679 __STATIC_INLINE void __enable_caches(void) {
Kojto 115:87f2f5183dfb 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 115:87f2f5183dfb 681 }
Kojto 115:87f2f5183dfb 682
Kojto 115:87f2f5183dfb 683 /** \brief Enable BTAC
Kojto 115:87f2f5183dfb 684
Kojto 115:87f2f5183dfb 685 Enable BTAC
Kojto 115:87f2f5183dfb 686 */
Kojto 115:87f2f5183dfb 687 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 688 __STATIC_INLINE void __enable_btac(void) {
Kojto 115:87f2f5183dfb 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 115:87f2f5183dfb 690 __ISB();
Kojto 115:87f2f5183dfb 691 }
Kojto 115:87f2f5183dfb 692
Kojto 115:87f2f5183dfb 693 /** \brief Enable MMU
Kojto 115:87f2f5183dfb 694
Kojto 115:87f2f5183dfb 695 Enable MMU
Kojto 115:87f2f5183dfb 696 */
Kojto 115:87f2f5183dfb 697 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 698 __STATIC_INLINE void __enable_mmu(void) {
Kojto 115:87f2f5183dfb 699 // Set M bit 0 to enable the MMU
Kojto 115:87f2f5183dfb 700 // Set AFE bit to enable simplified access permissions model
Kojto 115:87f2f5183dfb 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 115:87f2f5183dfb 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 115:87f2f5183dfb 703 __ISB();
Kojto 115:87f2f5183dfb 704 }
Kojto 115:87f2f5183dfb 705
Kojto 115:87f2f5183dfb 706 /******************************** TLB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 707 /** \brief Invalidate the whole tlb
Kojto 115:87f2f5183dfb 708
Kojto 115:87f2f5183dfb 709 TLBIALL. Invalidate the whole tlb
Kojto 115:87f2f5183dfb 710 */
Kojto 115:87f2f5183dfb 711 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 115:87f2f5183dfb 713 uint32_t val = 0;
Kojto 115:87f2f5183dfb 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
Kojto 115:87f2f5183dfb 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
Kojto 115:87f2f5183dfb 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 717 __DSB();
Kojto 115:87f2f5183dfb 718 __ISB();
Kojto 115:87f2f5183dfb 719 }
Kojto 115:87f2f5183dfb 720
Kojto 115:87f2f5183dfb 721 /******************************** BTB maintenance operations ************************************************/
Kojto 115:87f2f5183dfb 722 /** \brief Invalidate entire branch predictor array
Kojto 115:87f2f5183dfb 723
Kojto 115:87f2f5183dfb 724 BPIALL. Branch Predictor Invalidate All.
Kojto 115:87f2f5183dfb 725 */
Kojto 115:87f2f5183dfb 726 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 727 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 115:87f2f5183dfb 728 uint32_t val = 0;
Kojto 115:87f2f5183dfb 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
Kojto 115:87f2f5183dfb 730 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 731 __ISB(); //ensure instruction fetch path sees new state
Kojto 115:87f2f5183dfb 732 }
Kojto 115:87f2f5183dfb 733
Kojto 115:87f2f5183dfb 734
Kojto 115:87f2f5183dfb 735 /******************************** L1 cache operations ******************************************************/
Kojto 115:87f2f5183dfb 736
Kojto 115:87f2f5183dfb 737 /** \brief Invalidate the whole I$
Kojto 115:87f2f5183dfb 738
Kojto 115:87f2f5183dfb 739 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 115:87f2f5183dfb 740 */
Kojto 115:87f2f5183dfb 741 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 115:87f2f5183dfb 743 uint32_t val = 0;
Kojto 115:87f2f5183dfb 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
Kojto 115:87f2f5183dfb 745 __DSB(); //ensure completion of the invalidation
Kojto 115:87f2f5183dfb 746 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 115:87f2f5183dfb 747 }
Kojto 115:87f2f5183dfb 748
Kojto 115:87f2f5183dfb 749 // from __v7_inv_dcache_all()
Kojto 115:87f2f5183dfb 750 __arm static inline void __v7_all_cache(uint32_t op) {
Kojto 115:87f2f5183dfb 751 __asm(
Kojto 115:87f2f5183dfb 752 " ARM \n"
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 " PUSH {R4-R11} \n"
Kojto 115:87f2f5183dfb 755
Kojto 115:87f2f5183dfb 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
Kojto 115:87f2f5183dfb 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
Kojto 115:87f2f5183dfb 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
Kojto 115:87f2f5183dfb 759 " BEQ Finished\n" // If 0, no need to clean
Kojto 115:87f2f5183dfb 760
Kojto 115:87f2f5183dfb 761 " MOV R10, #0\n" // R10 holds current cache level << 1
Kojto 115:87f2f5183dfb 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
Kojto 115:87f2f5183dfb 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
Kojto 115:87f2f5183dfb 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
Kojto 115:87f2f5183dfb 765 " CMP R1, #2 \n"
Kojto 115:87f2f5183dfb 766 " BLT Skip \n" // No cache or only instruction cache at this level
Kojto 115:87f2f5183dfb 767
Kojto 115:87f2f5183dfb 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
Kojto 115:87f2f5183dfb 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
Kojto 115:87f2f5183dfb 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
Kojto 115:87f2f5183dfb 771 " AND R2, R1, #7 \n" // Extract the line length field
Kojto 115:87f2f5183dfb 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
Kojto 115:87f2f5183dfb 773 " movw R4, #0x3FF \n"
Kojto 115:87f2f5183dfb 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
Kojto 115:87f2f5183dfb 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
Kojto 115:87f2f5183dfb 776 " movw R7, #0x7FFF \n"
Kojto 115:87f2f5183dfb 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
Kojto 115:87f2f5183dfb 778
Kojto 115:87f2f5183dfb 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
Kojto 115:87f2f5183dfb 780
Kojto 115:87f2f5183dfb 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
Kojto 115:87f2f5183dfb 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
Kojto 115:87f2f5183dfb 783 " CMP R0, #0 \n"
Kojto 115:87f2f5183dfb 784 " BNE Dccsw \n"
Kojto 115:87f2f5183dfb 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 786 " B cont \n"
Kojto 115:87f2f5183dfb 787 "Dccsw: CMP R0, #1 \n"
Kojto 115:87f2f5183dfb 788 " BNE Dccisw \n"
Kojto 115:87f2f5183dfb 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
Kojto 115:87f2f5183dfb 790 " B cont \n"
Kojto 115:87f2f5183dfb 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
Kojto 115:87f2f5183dfb 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
Kojto 115:87f2f5183dfb 793 " BGE Loop3 \n"
Kojto 115:87f2f5183dfb 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
Kojto 115:87f2f5183dfb 795 " BGE Loop2 \n"
Kojto 115:87f2f5183dfb 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
Kojto 115:87f2f5183dfb 797 " CMP R3, R10 \n"
Kojto 115:87f2f5183dfb 798 " BGT Loop1 \n"
Kojto 115:87f2f5183dfb 799
Kojto 115:87f2f5183dfb 800 "Finished: \n"
Kojto 115:87f2f5183dfb 801 " DSB \n"
Kojto 115:87f2f5183dfb 802 " POP {R4-R11} \n"
Kojto 115:87f2f5183dfb 803 " BX lr \n" );
Kojto 115:87f2f5183dfb 804 }
Kojto 115:87f2f5183dfb 805
Kojto 115:87f2f5183dfb 806 /** \brief Invalidate the whole D$
Kojto 115:87f2f5183dfb 807
Kojto 115:87f2f5183dfb 808 DCISW. Invalidate by Set/Way
Kojto 115:87f2f5183dfb 809 */
Kojto 115:87f2f5183dfb 810 // from system_Renesas_RZ_A1.c
Kojto 115:87f2f5183dfb 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 115:87f2f5183dfb 812 __v7_all_cache(0);
Kojto 115:87f2f5183dfb 813 }
Kojto 121:6c34061e7c34 814 /** \brief Clean and Invalidate D$ by MVA
Kojto 121:6c34061e7c34 815
Kojto 121:6c34061e7c34 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 121:6c34061e7c34 817 */
Kojto 121:6c34061e7c34 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 121:6c34061e7c34 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
Kojto 121:6c34061e7c34 820 __DMB();
Kojto 121:6c34061e7c34 821 }
Kojto 121:6c34061e7c34 822
Kojto 115:87f2f5183dfb 823 #include "core_ca_mmu.h"
Kojto 101:7cff1c4259d7 824
Kojto 101:7cff1c4259d7 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 101:7cff1c4259d7 826 /* GNU gcc specific functions */
Kojto 101:7cff1c4259d7 827
Kojto 101:7cff1c4259d7 828 #define MODE_USR 0x10
Kojto 101:7cff1c4259d7 829 #define MODE_FIQ 0x11
Kojto 101:7cff1c4259d7 830 #define MODE_IRQ 0x12
Kojto 101:7cff1c4259d7 831 #define MODE_SVC 0x13
Kojto 101:7cff1c4259d7 832 #define MODE_MON 0x16
Kojto 101:7cff1c4259d7 833 #define MODE_ABT 0x17
Kojto 101:7cff1c4259d7 834 #define MODE_HYP 0x1A
Kojto 101:7cff1c4259d7 835 #define MODE_UND 0x1B
Kojto 101:7cff1c4259d7 836 #define MODE_SYS 0x1F
Kojto 101:7cff1c4259d7 837
Kojto 101:7cff1c4259d7 838
Kojto 101:7cff1c4259d7 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 101:7cff1c4259d7 840 {
Kojto 101:7cff1c4259d7 841 __ASM volatile ("cpsie i");
Kojto 101:7cff1c4259d7 842 }
Kojto 101:7cff1c4259d7 843
Kojto 101:7cff1c4259d7 844 /** \brief Disable IRQ Interrupts
Kojto 101:7cff1c4259d7 845
Kojto 101:7cff1c4259d7 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 101:7cff1c4259d7 847 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 848 */
Kojto 101:7cff1c4259d7 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 101:7cff1c4259d7 850 {
Kojto 101:7cff1c4259d7 851 uint32_t result;
Kojto 101:7cff1c4259d7 852
Kojto 101:7cff1c4259d7 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 101:7cff1c4259d7 854 __ASM volatile ("cpsid i");
Kojto 101:7cff1c4259d7 855 return(result & 0x80);
Kojto 101:7cff1c4259d7 856 }
Kojto 101:7cff1c4259d7 857
Kojto 101:7cff1c4259d7 858
Kojto 101:7cff1c4259d7 859 /** \brief Get APSR Register
Kojto 101:7cff1c4259d7 860
Kojto 101:7cff1c4259d7 861 This function returns the content of the APSR Register.
Kojto 101:7cff1c4259d7 862
Kojto 101:7cff1c4259d7 863 \return APSR Register value
Kojto 101:7cff1c4259d7 864 */
Kojto 101:7cff1c4259d7 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 101:7cff1c4259d7 866 {
Kojto 101:7cff1c4259d7 867 #if 1
Kojto 108:34e6b704fe68 868 register uint32_t __regAPSR;
Kojto 108:34e6b704fe68 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Kojto 101:7cff1c4259d7 870 #else
Kojto 101:7cff1c4259d7 871 register uint32_t __regAPSR __ASM("apsr");
Kojto 108:34e6b704fe68 872 #endif
Kojto 101:7cff1c4259d7 873 return(__regAPSR);
Kojto 101:7cff1c4259d7 874 }
Kojto 101:7cff1c4259d7 875
Kojto 101:7cff1c4259d7 876
Kojto 101:7cff1c4259d7 877 /** \brief Get CPSR Register
Kojto 101:7cff1c4259d7 878
Kojto 101:7cff1c4259d7 879 This function returns the content of the CPSR Register.
Kojto 101:7cff1c4259d7 880
Kojto 101:7cff1c4259d7 881 \return CPSR Register value
Kojto 101:7cff1c4259d7 882 */
Kojto 101:7cff1c4259d7 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 101:7cff1c4259d7 884 {
Kojto 101:7cff1c4259d7 885 #if 1
Kojto 101:7cff1c4259d7 886 register uint32_t __regCPSR;
Kojto 101:7cff1c4259d7 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 101:7cff1c4259d7 888 #else
Kojto 101:7cff1c4259d7 889 register uint32_t __regCPSR __ASM("cpsr");
Kojto 101:7cff1c4259d7 890 #endif
Kojto 101:7cff1c4259d7 891 return(__regCPSR);
Kojto 101:7cff1c4259d7 892 }
Kojto 101:7cff1c4259d7 893
Kojto 101:7cff1c4259d7 894 #if 0
Kojto 101:7cff1c4259d7 895 /** \brief Set Stack Pointer
Kojto 101:7cff1c4259d7 896
Kojto 101:7cff1c4259d7 897 This function assigns the given value to the current stack pointer.
Kojto 101:7cff1c4259d7 898
Kojto 101:7cff1c4259d7 899 \param [in] topOfStack Stack Pointer value to set
Kojto 101:7cff1c4259d7 900 */
Kojto 101:7cff1c4259d7 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 101:7cff1c4259d7 902 {
Kojto 101:7cff1c4259d7 903 register uint32_t __regSP __ASM("sp");
Kojto 101:7cff1c4259d7 904 __regSP = topOfStack;
Kojto 101:7cff1c4259d7 905 }
Kojto 101:7cff1c4259d7 906 #endif
Kojto 101:7cff1c4259d7 907
Kojto 101:7cff1c4259d7 908 /** \brief Get link register
Kojto 101:7cff1c4259d7 909
Kojto 101:7cff1c4259d7 910 This function returns the value of the link register
Kojto 101:7cff1c4259d7 911
Kojto 101:7cff1c4259d7 912 \return Value of link register
Kojto 101:7cff1c4259d7 913 */
Kojto 101:7cff1c4259d7 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 101:7cff1c4259d7 915 {
Kojto 101:7cff1c4259d7 916 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 917 return(__reglr);
Kojto 101:7cff1c4259d7 918 }
Kojto 101:7cff1c4259d7 919
Kojto 101:7cff1c4259d7 920 #if 0
Kojto 101:7cff1c4259d7 921 /** \brief Set link register
Kojto 101:7cff1c4259d7 922
Kojto 101:7cff1c4259d7 923 This function sets the value of the link register
Kojto 101:7cff1c4259d7 924
Kojto 101:7cff1c4259d7 925 \param [in] lr LR value to set
Kojto 101:7cff1c4259d7 926 */
Kojto 101:7cff1c4259d7 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 101:7cff1c4259d7 928 {
Kojto 101:7cff1c4259d7 929 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 930 __reglr = lr;
Kojto 101:7cff1c4259d7 931 }
Kojto 101:7cff1c4259d7 932 #endif
Kojto 101:7cff1c4259d7 933
Kojto 101:7cff1c4259d7 934 /** \brief Set Process Stack Pointer
Kojto 101:7cff1c4259d7 935
Kojto 101:7cff1c4259d7 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 101:7cff1c4259d7 937
Kojto 101:7cff1c4259d7 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 101:7cff1c4259d7 939 */
Kojto 108:34e6b704fe68 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Kojto 108:34e6b704fe68 941 {
Kojto 108:34e6b704fe68 942 __asm__ volatile (
Kojto 108:34e6b704fe68 943 ".ARM;"
Kojto 108:34e6b704fe68 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Kojto 108:34e6b704fe68 945
Kojto 108:34e6b704fe68 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Kojto 108:34e6b704fe68 947 "MRS R1, CPSR;"
Kojto 108:34e6b704fe68 948 "CPS %0;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 949 "MOV SP, R0;"
Kojto 108:34e6b704fe68 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Kojto 108:34e6b704fe68 951 "ISB;"
Kojto 108:34e6b704fe68 952 //"BX LR;"
Kojto 108:34e6b704fe68 953 :
Kojto 108:34e6b704fe68 954 : "i"(MODE_SYS)
Kojto 108:34e6b704fe68 955 : "r0", "r1");
Kojto 108:34e6b704fe68 956 return;
Kojto 108:34e6b704fe68 957 }
Kojto 101:7cff1c4259d7 958
Kojto 101:7cff1c4259d7 959 /** \brief Set User Mode
Kojto 101:7cff1c4259d7 960
Kojto 101:7cff1c4259d7 961 This function changes the processor state to User Mode
Kojto 108:34e6b704fe68 962 */
Kojto 108:34e6b704fe68 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Kojto 108:34e6b704fe68 964 {
Kojto 108:34e6b704fe68 965 __asm__ volatile (
Kojto 108:34e6b704fe68 966 ".ARM;"
Kojto 101:7cff1c4259d7 967
Kojto 108:34e6b704fe68 968 "CPS %0;"
Kojto 108:34e6b704fe68 969 //"BX LR;"
Kojto 108:34e6b704fe68 970 :
Kojto 108:34e6b704fe68 971 : "i"(MODE_USR)
Kojto 108:34e6b704fe68 972 : );
Kojto 108:34e6b704fe68 973 return;
Kojto 108:34e6b704fe68 974 }
Kojto 108:34e6b704fe68 975
Kojto 101:7cff1c4259d7 976
Kojto 101:7cff1c4259d7 977 /** \brief Enable FIQ
Kojto 101:7cff1c4259d7 978
Kojto 101:7cff1c4259d7 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 980 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 981 */
Kojto 108:34e6b704fe68 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Kojto 101:7cff1c4259d7 983
Kojto 101:7cff1c4259d7 984
Kojto 101:7cff1c4259d7 985 /** \brief Disable FIQ
Kojto 101:7cff1c4259d7 986
Kojto 101:7cff1c4259d7 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 988 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 989 */
Kojto 108:34e6b704fe68 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Kojto 101:7cff1c4259d7 991
Kojto 101:7cff1c4259d7 992
Kojto 101:7cff1c4259d7 993 /** \brief Get FPSCR
Kojto 101:7cff1c4259d7 994
Kojto 101:7cff1c4259d7 995 This function returns the current value of the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 996
Kojto 101:7cff1c4259d7 997 \return Floating Point Status/Control register value
Kojto 101:7cff1c4259d7 998 */
Kojto 101:7cff1c4259d7 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 101:7cff1c4259d7 1000 {
Kojto 101:7cff1c4259d7 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 1002 #if 1
Kojto 101:7cff1c4259d7 1003 uint32_t result;
Kojto 101:7cff1c4259d7 1004
Kojto 101:7cff1c4259d7 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 101:7cff1c4259d7 1006 return (result);
Kojto 101:7cff1c4259d7 1007 #else
Kojto 101:7cff1c4259d7 1008 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 1009 return(__regfpscr);
Kojto 101:7cff1c4259d7 1010 #endif
Kojto 101:7cff1c4259d7 1011 #else
Kojto 101:7cff1c4259d7 1012 return(0);
Kojto 101:7cff1c4259d7 1013 #endif
Kojto 101:7cff1c4259d7 1014 }
Kojto 101:7cff1c4259d7 1015
Kojto 101:7cff1c4259d7 1016
Kojto 101:7cff1c4259d7 1017 /** \brief Set FPSCR
Kojto 101:7cff1c4259d7 1018
Kojto 101:7cff1c4259d7 1019 This function assigns the given value to the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 1020
Kojto 101:7cff1c4259d7 1021 \param [in] fpscr Floating Point Status/Control value to set
Kojto 101:7cff1c4259d7 1022 */
Kojto 101:7cff1c4259d7 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 101:7cff1c4259d7 1024 {
Kojto 101:7cff1c4259d7 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 1026 #if 1
Kojto 101:7cff1c4259d7 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 101:7cff1c4259d7 1028 #else
Kojto 101:7cff1c4259d7 1029 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 1030 __regfpscr = (fpscr);
Kojto 101:7cff1c4259d7 1031 #endif
Kojto 101:7cff1c4259d7 1032 #endif
Kojto 101:7cff1c4259d7 1033 }
Kojto 101:7cff1c4259d7 1034
Kojto 101:7cff1c4259d7 1035 /** \brief Get FPEXC
Kojto 101:7cff1c4259d7 1036
Kojto 101:7cff1c4259d7 1037 This function returns the current value of the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 1038
Kojto 101:7cff1c4259d7 1039 \return Floating Point Exception Control register value
Kojto 101:7cff1c4259d7 1040 */
Kojto 101:7cff1c4259d7 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 101:7cff1c4259d7 1042 {
Kojto 101:7cff1c4259d7 1043 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 1044 #if 1
Kojto 101:7cff1c4259d7 1045 uint32_t result;
Kojto 101:7cff1c4259d7 1046
Kojto 101:7cff1c4259d7 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 101:7cff1c4259d7 1048 return (result);
Kojto 101:7cff1c4259d7 1049 #else
Kojto 101:7cff1c4259d7 1050 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 1051 return(__regfpexc);
Kojto 101:7cff1c4259d7 1052 #endif
Kojto 101:7cff1c4259d7 1053 #else
Kojto 101:7cff1c4259d7 1054 return(0);
Kojto 101:7cff1c4259d7 1055 #endif
Kojto 101:7cff1c4259d7 1056 }
Kojto 101:7cff1c4259d7 1057
Kojto 101:7cff1c4259d7 1058
Kojto 101:7cff1c4259d7 1059 /** \brief Set FPEXC
Kojto 101:7cff1c4259d7 1060
Kojto 101:7cff1c4259d7 1061 This function assigns the given value to the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 1062
Kojto 101:7cff1c4259d7 1063 \param [in] fpscr Floating Point Exception Control value to set
Kojto 101:7cff1c4259d7 1064 */
Kojto 101:7cff1c4259d7 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 101:7cff1c4259d7 1066 {
Kojto 101:7cff1c4259d7 1067 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 1068 #if 1
Kojto 101:7cff1c4259d7 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 101:7cff1c4259d7 1070 #else
Kojto 101:7cff1c4259d7 1071 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 1072 __regfpexc = (fpexc);
Kojto 101:7cff1c4259d7 1073 #endif
Kojto 101:7cff1c4259d7 1074 #endif
Kojto 101:7cff1c4259d7 1075 }
Kojto 101:7cff1c4259d7 1076
Kojto 101:7cff1c4259d7 1077 /** \brief Get CPACR
Kojto 101:7cff1c4259d7 1078
Kojto 101:7cff1c4259d7 1079 This function returns the current value of the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 1080
Kojto 101:7cff1c4259d7 1081 \return Coprocessor Access Control register value
Kojto 101:7cff1c4259d7 1082 */
Kojto 101:7cff1c4259d7 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 101:7cff1c4259d7 1084 {
Kojto 101:7cff1c4259d7 1085 #if 1
Kojto 101:7cff1c4259d7 1086 register uint32_t __regCPACR;
Kojto 101:7cff1c4259d7 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 101:7cff1c4259d7 1088 #else
Kojto 101:7cff1c4259d7 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 1090 #endif
Kojto 101:7cff1c4259d7 1091 return __regCPACR;
Kojto 101:7cff1c4259d7 1092 }
Kojto 101:7cff1c4259d7 1093
Kojto 101:7cff1c4259d7 1094 /** \brief Set CPACR
Kojto 101:7cff1c4259d7 1095
Kojto 101:7cff1c4259d7 1096 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 1097
Kojto 108:34e6b704fe68 1098 \param [in] cpacr Coprocessor Acccess Control value to set
Kojto 101:7cff1c4259d7 1099 */
Kojto 101:7cff1c4259d7 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 101:7cff1c4259d7 1101 {
Kojto 101:7cff1c4259d7 1102 #if 1
Kojto 101:7cff1c4259d7 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 101:7cff1c4259d7 1104 #else
Kojto 101:7cff1c4259d7 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 1106 __regCPACR = cpacr;
Kojto 101:7cff1c4259d7 1107 #endif
Kojto 101:7cff1c4259d7 1108 __ISB();
Kojto 101:7cff1c4259d7 1109 }
Kojto 101:7cff1c4259d7 1110
Kojto 101:7cff1c4259d7 1111 /** \brief Get CBAR
Kojto 101:7cff1c4259d7 1112
Kojto 101:7cff1c4259d7 1113 This function returns the value of the Configuration Base Address register.
Kojto 101:7cff1c4259d7 1114
Kojto 101:7cff1c4259d7 1115 \return Configuration Base Address register value
Kojto 101:7cff1c4259d7 1116 */
Kojto 101:7cff1c4259d7 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 101:7cff1c4259d7 1118 #if 1
Kojto 101:7cff1c4259d7 1119 register uint32_t __regCBAR;
Kojto 101:7cff1c4259d7 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 101:7cff1c4259d7 1121 #else
Kojto 101:7cff1c4259d7 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 101:7cff1c4259d7 1123 #endif
Kojto 101:7cff1c4259d7 1124 return(__regCBAR);
Kojto 101:7cff1c4259d7 1125 }
Kojto 101:7cff1c4259d7 1126
Kojto 101:7cff1c4259d7 1127 /** \brief Get TTBR0
Kojto 101:7cff1c4259d7 1128
Kojto 108:34e6b704fe68 1129 This function returns the value of the Translation Table Base Register 0.
Kojto 101:7cff1c4259d7 1130
Kojto 101:7cff1c4259d7 1131 \return Translation Table Base Register 0 value
Kojto 101:7cff1c4259d7 1132 */
Kojto 101:7cff1c4259d7 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 101:7cff1c4259d7 1134 #if 1
Kojto 101:7cff1c4259d7 1135 register uint32_t __regTTBR0;
Kojto 101:7cff1c4259d7 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 101:7cff1c4259d7 1137 #else
Kojto 101:7cff1c4259d7 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 1139 #endif
Kojto 101:7cff1c4259d7 1140 return(__regTTBR0);
Kojto 101:7cff1c4259d7 1141 }
Kojto 101:7cff1c4259d7 1142
Kojto 101:7cff1c4259d7 1143 /** \brief Set TTBR0
Kojto 101:7cff1c4259d7 1144
Kojto 108:34e6b704fe68 1145 This function assigns the given value to the Translation Table Base Register 0.
Kojto 101:7cff1c4259d7 1146
Kojto 101:7cff1c4259d7 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 101:7cff1c4259d7 1148 */
Kojto 101:7cff1c4259d7 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 101:7cff1c4259d7 1150 #if 1
Kojto 101:7cff1c4259d7 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 101:7cff1c4259d7 1152 #else
Kojto 101:7cff1c4259d7 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 1154 __regTTBR0 = ttbr0;
Kojto 101:7cff1c4259d7 1155 #endif
Kojto 101:7cff1c4259d7 1156 __ISB();
Kojto 101:7cff1c4259d7 1157 }
Kojto 101:7cff1c4259d7 1158
Kojto 101:7cff1c4259d7 1159 /** \brief Get DACR
Kojto 101:7cff1c4259d7 1160
Kojto 101:7cff1c4259d7 1161 This function returns the value of the Domain Access Control Register.
Kojto 101:7cff1c4259d7 1162
Kojto 101:7cff1c4259d7 1163 \return Domain Access Control Register value
Kojto 101:7cff1c4259d7 1164 */
Kojto 101:7cff1c4259d7 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 101:7cff1c4259d7 1166 #if 1
Kojto 101:7cff1c4259d7 1167 register uint32_t __regDACR;
Kojto 101:7cff1c4259d7 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 101:7cff1c4259d7 1169 #else
Kojto 101:7cff1c4259d7 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 1171 #endif
Kojto 101:7cff1c4259d7 1172 return(__regDACR);
Kojto 101:7cff1c4259d7 1173 }
Kojto 101:7cff1c4259d7 1174
Kojto 101:7cff1c4259d7 1175 /** \brief Set DACR
Kojto 101:7cff1c4259d7 1176
Kojto 108:34e6b704fe68 1177 This function assigns the given value to the Domain Access Control Register.
Kojto 101:7cff1c4259d7 1178
Kojto 101:7cff1c4259d7 1179 \param [in] dacr Domain Access Control Register value to set
Kojto 101:7cff1c4259d7 1180 */
Kojto 101:7cff1c4259d7 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 101:7cff1c4259d7 1182 #if 1
Kojto 101:7cff1c4259d7 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 101:7cff1c4259d7 1184 #else
Kojto 101:7cff1c4259d7 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 1186 __regDACR = dacr;
Kojto 101:7cff1c4259d7 1187 #endif
Kojto 101:7cff1c4259d7 1188 __ISB();
Kojto 101:7cff1c4259d7 1189 }
Kojto 101:7cff1c4259d7 1190
Kojto 101:7cff1c4259d7 1191 /******************************** Cache and BTAC enable ****************************************************/
Kojto 101:7cff1c4259d7 1192
Kojto 101:7cff1c4259d7 1193 /** \brief Set SCTLR
Kojto 101:7cff1c4259d7 1194
Kojto 101:7cff1c4259d7 1195 This function assigns the given value to the System Control Register.
Kojto 101:7cff1c4259d7 1196
Kojto 108:34e6b704fe68 1197 \param [in] sctlr System Control Register value to set
Kojto 101:7cff1c4259d7 1198 */
Kojto 101:7cff1c4259d7 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 101:7cff1c4259d7 1200 {
Kojto 101:7cff1c4259d7 1201 #if 1
Kojto 101:7cff1c4259d7 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 101:7cff1c4259d7 1203 #else
Kojto 101:7cff1c4259d7 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 1205 __regSCTLR = sctlr;
Kojto 101:7cff1c4259d7 1206 #endif
Kojto 101:7cff1c4259d7 1207 }
Kojto 101:7cff1c4259d7 1208
Kojto 101:7cff1c4259d7 1209 /** \brief Get SCTLR
Kojto 101:7cff1c4259d7 1210
Kojto 101:7cff1c4259d7 1211 This function returns the value of the System Control Register.
Kojto 101:7cff1c4259d7 1212
Kojto 101:7cff1c4259d7 1213 \return System Control Register value
Kojto 101:7cff1c4259d7 1214 */
Kojto 101:7cff1c4259d7 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 101:7cff1c4259d7 1216 #if 1
Kojto 101:7cff1c4259d7 1217 register uint32_t __regSCTLR;
Kojto 101:7cff1c4259d7 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 101:7cff1c4259d7 1219 #else
Kojto 101:7cff1c4259d7 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 1221 #endif
Kojto 101:7cff1c4259d7 1222 return(__regSCTLR);
Kojto 101:7cff1c4259d7 1223 }
Kojto 101:7cff1c4259d7 1224
Kojto 101:7cff1c4259d7 1225 /** \brief Enable Caches
Kojto 101:7cff1c4259d7 1226
Kojto 101:7cff1c4259d7 1227 Enable Caches
Kojto 101:7cff1c4259d7 1228 */
Kojto 101:7cff1c4259d7 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 101:7cff1c4259d7 1230 // Set I bit 12 to enable I Cache
Kojto 101:7cff1c4259d7 1231 // Set C bit 2 to enable D Cache
Kojto 101:7cff1c4259d7 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 101:7cff1c4259d7 1233 }
Kojto 101:7cff1c4259d7 1234
Kojto 101:7cff1c4259d7 1235 /** \brief Disable Caches
Kojto 101:7cff1c4259d7 1236
Kojto 101:7cff1c4259d7 1237 Disable Caches
Kojto 101:7cff1c4259d7 1238 */
Kojto 101:7cff1c4259d7 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 101:7cff1c4259d7 1240 // Clear I bit 12 to disable I Cache
Kojto 101:7cff1c4259d7 1241 // Clear C bit 2 to disable D Cache
Kojto 101:7cff1c4259d7 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 101:7cff1c4259d7 1243 __ISB();
Kojto 101:7cff1c4259d7 1244 }
Kojto 101:7cff1c4259d7 1245
Kojto 101:7cff1c4259d7 1246 /** \brief Enable BTAC
Kojto 101:7cff1c4259d7 1247
Kojto 101:7cff1c4259d7 1248 Enable BTAC
Kojto 101:7cff1c4259d7 1249 */
Kojto 101:7cff1c4259d7 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 101:7cff1c4259d7 1251 // Set Z bit 11 to enable branch prediction
Kojto 101:7cff1c4259d7 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 101:7cff1c4259d7 1253 __ISB();
Kojto 101:7cff1c4259d7 1254 }
Kojto 101:7cff1c4259d7 1255
Kojto 101:7cff1c4259d7 1256 /** \brief Disable BTAC
Kojto 101:7cff1c4259d7 1257
Kojto 101:7cff1c4259d7 1258 Disable BTAC
Kojto 101:7cff1c4259d7 1259 */
Kojto 101:7cff1c4259d7 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 101:7cff1c4259d7 1261 // Clear Z bit 11 to disable branch prediction
Kojto 101:7cff1c4259d7 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 101:7cff1c4259d7 1263 }
Kojto 101:7cff1c4259d7 1264
Kojto 101:7cff1c4259d7 1265
Kojto 101:7cff1c4259d7 1266 /** \brief Enable MMU
Kojto 101:7cff1c4259d7 1267
Kojto 101:7cff1c4259d7 1268 Enable MMU
Kojto 101:7cff1c4259d7 1269 */
Kojto 101:7cff1c4259d7 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 101:7cff1c4259d7 1271 // Set M bit 0 to enable the MMU
Kojto 101:7cff1c4259d7 1272 // Set AFE bit to enable simplified access permissions model
Kojto 101:7cff1c4259d7 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 101:7cff1c4259d7 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 101:7cff1c4259d7 1275 __ISB();
Kojto 101:7cff1c4259d7 1276 }
Kojto 101:7cff1c4259d7 1277
Kojto 108:34e6b704fe68 1278 /** \brief Disable MMU
Kojto 101:7cff1c4259d7 1279
Kojto 108:34e6b704fe68 1280 Disable MMU
Kojto 101:7cff1c4259d7 1281 */
Kojto 101:7cff1c4259d7 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 101:7cff1c4259d7 1283 // Clear M bit 0 to disable the MMU
Kojto 101:7cff1c4259d7 1284 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 101:7cff1c4259d7 1285 __ISB();
Kojto 101:7cff1c4259d7 1286 }
Kojto 101:7cff1c4259d7 1287
Kojto 101:7cff1c4259d7 1288 /******************************** TLB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 1289 /** \brief Invalidate the whole tlb
Kojto 101:7cff1c4259d7 1290
Kojto 101:7cff1c4259d7 1291 TLBIALL. Invalidate the whole tlb
Kojto 101:7cff1c4259d7 1292 */
Kojto 101:7cff1c4259d7 1293
Kojto 101:7cff1c4259d7 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 101:7cff1c4259d7 1295 #if 1
Kojto 101:7cff1c4259d7 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 101:7cff1c4259d7 1297 #else
Kojto 101:7cff1c4259d7 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 101:7cff1c4259d7 1299 __TLBIALL = 0;
Kojto 101:7cff1c4259d7 1300 #endif
Kojto 101:7cff1c4259d7 1301 __DSB();
Kojto 101:7cff1c4259d7 1302 __ISB();
Kojto 101:7cff1c4259d7 1303 }
Kojto 101:7cff1c4259d7 1304
Kojto 101:7cff1c4259d7 1305 /******************************** BTB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 1306 /** \brief Invalidate entire branch predictor array
Kojto 101:7cff1c4259d7 1307
Kojto 101:7cff1c4259d7 1308 BPIALL. Branch Predictor Invalidate All.
Kojto 101:7cff1c4259d7 1309 */
Kojto 101:7cff1c4259d7 1310
Kojto 101:7cff1c4259d7 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 101:7cff1c4259d7 1312 #if 1
Kojto 101:7cff1c4259d7 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 101:7cff1c4259d7 1314 #else
Kojto 101:7cff1c4259d7 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 101:7cff1c4259d7 1316 __BPIALL = 0;
Kojto 101:7cff1c4259d7 1317 #endif
Kojto 101:7cff1c4259d7 1318 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 1319 __ISB(); //ensure instruction fetch path sees new state
Kojto 101:7cff1c4259d7 1320 }
Kojto 101:7cff1c4259d7 1321
Kojto 101:7cff1c4259d7 1322
Kojto 101:7cff1c4259d7 1323 /******************************** L1 cache operations ******************************************************/
Kojto 101:7cff1c4259d7 1324
Kojto 101:7cff1c4259d7 1325 /** \brief Invalidate the whole I$
Kojto 101:7cff1c4259d7 1326
Kojto 101:7cff1c4259d7 1327 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 101:7cff1c4259d7 1328 */
Kojto 101:7cff1c4259d7 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 101:7cff1c4259d7 1330 #if 1
Kojto 101:7cff1c4259d7 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 101:7cff1c4259d7 1332 #else
Kojto 101:7cff1c4259d7 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 101:7cff1c4259d7 1334 __ICIALLU = 0;
Kojto 101:7cff1c4259d7 1335 #endif
Kojto 101:7cff1c4259d7 1336 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 1337 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 101:7cff1c4259d7 1338 }
Kojto 101:7cff1c4259d7 1339
Kojto 101:7cff1c4259d7 1340 /** \brief Clean D$ by MVA
Kojto 101:7cff1c4259d7 1341
Kojto 101:7cff1c4259d7 1342 DCCMVAC. Data cache clean by MVA to PoC
Kojto 101:7cff1c4259d7 1343 */
Kojto 101:7cff1c4259d7 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1345 #if 1
Kojto 101:7cff1c4259d7 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1347 #else
Kojto 101:7cff1c4259d7 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 101:7cff1c4259d7 1349 __DCCMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1350 #endif
Kojto 101:7cff1c4259d7 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1352 }
Kojto 101:7cff1c4259d7 1353
Kojto 101:7cff1c4259d7 1354 /** \brief Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 1355
Kojto 101:7cff1c4259d7 1356 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 1357 */
Kojto 101:7cff1c4259d7 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1359 #if 1
Kojto 101:7cff1c4259d7 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1361 #else
Kojto 101:7cff1c4259d7 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 101:7cff1c4259d7 1363 __DCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1364 #endif
Kojto 101:7cff1c4259d7 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1366 }
Kojto 101:7cff1c4259d7 1367
Kojto 101:7cff1c4259d7 1368 /** \brief Clean and Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 1369
Kojto 101:7cff1c4259d7 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 1371 */
Kojto 101:7cff1c4259d7 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1373 #if 1
Kojto 101:7cff1c4259d7 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1375 #else
Kojto 101:7cff1c4259d7 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 101:7cff1c4259d7 1377 __DCCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1378 #endif
Kojto 101:7cff1c4259d7 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1380 }
Kojto 101:7cff1c4259d7 1381
Kojto 108:34e6b704fe68 1382 /** \brief Clean and Invalidate the entire data or unified cache
Kojto 101:7cff1c4259d7 1383
Kojto 108:34e6b704fe68 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 101:7cff1c4259d7 1385 */
Kojto 101:7cff1c4259d7 1386 extern void __v7_all_cache(uint32_t op);
Kojto 101:7cff1c4259d7 1387
Kojto 101:7cff1c4259d7 1388
Kojto 101:7cff1c4259d7 1389 /** \brief Invalidate the whole D$
Kojto 101:7cff1c4259d7 1390
Kojto 101:7cff1c4259d7 1391 DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 1392 */
Kojto 101:7cff1c4259d7 1393
Kojto 101:7cff1c4259d7 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 1395 __v7_all_cache(0);
Kojto 101:7cff1c4259d7 1396 }
Kojto 101:7cff1c4259d7 1397
Kojto 101:7cff1c4259d7 1398 /** \brief Clean the whole D$
Kojto 101:7cff1c4259d7 1399
Kojto 101:7cff1c4259d7 1400 DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 1401 */
Kojto 101:7cff1c4259d7 1402
Kojto 101:7cff1c4259d7 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 101:7cff1c4259d7 1404 __v7_all_cache(1);
Kojto 101:7cff1c4259d7 1405 }
Kojto 101:7cff1c4259d7 1406
Kojto 101:7cff1c4259d7 1407 /** \brief Clean and invalidate the whole D$
Kojto 101:7cff1c4259d7 1408
Kojto 101:7cff1c4259d7 1409 DCCISW. Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 1410 */
Kojto 101:7cff1c4259d7 1411
Kojto 101:7cff1c4259d7 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 1413 __v7_all_cache(2);
Kojto 101:7cff1c4259d7 1414 }
Kojto 101:7cff1c4259d7 1415
Kojto 101:7cff1c4259d7 1416 #include "core_ca_mmu.h"
Kojto 101:7cff1c4259d7 1417
Kojto 101:7cff1c4259d7 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 101:7cff1c4259d7 1419
Kojto 101:7cff1c4259d7 1420 #error TASKING Compiler support not implemented for Cortex-A
Kojto 101:7cff1c4259d7 1421
Kojto 101:7cff1c4259d7 1422 #endif
Kojto 101:7cff1c4259d7 1423
Kojto 101:7cff1c4259d7 1424 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 101:7cff1c4259d7 1425
Kojto 101:7cff1c4259d7 1426
Kojto 101:7cff1c4259d7 1427 #endif /* __CORE_CAFUNC_H__ */