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TARGET_MAX32600MBED/core_caFunc.h@101:7cff1c4259d7, 2015-06-09 (annotated)

Committer:
Kojto
Date:
Tue Jun 09 14:29:26 2015 +0100
Revision:
101:7cff1c4259d7
Child:
108:34e6b704fe68
Release 101 of the mbed library



Changes:

- new platform: APPNEARME_MICRONFCBOARD, MTS_DRAGONFLY_F411RE, MAX32600MBED, WIZwiki_W7500

- Silabs memory optimization in gpio, pwm fixes

- SPI  - ssel documentation fixes and its use

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**************************************************************************//**
Kojto 101:7cff1c4259d7 2 * @file core_caFunc.h
Kojto 101:7cff1c4259d7 3 * @brief CMSIS Cortex-A Core Function Access Header File
Kojto 101:7cff1c4259d7 4 * @version V3.10
Kojto 101:7cff1c4259d7 5 * @date 9 May 2013
Kojto 101:7cff1c4259d7 6 *
Kojto 101:7cff1c4259d7 7 * @note
Kojto 101:7cff1c4259d7 8 *
Kojto 101:7cff1c4259d7 9 ******************************************************************************/
Kojto 101:7cff1c4259d7 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
Kojto 101:7cff1c4259d7 11
Kojto 101:7cff1c4259d7 12 All rights reserved.
Kojto 101:7cff1c4259d7 13 Redistribution and use in source and binary forms, with or without
Kojto 101:7cff1c4259d7 14 modification, are permitted provided that the following conditions are met:
Kojto 101:7cff1c4259d7 15 - Redistributions of source code must retain the above copyright
Kojto 101:7cff1c4259d7 16 notice, this list of conditions and the following disclaimer.
Kojto 101:7cff1c4259d7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 101:7cff1c4259d7 18 notice, this list of conditions and the following disclaimer in the
Kojto 101:7cff1c4259d7 19 documentation and/or other materials provided with the distribution.
Kojto 101:7cff1c4259d7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 101:7cff1c4259d7 21 to endorse or promote products derived from this software without
Kojto 101:7cff1c4259d7 22 specific prior written permission.
Kojto 101:7cff1c4259d7 23 *
Kojto 101:7cff1c4259d7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 101:7cff1c4259d7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 101:7cff1c4259d7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 101:7cff1c4259d7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 101:7cff1c4259d7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 101:7cff1c4259d7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 101:7cff1c4259d7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 101:7cff1c4259d7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 101:7cff1c4259d7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 101:7cff1c4259d7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 101:7cff1c4259d7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 101:7cff1c4259d7 35 ---------------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37
Kojto 101:7cff1c4259d7 38 #ifndef __CORE_CAFUNC_H__
Kojto 101:7cff1c4259d7 39 #define __CORE_CAFUNC_H__
Kojto 101:7cff1c4259d7 40
Kojto 101:7cff1c4259d7 41
Kojto 101:7cff1c4259d7 42 /* ########################### Core Function Access ########################### */
Kojto 101:7cff1c4259d7 43 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 101:7cff1c4259d7 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Kojto 101:7cff1c4259d7 45 @{
Kojto 101:7cff1c4259d7 46 */
Kojto 101:7cff1c4259d7 47
Kojto 101:7cff1c4259d7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Kojto 101:7cff1c4259d7 49 /* ARM armcc specific functions */
Kojto 101:7cff1c4259d7 50
Kojto 101:7cff1c4259d7 51 #if (__ARMCC_VERSION < 400677)
Kojto 101:7cff1c4259d7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Kojto 101:7cff1c4259d7 53 #endif
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 #define MODE_USR 0x10
Kojto 101:7cff1c4259d7 56 #define MODE_FIQ 0x11
Kojto 101:7cff1c4259d7 57 #define MODE_IRQ 0x12
Kojto 101:7cff1c4259d7 58 #define MODE_SVC 0x13
Kojto 101:7cff1c4259d7 59 #define MODE_MON 0x16
Kojto 101:7cff1c4259d7 60 #define MODE_ABT 0x17
Kojto 101:7cff1c4259d7 61 #define MODE_HYP 0x1A
Kojto 101:7cff1c4259d7 62 #define MODE_UND 0x1B
Kojto 101:7cff1c4259d7 63 #define MODE_SYS 0x1F
Kojto 101:7cff1c4259d7 64
Kojto 101:7cff1c4259d7 65 /** \brief Get APSR Register
Kojto 101:7cff1c4259d7 66
Kojto 101:7cff1c4259d7 67 This function returns the content of the APSR Register.
Kojto 101:7cff1c4259d7 68
Kojto 101:7cff1c4259d7 69 \return APSR Register value
Kojto 101:7cff1c4259d7 70 */
Kojto 101:7cff1c4259d7 71 __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 101:7cff1c4259d7 72 {
Kojto 101:7cff1c4259d7 73 register uint32_t __regAPSR __ASM("apsr");
Kojto 101:7cff1c4259d7 74 return(__regAPSR);
Kojto 101:7cff1c4259d7 75 }
Kojto 101:7cff1c4259d7 76
Kojto 101:7cff1c4259d7 77
Kojto 101:7cff1c4259d7 78 /** \brief Get CPSR Register
Kojto 101:7cff1c4259d7 79
Kojto 101:7cff1c4259d7 80 This function returns the content of the CPSR Register.
Kojto 101:7cff1c4259d7 81
Kojto 101:7cff1c4259d7 82 \return CPSR Register value
Kojto 101:7cff1c4259d7 83 */
Kojto 101:7cff1c4259d7 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 101:7cff1c4259d7 85 {
Kojto 101:7cff1c4259d7 86 register uint32_t __regCPSR __ASM("cpsr");
Kojto 101:7cff1c4259d7 87 return(__regCPSR);
Kojto 101:7cff1c4259d7 88 }
Kojto 101:7cff1c4259d7 89
Kojto 101:7cff1c4259d7 90 /** \brief Set Stack Pointer
Kojto 101:7cff1c4259d7 91
Kojto 101:7cff1c4259d7 92 This function assigns the given value to the current stack pointer.
Kojto 101:7cff1c4259d7 93
Kojto 101:7cff1c4259d7 94 \param [in] topOfStack Stack Pointer value to set
Kojto 101:7cff1c4259d7 95 */
Kojto 101:7cff1c4259d7 96 register uint32_t __regSP __ASM("sp");
Kojto 101:7cff1c4259d7 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 101:7cff1c4259d7 98 {
Kojto 101:7cff1c4259d7 99 __regSP = topOfStack;
Kojto 101:7cff1c4259d7 100 }
Kojto 101:7cff1c4259d7 101
Kojto 101:7cff1c4259d7 102
Kojto 101:7cff1c4259d7 103 /** \brief Get link register
Kojto 101:7cff1c4259d7 104
Kojto 101:7cff1c4259d7 105 This function returns the value of the link register
Kojto 101:7cff1c4259d7 106
Kojto 101:7cff1c4259d7 107 \return Value of link register
Kojto 101:7cff1c4259d7 108 */
Kojto 101:7cff1c4259d7 109 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 110 __STATIC_INLINE uint32_t __get_LR(void)
Kojto 101:7cff1c4259d7 111 {
Kojto 101:7cff1c4259d7 112 return(__reglr);
Kojto 101:7cff1c4259d7 113 }
Kojto 101:7cff1c4259d7 114
Kojto 101:7cff1c4259d7 115 /** \brief Set link register
Kojto 101:7cff1c4259d7 116
Kojto 101:7cff1c4259d7 117 This function sets the value of the link register
Kojto 101:7cff1c4259d7 118
Kojto 101:7cff1c4259d7 119 \param [in] lr LR value to set
Kojto 101:7cff1c4259d7 120 */
Kojto 101:7cff1c4259d7 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 101:7cff1c4259d7 122 {
Kojto 101:7cff1c4259d7 123 __reglr = lr;
Kojto 101:7cff1c4259d7 124 }
Kojto 101:7cff1c4259d7 125
Kojto 101:7cff1c4259d7 126 /** \brief Set Process Stack Pointer
Kojto 101:7cff1c4259d7 127
Kojto 101:7cff1c4259d7 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 101:7cff1c4259d7 129
Kojto 101:7cff1c4259d7 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 101:7cff1c4259d7 131 */
Kojto 101:7cff1c4259d7 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Kojto 101:7cff1c4259d7 133 {
Kojto 101:7cff1c4259d7 134 ARM
Kojto 101:7cff1c4259d7 135 PRESERVE8
Kojto 101:7cff1c4259d7 136
Kojto 101:7cff1c4259d7 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Kojto 101:7cff1c4259d7 138 MRS R1, CPSR
Kojto 101:7cff1c4259d7 139 CPS #MODE_SYS ;no effect in USR mode
Kojto 101:7cff1c4259d7 140 MOV SP, R0
Kojto 101:7cff1c4259d7 141 MSR CPSR_c, R1 ;no effect in USR mode
Kojto 101:7cff1c4259d7 142 ISB
Kojto 101:7cff1c4259d7 143 BX LR
Kojto 101:7cff1c4259d7 144
Kojto 101:7cff1c4259d7 145 }
Kojto 101:7cff1c4259d7 146
Kojto 101:7cff1c4259d7 147 /** \brief Set User Mode
Kojto 101:7cff1c4259d7 148
Kojto 101:7cff1c4259d7 149 This function changes the processor state to User Mode
Kojto 101:7cff1c4259d7 150
Kojto 101:7cff1c4259d7 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 101:7cff1c4259d7 152 */
Kojto 101:7cff1c4259d7 153 __STATIC_ASM void __set_CPS_USR(void)
Kojto 101:7cff1c4259d7 154 {
Kojto 101:7cff1c4259d7 155 ARM
Kojto 101:7cff1c4259d7 156
Kojto 101:7cff1c4259d7 157 CPS #MODE_USR
Kojto 101:7cff1c4259d7 158 BX LR
Kojto 101:7cff1c4259d7 159 }
Kojto 101:7cff1c4259d7 160
Kojto 101:7cff1c4259d7 161
Kojto 101:7cff1c4259d7 162 /** \brief Enable FIQ
Kojto 101:7cff1c4259d7 163
Kojto 101:7cff1c4259d7 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 165 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 166 */
Kojto 101:7cff1c4259d7 167 #define __enable_fault_irq __enable_fiq
Kojto 101:7cff1c4259d7 168
Kojto 101:7cff1c4259d7 169
Kojto 101:7cff1c4259d7 170 /** \brief Disable FIQ
Kojto 101:7cff1c4259d7 171
Kojto 101:7cff1c4259d7 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 173 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 174 */
Kojto 101:7cff1c4259d7 175 #define __disable_fault_irq __disable_fiq
Kojto 101:7cff1c4259d7 176
Kojto 101:7cff1c4259d7 177
Kojto 101:7cff1c4259d7 178 /** \brief Get FPSCR
Kojto 101:7cff1c4259d7 179
Kojto 101:7cff1c4259d7 180 This function returns the current value of the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 181
Kojto 101:7cff1c4259d7 182 \return Floating Point Status/Control register value
Kojto 101:7cff1c4259d7 183 */
Kojto 101:7cff1c4259d7 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 101:7cff1c4259d7 185 {
Kojto 101:7cff1c4259d7 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 187 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 188 return(__regfpscr);
Kojto 101:7cff1c4259d7 189 #else
Kojto 101:7cff1c4259d7 190 return(0);
Kojto 101:7cff1c4259d7 191 #endif
Kojto 101:7cff1c4259d7 192 }
Kojto 101:7cff1c4259d7 193
Kojto 101:7cff1c4259d7 194
Kojto 101:7cff1c4259d7 195 /** \brief Set FPSCR
Kojto 101:7cff1c4259d7 196
Kojto 101:7cff1c4259d7 197 This function assigns the given value to the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 198
Kojto 101:7cff1c4259d7 199 \param [in] fpscr Floating Point Status/Control value to set
Kojto 101:7cff1c4259d7 200 */
Kojto 101:7cff1c4259d7 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 101:7cff1c4259d7 202 {
Kojto 101:7cff1c4259d7 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 204 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 205 __regfpscr = (fpscr);
Kojto 101:7cff1c4259d7 206 #endif
Kojto 101:7cff1c4259d7 207 }
Kojto 101:7cff1c4259d7 208
Kojto 101:7cff1c4259d7 209 /** \brief Get FPEXC
Kojto 101:7cff1c4259d7 210
Kojto 101:7cff1c4259d7 211 This function returns the current value of the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 212
Kojto 101:7cff1c4259d7 213 \return Floating Point Exception Control register value
Kojto 101:7cff1c4259d7 214 */
Kojto 101:7cff1c4259d7 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 101:7cff1c4259d7 216 {
Kojto 101:7cff1c4259d7 217 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 218 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 219 return(__regfpexc);
Kojto 101:7cff1c4259d7 220 #else
Kojto 101:7cff1c4259d7 221 return(0);
Kojto 101:7cff1c4259d7 222 #endif
Kojto 101:7cff1c4259d7 223 }
Kojto 101:7cff1c4259d7 224
Kojto 101:7cff1c4259d7 225
Kojto 101:7cff1c4259d7 226 /** \brief Set FPEXC
Kojto 101:7cff1c4259d7 227
Kojto 101:7cff1c4259d7 228 This function assigns the given value to the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 229
Kojto 101:7cff1c4259d7 230 \param [in] fpscr Floating Point Exception Control value to set
Kojto 101:7cff1c4259d7 231 */
Kojto 101:7cff1c4259d7 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 101:7cff1c4259d7 233 {
Kojto 101:7cff1c4259d7 234 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 235 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 236 __regfpexc = (fpexc);
Kojto 101:7cff1c4259d7 237 #endif
Kojto 101:7cff1c4259d7 238 }
Kojto 101:7cff1c4259d7 239
Kojto 101:7cff1c4259d7 240 /** \brief Get CPACR
Kojto 101:7cff1c4259d7 241
Kojto 101:7cff1c4259d7 242 This function returns the current value of the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 243
Kojto 101:7cff1c4259d7 244 \return Coprocessor Access Control register value
Kojto 101:7cff1c4259d7 245 */
Kojto 101:7cff1c4259d7 246 __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 101:7cff1c4259d7 247 {
Kojto 101:7cff1c4259d7 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 249 return __regCPACR;
Kojto 101:7cff1c4259d7 250 }
Kojto 101:7cff1c4259d7 251
Kojto 101:7cff1c4259d7 252 /** \brief Set CPACR
Kojto 101:7cff1c4259d7 253
Kojto 101:7cff1c4259d7 254 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 255
Kojto 101:7cff1c4259d7 256 \param [in] cpacr Coporcessor Acccess Control value to set
Kojto 101:7cff1c4259d7 257 */
Kojto 101:7cff1c4259d7 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 101:7cff1c4259d7 259 {
Kojto 101:7cff1c4259d7 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 261 __regCPACR = cpacr;
Kojto 101:7cff1c4259d7 262 __ISB();
Kojto 101:7cff1c4259d7 263 }
Kojto 101:7cff1c4259d7 264
Kojto 101:7cff1c4259d7 265 /** \brief Get CBAR
Kojto 101:7cff1c4259d7 266
Kojto 101:7cff1c4259d7 267 This function returns the value of the Configuration Base Address register.
Kojto 101:7cff1c4259d7 268
Kojto 101:7cff1c4259d7 269 \return Configuration Base Address register value
Kojto 101:7cff1c4259d7 270 */
Kojto 101:7cff1c4259d7 271 __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 101:7cff1c4259d7 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 101:7cff1c4259d7 273 return(__regCBAR);
Kojto 101:7cff1c4259d7 274 }
Kojto 101:7cff1c4259d7 275
Kojto 101:7cff1c4259d7 276 /** \brief Get TTBR0
Kojto 101:7cff1c4259d7 277
Kojto 101:7cff1c4259d7 278 This function returns the value of the Configuration Base Address register.
Kojto 101:7cff1c4259d7 279
Kojto 101:7cff1c4259d7 280 \return Translation Table Base Register 0 value
Kojto 101:7cff1c4259d7 281 */
Kojto 101:7cff1c4259d7 282 __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 101:7cff1c4259d7 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 284 return(__regTTBR0);
Kojto 101:7cff1c4259d7 285 }
Kojto 101:7cff1c4259d7 286
Kojto 101:7cff1c4259d7 287 /** \brief Set TTBR0
Kojto 101:7cff1c4259d7 288
Kojto 101:7cff1c4259d7 289 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 290
Kojto 101:7cff1c4259d7 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 101:7cff1c4259d7 292 */
Kojto 101:7cff1c4259d7 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 101:7cff1c4259d7 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 295 __regTTBR0 = ttbr0;
Kojto 101:7cff1c4259d7 296 __ISB();
Kojto 101:7cff1c4259d7 297 }
Kojto 101:7cff1c4259d7 298
Kojto 101:7cff1c4259d7 299 /** \brief Get DACR
Kojto 101:7cff1c4259d7 300
Kojto 101:7cff1c4259d7 301 This function returns the value of the Domain Access Control Register.
Kojto 101:7cff1c4259d7 302
Kojto 101:7cff1c4259d7 303 \return Domain Access Control Register value
Kojto 101:7cff1c4259d7 304 */
Kojto 101:7cff1c4259d7 305 __STATIC_INLINE uint32_t __get_DACR() {
Kojto 101:7cff1c4259d7 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 307 return(__regDACR);
Kojto 101:7cff1c4259d7 308 }
Kojto 101:7cff1c4259d7 309
Kojto 101:7cff1c4259d7 310 /** \brief Set DACR
Kojto 101:7cff1c4259d7 311
Kojto 101:7cff1c4259d7 312 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 313
Kojto 101:7cff1c4259d7 314 \param [in] dacr Domain Access Control Register value to set
Kojto 101:7cff1c4259d7 315 */
Kojto 101:7cff1c4259d7 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 101:7cff1c4259d7 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 318 __regDACR = dacr;
Kojto 101:7cff1c4259d7 319 __ISB();
Kojto 101:7cff1c4259d7 320 }
Kojto 101:7cff1c4259d7 321
Kojto 101:7cff1c4259d7 322 /******************************** Cache and BTAC enable ****************************************************/
Kojto 101:7cff1c4259d7 323
Kojto 101:7cff1c4259d7 324 /** \brief Set SCTLR
Kojto 101:7cff1c4259d7 325
Kojto 101:7cff1c4259d7 326 This function assigns the given value to the System Control Register.
Kojto 101:7cff1c4259d7 327
Kojto 101:7cff1c4259d7 328 \param [in] sctlr System Control Register, value to set
Kojto 101:7cff1c4259d7 329 */
Kojto 101:7cff1c4259d7 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 101:7cff1c4259d7 331 {
Kojto 101:7cff1c4259d7 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 333 __regSCTLR = sctlr;
Kojto 101:7cff1c4259d7 334 }
Kojto 101:7cff1c4259d7 335
Kojto 101:7cff1c4259d7 336 /** \brief Get SCTLR
Kojto 101:7cff1c4259d7 337
Kojto 101:7cff1c4259d7 338 This function returns the value of the System Control Register.
Kojto 101:7cff1c4259d7 339
Kojto 101:7cff1c4259d7 340 \return System Control Register value
Kojto 101:7cff1c4259d7 341 */
Kojto 101:7cff1c4259d7 342 __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 101:7cff1c4259d7 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 344 return(__regSCTLR);
Kojto 101:7cff1c4259d7 345 }
Kojto 101:7cff1c4259d7 346
Kojto 101:7cff1c4259d7 347 /** \brief Enable Caches
Kojto 101:7cff1c4259d7 348
Kojto 101:7cff1c4259d7 349 Enable Caches
Kojto 101:7cff1c4259d7 350 */
Kojto 101:7cff1c4259d7 351 __STATIC_INLINE void __enable_caches(void) {
Kojto 101:7cff1c4259d7 352 // Set I bit 12 to enable I Cache
Kojto 101:7cff1c4259d7 353 // Set C bit 2 to enable D Cache
Kojto 101:7cff1c4259d7 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 101:7cff1c4259d7 355 }
Kojto 101:7cff1c4259d7 356
Kojto 101:7cff1c4259d7 357 /** \brief Disable Caches
Kojto 101:7cff1c4259d7 358
Kojto 101:7cff1c4259d7 359 Disable Caches
Kojto 101:7cff1c4259d7 360 */
Kojto 101:7cff1c4259d7 361 __STATIC_INLINE void __disable_caches(void) {
Kojto 101:7cff1c4259d7 362 // Clear I bit 12 to disable I Cache
Kojto 101:7cff1c4259d7 363 // Clear C bit 2 to disable D Cache
Kojto 101:7cff1c4259d7 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 101:7cff1c4259d7 365 __ISB();
Kojto 101:7cff1c4259d7 366 }
Kojto 101:7cff1c4259d7 367
Kojto 101:7cff1c4259d7 368 /** \brief Enable BTAC
Kojto 101:7cff1c4259d7 369
Kojto 101:7cff1c4259d7 370 Enable BTAC
Kojto 101:7cff1c4259d7 371 */
Kojto 101:7cff1c4259d7 372 __STATIC_INLINE void __enable_btac(void) {
Kojto 101:7cff1c4259d7 373 // Set Z bit 11 to enable branch prediction
Kojto 101:7cff1c4259d7 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 101:7cff1c4259d7 375 __ISB();
Kojto 101:7cff1c4259d7 376 }
Kojto 101:7cff1c4259d7 377
Kojto 101:7cff1c4259d7 378 /** \brief Disable BTAC
Kojto 101:7cff1c4259d7 379
Kojto 101:7cff1c4259d7 380 Disable BTAC
Kojto 101:7cff1c4259d7 381 */
Kojto 101:7cff1c4259d7 382 __STATIC_INLINE void __disable_btac(void) {
Kojto 101:7cff1c4259d7 383 // Clear Z bit 11 to disable branch prediction
Kojto 101:7cff1c4259d7 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 101:7cff1c4259d7 385 }
Kojto 101:7cff1c4259d7 386
Kojto 101:7cff1c4259d7 387
Kojto 101:7cff1c4259d7 388 /** \brief Enable MMU
Kojto 101:7cff1c4259d7 389
Kojto 101:7cff1c4259d7 390 Enable MMU
Kojto 101:7cff1c4259d7 391 */
Kojto 101:7cff1c4259d7 392 __STATIC_INLINE void __enable_mmu(void) {
Kojto 101:7cff1c4259d7 393 // Set M bit 0 to enable the MMU
Kojto 101:7cff1c4259d7 394 // Set AFE bit to enable simplified access permissions model
Kojto 101:7cff1c4259d7 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 101:7cff1c4259d7 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 101:7cff1c4259d7 397 __ISB();
Kojto 101:7cff1c4259d7 398 }
Kojto 101:7cff1c4259d7 399
Kojto 101:7cff1c4259d7 400 /** \brief Enable MMU
Kojto 101:7cff1c4259d7 401
Kojto 101:7cff1c4259d7 402 Enable MMU
Kojto 101:7cff1c4259d7 403 */
Kojto 101:7cff1c4259d7 404 __STATIC_INLINE void __disable_mmu(void) {
Kojto 101:7cff1c4259d7 405 // Clear M bit 0 to disable the MMU
Kojto 101:7cff1c4259d7 406 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 101:7cff1c4259d7 407 __ISB();
Kojto 101:7cff1c4259d7 408 }
Kojto 101:7cff1c4259d7 409
Kojto 101:7cff1c4259d7 410 /******************************** TLB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 411 /** \brief Invalidate the whole tlb
Kojto 101:7cff1c4259d7 412
Kojto 101:7cff1c4259d7 413 TLBIALL. Invalidate the whole tlb
Kojto 101:7cff1c4259d7 414 */
Kojto 101:7cff1c4259d7 415
Kojto 101:7cff1c4259d7 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 101:7cff1c4259d7 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 101:7cff1c4259d7 418 __TLBIALL = 0;
Kojto 101:7cff1c4259d7 419 __DSB();
Kojto 101:7cff1c4259d7 420 __ISB();
Kojto 101:7cff1c4259d7 421 }
Kojto 101:7cff1c4259d7 422
Kojto 101:7cff1c4259d7 423 /******************************** BTB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 424 /** \brief Invalidate entire branch predictor array
Kojto 101:7cff1c4259d7 425
Kojto 101:7cff1c4259d7 426 BPIALL. Branch Predictor Invalidate All.
Kojto 101:7cff1c4259d7 427 */
Kojto 101:7cff1c4259d7 428
Kojto 101:7cff1c4259d7 429 __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 101:7cff1c4259d7 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 101:7cff1c4259d7 431 __BPIALL = 0;
Kojto 101:7cff1c4259d7 432 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 433 __ISB(); //ensure instruction fetch path sees new state
Kojto 101:7cff1c4259d7 434 }
Kojto 101:7cff1c4259d7 435
Kojto 101:7cff1c4259d7 436
Kojto 101:7cff1c4259d7 437 /******************************** L1 cache operations ******************************************************/
Kojto 101:7cff1c4259d7 438
Kojto 101:7cff1c4259d7 439 /** \brief Invalidate the whole I$
Kojto 101:7cff1c4259d7 440
Kojto 101:7cff1c4259d7 441 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 101:7cff1c4259d7 442 */
Kojto 101:7cff1c4259d7 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 101:7cff1c4259d7 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 101:7cff1c4259d7 445 __ICIALLU = 0;
Kojto 101:7cff1c4259d7 446 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 447 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 101:7cff1c4259d7 448 }
Kojto 101:7cff1c4259d7 449
Kojto 101:7cff1c4259d7 450 /** \brief Clean D$ by MVA
Kojto 101:7cff1c4259d7 451
Kojto 101:7cff1c4259d7 452 DCCMVAC. Data cache clean by MVA to PoC
Kojto 101:7cff1c4259d7 453 */
Kojto 101:7cff1c4259d7 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 101:7cff1c4259d7 456 __DCCMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 458 }
Kojto 101:7cff1c4259d7 459
Kojto 101:7cff1c4259d7 460 /** \brief Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 461
Kojto 101:7cff1c4259d7 462 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 463 */
Kojto 101:7cff1c4259d7 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 101:7cff1c4259d7 466 __DCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 468 }
Kojto 101:7cff1c4259d7 469
Kojto 101:7cff1c4259d7 470 /** \brief Clean and Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 471
Kojto 101:7cff1c4259d7 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 473 */
Kojto 101:7cff1c4259d7 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 101:7cff1c4259d7 476 __DCCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 478 }
Kojto 101:7cff1c4259d7 479
Kojto 101:7cff1c4259d7 480 /** \brief
Kojto 101:7cff1c4259d7 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 101:7cff1c4259d7 482 */
Kojto 101:7cff1c4259d7 483 #pragma push
Kojto 101:7cff1c4259d7 484 #pragma arm
Kojto 101:7cff1c4259d7 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Kojto 101:7cff1c4259d7 486 ARM
Kojto 101:7cff1c4259d7 487
Kojto 101:7cff1c4259d7 488 PUSH {R4-R11}
Kojto 101:7cff1c4259d7 489
Kojto 101:7cff1c4259d7 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Kojto 101:7cff1c4259d7 491 ANDS R3, R6, #0x07000000 // Extract coherency level
Kojto 101:7cff1c4259d7 492 MOV R3, R3, LSR #23 // Total cache levels << 1
Kojto 101:7cff1c4259d7 493 BEQ Finished // If 0, no need to clean
Kojto 101:7cff1c4259d7 494
Kojto 101:7cff1c4259d7 495 MOV R10, #0 // R10 holds current cache level << 1
Kojto 101:7cff1c4259d7 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Kojto 101:7cff1c4259d7 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Kojto 101:7cff1c4259d7 498 AND R1, R1, #7 // Isolate those lower 3 bits
Kojto 101:7cff1c4259d7 499 CMP R1, #2
Kojto 101:7cff1c4259d7 500 BLT Skip // No cache or only instruction cache at this level
Kojto 101:7cff1c4259d7 501
Kojto 101:7cff1c4259d7 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Kojto 101:7cff1c4259d7 503 ISB // ISB to sync the change to the CacheSizeID reg
Kojto 101:7cff1c4259d7 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Kojto 101:7cff1c4259d7 505 AND R2, R1, #7 // Extract the line length field
Kojto 101:7cff1c4259d7 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Kojto 101:7cff1c4259d7 507 LDR R4, =0x3FF
Kojto 101:7cff1c4259d7 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Kojto 101:7cff1c4259d7 509 CLZ R5, R4 // R5 is the bit position of the way size increment
Kojto 101:7cff1c4259d7 510 LDR R7, =0x7FFF
Kojto 101:7cff1c4259d7 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Kojto 101:7cff1c4259d7 512
Kojto 101:7cff1c4259d7 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Kojto 101:7cff1c4259d7 514
Kojto 101:7cff1c4259d7 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Kojto 101:7cff1c4259d7 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Kojto 101:7cff1c4259d7 517 CMP R0, #0
Kojto 101:7cff1c4259d7 518 BNE Dccsw
Kojto 101:7cff1c4259d7 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 520 B cont
Kojto 101:7cff1c4259d7 521 Dccsw CMP R0, #1
Kojto 101:7cff1c4259d7 522 BNE Dccisw
Kojto 101:7cff1c4259d7 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 524 B cont
Kojto 101:7cff1c4259d7 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 526 cont SUBS R9, R9, #1 // Decrement the Way number
Kojto 101:7cff1c4259d7 527 BGE Loop3
Kojto 101:7cff1c4259d7 528 SUBS R7, R7, #1 // Decrement the Set number
Kojto 101:7cff1c4259d7 529 BGE Loop2
Kojto 101:7cff1c4259d7 530 Skip ADD R10, R10, #2 // increment the cache number
Kojto 101:7cff1c4259d7 531 CMP R3, R10
Kojto 101:7cff1c4259d7 532 BGT Loop1
Kojto 101:7cff1c4259d7 533
Kojto 101:7cff1c4259d7 534 Finished
Kojto 101:7cff1c4259d7 535 DSB
Kojto 101:7cff1c4259d7 536 POP {R4-R11}
Kojto 101:7cff1c4259d7 537 BX lr
Kojto 101:7cff1c4259d7 538
Kojto 101:7cff1c4259d7 539 }
Kojto 101:7cff1c4259d7 540 #pragma pop
Kojto 101:7cff1c4259d7 541
Kojto 101:7cff1c4259d7 542 /** \brief __v7_all_cache - helper function
Kojto 101:7cff1c4259d7 543
Kojto 101:7cff1c4259d7 544 */
Kojto 101:7cff1c4259d7 545
Kojto 101:7cff1c4259d7 546 /** \brief Invalidate the whole D$
Kojto 101:7cff1c4259d7 547
Kojto 101:7cff1c4259d7 548 DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 549 */
Kojto 101:7cff1c4259d7 550
Kojto 101:7cff1c4259d7 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 552 __v7_all_cache(0);
Kojto 101:7cff1c4259d7 553 }
Kojto 101:7cff1c4259d7 554
Kojto 101:7cff1c4259d7 555 /** \brief Clean the whole D$
Kojto 101:7cff1c4259d7 556
Kojto 101:7cff1c4259d7 557 DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 558 */
Kojto 101:7cff1c4259d7 559
Kojto 101:7cff1c4259d7 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 101:7cff1c4259d7 561 __v7_all_cache(1);
Kojto 101:7cff1c4259d7 562 }
Kojto 101:7cff1c4259d7 563
Kojto 101:7cff1c4259d7 564 /** \brief Clean and invalidate the whole D$
Kojto 101:7cff1c4259d7 565
Kojto 101:7cff1c4259d7 566 DCCISW. Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 567 */
Kojto 101:7cff1c4259d7 568
Kojto 101:7cff1c4259d7 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 570 __v7_all_cache(2);
Kojto 101:7cff1c4259d7 571 }
Kojto 101:7cff1c4259d7 572
Kojto 101:7cff1c4259d7 573 #include "core_ca_mmu.h"
Kojto 101:7cff1c4259d7 574
Kojto 101:7cff1c4259d7 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Kojto 101:7cff1c4259d7 576
Kojto 101:7cff1c4259d7 577 #error IAR Compiler support not implemented for Cortex-A
Kojto 101:7cff1c4259d7 578
Kojto 101:7cff1c4259d7 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Kojto 101:7cff1c4259d7 580
Kojto 101:7cff1c4259d7 581 /* GNU gcc specific functions */
Kojto 101:7cff1c4259d7 582
Kojto 101:7cff1c4259d7 583 #define MODE_USR 0x10
Kojto 101:7cff1c4259d7 584 #define MODE_FIQ 0x11
Kojto 101:7cff1c4259d7 585 #define MODE_IRQ 0x12
Kojto 101:7cff1c4259d7 586 #define MODE_SVC 0x13
Kojto 101:7cff1c4259d7 587 #define MODE_MON 0x16
Kojto 101:7cff1c4259d7 588 #define MODE_ABT 0x17
Kojto 101:7cff1c4259d7 589 #define MODE_HYP 0x1A
Kojto 101:7cff1c4259d7 590 #define MODE_UND 0x1B
Kojto 101:7cff1c4259d7 591 #define MODE_SYS 0x1F
Kojto 101:7cff1c4259d7 592
Kojto 101:7cff1c4259d7 593
Kojto 101:7cff1c4259d7 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Kojto 101:7cff1c4259d7 595 {
Kojto 101:7cff1c4259d7 596 __ASM volatile ("cpsie i");
Kojto 101:7cff1c4259d7 597 }
Kojto 101:7cff1c4259d7 598
Kojto 101:7cff1c4259d7 599 /** \brief Disable IRQ Interrupts
Kojto 101:7cff1c4259d7 600
Kojto 101:7cff1c4259d7 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Kojto 101:7cff1c4259d7 602 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 603 */
Kojto 101:7cff1c4259d7 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Kojto 101:7cff1c4259d7 605 {
Kojto 101:7cff1c4259d7 606 uint32_t result;
Kojto 101:7cff1c4259d7 607
Kojto 101:7cff1c4259d7 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Kojto 101:7cff1c4259d7 609 __ASM volatile ("cpsid i");
Kojto 101:7cff1c4259d7 610 return(result & 0x80);
Kojto 101:7cff1c4259d7 611 }
Kojto 101:7cff1c4259d7 612
Kojto 101:7cff1c4259d7 613
Kojto 101:7cff1c4259d7 614 /** \brief Get APSR Register
Kojto 101:7cff1c4259d7 615
Kojto 101:7cff1c4259d7 616 This function returns the content of the APSR Register.
Kojto 101:7cff1c4259d7 617
Kojto 101:7cff1c4259d7 618 \return APSR Register value
Kojto 101:7cff1c4259d7 619 */
Kojto 101:7cff1c4259d7 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Kojto 101:7cff1c4259d7 621 {
Kojto 101:7cff1c4259d7 622 #if 1
Kojto 101:7cff1c4259d7 623 uint32_t result;
Kojto 101:7cff1c4259d7 624
Kojto 101:7cff1c4259d7 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
Kojto 101:7cff1c4259d7 626 return (result);
Kojto 101:7cff1c4259d7 627 #else
Kojto 101:7cff1c4259d7 628 register uint32_t __regAPSR __ASM("apsr");
Kojto 101:7cff1c4259d7 629 return(__regAPSR);
Kojto 101:7cff1c4259d7 630 #endif
Kojto 101:7cff1c4259d7 631 }
Kojto 101:7cff1c4259d7 632
Kojto 101:7cff1c4259d7 633
Kojto 101:7cff1c4259d7 634 /** \brief Get CPSR Register
Kojto 101:7cff1c4259d7 635
Kojto 101:7cff1c4259d7 636 This function returns the content of the CPSR Register.
Kojto 101:7cff1c4259d7 637
Kojto 101:7cff1c4259d7 638 \return CPSR Register value
Kojto 101:7cff1c4259d7 639 */
Kojto 101:7cff1c4259d7 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Kojto 101:7cff1c4259d7 641 {
Kojto 101:7cff1c4259d7 642 #if 1
Kojto 101:7cff1c4259d7 643 register uint32_t __regCPSR;
Kojto 101:7cff1c4259d7 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Kojto 101:7cff1c4259d7 645 #else
Kojto 101:7cff1c4259d7 646 register uint32_t __regCPSR __ASM("cpsr");
Kojto 101:7cff1c4259d7 647 #endif
Kojto 101:7cff1c4259d7 648 return(__regCPSR);
Kojto 101:7cff1c4259d7 649 }
Kojto 101:7cff1c4259d7 650
Kojto 101:7cff1c4259d7 651 #if 0
Kojto 101:7cff1c4259d7 652 /** \brief Set Stack Pointer
Kojto 101:7cff1c4259d7 653
Kojto 101:7cff1c4259d7 654 This function assigns the given value to the current stack pointer.
Kojto 101:7cff1c4259d7 655
Kojto 101:7cff1c4259d7 656 \param [in] topOfStack Stack Pointer value to set
Kojto 101:7cff1c4259d7 657 */
Kojto 101:7cff1c4259d7 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Kojto 101:7cff1c4259d7 659 {
Kojto 101:7cff1c4259d7 660 register uint32_t __regSP __ASM("sp");
Kojto 101:7cff1c4259d7 661 __regSP = topOfStack;
Kojto 101:7cff1c4259d7 662 }
Kojto 101:7cff1c4259d7 663 #endif
Kojto 101:7cff1c4259d7 664
Kojto 101:7cff1c4259d7 665 /** \brief Get link register
Kojto 101:7cff1c4259d7 666
Kojto 101:7cff1c4259d7 667 This function returns the value of the link register
Kojto 101:7cff1c4259d7 668
Kojto 101:7cff1c4259d7 669 \return Value of link register
Kojto 101:7cff1c4259d7 670 */
Kojto 101:7cff1c4259d7 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Kojto 101:7cff1c4259d7 672 {
Kojto 101:7cff1c4259d7 673 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 674 return(__reglr);
Kojto 101:7cff1c4259d7 675 }
Kojto 101:7cff1c4259d7 676
Kojto 101:7cff1c4259d7 677 #if 0
Kojto 101:7cff1c4259d7 678 /** \brief Set link register
Kojto 101:7cff1c4259d7 679
Kojto 101:7cff1c4259d7 680 This function sets the value of the link register
Kojto 101:7cff1c4259d7 681
Kojto 101:7cff1c4259d7 682 \param [in] lr LR value to set
Kojto 101:7cff1c4259d7 683 */
Kojto 101:7cff1c4259d7 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Kojto 101:7cff1c4259d7 685 {
Kojto 101:7cff1c4259d7 686 register uint32_t __reglr __ASM("lr");
Kojto 101:7cff1c4259d7 687 __reglr = lr;
Kojto 101:7cff1c4259d7 688 }
Kojto 101:7cff1c4259d7 689 #endif
Kojto 101:7cff1c4259d7 690
Kojto 101:7cff1c4259d7 691 /** \brief Set Process Stack Pointer
Kojto 101:7cff1c4259d7 692
Kojto 101:7cff1c4259d7 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Kojto 101:7cff1c4259d7 694
Kojto 101:7cff1c4259d7 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 101:7cff1c4259d7 696 */
Kojto 101:7cff1c4259d7 697 extern void __set_PSP(uint32_t topOfProcStack);
Kojto 101:7cff1c4259d7 698
Kojto 101:7cff1c4259d7 699 /** \brief Set User Mode
Kojto 101:7cff1c4259d7 700
Kojto 101:7cff1c4259d7 701 This function changes the processor state to User Mode
Kojto 101:7cff1c4259d7 702
Kojto 101:7cff1c4259d7 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Kojto 101:7cff1c4259d7 704 */
Kojto 101:7cff1c4259d7 705 extern void __set_CPS_USR(void);
Kojto 101:7cff1c4259d7 706
Kojto 101:7cff1c4259d7 707 /** \brief Enable FIQ
Kojto 101:7cff1c4259d7 708
Kojto 101:7cff1c4259d7 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 710 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 711 */
Kojto 101:7cff1c4259d7 712 #define __enable_fault_irq __enable_fiq
Kojto 101:7cff1c4259d7 713
Kojto 101:7cff1c4259d7 714
Kojto 101:7cff1c4259d7 715 /** \brief Disable FIQ
Kojto 101:7cff1c4259d7 716
Kojto 101:7cff1c4259d7 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Kojto 101:7cff1c4259d7 718 Can only be executed in Privileged modes.
Kojto 101:7cff1c4259d7 719 */
Kojto 101:7cff1c4259d7 720 #define __disable_fault_irq __disable_fiq
Kojto 101:7cff1c4259d7 721
Kojto 101:7cff1c4259d7 722
Kojto 101:7cff1c4259d7 723 /** \brief Get FPSCR
Kojto 101:7cff1c4259d7 724
Kojto 101:7cff1c4259d7 725 This function returns the current value of the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 726
Kojto 101:7cff1c4259d7 727 \return Floating Point Status/Control register value
Kojto 101:7cff1c4259d7 728 */
Kojto 101:7cff1c4259d7 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Kojto 101:7cff1c4259d7 730 {
Kojto 101:7cff1c4259d7 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 732 #if 1
Kojto 101:7cff1c4259d7 733 uint32_t result;
Kojto 101:7cff1c4259d7 734
Kojto 101:7cff1c4259d7 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Kojto 101:7cff1c4259d7 736 return (result);
Kojto 101:7cff1c4259d7 737 #else
Kojto 101:7cff1c4259d7 738 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 739 return(__regfpscr);
Kojto 101:7cff1c4259d7 740 #endif
Kojto 101:7cff1c4259d7 741 #else
Kojto 101:7cff1c4259d7 742 return(0);
Kojto 101:7cff1c4259d7 743 #endif
Kojto 101:7cff1c4259d7 744 }
Kojto 101:7cff1c4259d7 745
Kojto 101:7cff1c4259d7 746
Kojto 101:7cff1c4259d7 747 /** \brief Set FPSCR
Kojto 101:7cff1c4259d7 748
Kojto 101:7cff1c4259d7 749 This function assigns the given value to the Floating Point Status/Control register.
Kojto 101:7cff1c4259d7 750
Kojto 101:7cff1c4259d7 751 \param [in] fpscr Floating Point Status/Control value to set
Kojto 101:7cff1c4259d7 752 */
Kojto 101:7cff1c4259d7 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Kojto 101:7cff1c4259d7 754 {
Kojto 101:7cff1c4259d7 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Kojto 101:7cff1c4259d7 756 #if 1
Kojto 101:7cff1c4259d7 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Kojto 101:7cff1c4259d7 758 #else
Kojto 101:7cff1c4259d7 759 register uint32_t __regfpscr __ASM("fpscr");
Kojto 101:7cff1c4259d7 760 __regfpscr = (fpscr);
Kojto 101:7cff1c4259d7 761 #endif
Kojto 101:7cff1c4259d7 762 #endif
Kojto 101:7cff1c4259d7 763 }
Kojto 101:7cff1c4259d7 764
Kojto 101:7cff1c4259d7 765 /** \brief Get FPEXC
Kojto 101:7cff1c4259d7 766
Kojto 101:7cff1c4259d7 767 This function returns the current value of the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 768
Kojto 101:7cff1c4259d7 769 \return Floating Point Exception Control register value
Kojto 101:7cff1c4259d7 770 */
Kojto 101:7cff1c4259d7 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Kojto 101:7cff1c4259d7 772 {
Kojto 101:7cff1c4259d7 773 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 774 #if 1
Kojto 101:7cff1c4259d7 775 uint32_t result;
Kojto 101:7cff1c4259d7 776
Kojto 101:7cff1c4259d7 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Kojto 101:7cff1c4259d7 778 return (result);
Kojto 101:7cff1c4259d7 779 #else
Kojto 101:7cff1c4259d7 780 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 781 return(__regfpexc);
Kojto 101:7cff1c4259d7 782 #endif
Kojto 101:7cff1c4259d7 783 #else
Kojto 101:7cff1c4259d7 784 return(0);
Kojto 101:7cff1c4259d7 785 #endif
Kojto 101:7cff1c4259d7 786 }
Kojto 101:7cff1c4259d7 787
Kojto 101:7cff1c4259d7 788
Kojto 101:7cff1c4259d7 789 /** \brief Set FPEXC
Kojto 101:7cff1c4259d7 790
Kojto 101:7cff1c4259d7 791 This function assigns the given value to the Floating Point Exception Control register.
Kojto 101:7cff1c4259d7 792
Kojto 101:7cff1c4259d7 793 \param [in] fpscr Floating Point Exception Control value to set
Kojto 101:7cff1c4259d7 794 */
Kojto 101:7cff1c4259d7 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Kojto 101:7cff1c4259d7 796 {
Kojto 101:7cff1c4259d7 797 #if (__FPU_PRESENT == 1)
Kojto 101:7cff1c4259d7 798 #if 1
Kojto 101:7cff1c4259d7 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Kojto 101:7cff1c4259d7 800 #else
Kojto 101:7cff1c4259d7 801 register uint32_t __regfpexc __ASM("fpexc");
Kojto 101:7cff1c4259d7 802 __regfpexc = (fpexc);
Kojto 101:7cff1c4259d7 803 #endif
Kojto 101:7cff1c4259d7 804 #endif
Kojto 101:7cff1c4259d7 805 }
Kojto 101:7cff1c4259d7 806
Kojto 101:7cff1c4259d7 807 /** \brief Get CPACR
Kojto 101:7cff1c4259d7 808
Kojto 101:7cff1c4259d7 809 This function returns the current value of the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 810
Kojto 101:7cff1c4259d7 811 \return Coprocessor Access Control register value
Kojto 101:7cff1c4259d7 812 */
Kojto 101:7cff1c4259d7 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Kojto 101:7cff1c4259d7 814 {
Kojto 101:7cff1c4259d7 815 #if 1
Kojto 101:7cff1c4259d7 816 register uint32_t __regCPACR;
Kojto 101:7cff1c4259d7 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Kojto 101:7cff1c4259d7 818 #else
Kojto 101:7cff1c4259d7 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 820 #endif
Kojto 101:7cff1c4259d7 821 return __regCPACR;
Kojto 101:7cff1c4259d7 822 }
Kojto 101:7cff1c4259d7 823
Kojto 101:7cff1c4259d7 824 /** \brief Set CPACR
Kojto 101:7cff1c4259d7 825
Kojto 101:7cff1c4259d7 826 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 827
Kojto 101:7cff1c4259d7 828 \param [in] cpacr Coporcessor Acccess Control value to set
Kojto 101:7cff1c4259d7 829 */
Kojto 101:7cff1c4259d7 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Kojto 101:7cff1c4259d7 831 {
Kojto 101:7cff1c4259d7 832 #if 1
Kojto 101:7cff1c4259d7 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Kojto 101:7cff1c4259d7 834 #else
Kojto 101:7cff1c4259d7 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Kojto 101:7cff1c4259d7 836 __regCPACR = cpacr;
Kojto 101:7cff1c4259d7 837 #endif
Kojto 101:7cff1c4259d7 838 __ISB();
Kojto 101:7cff1c4259d7 839 }
Kojto 101:7cff1c4259d7 840
Kojto 101:7cff1c4259d7 841 /** \brief Get CBAR
Kojto 101:7cff1c4259d7 842
Kojto 101:7cff1c4259d7 843 This function returns the value of the Configuration Base Address register.
Kojto 101:7cff1c4259d7 844
Kojto 101:7cff1c4259d7 845 \return Configuration Base Address register value
Kojto 101:7cff1c4259d7 846 */
Kojto 101:7cff1c4259d7 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Kojto 101:7cff1c4259d7 848 #if 1
Kojto 101:7cff1c4259d7 849 register uint32_t __regCBAR;
Kojto 101:7cff1c4259d7 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Kojto 101:7cff1c4259d7 851 #else
Kojto 101:7cff1c4259d7 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Kojto 101:7cff1c4259d7 853 #endif
Kojto 101:7cff1c4259d7 854 return(__regCBAR);
Kojto 101:7cff1c4259d7 855 }
Kojto 101:7cff1c4259d7 856
Kojto 101:7cff1c4259d7 857 /** \brief Get TTBR0
Kojto 101:7cff1c4259d7 858
Kojto 101:7cff1c4259d7 859 This function returns the value of the Configuration Base Address register.
Kojto 101:7cff1c4259d7 860
Kojto 101:7cff1c4259d7 861 \return Translation Table Base Register 0 value
Kojto 101:7cff1c4259d7 862 */
Kojto 101:7cff1c4259d7 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Kojto 101:7cff1c4259d7 864 #if 1
Kojto 101:7cff1c4259d7 865 register uint32_t __regTTBR0;
Kojto 101:7cff1c4259d7 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Kojto 101:7cff1c4259d7 867 #else
Kojto 101:7cff1c4259d7 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 869 #endif
Kojto 101:7cff1c4259d7 870 return(__regTTBR0);
Kojto 101:7cff1c4259d7 871 }
Kojto 101:7cff1c4259d7 872
Kojto 101:7cff1c4259d7 873 /** \brief Set TTBR0
Kojto 101:7cff1c4259d7 874
Kojto 101:7cff1c4259d7 875 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 876
Kojto 101:7cff1c4259d7 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
Kojto 101:7cff1c4259d7 878 */
Kojto 101:7cff1c4259d7 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Kojto 101:7cff1c4259d7 880 #if 1
Kojto 101:7cff1c4259d7 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Kojto 101:7cff1c4259d7 882 #else
Kojto 101:7cff1c4259d7 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Kojto 101:7cff1c4259d7 884 __regTTBR0 = ttbr0;
Kojto 101:7cff1c4259d7 885 #endif
Kojto 101:7cff1c4259d7 886 __ISB();
Kojto 101:7cff1c4259d7 887 }
Kojto 101:7cff1c4259d7 888
Kojto 101:7cff1c4259d7 889 /** \brief Get DACR
Kojto 101:7cff1c4259d7 890
Kojto 101:7cff1c4259d7 891 This function returns the value of the Domain Access Control Register.
Kojto 101:7cff1c4259d7 892
Kojto 101:7cff1c4259d7 893 \return Domain Access Control Register value
Kojto 101:7cff1c4259d7 894 */
Kojto 101:7cff1c4259d7 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Kojto 101:7cff1c4259d7 896 #if 1
Kojto 101:7cff1c4259d7 897 register uint32_t __regDACR;
Kojto 101:7cff1c4259d7 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Kojto 101:7cff1c4259d7 899 #else
Kojto 101:7cff1c4259d7 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 901 #endif
Kojto 101:7cff1c4259d7 902 return(__regDACR);
Kojto 101:7cff1c4259d7 903 }
Kojto 101:7cff1c4259d7 904
Kojto 101:7cff1c4259d7 905 /** \brief Set DACR
Kojto 101:7cff1c4259d7 906
Kojto 101:7cff1c4259d7 907 This function assigns the given value to the Coprocessor Access Control register.
Kojto 101:7cff1c4259d7 908
Kojto 101:7cff1c4259d7 909 \param [in] dacr Domain Access Control Register value to set
Kojto 101:7cff1c4259d7 910 */
Kojto 101:7cff1c4259d7 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Kojto 101:7cff1c4259d7 912 #if 1
Kojto 101:7cff1c4259d7 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Kojto 101:7cff1c4259d7 914 #else
Kojto 101:7cff1c4259d7 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Kojto 101:7cff1c4259d7 916 __regDACR = dacr;
Kojto 101:7cff1c4259d7 917 #endif
Kojto 101:7cff1c4259d7 918 __ISB();
Kojto 101:7cff1c4259d7 919 }
Kojto 101:7cff1c4259d7 920
Kojto 101:7cff1c4259d7 921 /******************************** Cache and BTAC enable ****************************************************/
Kojto 101:7cff1c4259d7 922
Kojto 101:7cff1c4259d7 923 /** \brief Set SCTLR
Kojto 101:7cff1c4259d7 924
Kojto 101:7cff1c4259d7 925 This function assigns the given value to the System Control Register.
Kojto 101:7cff1c4259d7 926
Kojto 101:7cff1c4259d7 927 \param [in] sctlr System Control Register, value to set
Kojto 101:7cff1c4259d7 928 */
Kojto 101:7cff1c4259d7 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Kojto 101:7cff1c4259d7 930 {
Kojto 101:7cff1c4259d7 931 #if 1
Kojto 101:7cff1c4259d7 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Kojto 101:7cff1c4259d7 933 #else
Kojto 101:7cff1c4259d7 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 935 __regSCTLR = sctlr;
Kojto 101:7cff1c4259d7 936 #endif
Kojto 101:7cff1c4259d7 937 }
Kojto 101:7cff1c4259d7 938
Kojto 101:7cff1c4259d7 939 /** \brief Get SCTLR
Kojto 101:7cff1c4259d7 940
Kojto 101:7cff1c4259d7 941 This function returns the value of the System Control Register.
Kojto 101:7cff1c4259d7 942
Kojto 101:7cff1c4259d7 943 \return System Control Register value
Kojto 101:7cff1c4259d7 944 */
Kojto 101:7cff1c4259d7 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Kojto 101:7cff1c4259d7 946 #if 1
Kojto 101:7cff1c4259d7 947 register uint32_t __regSCTLR;
Kojto 101:7cff1c4259d7 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Kojto 101:7cff1c4259d7 949 #else
Kojto 101:7cff1c4259d7 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Kojto 101:7cff1c4259d7 951 #endif
Kojto 101:7cff1c4259d7 952 return(__regSCTLR);
Kojto 101:7cff1c4259d7 953 }
Kojto 101:7cff1c4259d7 954
Kojto 101:7cff1c4259d7 955 /** \brief Enable Caches
Kojto 101:7cff1c4259d7 956
Kojto 101:7cff1c4259d7 957 Enable Caches
Kojto 101:7cff1c4259d7 958 */
Kojto 101:7cff1c4259d7 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Kojto 101:7cff1c4259d7 960 // Set I bit 12 to enable I Cache
Kojto 101:7cff1c4259d7 961 // Set C bit 2 to enable D Cache
Kojto 101:7cff1c4259d7 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Kojto 101:7cff1c4259d7 963 }
Kojto 101:7cff1c4259d7 964
Kojto 101:7cff1c4259d7 965 /** \brief Disable Caches
Kojto 101:7cff1c4259d7 966
Kojto 101:7cff1c4259d7 967 Disable Caches
Kojto 101:7cff1c4259d7 968 */
Kojto 101:7cff1c4259d7 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Kojto 101:7cff1c4259d7 970 // Clear I bit 12 to disable I Cache
Kojto 101:7cff1c4259d7 971 // Clear C bit 2 to disable D Cache
Kojto 101:7cff1c4259d7 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Kojto 101:7cff1c4259d7 973 __ISB();
Kojto 101:7cff1c4259d7 974 }
Kojto 101:7cff1c4259d7 975
Kojto 101:7cff1c4259d7 976 /** \brief Enable BTAC
Kojto 101:7cff1c4259d7 977
Kojto 101:7cff1c4259d7 978 Enable BTAC
Kojto 101:7cff1c4259d7 979 */
Kojto 101:7cff1c4259d7 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Kojto 101:7cff1c4259d7 981 // Set Z bit 11 to enable branch prediction
Kojto 101:7cff1c4259d7 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
Kojto 101:7cff1c4259d7 983 __ISB();
Kojto 101:7cff1c4259d7 984 }
Kojto 101:7cff1c4259d7 985
Kojto 101:7cff1c4259d7 986 /** \brief Disable BTAC
Kojto 101:7cff1c4259d7 987
Kojto 101:7cff1c4259d7 988 Disable BTAC
Kojto 101:7cff1c4259d7 989 */
Kojto 101:7cff1c4259d7 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Kojto 101:7cff1c4259d7 991 // Clear Z bit 11 to disable branch prediction
Kojto 101:7cff1c4259d7 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Kojto 101:7cff1c4259d7 993 }
Kojto 101:7cff1c4259d7 994
Kojto 101:7cff1c4259d7 995
Kojto 101:7cff1c4259d7 996 /** \brief Enable MMU
Kojto 101:7cff1c4259d7 997
Kojto 101:7cff1c4259d7 998 Enable MMU
Kojto 101:7cff1c4259d7 999 */
Kojto 101:7cff1c4259d7 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Kojto 101:7cff1c4259d7 1001 // Set M bit 0 to enable the MMU
Kojto 101:7cff1c4259d7 1002 // Set AFE bit to enable simplified access permissions model
Kojto 101:7cff1c4259d7 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Kojto 101:7cff1c4259d7 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Kojto 101:7cff1c4259d7 1005 __ISB();
Kojto 101:7cff1c4259d7 1006 }
Kojto 101:7cff1c4259d7 1007
Kojto 101:7cff1c4259d7 1008 /** \brief Enable MMU
Kojto 101:7cff1c4259d7 1009
Kojto 101:7cff1c4259d7 1010 Enable MMU
Kojto 101:7cff1c4259d7 1011 */
Kojto 101:7cff1c4259d7 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Kojto 101:7cff1c4259d7 1013 // Clear M bit 0 to disable the MMU
Kojto 101:7cff1c4259d7 1014 __set_SCTLR( __get_SCTLR() & ~1);
Kojto 101:7cff1c4259d7 1015 __ISB();
Kojto 101:7cff1c4259d7 1016 }
Kojto 101:7cff1c4259d7 1017
Kojto 101:7cff1c4259d7 1018 /******************************** TLB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 1019 /** \brief Invalidate the whole tlb
Kojto 101:7cff1c4259d7 1020
Kojto 101:7cff1c4259d7 1021 TLBIALL. Invalidate the whole tlb
Kojto 101:7cff1c4259d7 1022 */
Kojto 101:7cff1c4259d7 1023
Kojto 101:7cff1c4259d7 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Kojto 101:7cff1c4259d7 1025 #if 1
Kojto 101:7cff1c4259d7 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Kojto 101:7cff1c4259d7 1027 #else
Kojto 101:7cff1c4259d7 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Kojto 101:7cff1c4259d7 1029 __TLBIALL = 0;
Kojto 101:7cff1c4259d7 1030 #endif
Kojto 101:7cff1c4259d7 1031 __DSB();
Kojto 101:7cff1c4259d7 1032 __ISB();
Kojto 101:7cff1c4259d7 1033 }
Kojto 101:7cff1c4259d7 1034
Kojto 101:7cff1c4259d7 1035 /******************************** BTB maintenance operations ************************************************/
Kojto 101:7cff1c4259d7 1036 /** \brief Invalidate entire branch predictor array
Kojto 101:7cff1c4259d7 1037
Kojto 101:7cff1c4259d7 1038 BPIALL. Branch Predictor Invalidate All.
Kojto 101:7cff1c4259d7 1039 */
Kojto 101:7cff1c4259d7 1040
Kojto 101:7cff1c4259d7 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Kojto 101:7cff1c4259d7 1042 #if 1
Kojto 101:7cff1c4259d7 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Kojto 101:7cff1c4259d7 1044 #else
Kojto 101:7cff1c4259d7 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Kojto 101:7cff1c4259d7 1046 __BPIALL = 0;
Kojto 101:7cff1c4259d7 1047 #endif
Kojto 101:7cff1c4259d7 1048 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 1049 __ISB(); //ensure instruction fetch path sees new state
Kojto 101:7cff1c4259d7 1050 }
Kojto 101:7cff1c4259d7 1051
Kojto 101:7cff1c4259d7 1052
Kojto 101:7cff1c4259d7 1053 /******************************** L1 cache operations ******************************************************/
Kojto 101:7cff1c4259d7 1054
Kojto 101:7cff1c4259d7 1055 /** \brief Invalidate the whole I$
Kojto 101:7cff1c4259d7 1056
Kojto 101:7cff1c4259d7 1057 ICIALLU. Instruction Cache Invalidate All to PoU
Kojto 101:7cff1c4259d7 1058 */
Kojto 101:7cff1c4259d7 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Kojto 101:7cff1c4259d7 1060 #if 1
Kojto 101:7cff1c4259d7 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Kojto 101:7cff1c4259d7 1062 #else
Kojto 101:7cff1c4259d7 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Kojto 101:7cff1c4259d7 1064 __ICIALLU = 0;
Kojto 101:7cff1c4259d7 1065 #endif
Kojto 101:7cff1c4259d7 1066 __DSB(); //ensure completion of the invalidation
Kojto 101:7cff1c4259d7 1067 __ISB(); //ensure instruction fetch path sees new I cache state
Kojto 101:7cff1c4259d7 1068 }
Kojto 101:7cff1c4259d7 1069
Kojto 101:7cff1c4259d7 1070 /** \brief Clean D$ by MVA
Kojto 101:7cff1c4259d7 1071
Kojto 101:7cff1c4259d7 1072 DCCMVAC. Data cache clean by MVA to PoC
Kojto 101:7cff1c4259d7 1073 */
Kojto 101:7cff1c4259d7 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1075 #if 1
Kojto 101:7cff1c4259d7 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1077 #else
Kojto 101:7cff1c4259d7 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Kojto 101:7cff1c4259d7 1079 __DCCMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1080 #endif
Kojto 101:7cff1c4259d7 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1082 }
Kojto 101:7cff1c4259d7 1083
Kojto 101:7cff1c4259d7 1084 /** \brief Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 1085
Kojto 101:7cff1c4259d7 1086 DCIMVAC. Data cache invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 1087 */
Kojto 101:7cff1c4259d7 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1089 #if 1
Kojto 101:7cff1c4259d7 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1091 #else
Kojto 101:7cff1c4259d7 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Kojto 101:7cff1c4259d7 1093 __DCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1094 #endif
Kojto 101:7cff1c4259d7 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1096 }
Kojto 101:7cff1c4259d7 1097
Kojto 101:7cff1c4259d7 1098 /** \brief Clean and Invalidate D$ by MVA
Kojto 101:7cff1c4259d7 1099
Kojto 101:7cff1c4259d7 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Kojto 101:7cff1c4259d7 1101 */
Kojto 101:7cff1c4259d7 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Kojto 101:7cff1c4259d7 1103 #if 1
Kojto 101:7cff1c4259d7 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Kojto 101:7cff1c4259d7 1105 #else
Kojto 101:7cff1c4259d7 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Kojto 101:7cff1c4259d7 1107 __DCCIMVAC = (uint32_t)va;
Kojto 101:7cff1c4259d7 1108 #endif
Kojto 101:7cff1c4259d7 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Kojto 101:7cff1c4259d7 1110 }
Kojto 101:7cff1c4259d7 1111
Kojto 101:7cff1c4259d7 1112 /** \brief
Kojto 101:7cff1c4259d7 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Kojto 101:7cff1c4259d7 1114 */
Kojto 101:7cff1c4259d7 1115
Kojto 101:7cff1c4259d7 1116 /** \brief __v7_all_cache - helper function
Kojto 101:7cff1c4259d7 1117
Kojto 101:7cff1c4259d7 1118 */
Kojto 101:7cff1c4259d7 1119
Kojto 101:7cff1c4259d7 1120 extern void __v7_all_cache(uint32_t op);
Kojto 101:7cff1c4259d7 1121
Kojto 101:7cff1c4259d7 1122
Kojto 101:7cff1c4259d7 1123 /** \brief Invalidate the whole D$
Kojto 101:7cff1c4259d7 1124
Kojto 101:7cff1c4259d7 1125 DCISW. Invalidate by Set/Way
Kojto 101:7cff1c4259d7 1126 */
Kojto 101:7cff1c4259d7 1127
Kojto 101:7cff1c4259d7 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 1129 __v7_all_cache(0);
Kojto 101:7cff1c4259d7 1130 }
Kojto 101:7cff1c4259d7 1131
Kojto 101:7cff1c4259d7 1132 /** \brief Clean the whole D$
Kojto 101:7cff1c4259d7 1133
Kojto 101:7cff1c4259d7 1134 DCCSW. Clean by Set/Way
Kojto 101:7cff1c4259d7 1135 */
Kojto 101:7cff1c4259d7 1136
Kojto 101:7cff1c4259d7 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Kojto 101:7cff1c4259d7 1138 __v7_all_cache(1);
Kojto 101:7cff1c4259d7 1139 }
Kojto 101:7cff1c4259d7 1140
Kojto 101:7cff1c4259d7 1141 /** \brief Clean and invalidate the whole D$
Kojto 101:7cff1c4259d7 1142
Kojto 101:7cff1c4259d7 1143 DCCISW. Clean and Invalidate by Set/Way
Kojto 101:7cff1c4259d7 1144 */
Kojto 101:7cff1c4259d7 1145
Kojto 101:7cff1c4259d7 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Kojto 101:7cff1c4259d7 1147 __v7_all_cache(2);
Kojto 101:7cff1c4259d7 1148 }
Kojto 101:7cff1c4259d7 1149
Kojto 101:7cff1c4259d7 1150 #include "core_ca_mmu.h"
Kojto 101:7cff1c4259d7 1151
Kojto 101:7cff1c4259d7 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Kojto 101:7cff1c4259d7 1153
Kojto 101:7cff1c4259d7 1154 #error TASKING Compiler support not implemented for Cortex-A
Kojto 101:7cff1c4259d7 1155
Kojto 101:7cff1c4259d7 1156 #endif
Kojto 101:7cff1c4259d7 1157
Kojto 101:7cff1c4259d7 1158 /*@} end of CMSIS_Core_RegAccFunctions */
Kojto 101:7cff1c4259d7 1159
Kojto 101:7cff1c4259d7 1160
Kojto 101:7cff1c4259d7 1161 #endif /* __CORE_CAFUNC_H__ */