mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_KW24D/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
128:9bcdf88f62b0
Child:
141:794e51388b66
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 #! armcc -E
<> 128:9bcdf88f62b0 2 /*
<> 128:9bcdf88f62b0 3 ** ###################################################################
<> 128:9bcdf88f62b0 4 ** Processor: MKW24D512VHA5
<> 128:9bcdf88f62b0 5 ** Compiler: Keil ARM C/C++ Compiler
<> 128:9bcdf88f62b0 6 ** Reference manual: MKW2xDRM Rev.2 July 2014
<> 128:9bcdf88f62b0 7 ** Version: rev. 2.0, 2014-11-26
<> 128:9bcdf88f62b0 8 ** Build: b160512
<> 128:9bcdf88f62b0 9 **
<> 128:9bcdf88f62b0 10 ** Abstract:
<> 128:9bcdf88f62b0 11 ** Linker file for the Keil ARM C/C++ Compiler
<> 128:9bcdf88f62b0 12 **
<> 128:9bcdf88f62b0 13 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
<> 128:9bcdf88f62b0 14 ** All rights reserved.
<> 128:9bcdf88f62b0 15 **
<> 128:9bcdf88f62b0 16 ** Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 17 ** are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 18 **
<> 128:9bcdf88f62b0 19 ** o Redistributions of source code must retain the above copyright notice, this list
<> 128:9bcdf88f62b0 20 ** of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 21 **
<> 128:9bcdf88f62b0 22 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 128:9bcdf88f62b0 23 ** list of conditions and the following disclaimer in the documentation and/or
<> 128:9bcdf88f62b0 24 ** other materials provided with the distribution.
<> 128:9bcdf88f62b0 25 **
<> 128:9bcdf88f62b0 26 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 128:9bcdf88f62b0 27 ** contributors may be used to endorse or promote products derived from this
<> 128:9bcdf88f62b0 28 ** software without specific prior written permission.
<> 128:9bcdf88f62b0 29 **
<> 128:9bcdf88f62b0 30 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 128:9bcdf88f62b0 31 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 128:9bcdf88f62b0 32 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 33 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 128:9bcdf88f62b0 34 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 128:9bcdf88f62b0 35 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 128:9bcdf88f62b0 36 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 128:9bcdf88f62b0 37 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 128:9bcdf88f62b0 38 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 128:9bcdf88f62b0 39 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 40 **
<> 128:9bcdf88f62b0 41 ** http: www.freescale.com
<> 128:9bcdf88f62b0 42 ** mail: support@freescale.com
<> 128:9bcdf88f62b0 43 **
<> 128:9bcdf88f62b0 44 ** ###################################################################
<> 128:9bcdf88f62b0 45 */
<> 128:9bcdf88f62b0 46 #define __ram_vector_table__ 1
<> 128:9bcdf88f62b0 47
<> 128:9bcdf88f62b0 48 /* Heap 1/4 of ram and stack 1/8 */
<> 128:9bcdf88f62b0 49 #define __stack_size__ 0x2000
<> 128:9bcdf88f62b0 50 #define __heap_size__ 0x4000
<> 128:9bcdf88f62b0 51
<> 128:9bcdf88f62b0 52 #if (defined(__ram_vector_table__))
<> 128:9bcdf88f62b0 53 #define __ram_vector_table_size__ 0x00000400
<> 128:9bcdf88f62b0 54 #else
<> 128:9bcdf88f62b0 55 #define __ram_vector_table_size__ 0x00000000
<> 128:9bcdf88f62b0 56 #endif
<> 128:9bcdf88f62b0 57
<> 128:9bcdf88f62b0 58 #define m_interrupts_start 0x00000000
<> 128:9bcdf88f62b0 59 #define m_interrupts_size 0x00000400
<> 128:9bcdf88f62b0 60
<> 128:9bcdf88f62b0 61 #define m_flash_config_start 0x00000400
<> 128:9bcdf88f62b0 62 #define m_flash_config_size 0x00000010
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 #define m_text_start 0x00000410
<> 128:9bcdf88f62b0 65 #define m_text_size 0x0007FBF0
<> 128:9bcdf88f62b0 66
<> 128:9bcdf88f62b0 67 #define m_interrupts_ram_start 0x1FFF8000
<> 128:9bcdf88f62b0 68 #define m_interrupts_ram_size __ram_vector_table_size__
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 #define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
<> 128:9bcdf88f62b0 71 #define m_data_size (0x00008000 - m_interrupts_ram_size)
<> 128:9bcdf88f62b0 72
<> 128:9bcdf88f62b0 73 #define m_data_2_start 0x20000000
<> 128:9bcdf88f62b0 74 #define m_data_2_size 0x00008000
<> 128:9bcdf88f62b0 75
<> 128:9bcdf88f62b0 76 /* Sizes */
<> 128:9bcdf88f62b0 77 #if (defined(__stack_size__))
<> 128:9bcdf88f62b0 78 #define Stack_Size __stack_size__
<> 128:9bcdf88f62b0 79 #else
<> 128:9bcdf88f62b0 80 #define Stack_Size 0x0400
<> 128:9bcdf88f62b0 81 #endif
<> 128:9bcdf88f62b0 82
<> 128:9bcdf88f62b0 83 #if (defined(__heap_size__))
<> 128:9bcdf88f62b0 84 #define Heap_Size __heap_size__
<> 128:9bcdf88f62b0 85 #else
<> 128:9bcdf88f62b0 86 #define Heap_Size 0x0400
<> 128:9bcdf88f62b0 87 #endif
<> 128:9bcdf88f62b0 88
<> 128:9bcdf88f62b0 89 LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
<> 128:9bcdf88f62b0 90 VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
<> 128:9bcdf88f62b0 91 * (RESET,+FIRST)
<> 128:9bcdf88f62b0 92 }
<> 128:9bcdf88f62b0 93 ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
<> 128:9bcdf88f62b0 94 * (FlashConfig)
<> 128:9bcdf88f62b0 95 }
<> 128:9bcdf88f62b0 96 ER_m_text m_text_start m_text_size { ; load address = execution address
<> 128:9bcdf88f62b0 97 * (InRoot$$Sections)
<> 128:9bcdf88f62b0 98 .ANY (+RO)
<> 128:9bcdf88f62b0 99 }
<> 128:9bcdf88f62b0 100
<> 128:9bcdf88f62b0 101 #if (defined(__ram_vector_table__))
<> 128:9bcdf88f62b0 102 VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
<> 128:9bcdf88f62b0 103 }
<> 128:9bcdf88f62b0 104 #else
<> 128:9bcdf88f62b0 105 VECTOR_RAM m_interrupts_start EMPTY 0 {
<> 128:9bcdf88f62b0 106 }
<> 128:9bcdf88f62b0 107 #endif
<> 128:9bcdf88f62b0 108 RW_m_data m_data_start m_data_size { ; RW data
<> 128:9bcdf88f62b0 109 .ANY (+RW +ZI)
<> 128:9bcdf88f62b0 110 }
<> 128:9bcdf88f62b0 111 RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data
<> 128:9bcdf88f62b0 112 .ANY (+RW +ZI)
<> 128:9bcdf88f62b0 113 }
<> 128:9bcdf88f62b0 114 RW_IRAM1 ImageLimit(RW_m_data_2) { ; Heap region growing up
<> 128:9bcdf88f62b0 115 }
<> 128:9bcdf88f62b0 116 }
<> 128:9bcdf88f62b0 117