mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_KW24D/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct@141:794e51388b66, 2017-04-28 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 28 13:09:19 2017 +0100
Revision:
141:794e51388b66
Parent:
128:9bcdf88f62b0
Child:
152:235179ab3f27
Release 141 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



4008: [NUC472/M453] Support Bootloader and FlashIAP https://github.com/ARMmbed/mbed-os/pull/4008

4102: Add SCL and SDA defs for I2C[0-2]; redefine I2C_[SCL,SDA] to I2C2 https://github.com/ARMmbed/mbed-os/pull/4102

4118: STM32F4 Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4118

4126: STM32F4 : remove SERIAL_TX and SERIAL_RX from available pins https://github.com/ARMmbed/mbed-os/pull/4126

4148: Revert "STM32F4 Internal ADC channels rework" https://github.com/ARMmbed/mbed-os/pull/4148

4152: STM32F4 Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4152

4074: [Silicon Labs] Update pinout https://github.com/ARMmbed/mbed-os/pull/4074

4133: U-BLOX_C030: Default XTAL is now 12MHz onboard. Option to use Debug 8MHz https://github.com/ARMmbed/mbed-os/pull/4133

4142: EFM32: Fixed `pwmout_all_inactive` being inversed https://github.com/ARMmbed/mbed-os/pull/4142

4016: [NRF5]: fix rtc overflow-while-set-timestamp issue https://github.com/ARMmbed/mbed-os/pull/4016

4031: STM32 increase IAR heap size for big RAM targets https://github.com/ARMmbed/mbed-os/pull/4031

4137: MCUXpresso: Update ARM linker files to eliminate reserving RAM for stack & heap https://github.com/ARMmbed/mbed-os/pull/4137

4176: STM32L4 Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4176

4154: STM32F7 Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4154

4174: [NRF52840]:  fix rtc overflow-while-set-timestamp issue https://github.com/ARMmbed/mbed-os/pull/4174

4180: [UBLOX_C030] create target hierarchy for the specific versions of the C030 board https://github.com/ARMmbed/mbed-os/pull/4180

4153: STM32F2: Internal ADC channels rework https://github.com/ARMmbed/mbed-os/pull/4153

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 #! armcc -E
<> 128:9bcdf88f62b0 2 /*
<> 128:9bcdf88f62b0 3 ** ###################################################################
<> 128:9bcdf88f62b0 4 ** Processor: MKW24D512VHA5
<> 128:9bcdf88f62b0 5 ** Compiler: Keil ARM C/C++ Compiler
<> 128:9bcdf88f62b0 6 ** Reference manual: MKW2xDRM Rev.2 July 2014
<> 128:9bcdf88f62b0 7 ** Version: rev. 2.0, 2014-11-26
<> 128:9bcdf88f62b0 8 ** Build: b160512
<> 128:9bcdf88f62b0 9 **
<> 128:9bcdf88f62b0 10 ** Abstract:
<> 128:9bcdf88f62b0 11 ** Linker file for the Keil ARM C/C++ Compiler
<> 128:9bcdf88f62b0 12 **
<> 128:9bcdf88f62b0 13 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
<> 128:9bcdf88f62b0 14 ** All rights reserved.
<> 128:9bcdf88f62b0 15 **
<> 128:9bcdf88f62b0 16 ** Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 17 ** are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 18 **
<> 128:9bcdf88f62b0 19 ** o Redistributions of source code must retain the above copyright notice, this list
<> 128:9bcdf88f62b0 20 ** of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 21 **
<> 128:9bcdf88f62b0 22 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 128:9bcdf88f62b0 23 ** list of conditions and the following disclaimer in the documentation and/or
<> 128:9bcdf88f62b0 24 ** other materials provided with the distribution.
<> 128:9bcdf88f62b0 25 **
<> 128:9bcdf88f62b0 26 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 128:9bcdf88f62b0 27 ** contributors may be used to endorse or promote products derived from this
<> 128:9bcdf88f62b0 28 ** software without specific prior written permission.
<> 128:9bcdf88f62b0 29 **
<> 128:9bcdf88f62b0 30 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 128:9bcdf88f62b0 31 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 128:9bcdf88f62b0 32 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 33 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 128:9bcdf88f62b0 34 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 128:9bcdf88f62b0 35 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 128:9bcdf88f62b0 36 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 128:9bcdf88f62b0 37 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 128:9bcdf88f62b0 38 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 128:9bcdf88f62b0 39 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 40 **
<> 128:9bcdf88f62b0 41 ** http: www.freescale.com
<> 128:9bcdf88f62b0 42 ** mail: support@freescale.com
<> 128:9bcdf88f62b0 43 **
<> 128:9bcdf88f62b0 44 ** ###################################################################
<> 128:9bcdf88f62b0 45 */
<> 128:9bcdf88f62b0 46 #define __ram_vector_table__ 1
<> 128:9bcdf88f62b0 47
<> 128:9bcdf88f62b0 48 #if (defined(__ram_vector_table__))
<> 128:9bcdf88f62b0 49 #define __ram_vector_table_size__ 0x00000400
<> 128:9bcdf88f62b0 50 #else
<> 128:9bcdf88f62b0 51 #define __ram_vector_table_size__ 0x00000000
<> 128:9bcdf88f62b0 52 #endif
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 #define m_interrupts_start 0x00000000
<> 128:9bcdf88f62b0 55 #define m_interrupts_size 0x00000400
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 #define m_flash_config_start 0x00000400
<> 128:9bcdf88f62b0 58 #define m_flash_config_size 0x00000010
<> 128:9bcdf88f62b0 59
<> 128:9bcdf88f62b0 60 #define m_text_start 0x00000410
<> 128:9bcdf88f62b0 61 #define m_text_size 0x0007FBF0
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 #define m_interrupts_ram_start 0x1FFF8000
<> 128:9bcdf88f62b0 64 #define m_interrupts_ram_size __ram_vector_table_size__
<> 128:9bcdf88f62b0 65
<> 128:9bcdf88f62b0 66 #define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
<> 128:9bcdf88f62b0 67 #define m_data_size (0x00008000 - m_interrupts_ram_size)
<> 128:9bcdf88f62b0 68
<> 128:9bcdf88f62b0 69 #define m_data_2_start 0x20000000
<> 128:9bcdf88f62b0 70 #define m_data_2_size 0x00008000
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 /* Sizes */
<> 128:9bcdf88f62b0 73 #if (defined(__stack_size__))
<> 128:9bcdf88f62b0 74 #define Stack_Size __stack_size__
<> 128:9bcdf88f62b0 75 #else
<> 128:9bcdf88f62b0 76 #define Stack_Size 0x0400
<> 128:9bcdf88f62b0 77 #endif
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 #if (defined(__heap_size__))
<> 128:9bcdf88f62b0 80 #define Heap_Size __heap_size__
<> 128:9bcdf88f62b0 81 #else
<> 128:9bcdf88f62b0 82 #define Heap_Size 0x0400
<> 128:9bcdf88f62b0 83 #endif
<> 128:9bcdf88f62b0 84
<> 128:9bcdf88f62b0 85 LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
<> 128:9bcdf88f62b0 86 VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
<> 128:9bcdf88f62b0 87 * (RESET,+FIRST)
<> 128:9bcdf88f62b0 88 }
<> 128:9bcdf88f62b0 89 ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
<> 128:9bcdf88f62b0 90 * (FlashConfig)
<> 128:9bcdf88f62b0 91 }
<> 128:9bcdf88f62b0 92 ER_m_text m_text_start m_text_size { ; load address = execution address
<> 128:9bcdf88f62b0 93 * (InRoot$$Sections)
<> 128:9bcdf88f62b0 94 .ANY (+RO)
<> 128:9bcdf88f62b0 95 }
<> 128:9bcdf88f62b0 96
<> 128:9bcdf88f62b0 97 #if (defined(__ram_vector_table__))
<> 128:9bcdf88f62b0 98 VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
<> 128:9bcdf88f62b0 99 }
<> 128:9bcdf88f62b0 100 #else
<> 128:9bcdf88f62b0 101 VECTOR_RAM m_interrupts_start EMPTY 0 {
<> 128:9bcdf88f62b0 102 }
<> 128:9bcdf88f62b0 103 #endif
<> 128:9bcdf88f62b0 104 RW_m_data m_data_start m_data_size { ; RW data
<> 128:9bcdf88f62b0 105 .ANY (+RW +ZI)
<> 128:9bcdf88f62b0 106 }
<> 128:9bcdf88f62b0 107 RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data
<> 128:9bcdf88f62b0 108 .ANY (+RW +ZI)
<> 128:9bcdf88f62b0 109 }
<> 128:9bcdf88f62b0 110 RW_IRAM1 ImageLimit(RW_m_data_2) { ; Heap region growing up
<> 128:9bcdf88f62b0 111 }
<> 128:9bcdf88f62b0 112 }
<> 128:9bcdf88f62b0 113