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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_tim.c
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	161:2cc1468da177	7	* @brief TIM LL module driver.
<>	161:2cc1468da177	8	******************************************************************************
<>	161:2cc1468da177	9	* @attention
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	12	*
<>	161:2cc1468da177	13	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	14	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	18	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	19	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	21	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	22	* without specific prior written permission.
<>	161:2cc1468da177	23	*
<>	161:2cc1468da177	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	34	*
<>	161:2cc1468da177	35	******************************************************************************
<>	161:2cc1468da177	36	*/
<>	161:2cc1468da177	37	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	38
<>	161:2cc1468da177	39	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	40	#include "stm32f7xx_ll_tim.h"
<>	161:2cc1468da177	41	#include "stm32f7xx_ll_bus.h"
<>	161:2cc1468da177	42
<>	161:2cc1468da177	43	#ifdef USE_FULL_ASSERT
<>	161:2cc1468da177	44	#include "stm32_assert.h"
<>	161:2cc1468da177	45	#else
<>	161:2cc1468da177	46	#define assert_param(expr) ((void)0U)
<>	161:2cc1468da177	47	#endif
<>	161:2cc1468da177	48
<>	161:2cc1468da177	49	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	50	* @{
<>	161:2cc1468da177	51	*/
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	#if defined (TIM1) \|\| defined (TIM8) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM6) \|\| defined (TIM7)
<>	161:2cc1468da177	54
<>	161:2cc1468da177	55	/** @addtogroup TIM_LL
<>	161:2cc1468da177	56	* @{
<>	161:2cc1468da177	57	*/
<>	161:2cc1468da177	58
<>	161:2cc1468da177	59	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	60	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	61	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	62	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	63	/** @addtogroup TIM_LL_Private_Macros
<>	161:2cc1468da177	64	* @{
<>	161:2cc1468da177	65	*/
<>	161:2cc1468da177	66	#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
<>	161:2cc1468da177	67	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
<>	161:2cc1468da177	68	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
<>	161:2cc1468da177	69	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
<>	161:2cc1468da177	70	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
<>	161:2cc1468da177	71
<>	161:2cc1468da177	72	#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
<>	161:2cc1468da177	73	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
<>	161:2cc1468da177	74	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
<>	161:2cc1468da177	75
<>	161:2cc1468da177	76	#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
<>	161:2cc1468da177	77	\|\| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
<>	161:2cc1468da177	78	\|\| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
<>	161:2cc1468da177	79	\|\| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
<>	161:2cc1468da177	80	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
<>	161:2cc1468da177	81	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
<>	161:2cc1468da177	82	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
<>	161:2cc1468da177	83	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
<>	161:2cc1468da177	84	\|\| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
<>	161:2cc1468da177	85	\|\| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
<>	161:2cc1468da177	86	\|\| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
<>	161:2cc1468da177	87	\|\| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
<>	161:2cc1468da177	88	\|\| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
<>	161:2cc1468da177	89	\|\| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
<>	161:2cc1468da177	90
<>	161:2cc1468da177	91	#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
<>	161:2cc1468da177	92	\|\| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
<>	161:2cc1468da177	93
<>	161:2cc1468da177	94	#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
<>	161:2cc1468da177	95	\|\| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
<>	161:2cc1468da177	96
<>	161:2cc1468da177	97	#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
<>	161:2cc1468da177	98	\|\| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
<>	161:2cc1468da177	99
<>	161:2cc1468da177	100	#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
<>	161:2cc1468da177	101	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
<>	161:2cc1468da177	102	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
<>	161:2cc1468da177	103
<>	161:2cc1468da177	104	#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
<>	161:2cc1468da177	105	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
<>	161:2cc1468da177	106	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
<>	161:2cc1468da177	107	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
<>	161:2cc1468da177	108
<>	161:2cc1468da177	109	#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
<>	161:2cc1468da177	110	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
<>	161:2cc1468da177	111	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
<>	161:2cc1468da177	112	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
<>	161:2cc1468da177	113	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
<>	161:2cc1468da177	114	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
<>	161:2cc1468da177	115	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
<>	161:2cc1468da177	116	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
<>	161:2cc1468da177	117	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
<>	161:2cc1468da177	118	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
<>	161:2cc1468da177	119	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
<>	161:2cc1468da177	120	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
<>	161:2cc1468da177	121	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
<>	161:2cc1468da177	122	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
<>	161:2cc1468da177	123	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
<>	161:2cc1468da177	124	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
<>	161:2cc1468da177	125
<>	161:2cc1468da177	126	#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
<>	161:2cc1468da177	127	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
<>	161:2cc1468da177	128	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
<>	161:2cc1468da177	129
<>	161:2cc1468da177	130	#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
<>	161:2cc1468da177	131	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
<>	161:2cc1468da177	132	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
<>	161:2cc1468da177	133
<>	161:2cc1468da177	134	#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
<>	161:2cc1468da177	135	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
<>	161:2cc1468da177	136
<>	161:2cc1468da177	137	#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
<>	161:2cc1468da177	138	\|\| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
<>	161:2cc1468da177	139
<>	161:2cc1468da177	140	#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
<>	161:2cc1468da177	141	\|\| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
<>	161:2cc1468da177	142
<>	161:2cc1468da177	143	#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
<>	161:2cc1468da177	144	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
<>	161:2cc1468da177	145	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
<>	161:2cc1468da177	146	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
<>	161:2cc1468da177	147
<>	161:2cc1468da177	148	#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
<>	161:2cc1468da177	149	\|\| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
<>	161:2cc1468da177	150
<>	161:2cc1468da177	151	#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
<>	161:2cc1468da177	152	\|\| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
<>	161:2cc1468da177	153
<>	161:2cc1468da177	154	#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
<>	161:2cc1468da177	155	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
<>	161:2cc1468da177	156	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
<>	161:2cc1468da177	157	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
<>	161:2cc1468da177	158	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
<>	161:2cc1468da177	159	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
<>	161:2cc1468da177	160	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
<>	161:2cc1468da177	161	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
<>	161:2cc1468da177	162	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
<>	161:2cc1468da177	163	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
<>	161:2cc1468da177	164	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
<>	161:2cc1468da177	165	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
<>	161:2cc1468da177	166	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
<>	161:2cc1468da177	167	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
<>	161:2cc1468da177	168	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
<>	161:2cc1468da177	169	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
<>	161:2cc1468da177	170
<>	161:2cc1468da177	171	#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
<>	161:2cc1468da177	172	\|\| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
<>	161:2cc1468da177	173
<>	161:2cc1468da177	174	#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
<>	161:2cc1468da177	175	\|\| ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
<>	161:2cc1468da177	176
<>	161:2cc1468da177	177	#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
<>	161:2cc1468da177	178	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
<>	161:2cc1468da177	179	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
<>	161:2cc1468da177	180	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
<>	161:2cc1468da177	181	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
<>	161:2cc1468da177	182	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
<>	161:2cc1468da177	183	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
<>	161:2cc1468da177	184	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
<>	161:2cc1468da177	185	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
<>	161:2cc1468da177	186	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
<>	161:2cc1468da177	187	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
<>	161:2cc1468da177	188	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
<>	161:2cc1468da177	189	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
<>	161:2cc1468da177	190	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
<>	161:2cc1468da177	191	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
<>	161:2cc1468da177	192	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
<>	161:2cc1468da177	193
<>	161:2cc1468da177	194	#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
<>	161:2cc1468da177	195	\|\| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
<>	161:2cc1468da177	196	/**
<>	161:2cc1468da177	197	* @}
<>	161:2cc1468da177	198	*/
<>	161:2cc1468da177	199
<>	161:2cc1468da177	200
<>	161:2cc1468da177	201	/* Private function prototypes -----------------------------------------------*/
<>	161:2cc1468da177	202	/** @defgroup TIM_LL_Private_Functions TIM Private Functions
<>	161:2cc1468da177	203	* @{
<>	161:2cc1468da177	204	*/
<>	161:2cc1468da177	205	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	206	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	207	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	208	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	209	static ErrorStatus OC5Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	210	static ErrorStatus OC6Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	211	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	161:2cc1468da177	212	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	161:2cc1468da177	213	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	161:2cc1468da177	214	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	161:2cc1468da177	215	/**
<>	161:2cc1468da177	216	* @}
<>	161:2cc1468da177	217	*/
<>	161:2cc1468da177	218
<>	161:2cc1468da177	219	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	220	/** @addtogroup TIM_LL_Exported_Functions
<>	161:2cc1468da177	221	* @{
<>	161:2cc1468da177	222	*/
<>	161:2cc1468da177	223
<>	161:2cc1468da177	224	/** @addtogroup TIM_LL_EF_Init
<>	161:2cc1468da177	225	* @{
<>	161:2cc1468da177	226	*/
<>	161:2cc1468da177	227
<>	161:2cc1468da177	228	/**
<>	161:2cc1468da177	229	* @brief Set TIMx registers to their reset values.
<>	161:2cc1468da177	230	* @param TIMx Timer instance
<>	161:2cc1468da177	231	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	232	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	233	* - ERROR: invalid TIMx instance
<>	161:2cc1468da177	234	*/
<>	161:2cc1468da177	235	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	236	{
<>	161:2cc1468da177	237	ErrorStatus result = SUCCESS;
<>	161:2cc1468da177	238
<>	161:2cc1468da177	239	/* Check the parameters */
<>	161:2cc1468da177	240	assert_param(IS_TIM_INSTANCE(TIMx));
<>	161:2cc1468da177	241
<>	161:2cc1468da177	242	if (TIMx == TIM1)
<>	161:2cc1468da177	243	{
<>	161:2cc1468da177	244	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
<>	161:2cc1468da177	245	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
<>	161:2cc1468da177	246	}
<>	161:2cc1468da177	247	else if (TIMx == TIM2)
<>	161:2cc1468da177	248	{
<>	161:2cc1468da177	249	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
<>	161:2cc1468da177	250	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
<>	161:2cc1468da177	251	}
<>	161:2cc1468da177	252	#if defined(TIM3)
<>	161:2cc1468da177	253	else if (TIMx == TIM3)
<>	161:2cc1468da177	254	{
<>	161:2cc1468da177	255	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
<>	161:2cc1468da177	256	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
<>	161:2cc1468da177	257	}
<>	161:2cc1468da177	258	#endif
<>	161:2cc1468da177	259	#if defined(TIM4)
<>	161:2cc1468da177	260	else if (TIMx == TIM4)
<>	161:2cc1468da177	261	{
<>	161:2cc1468da177	262	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
<>	161:2cc1468da177	263	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
<>	161:2cc1468da177	264	}
<>	161:2cc1468da177	265	#endif
<>	161:2cc1468da177	266	#if defined(TIM5)
<>	161:2cc1468da177	267	else if (TIMx == TIM5)
<>	161:2cc1468da177	268	{
<>	161:2cc1468da177	269	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
<>	161:2cc1468da177	270	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
<>	161:2cc1468da177	271	}
<>	161:2cc1468da177	272	#endif
<>	161:2cc1468da177	273	#if defined(TIM6)
<>	161:2cc1468da177	274	else if (TIMx == TIM6)
<>	161:2cc1468da177	275	{
<>	161:2cc1468da177	276	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
<>	161:2cc1468da177	277	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
<>	161:2cc1468da177	278	}
<>	161:2cc1468da177	279	#endif
<>	161:2cc1468da177	280	#if defined (TIM7)
<>	161:2cc1468da177	281	else if (TIMx == TIM7)
<>	161:2cc1468da177	282	{
<>	161:2cc1468da177	283	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
<>	161:2cc1468da177	284	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
<>	161:2cc1468da177	285	}
<>	161:2cc1468da177	286	#endif
<>	161:2cc1468da177	287	#if defined(TIM8)
<>	161:2cc1468da177	288	else if (TIMx == TIM8)
<>	161:2cc1468da177	289	{
<>	161:2cc1468da177	290	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
<>	161:2cc1468da177	291	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
<>	161:2cc1468da177	292	}
<>	161:2cc1468da177	293	#endif
<>	161:2cc1468da177	294	#if defined(TIM9)
<>	161:2cc1468da177	295	else if (TIMx == TIM9)
<>	161:2cc1468da177	296	{
<>	161:2cc1468da177	297	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
<>	161:2cc1468da177	298	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
<>	161:2cc1468da177	299	}
<>	161:2cc1468da177	300	#endif
<>	161:2cc1468da177	301	#if defined(TIM10)
<>	161:2cc1468da177	302	else if (TIMx == TIM10)
<>	161:2cc1468da177	303	{
<>	161:2cc1468da177	304	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
<>	161:2cc1468da177	305	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
<>	161:2cc1468da177	306	}
<>	161:2cc1468da177	307	#endif
<>	161:2cc1468da177	308	#if defined(TIM11)
<>	161:2cc1468da177	309	else if (TIMx == TIM11)
<>	161:2cc1468da177	310	{
<>	161:2cc1468da177	311	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
<>	161:2cc1468da177	312	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
<>	161:2cc1468da177	313	}
<>	161:2cc1468da177	314	#endif
<>	161:2cc1468da177	315	#if defined(TIM12)
<>	161:2cc1468da177	316	else if (TIMx == TIM12)
<>	161:2cc1468da177	317	{
<>	161:2cc1468da177	318	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
<>	161:2cc1468da177	319	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
<>	161:2cc1468da177	320	}
<>	161:2cc1468da177	321	#endif
<>	161:2cc1468da177	322	#if defined(TIM13)
<>	161:2cc1468da177	323	else if (TIMx == TIM13)
<>	161:2cc1468da177	324	{
<>	161:2cc1468da177	325	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
<>	161:2cc1468da177	326	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
<>	161:2cc1468da177	327	}
<>	161:2cc1468da177	328	#endif
<>	161:2cc1468da177	329	#if defined(TIM14)
<>	161:2cc1468da177	330	else if (TIMx == TIM14)
<>	161:2cc1468da177	331	{
<>	161:2cc1468da177	332	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
<>	161:2cc1468da177	333	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
<>	161:2cc1468da177	334	}
<>	161:2cc1468da177	335	#endif
<>	161:2cc1468da177	336	else
<>	161:2cc1468da177	337	{
<>	161:2cc1468da177	338	result = ERROR;
<>	161:2cc1468da177	339	}
<>	161:2cc1468da177	340
<>	161:2cc1468da177	341	return result;
<>	161:2cc1468da177	342	}
<>	161:2cc1468da177	343
<>	161:2cc1468da177	344	/**
<>	161:2cc1468da177	345	* @brief Set the fields of the time base unit configuration data structure
<>	161:2cc1468da177	346	* to their default values.
<>	161:2cc1468da177	347	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
<>	161:2cc1468da177	348	* @retval None
<>	161:2cc1468da177	349	*/
<>	161:2cc1468da177	350	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
<>	161:2cc1468da177	351	{
<>	161:2cc1468da177	352	/* Set the default configuration */
<>	161:2cc1468da177	353	TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
<>	161:2cc1468da177	354	TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
<>	161:2cc1468da177	355	TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
<>	161:2cc1468da177	356	TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
<>	161:2cc1468da177	357	TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
<>	161:2cc1468da177	358	}
<>	161:2cc1468da177	359
<>	161:2cc1468da177	360	/**
<>	161:2cc1468da177	361	* @brief Configure the TIMx time base unit.
<>	161:2cc1468da177	362	* @param TIMx Timer Instance
<>	161:2cc1468da177	363	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
<>	161:2cc1468da177	364	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	365	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	366	* - ERROR: not applicable
<>	161:2cc1468da177	367	*/
<>	161:2cc1468da177	368	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct)
<>	161:2cc1468da177	369	{
<>	161:2cc1468da177	370	uint32_t tmpcr1 = 0U;
<>	161:2cc1468da177	371
<>	161:2cc1468da177	372	/* Check the parameters */
<>	161:2cc1468da177	373	assert_param(IS_TIM_INSTANCE(TIMx));
<>	161:2cc1468da177	374	assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
<>	161:2cc1468da177	375	assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
<>	161:2cc1468da177	376
<>	161:2cc1468da177	377	tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
<>	161:2cc1468da177	378
<>	161:2cc1468da177	379	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<>	161:2cc1468da177	380	{
<>	161:2cc1468da177	381	/* Select the Counter Mode */
<>	161:2cc1468da177	382	MODIFY_REG(tmpcr1, (TIM_CR1_DIR \| TIM_CR1_CMS), TIM_InitStruct->CounterMode);
<>	161:2cc1468da177	383	}
<>	161:2cc1468da177	384
<>	161:2cc1468da177	385	if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<>	161:2cc1468da177	386	{
<>	161:2cc1468da177	387	/* Set the clock division */
<>	161:2cc1468da177	388	MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
<>	161:2cc1468da177	389	}
<>	161:2cc1468da177	390
<>	161:2cc1468da177	391	/* Write to TIMx CR1 */
<>	161:2cc1468da177	392	LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
<>	161:2cc1468da177	393
<>	161:2cc1468da177	394	/* Set the Autoreload value */
<>	161:2cc1468da177	395	LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
<>	161:2cc1468da177	396
<>	161:2cc1468da177	397	/* Set the Prescaler value */
<>	161:2cc1468da177	398	LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
<>	161:2cc1468da177	399
<>	161:2cc1468da177	400	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<>	161:2cc1468da177	401	{
<>	161:2cc1468da177	402	/* Set the Repetition Counter value */
<>	161:2cc1468da177	403	LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
<>	161:2cc1468da177	404	}
<>	161:2cc1468da177	405
<>	161:2cc1468da177	406	/* Generate an update event to reload the Prescaler
<>	161:2cc1468da177	407	and the repetition counter value (if applicable) immediately */
<>	161:2cc1468da177	408	LL_TIM_GenerateEvent_UPDATE(TIMx);
<>	161:2cc1468da177	409
<>	161:2cc1468da177	410	return SUCCESS;
<>	161:2cc1468da177	411	}
<>	161:2cc1468da177	412
<>	161:2cc1468da177	413	/**
<>	161:2cc1468da177	414	* @brief Set the fields of the TIMx output channel configuration data
<>	161:2cc1468da177	415	* structure to their default values.
<>	161:2cc1468da177	416	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
<>	161:2cc1468da177	417	* @retval None
<>	161:2cc1468da177	418	*/
<>	161:2cc1468da177	419	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
<>	161:2cc1468da177	420	{
<>	161:2cc1468da177	421	/* Set the default configuration */
<>	161:2cc1468da177	422	TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
<>	161:2cc1468da177	423	TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
<>	161:2cc1468da177	424	TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
<>	161:2cc1468da177	425	TIM_OC_InitStruct->CompareValue = 0x00000000U;
<>	161:2cc1468da177	426	TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
<>	161:2cc1468da177	427	TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
<>	161:2cc1468da177	428	TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
<>	161:2cc1468da177	429	TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
<>	161:2cc1468da177	430	}
<>	161:2cc1468da177	431
<>	161:2cc1468da177	432	/**
<>	161:2cc1468da177	433	* @brief Configure the TIMx output channel.
<>	161:2cc1468da177	434	* @param TIMx Timer Instance
<>	161:2cc1468da177	435	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	436	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	437	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	438	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	439	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	440	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	441	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	442	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
<>	161:2cc1468da177	443	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	444	* - SUCCESS: TIMx output channel is initialized
<>	161:2cc1468da177	445	* - ERROR: TIMx output channel is not initialized
<>	161:2cc1468da177	446	*/
<>	161:2cc1468da177	447	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct)
<>	161:2cc1468da177	448	{
<>	161:2cc1468da177	449	ErrorStatus result = ERROR;
<>	161:2cc1468da177	450
<>	161:2cc1468da177	451	switch (Channel)
<>	161:2cc1468da177	452	{
<>	161:2cc1468da177	453	case LL_TIM_CHANNEL_CH1:
<>	161:2cc1468da177	454	result = OC1Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	455	break;
<>	161:2cc1468da177	456	case LL_TIM_CHANNEL_CH2:
<>	161:2cc1468da177	457	result = OC2Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	458	break;
<>	161:2cc1468da177	459	case LL_TIM_CHANNEL_CH3:
<>	161:2cc1468da177	460	result = OC3Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	461	break;
<>	161:2cc1468da177	462	case LL_TIM_CHANNEL_CH4:
<>	161:2cc1468da177	463	result = OC4Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	464	break;
<>	161:2cc1468da177	465	case LL_TIM_CHANNEL_CH5:
<>	161:2cc1468da177	466	result = OC5Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	467	break;
<>	161:2cc1468da177	468	case LL_TIM_CHANNEL_CH6:
<>	161:2cc1468da177	469	result = OC6Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	470	break;
<>	161:2cc1468da177	471	default:
<>	161:2cc1468da177	472	break;
<>	161:2cc1468da177	473	}
<>	161:2cc1468da177	474
<>	161:2cc1468da177	475	return result;
<>	161:2cc1468da177	476	}
<>	161:2cc1468da177	477
<>	161:2cc1468da177	478	/**
<>	161:2cc1468da177	479	* @brief Set the fields of the TIMx input channel configuration data
<>	161:2cc1468da177	480	* structure to their default values.
<>	161:2cc1468da177	481	* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
<>	161:2cc1468da177	482	* @retval None
<>	161:2cc1468da177	483	*/
<>	161:2cc1468da177	484	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
<>	161:2cc1468da177	485	{
<>	161:2cc1468da177	486	/* Set the default configuration */
<>	161:2cc1468da177	487	TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
<>	161:2cc1468da177	488	TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	161:2cc1468da177	489	TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
<>	161:2cc1468da177	490	TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
<>	161:2cc1468da177	491	}
<>	161:2cc1468da177	492
<>	161:2cc1468da177	493	/**
<>	161:2cc1468da177	494	* @brief Configure the TIMx input channel.
<>	161:2cc1468da177	495	* @param TIMx Timer Instance
<>	161:2cc1468da177	496	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	497	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	498	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	499	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	500	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	501	* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
<>	161:2cc1468da177	502	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	503	* - SUCCESS: TIMx output channel is initialized
<>	161:2cc1468da177	504	* - ERROR: TIMx output channel is not initialized
<>	161:2cc1468da177	505	*/
<>	161:2cc1468da177	506	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct)
<>	161:2cc1468da177	507	{
<>	161:2cc1468da177	508	ErrorStatus result = ERROR;
<>	161:2cc1468da177	509
<>	161:2cc1468da177	510	switch (Channel)
<>	161:2cc1468da177	511	{
<>	161:2cc1468da177	512	case LL_TIM_CHANNEL_CH1:
<>	161:2cc1468da177	513	result = IC1Config(TIMx, TIM_IC_InitStruct);
<>	161:2cc1468da177	514	break;
<>	161:2cc1468da177	515	case LL_TIM_CHANNEL_CH2:
<>	161:2cc1468da177	516	result = IC2Config(TIMx, TIM_IC_InitStruct);
<>	161:2cc1468da177	517	break;
<>	161:2cc1468da177	518	case LL_TIM_CHANNEL_CH3:
<>	161:2cc1468da177	519	result = IC3Config(TIMx, TIM_IC_InitStruct);
<>	161:2cc1468da177	520	break;
<>	161:2cc1468da177	521	case LL_TIM_CHANNEL_CH4:
<>	161:2cc1468da177	522	result = IC4Config(TIMx, TIM_IC_InitStruct);
<>	161:2cc1468da177	523	break;
<>	161:2cc1468da177	524	default:
<>	161:2cc1468da177	525	break;
<>	161:2cc1468da177	526	}
<>	161:2cc1468da177	527
<>	161:2cc1468da177	528	return result;
<>	161:2cc1468da177	529	}
<>	161:2cc1468da177	530
<>	161:2cc1468da177	531	/**
<>	161:2cc1468da177	532	* @brief Fills each TIM_EncoderInitStruct field with its default value
<>	161:2cc1468da177	533	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
<>	161:2cc1468da177	534	* @retval None
<>	161:2cc1468da177	535	*/
<>	161:2cc1468da177	536	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
<>	161:2cc1468da177	537	{
<>	161:2cc1468da177	538	/* Set the default configuration */
<>	161:2cc1468da177	539	TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
<>	161:2cc1468da177	540	TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
<>	161:2cc1468da177	541	TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	161:2cc1468da177	542	TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
<>	161:2cc1468da177	543	TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
<>	161:2cc1468da177	544	TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
<>	161:2cc1468da177	545	TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	161:2cc1468da177	546	TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
<>	161:2cc1468da177	547	TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
<>	161:2cc1468da177	548	}
<>	161:2cc1468da177	549
<>	161:2cc1468da177	550	/**
<>	161:2cc1468da177	551	* @brief Configure the encoder interface of the timer instance.
<>	161:2cc1468da177	552	* @param TIMx Timer Instance
<>	161:2cc1468da177	553	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
<>	161:2cc1468da177	554	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	555	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	556	* - ERROR: not applicable
<>	161:2cc1468da177	557	*/
<>	161:2cc1468da177	558	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct)
<>	161:2cc1468da177	559	{
<>	161:2cc1468da177	560	uint32_t tmpccmr1 = 0U;
<>	161:2cc1468da177	561	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	562
<>	161:2cc1468da177	563	/* Check the parameters */
<>	161:2cc1468da177	564	assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
<>	161:2cc1468da177	565	assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
<>	161:2cc1468da177	566	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
<>	161:2cc1468da177	567	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
<>	161:2cc1468da177	568	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
<>	161:2cc1468da177	569	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
<>	161:2cc1468da177	570	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
<>	161:2cc1468da177	571	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
<>	161:2cc1468da177	572	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
<>	161:2cc1468da177	573	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
<>	161:2cc1468da177	574
<>	161:2cc1468da177	575	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
<>	161:2cc1468da177	576	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	161:2cc1468da177	577
<>	161:2cc1468da177	578	/* Get the TIMx CCMR1 register value */
<>	161:2cc1468da177	579	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	161:2cc1468da177	580
<>	161:2cc1468da177	581	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	582	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	583
<>	161:2cc1468da177	584	/* Configure TI1 */
<>	161:2cc1468da177	585	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
<>	161:2cc1468da177	586	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
<>	161:2cc1468da177	587	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
<>	161:2cc1468da177	588	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
<>	161:2cc1468da177	589
<>	161:2cc1468da177	590	/* Configure TI2 */
<>	161:2cc1468da177	591	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC);
<>	161:2cc1468da177	592	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
<>	161:2cc1468da177	593	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
<>	161:2cc1468da177	594	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
<>	161:2cc1468da177	595
<>	161:2cc1468da177	596	/* Set TI1 and TI2 polarity and enable TI1 and TI2 */
<>	161:2cc1468da177	597	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	161:2cc1468da177	598	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
<>	161:2cc1468da177	599	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
<>	161:2cc1468da177	600	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	161:2cc1468da177	601
<>	161:2cc1468da177	602	/* Set encoder mode */
<>	161:2cc1468da177	603	LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
<>	161:2cc1468da177	604
<>	161:2cc1468da177	605	/* Write to TIMx CCMR1 */
<>	161:2cc1468da177	606	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	161:2cc1468da177	607
<>	161:2cc1468da177	608	/* Write to TIMx CCER */
<>	161:2cc1468da177	609	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	610
<>	161:2cc1468da177	611	return SUCCESS;
<>	161:2cc1468da177	612	}
<>	161:2cc1468da177	613
<>	161:2cc1468da177	614	/**
<>	161:2cc1468da177	615	* @brief Set the fields of the TIMx Hall sensor interface configuration data
<>	161:2cc1468da177	616	* structure to their default values.
<>	161:2cc1468da177	617	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
<>	161:2cc1468da177	618	* @retval None
<>	161:2cc1468da177	619	*/
<>	161:2cc1468da177	620	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
<>	161:2cc1468da177	621	{
<>	161:2cc1468da177	622	/* Set the default configuration */
<>	161:2cc1468da177	623	TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
<>	161:2cc1468da177	624	TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
<>	161:2cc1468da177	625	TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
<>	161:2cc1468da177	626	TIM_HallSensorInitStruct->CommutationDelay = 0U;
<>	161:2cc1468da177	627	}
<>	161:2cc1468da177	628
<>	161:2cc1468da177	629	/**
<>	161:2cc1468da177	630	* @brief Configure the Hall sensor interface of the timer instance.
<>	161:2cc1468da177	631	* @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
<>	161:2cc1468da177	632	* to the TI1 input channel
<>	161:2cc1468da177	633	* @note TIMx slave mode controller is configured in reset mode.
<>	161:2cc1468da177	634	Selected internal trigger is TI1F_ED.
<>	161:2cc1468da177	635	* @note Channel 1 is configured as input, IC1 is mapped on TRC.
<>	161:2cc1468da177	636	* @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
<>	161:2cc1468da177	637	* between 2 changes on the inputs. It gives information about motor speed.
<>	161:2cc1468da177	638	* @note Channel 2 is configured in output PWM 2 mode.
<>	161:2cc1468da177	639	* @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
<>	161:2cc1468da177	640	* @note OC2REF is selected as trigger output on TRGO.
<>	161:2cc1468da177	641	* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
<>	161:2cc1468da177	642	* when TIMx operates in Hall sensor interface mode.
<>	161:2cc1468da177	643	* @param TIMx Timer Instance
<>	161:2cc1468da177	644	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
<>	161:2cc1468da177	645	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	646	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	647	* - ERROR: not applicable
<>	161:2cc1468da177	648	*/
<>	161:2cc1468da177	649	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct)
<>	161:2cc1468da177	650	{
<>	161:2cc1468da177	651	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	652	uint32_t tmpccmr1 = 0U;
<>	161:2cc1468da177	653	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	654	uint32_t tmpsmcr = 0U;
<>	161:2cc1468da177	655
<>	161:2cc1468da177	656	/* Check the parameters */
<>	161:2cc1468da177	657	assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
<>	161:2cc1468da177	658	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
<>	161:2cc1468da177	659	assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
<>	161:2cc1468da177	660	assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
<>	161:2cc1468da177	661
<>	161:2cc1468da177	662	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
<>	161:2cc1468da177	663	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	161:2cc1468da177	664
<>	161:2cc1468da177	665	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	666	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	667
<>	161:2cc1468da177	668	/* Get the TIMx CCMR1 register value */
<>	161:2cc1468da177	669	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	161:2cc1468da177	670
<>	161:2cc1468da177	671	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	672	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	673
<>	161:2cc1468da177	674	/* Get the TIMx SMCR register value */
<>	161:2cc1468da177	675	tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
<>	161:2cc1468da177	676
<>	161:2cc1468da177	677	/* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
<>	161:2cc1468da177	678	tmpcr2 \|= TIM_CR2_TI1S;
<>	161:2cc1468da177	679
<>	161:2cc1468da177	680	/* OC2REF signal is used as trigger output (TRGO) */
<>	161:2cc1468da177	681	tmpcr2 \|= LL_TIM_TRGO_OC2REF;
<>	161:2cc1468da177	682
<>	161:2cc1468da177	683	/* Configure the slave mode controller */
<>	161:2cc1468da177	684	tmpsmcr &= (uint32_t)~(TIM_SMCR_TS \| TIM_SMCR_SMS);
<>	161:2cc1468da177	685	tmpsmcr \|= LL_TIM_TS_TI1F_ED;
<>	161:2cc1468da177	686	tmpsmcr \|= LL_TIM_SLAVEMODE_RESET;
<>	161:2cc1468da177	687
<>	161:2cc1468da177	688	/* Configure input channel 1 */
<>	161:2cc1468da177	689	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
<>	161:2cc1468da177	690	tmpccmr1 \|= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
<>	161:2cc1468da177	691	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
<>	161:2cc1468da177	692	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
<>	161:2cc1468da177	693
<>	161:2cc1468da177	694	/* Configure input channel 2 */
<>	161:2cc1468da177	695	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M \| TIM_CCMR1_OC2FE \| TIM_CCMR1_OC2PE \| TIM_CCMR1_OC2CE);
<>	161:2cc1468da177	696	tmpccmr1 \|= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
<>	161:2cc1468da177	697
<>	161:2cc1468da177	698	/* Set Channel 1 polarity and enable Channel 1 and Channel2 */
<>	161:2cc1468da177	699	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	161:2cc1468da177	700	tmpccer \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
<>	161:2cc1468da177	701	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	161:2cc1468da177	702
<>	161:2cc1468da177	703	/* Write to TIMx CR2 */
<>	161:2cc1468da177	704	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	705
<>	161:2cc1468da177	706	/* Write to TIMx SMCR */
<>	161:2cc1468da177	707	LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
<>	161:2cc1468da177	708
<>	161:2cc1468da177	709	/* Write to TIMx CCMR1 */
<>	161:2cc1468da177	710	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	161:2cc1468da177	711
<>	161:2cc1468da177	712	/* Write to TIMx CCER */
<>	161:2cc1468da177	713	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	714
<>	161:2cc1468da177	715	/* Write to TIMx CCR2 */
<>	161:2cc1468da177	716	LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
<>	161:2cc1468da177	717
<>	161:2cc1468da177	718	return SUCCESS;
<>	161:2cc1468da177	719	}
<>	161:2cc1468da177	720
<>	161:2cc1468da177	721	/**
<>	161:2cc1468da177	722	* @brief Set the fields of the Break and Dead Time configuration data structure
<>	161:2cc1468da177	723	* to their default values.
<>	161:2cc1468da177	724	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
<>	161:2cc1468da177	725	* @retval None
<>	161:2cc1468da177	726	*/
<>	161:2cc1468da177	727	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
<>	161:2cc1468da177	728	{
<>	161:2cc1468da177	729	/* Set the default configuration */
<>	161:2cc1468da177	730	TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
<>	161:2cc1468da177	731	TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
<>	161:2cc1468da177	732	TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
<>	161:2cc1468da177	733	TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
<>	161:2cc1468da177	734	TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
<>	161:2cc1468da177	735	TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
<>	161:2cc1468da177	736	TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
<>	161:2cc1468da177	737	TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
<>	161:2cc1468da177	738	TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
<>	161:2cc1468da177	739	TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
<>	161:2cc1468da177	740	TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
<>	161:2cc1468da177	741	}
<>	161:2cc1468da177	742
<>	161:2cc1468da177	743	/**
<>	161:2cc1468da177	744	* @brief Configure the Break and Dead Time feature of the timer instance.
<>	161:2cc1468da177	745	* @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
<>	161:2cc1468da177	746	* and DTG[7:0] can be write-locked depending on the LOCK configuration, it
<>	161:2cc1468da177	747	* can be necessary to configure all of them during the first write access to
<>	161:2cc1468da177	748	* the TIMx_BDTR register.
<>	161:2cc1468da177	749	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	750	* a timer instance provides a break input.
<>	161:2cc1468da177	751	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	752	* a timer instance provides a second break input.
<>	161:2cc1468da177	753	* @param TIMx Timer Instance
<>	161:2cc1468da177	754	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
<>	161:2cc1468da177	755	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	756	* - SUCCESS: Break and Dead Time is initialized
<>	161:2cc1468da177	757	* - ERROR: not applicable
<>	161:2cc1468da177	758	*/
<>	161:2cc1468da177	759	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct)
<>	161:2cc1468da177	760	{
<>	161:2cc1468da177	761	uint32_t tmpbdtr = 0;
<>	161:2cc1468da177	762
<>	161:2cc1468da177	763	/* Check the parameters */
<>	161:2cc1468da177	764	assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
<>	161:2cc1468da177	765	assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
<>	161:2cc1468da177	766	assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
<>	161:2cc1468da177	767	assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
<>	161:2cc1468da177	768	assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
<>	161:2cc1468da177	769	assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
<>	161:2cc1468da177	770	assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
<>	161:2cc1468da177	771
<>	161:2cc1468da177	772	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<>	161:2cc1468da177	773	the OSSI State, the dead time value and the Automatic Output Enable Bit */
<>	161:2cc1468da177	774
<>	161:2cc1468da177	775	/* Set the BDTR bits */
<>	161:2cc1468da177	776	MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
<>	161:2cc1468da177	777	MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
<>	161:2cc1468da177	778	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
<>	161:2cc1468da177	779	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
<>	161:2cc1468da177	780	MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
<>	161:2cc1468da177	781	MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
<>	161:2cc1468da177	782	MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
<>	161:2cc1468da177	783	MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
<>	161:2cc1468da177	784	if (IS_TIM_ADVANCED_INSTANCE(TIMx))
<>	161:2cc1468da177	785	{
<>	161:2cc1468da177	786	assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
<>	161:2cc1468da177	787	MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
<>	161:2cc1468da177	788	}
<>	161:2cc1468da177	789
<>	161:2cc1468da177	790	if (IS_TIM_BKIN2_INSTANCE(TIMx))
<>	161:2cc1468da177	791	{
<>	161:2cc1468da177	792	assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
<>	161:2cc1468da177	793	assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
<>	161:2cc1468da177	794	assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
<>	161:2cc1468da177	795
<>	161:2cc1468da177	796	/* Set the BREAK2 input related BDTR bit-fields */
<>	161:2cc1468da177	797	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
<>	161:2cc1468da177	798	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
<>	161:2cc1468da177	799	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
<>	161:2cc1468da177	800	}
<>	161:2cc1468da177	801
<>	161:2cc1468da177	802	/* Set TIMx_BDTR */
<>	161:2cc1468da177	803	LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
<>	161:2cc1468da177	804
<>	161:2cc1468da177	805	return SUCCESS;
<>	161:2cc1468da177	806	}
<>	161:2cc1468da177	807	/**
<>	161:2cc1468da177	808	* @}
<>	161:2cc1468da177	809	*/
<>	161:2cc1468da177	810
<>	161:2cc1468da177	811	/**
<>	161:2cc1468da177	812	* @}
<>	161:2cc1468da177	813	*/
<>	161:2cc1468da177	814
<>	161:2cc1468da177	815	/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
<>	161:2cc1468da177	816	* @brief Private functions
<>	161:2cc1468da177	817	* @{
<>	161:2cc1468da177	818	*/
<>	161:2cc1468da177	819	/**
<>	161:2cc1468da177	820	* @brief Configure the TIMx output channel 1.
<>	161:2cc1468da177	821	* @param TIMx Timer Instance
<>	161:2cc1468da177	822	* @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
<>	161:2cc1468da177	823	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	824	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	825	* - ERROR: not applicable
<>	161:2cc1468da177	826	*/
<>	161:2cc1468da177	827	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	828	{
<>	161:2cc1468da177	829	uint32_t tmpccmr1 = 0U;
<>	161:2cc1468da177	830	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	831	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	832
<>	161:2cc1468da177	833	/* Check the parameters */
<>	161:2cc1468da177	834	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	161:2cc1468da177	835	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	836	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	837	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	838	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	839	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	840
<>	161:2cc1468da177	841	/* Disable the Channel 1: Reset the CC1E Bit */
<>	161:2cc1468da177	842	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
<>	161:2cc1468da177	843
<>	161:2cc1468da177	844	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	845	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	846
<>	161:2cc1468da177	847	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	848	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	849
<>	161:2cc1468da177	850	/* Get the TIMx CCMR1 register value */
<>	161:2cc1468da177	851	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	161:2cc1468da177	852
<>	161:2cc1468da177	853	/* Reset Capture/Compare selection Bits */
<>	161:2cc1468da177	854	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
<>	161:2cc1468da177	855
<>	161:2cc1468da177	856	/* Set the Output Compare Mode */
<>	161:2cc1468da177	857	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
<>	161:2cc1468da177	858
<>	161:2cc1468da177	859	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	860	MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
<>	161:2cc1468da177	861
<>	161:2cc1468da177	862	/* Set the Output State */
<>	161:2cc1468da177	863	MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
<>	161:2cc1468da177	864
<>	161:2cc1468da177	865	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	866	{
<>	161:2cc1468da177	867	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	868	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	869
<>	161:2cc1468da177	870	/* Set the complementary output Polarity */
<>	161:2cc1468da177	871	MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
<>	161:2cc1468da177	872
<>	161:2cc1468da177	873	/* Set the complementary output State */
<>	161:2cc1468da177	874	MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
<>	161:2cc1468da177	875
<>	161:2cc1468da177	876	/* Set the Output Idle state */
<>	161:2cc1468da177	877	MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
<>	161:2cc1468da177	878
<>	161:2cc1468da177	879	/* Set the complementary output Idle state */
<>	161:2cc1468da177	880	MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
<>	161:2cc1468da177	881	}
<>	161:2cc1468da177	882
<>	161:2cc1468da177	883	/* Write to TIMx CR2 */
<>	161:2cc1468da177	884	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	885
<>	161:2cc1468da177	886	/* Write to TIMx CCMR1 */
<>	161:2cc1468da177	887	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	161:2cc1468da177	888
<>	161:2cc1468da177	889	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	890	LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	891
<>	161:2cc1468da177	892	/* Write to TIMx CCER */
<>	161:2cc1468da177	893	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	894
<>	161:2cc1468da177	895	return SUCCESS;
<>	161:2cc1468da177	896	}
<>	161:2cc1468da177	897
<>	161:2cc1468da177	898	/**
<>	161:2cc1468da177	899	* @brief Configure the TIMx output channel 2.
<>	161:2cc1468da177	900	* @param TIMx Timer Instance
<>	161:2cc1468da177	901	* @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
<>	161:2cc1468da177	902	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	903	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	904	* - ERROR: not applicable
<>	161:2cc1468da177	905	*/
<>	161:2cc1468da177	906	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	907	{
<>	161:2cc1468da177	908	uint32_t tmpccmr1 = 0U;
<>	161:2cc1468da177	909	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	910	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	911
<>	161:2cc1468da177	912	/* Check the parameters */
<>	161:2cc1468da177	913	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
<>	161:2cc1468da177	914	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	915	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	916	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	917	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	918	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	919
<>	161:2cc1468da177	920	/* Disable the Channel 2: Reset the CC2E Bit */
<>	161:2cc1468da177	921	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
<>	161:2cc1468da177	922
<>	161:2cc1468da177	923	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	924	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	925
<>	161:2cc1468da177	926	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	927	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	928
<>	161:2cc1468da177	929	/* Get the TIMx CCMR1 register value */
<>	161:2cc1468da177	930	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	161:2cc1468da177	931
<>	161:2cc1468da177	932	/* Reset Capture/Compare selection Bits */
<>	161:2cc1468da177	933	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
<>	161:2cc1468da177	934
<>	161:2cc1468da177	935	/* Select the Output Compare Mode */
<>	161:2cc1468da177	936	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
<>	161:2cc1468da177	937
<>	161:2cc1468da177	938	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	939	MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
<>	161:2cc1468da177	940
<>	161:2cc1468da177	941	/* Set the Output State */
<>	161:2cc1468da177	942	MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
<>	161:2cc1468da177	943
<>	161:2cc1468da177	944	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	945	{
<>	161:2cc1468da177	946	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	947	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	948
<>	161:2cc1468da177	949	/* Set the complementary output Polarity */
<>	161:2cc1468da177	950	MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
<>	161:2cc1468da177	951
<>	161:2cc1468da177	952	/* Set the complementary output State */
<>	161:2cc1468da177	953	MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
<>	161:2cc1468da177	954
<>	161:2cc1468da177	955	/* Set the Output Idle state */
<>	161:2cc1468da177	956	MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
<>	161:2cc1468da177	957
<>	161:2cc1468da177	958	/* Set the complementary output Idle state */
<>	161:2cc1468da177	959	MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
<>	161:2cc1468da177	960	}
<>	161:2cc1468da177	961
<>	161:2cc1468da177	962	/* Write to TIMx CR2 */
<>	161:2cc1468da177	963	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	964
<>	161:2cc1468da177	965	/* Write to TIMx CCMR1 */
<>	161:2cc1468da177	966	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	161:2cc1468da177	967
<>	161:2cc1468da177	968	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	969	LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	970
<>	161:2cc1468da177	971	/* Write to TIMx CCER */
<>	161:2cc1468da177	972	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	973
<>	161:2cc1468da177	974	return SUCCESS;
<>	161:2cc1468da177	975	}
<>	161:2cc1468da177	976
<>	161:2cc1468da177	977	/**
<>	161:2cc1468da177	978	* @brief Configure the TIMx output channel 3.
<>	161:2cc1468da177	979	* @param TIMx Timer Instance
<>	161:2cc1468da177	980	* @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
<>	161:2cc1468da177	981	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	982	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	983	* - ERROR: not applicable
<>	161:2cc1468da177	984	*/
<>	161:2cc1468da177	985	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	986	{
<>	161:2cc1468da177	987	uint32_t tmpccmr2 = 0U;
<>	161:2cc1468da177	988	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	989	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	990
<>	161:2cc1468da177	991	/* Check the parameters */
<>	161:2cc1468da177	992	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
<>	161:2cc1468da177	993	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	994	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	995	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	996	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	997	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	998
<>	161:2cc1468da177	999	/* Disable the Channel 3: Reset the CC3E Bit */
<>	161:2cc1468da177	1000	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
<>	161:2cc1468da177	1001
<>	161:2cc1468da177	1002	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	1003	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	1004
<>	161:2cc1468da177	1005	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	1006	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	1007
<>	161:2cc1468da177	1008	/* Get the TIMx CCMR2 register value */
<>	161:2cc1468da177	1009	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
<>	161:2cc1468da177	1010
<>	161:2cc1468da177	1011	/* Reset Capture/Compare selection Bits */
<>	161:2cc1468da177	1012	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
<>	161:2cc1468da177	1013
<>	161:2cc1468da177	1014	/* Select the Output Compare Mode */
<>	161:2cc1468da177	1015	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
<>	161:2cc1468da177	1016
<>	161:2cc1468da177	1017	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	1018	MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
<>	161:2cc1468da177	1019
<>	161:2cc1468da177	1020	/* Set the Output State */
<>	161:2cc1468da177	1021	MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
<>	161:2cc1468da177	1022
<>	161:2cc1468da177	1023	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	1024	{
<>	161:2cc1468da177	1025	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	1026	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	1027
<>	161:2cc1468da177	1028	/* Set the complementary output Polarity */
<>	161:2cc1468da177	1029	MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
<>	161:2cc1468da177	1030
<>	161:2cc1468da177	1031	/* Set the complementary output State */
<>	161:2cc1468da177	1032	MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
<>	161:2cc1468da177	1033
<>	161:2cc1468da177	1034	/* Set the Output Idle state */
<>	161:2cc1468da177	1035	MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
<>	161:2cc1468da177	1036
<>	161:2cc1468da177	1037	/* Set the complementary output Idle state */
<>	161:2cc1468da177	1038	MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
<>	161:2cc1468da177	1039	}
<>	161:2cc1468da177	1040
<>	161:2cc1468da177	1041	/* Write to TIMx CR2 */
<>	161:2cc1468da177	1042	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	1043
<>	161:2cc1468da177	1044	/* Write to TIMx CCMR2 */
<>	161:2cc1468da177	1045	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
<>	161:2cc1468da177	1046
<>	161:2cc1468da177	1047	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	1048	LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	1049
<>	161:2cc1468da177	1050	/* Write to TIMx CCER */
<>	161:2cc1468da177	1051	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	1052
<>	161:2cc1468da177	1053	return SUCCESS;
<>	161:2cc1468da177	1054	}
<>	161:2cc1468da177	1055
<>	161:2cc1468da177	1056	/**
<>	161:2cc1468da177	1057	* @brief Configure the TIMx output channel 4.
<>	161:2cc1468da177	1058	* @param TIMx Timer Instance
<>	161:2cc1468da177	1059	* @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
<>	161:2cc1468da177	1060	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1061	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1062	* - ERROR: not applicable
<>	161:2cc1468da177	1063	*/
<>	161:2cc1468da177	1064	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	1065	{
<>	161:2cc1468da177	1066	uint32_t tmpccmr2 = 0U;
<>	161:2cc1468da177	1067	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	1068	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	1069
<>	161:2cc1468da177	1070	/* Check the parameters */
<>	161:2cc1468da177	1071	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<>	161:2cc1468da177	1072	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	1073	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	1074	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	1075	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	1076	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	1077
<>	161:2cc1468da177	1078	/* Disable the Channel 4: Reset the CC4E Bit */
<>	161:2cc1468da177	1079	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
<>	161:2cc1468da177	1080
<>	161:2cc1468da177	1081	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	1082	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	1083
<>	161:2cc1468da177	1084	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	1085	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	1086
<>	161:2cc1468da177	1087	/* Get the TIMx CCMR2 register value */
<>	161:2cc1468da177	1088	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
<>	161:2cc1468da177	1089
<>	161:2cc1468da177	1090	/* Reset Capture/Compare selection Bits */
<>	161:2cc1468da177	1091	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
<>	161:2cc1468da177	1092
<>	161:2cc1468da177	1093	/* Select the Output Compare Mode */
<>	161:2cc1468da177	1094	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
<>	161:2cc1468da177	1095
<>	161:2cc1468da177	1096	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	1097	MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
<>	161:2cc1468da177	1098
<>	161:2cc1468da177	1099	/* Set the Output State */
<>	161:2cc1468da177	1100	MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
<>	161:2cc1468da177	1101
<>	161:2cc1468da177	1102	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	1103	{
<>	161:2cc1468da177	1104	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	1105	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	1106
<>	161:2cc1468da177	1107	/* Set the Output Idle state */
<>	161:2cc1468da177	1108	MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
<>	161:2cc1468da177	1109	}
<>	161:2cc1468da177	1110
<>	161:2cc1468da177	1111	/* Write to TIMx CR2 */
<>	161:2cc1468da177	1112	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	1113
<>	161:2cc1468da177	1114	/* Write to TIMx CCMR2 */
<>	161:2cc1468da177	1115	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
<>	161:2cc1468da177	1116
<>	161:2cc1468da177	1117	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	1118	LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	1119
<>	161:2cc1468da177	1120	/* Write to TIMx CCER */
<>	161:2cc1468da177	1121	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	1122
<>	161:2cc1468da177	1123	return SUCCESS;
<>	161:2cc1468da177	1124	}
<>	161:2cc1468da177	1125
<>	161:2cc1468da177	1126	/**
<>	161:2cc1468da177	1127	* @brief Configure the TIMx output channel 5.
<>	161:2cc1468da177	1128	* @param TIMx Timer Instance
<>	161:2cc1468da177	1129	* @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
<>	161:2cc1468da177	1130	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1131	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1132	* - ERROR: not applicable
<>	161:2cc1468da177	1133	*/
<>	161:2cc1468da177	1134	static ErrorStatus OC5Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	1135	{
<>	161:2cc1468da177	1136	uint32_t tmpccmr3 = 0U;
<>	161:2cc1468da177	1137	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	1138
<>	161:2cc1468da177	1139	/* Check the parameters */
<>	161:2cc1468da177	1140	assert_param(IS_TIM_CC5_INSTANCE(TIMx));
<>	161:2cc1468da177	1141	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	1142	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	1143	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	1144	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	1145	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	1146
<>	161:2cc1468da177	1147	/* Disable the Channel 5: Reset the CC5E Bit */
<>	161:2cc1468da177	1148	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
<>	161:2cc1468da177	1149
<>	161:2cc1468da177	1150	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	1151	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	1152
<>	161:2cc1468da177	1153	/* Get the TIMx CCMR3 register value */
<>	161:2cc1468da177	1154	tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
<>	161:2cc1468da177	1155
<>	161:2cc1468da177	1156	/* Select the Output Compare Mode */
<>	161:2cc1468da177	1157	MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
<>	161:2cc1468da177	1158
<>	161:2cc1468da177	1159	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	1160	MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
<>	161:2cc1468da177	1161
<>	161:2cc1468da177	1162	/* Set the Output State */
<>	161:2cc1468da177	1163	MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
<>	161:2cc1468da177	1164
<>	161:2cc1468da177	1165	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	1166	{
<>	161:2cc1468da177	1167	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	1168	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	1169
<>	161:2cc1468da177	1170	/* Set the Output Idle state */
<>	161:2cc1468da177	1171	MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
<>	161:2cc1468da177	1172
<>	161:2cc1468da177	1173	}
<>	161:2cc1468da177	1174
<>	161:2cc1468da177	1175	/* Write to TIMx CCMR3 */
<>	161:2cc1468da177	1176	LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
<>	161:2cc1468da177	1177
<>	161:2cc1468da177	1178	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	1179	LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	1180
<>	161:2cc1468da177	1181	/* Write to TIMx CCER */
<>	161:2cc1468da177	1182	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	1183
<>	161:2cc1468da177	1184	return SUCCESS;
<>	161:2cc1468da177	1185	}
<>	161:2cc1468da177	1186
<>	161:2cc1468da177	1187	/**
<>	161:2cc1468da177	1188	* @brief Configure the TIMx output channel 6.
<>	161:2cc1468da177	1189	* @param TIMx Timer Instance
<>	161:2cc1468da177	1190	* @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
<>	161:2cc1468da177	1191	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1192	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1193	* - ERROR: not applicable
<>	161:2cc1468da177	1194	*/
<>	161:2cc1468da177	1195	static ErrorStatus OC6Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	1196	{
<>	161:2cc1468da177	1197	uint32_t tmpccmr3 = 0U;
<>	161:2cc1468da177	1198	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	1199
<>	161:2cc1468da177	1200	/* Check the parameters */
<>	161:2cc1468da177	1201	assert_param(IS_TIM_CC6_INSTANCE(TIMx));
<>	161:2cc1468da177	1202	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	1203	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	1204	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	1205	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	1206	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	1207
<>	161:2cc1468da177	1208	/* Disable the Channel 5: Reset the CC6E Bit */
<>	161:2cc1468da177	1209	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
<>	161:2cc1468da177	1210
<>	161:2cc1468da177	1211	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	1212	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	1213
<>	161:2cc1468da177	1214	/* Get the TIMx CCMR3 register value */
<>	161:2cc1468da177	1215	tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
<>	161:2cc1468da177	1216
<>	161:2cc1468da177	1217	/* Select the Output Compare Mode */
<>	161:2cc1468da177	1218	MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
<>	161:2cc1468da177	1219
<>	161:2cc1468da177	1220	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	1221	MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
<>	161:2cc1468da177	1222
<>	161:2cc1468da177	1223	/* Set the Output State */
<>	161:2cc1468da177	1224	MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
<>	161:2cc1468da177	1225
<>	161:2cc1468da177	1226	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	1227	{
<>	161:2cc1468da177	1228	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	1229	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	1230
<>	161:2cc1468da177	1231	/* Set the Output Idle state */
<>	161:2cc1468da177	1232	MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
<>	161:2cc1468da177	1233	}
<>	161:2cc1468da177	1234
<>	161:2cc1468da177	1235	/* Write to TIMx CCMR3 */
<>	161:2cc1468da177	1236	LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
<>	161:2cc1468da177	1237
<>	161:2cc1468da177	1238	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	1239	LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	1240
<>	161:2cc1468da177	1241	/* Write to TIMx CCER */
<>	161:2cc1468da177	1242	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	1243
<>	161:2cc1468da177	1244	return SUCCESS;
<>	161:2cc1468da177	1245	}
<>	161:2cc1468da177	1246
<>	161:2cc1468da177	1247	/**
<>	161:2cc1468da177	1248	* @brief Configure the TIMx input channel 1.
<>	161:2cc1468da177	1249	* @param TIMx Timer Instance
<>	161:2cc1468da177	1250	* @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
<>	161:2cc1468da177	1251	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1252	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1253	* - ERROR: not applicable
<>	161:2cc1468da177	1254	*/
<>	161:2cc1468da177	1255	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	161:2cc1468da177	1256	{
<>	161:2cc1468da177	1257	/* Check the parameters */
<>	161:2cc1468da177	1258	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	161:2cc1468da177	1259	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	161:2cc1468da177	1260	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	161:2cc1468da177	1261	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	161:2cc1468da177	1262	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	161:2cc1468da177	1263
<>	161:2cc1468da177	1264	/* Disable the Channel 1: Reset the CC1E Bit */
<>	161:2cc1468da177	1265	TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
<>	161:2cc1468da177	1266
<>	161:2cc1468da177	1267	/* Select the Input and set the filter and the prescaler value */
<>	161:2cc1468da177	1268	MODIFY_REG(TIMx->CCMR1,
<>	161:2cc1468da177	1269	(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC),
<>	161:2cc1468da177	1270	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
<>	161:2cc1468da177	1271
<>	161:2cc1468da177	1272	/* Select the Polarity and set the CC1E Bit */
<>	161:2cc1468da177	1273	MODIFY_REG(TIMx->CCER,
<>	161:2cc1468da177	1274	(TIM_CCER_CC1P \| TIM_CCER_CC1NP),
<>	161:2cc1468da177	1275	(TIM_ICInitStruct->ICPolarity \| TIM_CCER_CC1E));
<>	161:2cc1468da177	1276
<>	161:2cc1468da177	1277	return SUCCESS;
<>	161:2cc1468da177	1278	}
<>	161:2cc1468da177	1279
<>	161:2cc1468da177	1280	/**
<>	161:2cc1468da177	1281	* @brief Configure the TIMx input channel 2.
<>	161:2cc1468da177	1282	* @param TIMx Timer Instance
<>	161:2cc1468da177	1283	* @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
<>	161:2cc1468da177	1284	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1285	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1286	* - ERROR: not applicable
<>	161:2cc1468da177	1287	*/
<>	161:2cc1468da177	1288	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	161:2cc1468da177	1289	{
<>	161:2cc1468da177	1290	/* Check the parameters */
<>	161:2cc1468da177	1291	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
<>	161:2cc1468da177	1292	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	161:2cc1468da177	1293	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	161:2cc1468da177	1294	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	161:2cc1468da177	1295	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	161:2cc1468da177	1296
<>	161:2cc1468da177	1297	/* Disable the Channel 2: Reset the CC2E Bit */
<>	161:2cc1468da177	1298	TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
<>	161:2cc1468da177	1299
<>	161:2cc1468da177	1300	/* Select the Input and set the filter and the prescaler value */
<>	161:2cc1468da177	1301	MODIFY_REG(TIMx->CCMR1,
<>	161:2cc1468da177	1302	(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC),
<>	161:2cc1468da177	1303	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
<>	161:2cc1468da177	1304
<>	161:2cc1468da177	1305	/* Select the Polarity and set the CC2E Bit */
<>	161:2cc1468da177	1306	MODIFY_REG(TIMx->CCER,
<>	161:2cc1468da177	1307	(TIM_CCER_CC2P \| TIM_CCER_CC2NP),
<>	161:2cc1468da177	1308	((TIM_ICInitStruct->ICPolarity << 4U) \| TIM_CCER_CC2E));
<>	161:2cc1468da177	1309
<>	161:2cc1468da177	1310	return SUCCESS;
<>	161:2cc1468da177	1311	}
<>	161:2cc1468da177	1312
<>	161:2cc1468da177	1313	/**
<>	161:2cc1468da177	1314	* @brief Configure the TIMx input channel 3.
<>	161:2cc1468da177	1315	* @param TIMx Timer Instance
<>	161:2cc1468da177	1316	* @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
<>	161:2cc1468da177	1317	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1318	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1319	* - ERROR: not applicable
<>	161:2cc1468da177	1320	*/
<>	161:2cc1468da177	1321	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	161:2cc1468da177	1322	{
<>	161:2cc1468da177	1323	/* Check the parameters */
<>	161:2cc1468da177	1324	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
<>	161:2cc1468da177	1325	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	161:2cc1468da177	1326	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	161:2cc1468da177	1327	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	161:2cc1468da177	1328	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	161:2cc1468da177	1329
<>	161:2cc1468da177	1330	/* Disable the Channel 3: Reset the CC3E Bit */
<>	161:2cc1468da177	1331	TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
<>	161:2cc1468da177	1332
<>	161:2cc1468da177	1333	/* Select the Input and set the filter and the prescaler value */
<>	161:2cc1468da177	1334	MODIFY_REG(TIMx->CCMR2,
<>	161:2cc1468da177	1335	(TIM_CCMR2_CC3S \| TIM_CCMR2_IC3F \| TIM_CCMR2_IC3PSC),
<>	161:2cc1468da177	1336	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
<>	161:2cc1468da177	1337
<>	161:2cc1468da177	1338	/* Select the Polarity and set the CC3E Bit */
<>	161:2cc1468da177	1339	MODIFY_REG(TIMx->CCER,
<>	161:2cc1468da177	1340	(TIM_CCER_CC3P \| TIM_CCER_CC3NP),
<>	161:2cc1468da177	1341	((TIM_ICInitStruct->ICPolarity << 8U) \| TIM_CCER_CC3E));
<>	161:2cc1468da177	1342
<>	161:2cc1468da177	1343	return SUCCESS;
<>	161:2cc1468da177	1344	}
<>	161:2cc1468da177	1345
<>	161:2cc1468da177	1346	/**
<>	161:2cc1468da177	1347	* @brief Configure the TIMx input channel 4.
<>	161:2cc1468da177	1348	* @param TIMx Timer Instance
<>	161:2cc1468da177	1349	* @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
<>	161:2cc1468da177	1350	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1351	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1352	* - ERROR: not applicable
<>	161:2cc1468da177	1353	*/
<>	161:2cc1468da177	1354	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	161:2cc1468da177	1355	{
<>	161:2cc1468da177	1356	/* Check the parameters */
<>	161:2cc1468da177	1357	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<>	161:2cc1468da177	1358	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	161:2cc1468da177	1359	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	161:2cc1468da177	1360	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	161:2cc1468da177	1361	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	161:2cc1468da177	1362
<>	161:2cc1468da177	1363	/* Disable the Channel 4: Reset the CC4E Bit */
<>	161:2cc1468da177	1364	TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
<>	161:2cc1468da177	1365
<>	161:2cc1468da177	1366	/* Select the Input and set the filter and the prescaler value */
<>	161:2cc1468da177	1367	MODIFY_REG(TIMx->CCMR2,
<>	161:2cc1468da177	1368	(TIM_CCMR2_CC4S \| TIM_CCMR2_IC4F \| TIM_CCMR2_IC4PSC),
<>	161:2cc1468da177	1369	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
<>	161:2cc1468da177	1370
<>	161:2cc1468da177	1371	/* Select the Polarity and set the CC2E Bit */
<>	161:2cc1468da177	1372	MODIFY_REG(TIMx->CCER,
<>	161:2cc1468da177	1373	(TIM_CCER_CC4P \| TIM_CCER_CC4NP),
<>	161:2cc1468da177	1374	((TIM_ICInitStruct->ICPolarity << 12U) \| TIM_CCER_CC4E));
<>	161:2cc1468da177	1375
<>	161:2cc1468da177	1376	return SUCCESS;
<>	161:2cc1468da177	1377	}
<>	161:2cc1468da177	1378
<>	161:2cc1468da177	1379
<>	161:2cc1468da177	1380	/**
<>	161:2cc1468da177	1381	* @}
<>	161:2cc1468da177	1382	*/
<>	161:2cc1468da177	1383
<>	161:2cc1468da177	1384	/**
<>	161:2cc1468da177	1385	* @}
<>	161:2cc1468da177	1386	*/
<>	161:2cc1468da177	1387
<>	161:2cc1468da177	1388	#endif /* TIM1 \|\| TIM8 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\|TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM6 \|\| TIM7 */
<>	161:2cc1468da177	1389
<>	161:2cc1468da177	1390	/**
<>	161:2cc1468da177	1391	* @}
<>	161:2cc1468da177	1392	*/
<>	161:2cc1468da177	1393
<>	161:2cc1468da177	1394	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	1395
<>	161:2cc1468da177	1396	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/