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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.c@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:: AnnaBridge
Date:: Tue Mar 20 16:56:18 2018 +0000
Revision:: 182:a56a73fd2a6f
Parent:: 161:2cc1468da177

mbed-dev library. Release version 160

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_tim.c
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @brief TIM LL module driver.
<>	161:2cc1468da177	6	******************************************************************************
<>	161:2cc1468da177	7	* @attention
<>	161:2cc1468da177	8	*
<>	161:2cc1468da177	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	12	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	14	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	17	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	19	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	20	* without specific prior written permission.
<>	161:2cc1468da177	21	*
<>	161:2cc1468da177	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	32	*
<>	161:2cc1468da177	33	******************************************************************************
<>	161:2cc1468da177	34	*/
<>	161:2cc1468da177	35	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	36
<>	161:2cc1468da177	37	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	38	#include "stm32f7xx_ll_tim.h"
<>	161:2cc1468da177	39	#include "stm32f7xx_ll_bus.h"
<>	161:2cc1468da177	40
<>	161:2cc1468da177	41	#ifdef USE_FULL_ASSERT
<>	161:2cc1468da177	42	#include "stm32_assert.h"
<>	161:2cc1468da177	43	#else
<>	161:2cc1468da177	44	#define assert_param(expr) ((void)0U)
<>	161:2cc1468da177	45	#endif
<>	161:2cc1468da177	46
<>	161:2cc1468da177	47	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	48	* @{
<>	161:2cc1468da177	49	*/
<>	161:2cc1468da177	50
<>	161:2cc1468da177	51	#if defined (TIM1) \|\| defined (TIM8) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM6) \|\| defined (TIM7)
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	/** @addtogroup TIM_LL
<>	161:2cc1468da177	54	* @{
<>	161:2cc1468da177	55	*/
<>	161:2cc1468da177	56
<>	161:2cc1468da177	57	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	58	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	59	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	60	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	61	/** @addtogroup TIM_LL_Private_Macros
<>	161:2cc1468da177	62	* @{
<>	161:2cc1468da177	63	*/
<>	161:2cc1468da177	64	#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
<>	161:2cc1468da177	65	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
<>	161:2cc1468da177	66	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
<>	161:2cc1468da177	67	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
<>	161:2cc1468da177	68	\|\| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
<>	161:2cc1468da177	69
<>	161:2cc1468da177	70	#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
<>	161:2cc1468da177	71	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
<>	161:2cc1468da177	72	\|\| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
<>	161:2cc1468da177	73
<>	161:2cc1468da177	74	#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
<>	161:2cc1468da177	75	\|\| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
<>	161:2cc1468da177	76	\|\| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
<>	161:2cc1468da177	77	\|\| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
<>	161:2cc1468da177	78	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
<>	161:2cc1468da177	79	\|\| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
<>	161:2cc1468da177	80	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
<>	161:2cc1468da177	81	\|\| ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
<>	161:2cc1468da177	82	\|\| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
<>	161:2cc1468da177	83	\|\| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
<>	161:2cc1468da177	84	\|\| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
<>	161:2cc1468da177	85	\|\| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
<>	161:2cc1468da177	86	\|\| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
<>	161:2cc1468da177	87	\|\| ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
<>	161:2cc1468da177	88
<>	161:2cc1468da177	89	#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
<>	161:2cc1468da177	90	\|\| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
<>	161:2cc1468da177	91
<>	161:2cc1468da177	92	#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
<>	161:2cc1468da177	93	\|\| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
<>	161:2cc1468da177	94
<>	161:2cc1468da177	95	#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
<>	161:2cc1468da177	96	\|\| ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
<>	161:2cc1468da177	97
<>	161:2cc1468da177	98	#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
<>	161:2cc1468da177	99	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
<>	161:2cc1468da177	100	\|\| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
<>	161:2cc1468da177	101
<>	161:2cc1468da177	102	#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
<>	161:2cc1468da177	103	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
<>	161:2cc1468da177	104	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
<>	161:2cc1468da177	105	\|\| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
<>	161:2cc1468da177	106
<>	161:2cc1468da177	107	#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
<>	161:2cc1468da177	108	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
<>	161:2cc1468da177	109	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
<>	161:2cc1468da177	110	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
<>	161:2cc1468da177	111	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
<>	161:2cc1468da177	112	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
<>	161:2cc1468da177	113	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
<>	161:2cc1468da177	114	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
<>	161:2cc1468da177	115	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
<>	161:2cc1468da177	116	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
<>	161:2cc1468da177	117	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
<>	161:2cc1468da177	118	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
<>	161:2cc1468da177	119	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
<>	161:2cc1468da177	120	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
<>	161:2cc1468da177	121	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
<>	161:2cc1468da177	122	\|\| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
<>	161:2cc1468da177	123
<>	161:2cc1468da177	124	#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
<>	161:2cc1468da177	125	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
<>	161:2cc1468da177	126	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
<>	161:2cc1468da177	127
<>	161:2cc1468da177	128	#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
<>	161:2cc1468da177	129	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
<>	161:2cc1468da177	130	\|\| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
<>	161:2cc1468da177	131
<>	161:2cc1468da177	132	#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
<>	161:2cc1468da177	133	\|\| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
<>	161:2cc1468da177	134
<>	161:2cc1468da177	135	#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
<>	161:2cc1468da177	136	\|\| ((__VALUE__) == LL_TIM_OSSR_ENABLE))
<>	161:2cc1468da177	137
<>	161:2cc1468da177	138	#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
<>	161:2cc1468da177	139	\|\| ((__VALUE__) == LL_TIM_OSSI_ENABLE))
<>	161:2cc1468da177	140
<>	161:2cc1468da177	141	#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
<>	161:2cc1468da177	142	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
<>	161:2cc1468da177	143	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
<>	161:2cc1468da177	144	\|\| ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
<>	161:2cc1468da177	145
<>	161:2cc1468da177	146	#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
<>	161:2cc1468da177	147	\|\| ((__VALUE__) == LL_TIM_BREAK_ENABLE))
<>	161:2cc1468da177	148
<>	161:2cc1468da177	149	#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
<>	161:2cc1468da177	150	\|\| ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
<>	161:2cc1468da177	151
<>	161:2cc1468da177	152	#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
<>	161:2cc1468da177	153	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
<>	161:2cc1468da177	154	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
<>	161:2cc1468da177	155	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
<>	161:2cc1468da177	156	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
<>	161:2cc1468da177	157	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
<>	161:2cc1468da177	158	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
<>	161:2cc1468da177	159	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
<>	161:2cc1468da177	160	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
<>	161:2cc1468da177	161	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
<>	161:2cc1468da177	162	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
<>	161:2cc1468da177	163	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
<>	161:2cc1468da177	164	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
<>	161:2cc1468da177	165	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
<>	161:2cc1468da177	166	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
<>	161:2cc1468da177	167	\|\| ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
<>	161:2cc1468da177	168
<>	161:2cc1468da177	169	#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
<>	161:2cc1468da177	170	\|\| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
<>	161:2cc1468da177	171
<>	161:2cc1468da177	172	#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
<>	161:2cc1468da177	173	\|\| ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
<>	161:2cc1468da177	174
<>	161:2cc1468da177	175	#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
<>	161:2cc1468da177	176	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
<>	161:2cc1468da177	177	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
<>	161:2cc1468da177	178	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
<>	161:2cc1468da177	179	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
<>	161:2cc1468da177	180	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
<>	161:2cc1468da177	181	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
<>	161:2cc1468da177	182	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
<>	161:2cc1468da177	183	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
<>	161:2cc1468da177	184	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
<>	161:2cc1468da177	185	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
<>	161:2cc1468da177	186	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
<>	161:2cc1468da177	187	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
<>	161:2cc1468da177	188	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
<>	161:2cc1468da177	189	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
<>	161:2cc1468da177	190	\|\| ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
<>	161:2cc1468da177	191
<>	161:2cc1468da177	192	#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
<>	161:2cc1468da177	193	\|\| ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
<>	161:2cc1468da177	194	/**
<>	161:2cc1468da177	195	* @}
<>	161:2cc1468da177	196	*/
<>	161:2cc1468da177	197
<>	161:2cc1468da177	198
<>	161:2cc1468da177	199	/* Private function prototypes -----------------------------------------------*/
<>	161:2cc1468da177	200	/** @defgroup TIM_LL_Private_Functions TIM Private Functions
<>	161:2cc1468da177	201	* @{
<>	161:2cc1468da177	202	*/
<>	161:2cc1468da177	203	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	204	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	205	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	206	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	207	static ErrorStatus OC5Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	208	static ErrorStatus OC6Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct);
<>	161:2cc1468da177	209	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	161:2cc1468da177	210	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	161:2cc1468da177	211	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	161:2cc1468da177	212	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct);
<>	161:2cc1468da177	213	/**
<>	161:2cc1468da177	214	* @}
<>	161:2cc1468da177	215	*/
<>	161:2cc1468da177	216
<>	161:2cc1468da177	217	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	218	/** @addtogroup TIM_LL_Exported_Functions
<>	161:2cc1468da177	219	* @{
<>	161:2cc1468da177	220	*/
<>	161:2cc1468da177	221
<>	161:2cc1468da177	222	/** @addtogroup TIM_LL_EF_Init
<>	161:2cc1468da177	223	* @{
<>	161:2cc1468da177	224	*/
<>	161:2cc1468da177	225
<>	161:2cc1468da177	226	/**
<>	161:2cc1468da177	227	* @brief Set TIMx registers to their reset values.
<>	161:2cc1468da177	228	* @param TIMx Timer instance
<>	161:2cc1468da177	229	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	230	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	231	* - ERROR: invalid TIMx instance
<>	161:2cc1468da177	232	*/
<>	161:2cc1468da177	233	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	234	{
<>	161:2cc1468da177	235	ErrorStatus result = SUCCESS;
<>	161:2cc1468da177	236
<>	161:2cc1468da177	237	/* Check the parameters */
<>	161:2cc1468da177	238	assert_param(IS_TIM_INSTANCE(TIMx));
<>	161:2cc1468da177	239
<>	161:2cc1468da177	240	if (TIMx == TIM1)
<>	161:2cc1468da177	241	{
<>	161:2cc1468da177	242	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
<>	161:2cc1468da177	243	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
<>	161:2cc1468da177	244	}
<>	161:2cc1468da177	245	else if (TIMx == TIM2)
<>	161:2cc1468da177	246	{
<>	161:2cc1468da177	247	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
<>	161:2cc1468da177	248	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
<>	161:2cc1468da177	249	}
<>	161:2cc1468da177	250	#if defined(TIM3)
<>	161:2cc1468da177	251	else if (TIMx == TIM3)
<>	161:2cc1468da177	252	{
<>	161:2cc1468da177	253	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
<>	161:2cc1468da177	254	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
<>	161:2cc1468da177	255	}
<>	161:2cc1468da177	256	#endif
<>	161:2cc1468da177	257	#if defined(TIM4)
<>	161:2cc1468da177	258	else if (TIMx == TIM4)
<>	161:2cc1468da177	259	{
<>	161:2cc1468da177	260	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
<>	161:2cc1468da177	261	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
<>	161:2cc1468da177	262	}
<>	161:2cc1468da177	263	#endif
<>	161:2cc1468da177	264	#if defined(TIM5)
<>	161:2cc1468da177	265	else if (TIMx == TIM5)
<>	161:2cc1468da177	266	{
<>	161:2cc1468da177	267	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
<>	161:2cc1468da177	268	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
<>	161:2cc1468da177	269	}
<>	161:2cc1468da177	270	#endif
<>	161:2cc1468da177	271	#if defined(TIM6)
<>	161:2cc1468da177	272	else if (TIMx == TIM6)
<>	161:2cc1468da177	273	{
<>	161:2cc1468da177	274	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
<>	161:2cc1468da177	275	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
<>	161:2cc1468da177	276	}
<>	161:2cc1468da177	277	#endif
<>	161:2cc1468da177	278	#if defined (TIM7)
<>	161:2cc1468da177	279	else if (TIMx == TIM7)
<>	161:2cc1468da177	280	{
<>	161:2cc1468da177	281	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
<>	161:2cc1468da177	282	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
<>	161:2cc1468da177	283	}
<>	161:2cc1468da177	284	#endif
<>	161:2cc1468da177	285	#if defined(TIM8)
<>	161:2cc1468da177	286	else if (TIMx == TIM8)
<>	161:2cc1468da177	287	{
<>	161:2cc1468da177	288	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
<>	161:2cc1468da177	289	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
<>	161:2cc1468da177	290	}
<>	161:2cc1468da177	291	#endif
<>	161:2cc1468da177	292	#if defined(TIM9)
<>	161:2cc1468da177	293	else if (TIMx == TIM9)
<>	161:2cc1468da177	294	{
<>	161:2cc1468da177	295	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
<>	161:2cc1468da177	296	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
<>	161:2cc1468da177	297	}
<>	161:2cc1468da177	298	#endif
<>	161:2cc1468da177	299	#if defined(TIM10)
<>	161:2cc1468da177	300	else if (TIMx == TIM10)
<>	161:2cc1468da177	301	{
<>	161:2cc1468da177	302	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
<>	161:2cc1468da177	303	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
<>	161:2cc1468da177	304	}
<>	161:2cc1468da177	305	#endif
<>	161:2cc1468da177	306	#if defined(TIM11)
<>	161:2cc1468da177	307	else if (TIMx == TIM11)
<>	161:2cc1468da177	308	{
<>	161:2cc1468da177	309	LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
<>	161:2cc1468da177	310	LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
<>	161:2cc1468da177	311	}
<>	161:2cc1468da177	312	#endif
<>	161:2cc1468da177	313	#if defined(TIM12)
<>	161:2cc1468da177	314	else if (TIMx == TIM12)
<>	161:2cc1468da177	315	{
<>	161:2cc1468da177	316	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
<>	161:2cc1468da177	317	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
<>	161:2cc1468da177	318	}
<>	161:2cc1468da177	319	#endif
<>	161:2cc1468da177	320	#if defined(TIM13)
<>	161:2cc1468da177	321	else if (TIMx == TIM13)
<>	161:2cc1468da177	322	{
<>	161:2cc1468da177	323	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
<>	161:2cc1468da177	324	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
<>	161:2cc1468da177	325	}
<>	161:2cc1468da177	326	#endif
<>	161:2cc1468da177	327	#if defined(TIM14)
<>	161:2cc1468da177	328	else if (TIMx == TIM14)
<>	161:2cc1468da177	329	{
<>	161:2cc1468da177	330	LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
<>	161:2cc1468da177	331	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
<>	161:2cc1468da177	332	}
<>	161:2cc1468da177	333	#endif
<>	161:2cc1468da177	334	else
<>	161:2cc1468da177	335	{
<>	161:2cc1468da177	336	result = ERROR;
<>	161:2cc1468da177	337	}
<>	161:2cc1468da177	338
<>	161:2cc1468da177	339	return result;
<>	161:2cc1468da177	340	}
<>	161:2cc1468da177	341
<>	161:2cc1468da177	342	/**
<>	161:2cc1468da177	343	* @brief Set the fields of the time base unit configuration data structure
<>	161:2cc1468da177	344	* to their default values.
<>	161:2cc1468da177	345	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
<>	161:2cc1468da177	346	* @retval None
<>	161:2cc1468da177	347	*/
<>	161:2cc1468da177	348	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
<>	161:2cc1468da177	349	{
<>	161:2cc1468da177	350	/* Set the default configuration */
<>	161:2cc1468da177	351	TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
<>	161:2cc1468da177	352	TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
<>	161:2cc1468da177	353	TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
<>	161:2cc1468da177	354	TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
<>	161:2cc1468da177	355	TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
<>	161:2cc1468da177	356	}
<>	161:2cc1468da177	357
<>	161:2cc1468da177	358	/**
<>	161:2cc1468da177	359	* @brief Configure the TIMx time base unit.
<>	161:2cc1468da177	360	* @param TIMx Timer Instance
<>	161:2cc1468da177	361	* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
<>	161:2cc1468da177	362	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	363	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	364	* - ERROR: not applicable
<>	161:2cc1468da177	365	*/
<>	161:2cc1468da177	366	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct)
<>	161:2cc1468da177	367	{
<>	161:2cc1468da177	368	uint32_t tmpcr1 = 0U;
<>	161:2cc1468da177	369
<>	161:2cc1468da177	370	/* Check the parameters */
<>	161:2cc1468da177	371	assert_param(IS_TIM_INSTANCE(TIMx));
<>	161:2cc1468da177	372	assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
<>	161:2cc1468da177	373	assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
<>	161:2cc1468da177	374
<>	161:2cc1468da177	375	tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
<>	161:2cc1468da177	376
<>	161:2cc1468da177	377	if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
<>	161:2cc1468da177	378	{
<>	161:2cc1468da177	379	/* Select the Counter Mode */
<>	161:2cc1468da177	380	MODIFY_REG(tmpcr1, (TIM_CR1_DIR \| TIM_CR1_CMS), TIM_InitStruct->CounterMode);
<>	161:2cc1468da177	381	}
<>	161:2cc1468da177	382
<>	161:2cc1468da177	383	if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
<>	161:2cc1468da177	384	{
<>	161:2cc1468da177	385	/* Set the clock division */
<>	161:2cc1468da177	386	MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
<>	161:2cc1468da177	387	}
<>	161:2cc1468da177	388
<>	161:2cc1468da177	389	/* Write to TIMx CR1 */
<>	161:2cc1468da177	390	LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
<>	161:2cc1468da177	391
<>	161:2cc1468da177	392	/* Set the Autoreload value */
<>	161:2cc1468da177	393	LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
<>	161:2cc1468da177	394
<>	161:2cc1468da177	395	/* Set the Prescaler value */
<>	161:2cc1468da177	396	LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
<>	161:2cc1468da177	397
<>	161:2cc1468da177	398	if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
<>	161:2cc1468da177	399	{
<>	161:2cc1468da177	400	/* Set the Repetition Counter value */
<>	161:2cc1468da177	401	LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
<>	161:2cc1468da177	402	}
<>	161:2cc1468da177	403
<>	161:2cc1468da177	404	/* Generate an update event to reload the Prescaler
<>	161:2cc1468da177	405	and the repetition counter value (if applicable) immediately */
<>	161:2cc1468da177	406	LL_TIM_GenerateEvent_UPDATE(TIMx);
<>	161:2cc1468da177	407
<>	161:2cc1468da177	408	return SUCCESS;
<>	161:2cc1468da177	409	}
<>	161:2cc1468da177	410
<>	161:2cc1468da177	411	/**
<>	161:2cc1468da177	412	* @brief Set the fields of the TIMx output channel configuration data
<>	161:2cc1468da177	413	* structure to their default values.
<>	161:2cc1468da177	414	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
<>	161:2cc1468da177	415	* @retval None
<>	161:2cc1468da177	416	*/
<>	161:2cc1468da177	417	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
<>	161:2cc1468da177	418	{
<>	161:2cc1468da177	419	/* Set the default configuration */
<>	161:2cc1468da177	420	TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
<>	161:2cc1468da177	421	TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
<>	161:2cc1468da177	422	TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
<>	161:2cc1468da177	423	TIM_OC_InitStruct->CompareValue = 0x00000000U;
<>	161:2cc1468da177	424	TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
<>	161:2cc1468da177	425	TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
<>	161:2cc1468da177	426	TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
<>	161:2cc1468da177	427	TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
<>	161:2cc1468da177	428	}
<>	161:2cc1468da177	429
<>	161:2cc1468da177	430	/**
<>	161:2cc1468da177	431	* @brief Configure the TIMx output channel.
<>	161:2cc1468da177	432	* @param TIMx Timer Instance
<>	161:2cc1468da177	433	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	434	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	435	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	436	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	437	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	438	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	439	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	440	* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
<>	161:2cc1468da177	441	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	442	* - SUCCESS: TIMx output channel is initialized
<>	161:2cc1468da177	443	* - ERROR: TIMx output channel is not initialized
<>	161:2cc1468da177	444	*/
<>	161:2cc1468da177	445	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct)
<>	161:2cc1468da177	446	{
<>	161:2cc1468da177	447	ErrorStatus result = ERROR;
<>	161:2cc1468da177	448
<>	161:2cc1468da177	449	switch (Channel)
<>	161:2cc1468da177	450	{
<>	161:2cc1468da177	451	case LL_TIM_CHANNEL_CH1:
<>	161:2cc1468da177	452	result = OC1Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	453	break;
<>	161:2cc1468da177	454	case LL_TIM_CHANNEL_CH2:
<>	161:2cc1468da177	455	result = OC2Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	456	break;
<>	161:2cc1468da177	457	case LL_TIM_CHANNEL_CH3:
<>	161:2cc1468da177	458	result = OC3Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	459	break;
<>	161:2cc1468da177	460	case LL_TIM_CHANNEL_CH4:
<>	161:2cc1468da177	461	result = OC4Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	462	break;
<>	161:2cc1468da177	463	case LL_TIM_CHANNEL_CH5:
<>	161:2cc1468da177	464	result = OC5Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	465	break;
<>	161:2cc1468da177	466	case LL_TIM_CHANNEL_CH6:
<>	161:2cc1468da177	467	result = OC6Config(TIMx, TIM_OC_InitStruct);
<>	161:2cc1468da177	468	break;
<>	161:2cc1468da177	469	default:
<>	161:2cc1468da177	470	break;
<>	161:2cc1468da177	471	}
<>	161:2cc1468da177	472
<>	161:2cc1468da177	473	return result;
<>	161:2cc1468da177	474	}
<>	161:2cc1468da177	475
<>	161:2cc1468da177	476	/**
<>	161:2cc1468da177	477	* @brief Set the fields of the TIMx input channel configuration data
<>	161:2cc1468da177	478	* structure to their default values.
<>	161:2cc1468da177	479	* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
<>	161:2cc1468da177	480	* @retval None
<>	161:2cc1468da177	481	*/
<>	161:2cc1468da177	482	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
<>	161:2cc1468da177	483	{
<>	161:2cc1468da177	484	/* Set the default configuration */
<>	161:2cc1468da177	485	TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
<>	161:2cc1468da177	486	TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	161:2cc1468da177	487	TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
<>	161:2cc1468da177	488	TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
<>	161:2cc1468da177	489	}
<>	161:2cc1468da177	490
<>	161:2cc1468da177	491	/**
<>	161:2cc1468da177	492	* @brief Configure the TIMx input channel.
<>	161:2cc1468da177	493	* @param TIMx Timer Instance
<>	161:2cc1468da177	494	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	495	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	496	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	497	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	498	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	499	* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
<>	161:2cc1468da177	500	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	501	* - SUCCESS: TIMx output channel is initialized
<>	161:2cc1468da177	502	* - ERROR: TIMx output channel is not initialized
<>	161:2cc1468da177	503	*/
<>	161:2cc1468da177	504	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct)
<>	161:2cc1468da177	505	{
<>	161:2cc1468da177	506	ErrorStatus result = ERROR;
<>	161:2cc1468da177	507
<>	161:2cc1468da177	508	switch (Channel)
<>	161:2cc1468da177	509	{
<>	161:2cc1468da177	510	case LL_TIM_CHANNEL_CH1:
<>	161:2cc1468da177	511	result = IC1Config(TIMx, TIM_IC_InitStruct);
<>	161:2cc1468da177	512	break;
<>	161:2cc1468da177	513	case LL_TIM_CHANNEL_CH2:
<>	161:2cc1468da177	514	result = IC2Config(TIMx, TIM_IC_InitStruct);
<>	161:2cc1468da177	515	break;
<>	161:2cc1468da177	516	case LL_TIM_CHANNEL_CH3:
<>	161:2cc1468da177	517	result = IC3Config(TIMx, TIM_IC_InitStruct);
<>	161:2cc1468da177	518	break;
<>	161:2cc1468da177	519	case LL_TIM_CHANNEL_CH4:
<>	161:2cc1468da177	520	result = IC4Config(TIMx, TIM_IC_InitStruct);
<>	161:2cc1468da177	521	break;
<>	161:2cc1468da177	522	default:
<>	161:2cc1468da177	523	break;
<>	161:2cc1468da177	524	}
<>	161:2cc1468da177	525
<>	161:2cc1468da177	526	return result;
<>	161:2cc1468da177	527	}
<>	161:2cc1468da177	528
<>	161:2cc1468da177	529	/**
<>	161:2cc1468da177	530	* @brief Fills each TIM_EncoderInitStruct field with its default value
<>	161:2cc1468da177	531	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
<>	161:2cc1468da177	532	* @retval None
<>	161:2cc1468da177	533	*/
<>	161:2cc1468da177	534	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
<>	161:2cc1468da177	535	{
<>	161:2cc1468da177	536	/* Set the default configuration */
<>	161:2cc1468da177	537	TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
<>	161:2cc1468da177	538	TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
<>	161:2cc1468da177	539	TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	161:2cc1468da177	540	TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
<>	161:2cc1468da177	541	TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
<>	161:2cc1468da177	542	TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
<>	161:2cc1468da177	543	TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
<>	161:2cc1468da177	544	TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
<>	161:2cc1468da177	545	TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
<>	161:2cc1468da177	546	}
<>	161:2cc1468da177	547
<>	161:2cc1468da177	548	/**
<>	161:2cc1468da177	549	* @brief Configure the encoder interface of the timer instance.
<>	161:2cc1468da177	550	* @param TIMx Timer Instance
<>	161:2cc1468da177	551	* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
<>	161:2cc1468da177	552	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	553	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	554	* - ERROR: not applicable
<>	161:2cc1468da177	555	*/
<>	161:2cc1468da177	556	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct)
<>	161:2cc1468da177	557	{
<>	161:2cc1468da177	558	uint32_t tmpccmr1 = 0U;
<>	161:2cc1468da177	559	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	560
<>	161:2cc1468da177	561	/* Check the parameters */
<>	161:2cc1468da177	562	assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
<>	161:2cc1468da177	563	assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
<>	161:2cc1468da177	564	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
<>	161:2cc1468da177	565	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
<>	161:2cc1468da177	566	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
<>	161:2cc1468da177	567	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
<>	161:2cc1468da177	568	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
<>	161:2cc1468da177	569	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
<>	161:2cc1468da177	570	assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
<>	161:2cc1468da177	571	assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
<>	161:2cc1468da177	572
<>	161:2cc1468da177	573	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
<>	161:2cc1468da177	574	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	161:2cc1468da177	575
<>	161:2cc1468da177	576	/* Get the TIMx CCMR1 register value */
<>	161:2cc1468da177	577	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	161:2cc1468da177	578
<>	161:2cc1468da177	579	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	580	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	581
<>	161:2cc1468da177	582	/* Configure TI1 */
<>	161:2cc1468da177	583	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
<>	161:2cc1468da177	584	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
<>	161:2cc1468da177	585	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
<>	161:2cc1468da177	586	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
<>	161:2cc1468da177	587
<>	161:2cc1468da177	588	/* Configure TI2 */
<>	161:2cc1468da177	589	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC);
<>	161:2cc1468da177	590	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
<>	161:2cc1468da177	591	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
<>	161:2cc1468da177	592	tmpccmr1 \|= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
<>	161:2cc1468da177	593
<>	161:2cc1468da177	594	/* Set TI1 and TI2 polarity and enable TI1 and TI2 */
<>	161:2cc1468da177	595	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	161:2cc1468da177	596	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
<>	161:2cc1468da177	597	tmpccer \|= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
<>	161:2cc1468da177	598	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	161:2cc1468da177	599
<>	161:2cc1468da177	600	/* Set encoder mode */
<>	161:2cc1468da177	601	LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
<>	161:2cc1468da177	602
<>	161:2cc1468da177	603	/* Write to TIMx CCMR1 */
<>	161:2cc1468da177	604	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	161:2cc1468da177	605
<>	161:2cc1468da177	606	/* Write to TIMx CCER */
<>	161:2cc1468da177	607	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	608
<>	161:2cc1468da177	609	return SUCCESS;
<>	161:2cc1468da177	610	}
<>	161:2cc1468da177	611
<>	161:2cc1468da177	612	/**
<>	161:2cc1468da177	613	* @brief Set the fields of the TIMx Hall sensor interface configuration data
<>	161:2cc1468da177	614	* structure to their default values.
<>	161:2cc1468da177	615	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
<>	161:2cc1468da177	616	* @retval None
<>	161:2cc1468da177	617	*/
<>	161:2cc1468da177	618	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
<>	161:2cc1468da177	619	{
<>	161:2cc1468da177	620	/* Set the default configuration */
<>	161:2cc1468da177	621	TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
<>	161:2cc1468da177	622	TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
<>	161:2cc1468da177	623	TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
<>	161:2cc1468da177	624	TIM_HallSensorInitStruct->CommutationDelay = 0U;
<>	161:2cc1468da177	625	}
<>	161:2cc1468da177	626
<>	161:2cc1468da177	627	/**
<>	161:2cc1468da177	628	* @brief Configure the Hall sensor interface of the timer instance.
<>	161:2cc1468da177	629	* @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
<>	161:2cc1468da177	630	* to the TI1 input channel
<>	161:2cc1468da177	631	* @note TIMx slave mode controller is configured in reset mode.
<>	161:2cc1468da177	632	Selected internal trigger is TI1F_ED.
<>	161:2cc1468da177	633	* @note Channel 1 is configured as input, IC1 is mapped on TRC.
<>	161:2cc1468da177	634	* @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
<>	161:2cc1468da177	635	* between 2 changes on the inputs. It gives information about motor speed.
<>	161:2cc1468da177	636	* @note Channel 2 is configured in output PWM 2 mode.
<>	161:2cc1468da177	637	* @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
<>	161:2cc1468da177	638	* @note OC2REF is selected as trigger output on TRGO.
<>	161:2cc1468da177	639	* @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
<>	161:2cc1468da177	640	* when TIMx operates in Hall sensor interface mode.
<>	161:2cc1468da177	641	* @param TIMx Timer Instance
<>	161:2cc1468da177	642	* @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
<>	161:2cc1468da177	643	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	644	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	645	* - ERROR: not applicable
<>	161:2cc1468da177	646	*/
<>	161:2cc1468da177	647	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct)
<>	161:2cc1468da177	648	{
<>	161:2cc1468da177	649	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	650	uint32_t tmpccmr1 = 0U;
<>	161:2cc1468da177	651	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	652	uint32_t tmpsmcr = 0U;
<>	161:2cc1468da177	653
<>	161:2cc1468da177	654	/* Check the parameters */
<>	161:2cc1468da177	655	assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
<>	161:2cc1468da177	656	assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
<>	161:2cc1468da177	657	assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
<>	161:2cc1468da177	658	assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
<>	161:2cc1468da177	659
<>	161:2cc1468da177	660	/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
<>	161:2cc1468da177	661	TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	161:2cc1468da177	662
<>	161:2cc1468da177	663	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	664	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	665
<>	161:2cc1468da177	666	/* Get the TIMx CCMR1 register value */
<>	161:2cc1468da177	667	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	161:2cc1468da177	668
<>	161:2cc1468da177	669	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	670	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	671
<>	161:2cc1468da177	672	/* Get the TIMx SMCR register value */
<>	161:2cc1468da177	673	tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
<>	161:2cc1468da177	674
<>	161:2cc1468da177	675	/* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
<>	161:2cc1468da177	676	tmpcr2 \|= TIM_CR2_TI1S;
<>	161:2cc1468da177	677
<>	161:2cc1468da177	678	/* OC2REF signal is used as trigger output (TRGO) */
<>	161:2cc1468da177	679	tmpcr2 \|= LL_TIM_TRGO_OC2REF;
<>	161:2cc1468da177	680
<>	161:2cc1468da177	681	/* Configure the slave mode controller */
<>	161:2cc1468da177	682	tmpsmcr &= (uint32_t)~(TIM_SMCR_TS \| TIM_SMCR_SMS);
<>	161:2cc1468da177	683	tmpsmcr \|= LL_TIM_TS_TI1F_ED;
<>	161:2cc1468da177	684	tmpsmcr \|= LL_TIM_SLAVEMODE_RESET;
<>	161:2cc1468da177	685
<>	161:2cc1468da177	686	/* Configure input channel 1 */
<>	161:2cc1468da177	687	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC);
<>	161:2cc1468da177	688	tmpccmr1 \|= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
<>	161:2cc1468da177	689	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
<>	161:2cc1468da177	690	tmpccmr1 \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
<>	161:2cc1468da177	691
<>	161:2cc1468da177	692	/* Configure input channel 2 */
<>	161:2cc1468da177	693	tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M \| TIM_CCMR1_OC2FE \| TIM_CCMR1_OC2PE \| TIM_CCMR1_OC2CE);
<>	161:2cc1468da177	694	tmpccmr1 \|= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
<>	161:2cc1468da177	695
<>	161:2cc1468da177	696	/* Set Channel 1 polarity and enable Channel 1 and Channel2 */
<>	161:2cc1468da177	697	tmpccer &= (uint32_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP \| TIM_CCER_CC2P \| TIM_CCER_CC2NP);
<>	161:2cc1468da177	698	tmpccer \|= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
<>	161:2cc1468da177	699	tmpccer \|= (uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E);
<>	161:2cc1468da177	700
<>	161:2cc1468da177	701	/* Write to TIMx CR2 */
<>	161:2cc1468da177	702	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	703
<>	161:2cc1468da177	704	/* Write to TIMx SMCR */
<>	161:2cc1468da177	705	LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
<>	161:2cc1468da177	706
<>	161:2cc1468da177	707	/* Write to TIMx CCMR1 */
<>	161:2cc1468da177	708	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	161:2cc1468da177	709
<>	161:2cc1468da177	710	/* Write to TIMx CCER */
<>	161:2cc1468da177	711	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	712
<>	161:2cc1468da177	713	/* Write to TIMx CCR2 */
<>	161:2cc1468da177	714	LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
<>	161:2cc1468da177	715
<>	161:2cc1468da177	716	return SUCCESS;
<>	161:2cc1468da177	717	}
<>	161:2cc1468da177	718
<>	161:2cc1468da177	719	/**
<>	161:2cc1468da177	720	* @brief Set the fields of the Break and Dead Time configuration data structure
<>	161:2cc1468da177	721	* to their default values.
<>	161:2cc1468da177	722	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
<>	161:2cc1468da177	723	* @retval None
<>	161:2cc1468da177	724	*/
<>	161:2cc1468da177	725	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
<>	161:2cc1468da177	726	{
<>	161:2cc1468da177	727	/* Set the default configuration */
<>	161:2cc1468da177	728	TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
<>	161:2cc1468da177	729	TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
<>	161:2cc1468da177	730	TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
<>	161:2cc1468da177	731	TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
<>	161:2cc1468da177	732	TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
<>	161:2cc1468da177	733	TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
<>	161:2cc1468da177	734	TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
<>	161:2cc1468da177	735	TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
<>	161:2cc1468da177	736	TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
<>	161:2cc1468da177	737	TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
<>	161:2cc1468da177	738	TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
<>	161:2cc1468da177	739	}
<>	161:2cc1468da177	740
<>	161:2cc1468da177	741	/**
<>	161:2cc1468da177	742	* @brief Configure the Break and Dead Time feature of the timer instance.
<>	161:2cc1468da177	743	* @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
<>	161:2cc1468da177	744	* and DTG[7:0] can be write-locked depending on the LOCK configuration, it
<>	161:2cc1468da177	745	* can be necessary to configure all of them during the first write access to
<>	161:2cc1468da177	746	* the TIMx_BDTR register.
<>	161:2cc1468da177	747	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	748	* a timer instance provides a break input.
<>	161:2cc1468da177	749	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	750	* a timer instance provides a second break input.
<>	161:2cc1468da177	751	* @param TIMx Timer Instance
<>	161:2cc1468da177	752	* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
<>	161:2cc1468da177	753	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	754	* - SUCCESS: Break and Dead Time is initialized
<>	161:2cc1468da177	755	* - ERROR: not applicable
<>	161:2cc1468da177	756	*/
<>	161:2cc1468da177	757	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct)
<>	161:2cc1468da177	758	{
<>	161:2cc1468da177	759	uint32_t tmpbdtr = 0;
<>	161:2cc1468da177	760
<>	161:2cc1468da177	761	/* Check the parameters */
<>	161:2cc1468da177	762	assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
<>	161:2cc1468da177	763	assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
<>	161:2cc1468da177	764	assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
<>	161:2cc1468da177	765	assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
<>	161:2cc1468da177	766	assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
<>	161:2cc1468da177	767	assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
<>	161:2cc1468da177	768	assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
<>	161:2cc1468da177	769
<>	161:2cc1468da177	770	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<>	161:2cc1468da177	771	the OSSI State, the dead time value and the Automatic Output Enable Bit */
<>	161:2cc1468da177	772
<>	161:2cc1468da177	773	/* Set the BDTR bits */
<>	161:2cc1468da177	774	MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
<>	161:2cc1468da177	775	MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
<>	161:2cc1468da177	776	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
<>	161:2cc1468da177	777	MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
<>	161:2cc1468da177	778	MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
<>	161:2cc1468da177	779	MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
<>	161:2cc1468da177	780	MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
<>	161:2cc1468da177	781	MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
<>	161:2cc1468da177	782	if (IS_TIM_ADVANCED_INSTANCE(TIMx))
<>	161:2cc1468da177	783	{
<>	161:2cc1468da177	784	assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
<>	161:2cc1468da177	785	MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
<>	161:2cc1468da177	786	}
<>	161:2cc1468da177	787
<>	161:2cc1468da177	788	if (IS_TIM_BKIN2_INSTANCE(TIMx))
<>	161:2cc1468da177	789	{
<>	161:2cc1468da177	790	assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
<>	161:2cc1468da177	791	assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
<>	161:2cc1468da177	792	assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
<>	161:2cc1468da177	793
<>	161:2cc1468da177	794	/* Set the BREAK2 input related BDTR bit-fields */
<>	161:2cc1468da177	795	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
<>	161:2cc1468da177	796	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
<>	161:2cc1468da177	797	MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
<>	161:2cc1468da177	798	}
<>	161:2cc1468da177	799
<>	161:2cc1468da177	800	/* Set TIMx_BDTR */
<>	161:2cc1468da177	801	LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
<>	161:2cc1468da177	802
<>	161:2cc1468da177	803	return SUCCESS;
<>	161:2cc1468da177	804	}
<>	161:2cc1468da177	805	/**
<>	161:2cc1468da177	806	* @}
<>	161:2cc1468da177	807	*/
<>	161:2cc1468da177	808
<>	161:2cc1468da177	809	/**
<>	161:2cc1468da177	810	* @}
<>	161:2cc1468da177	811	*/
<>	161:2cc1468da177	812
<>	161:2cc1468da177	813	/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
<>	161:2cc1468da177	814	* @brief Private functions
<>	161:2cc1468da177	815	* @{
<>	161:2cc1468da177	816	*/
<>	161:2cc1468da177	817	/**
<>	161:2cc1468da177	818	* @brief Configure the TIMx output channel 1.
<>	161:2cc1468da177	819	* @param TIMx Timer Instance
<>	161:2cc1468da177	820	* @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
<>	161:2cc1468da177	821	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	822	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	823	* - ERROR: not applicable
<>	161:2cc1468da177	824	*/
<>	161:2cc1468da177	825	static ErrorStatus OC1Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	826	{
<>	161:2cc1468da177	827	uint32_t tmpccmr1 = 0U;
<>	161:2cc1468da177	828	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	829	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	830
<>	161:2cc1468da177	831	/* Check the parameters */
<>	161:2cc1468da177	832	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	161:2cc1468da177	833	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	834	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	835	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	836	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	837	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	838
<>	161:2cc1468da177	839	/* Disable the Channel 1: Reset the CC1E Bit */
<>	161:2cc1468da177	840	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
<>	161:2cc1468da177	841
<>	161:2cc1468da177	842	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	843	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	844
<>	161:2cc1468da177	845	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	846	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	847
<>	161:2cc1468da177	848	/* Get the TIMx CCMR1 register value */
<>	161:2cc1468da177	849	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	161:2cc1468da177	850
<>	161:2cc1468da177	851	/* Reset Capture/Compare selection Bits */
<>	161:2cc1468da177	852	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
<>	161:2cc1468da177	853
<>	161:2cc1468da177	854	/* Set the Output Compare Mode */
<>	161:2cc1468da177	855	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
<>	161:2cc1468da177	856
<>	161:2cc1468da177	857	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	858	MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
<>	161:2cc1468da177	859
<>	161:2cc1468da177	860	/* Set the Output State */
<>	161:2cc1468da177	861	MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
<>	161:2cc1468da177	862
<>	161:2cc1468da177	863	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	864	{
<>	161:2cc1468da177	865	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	866	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	867
<>	161:2cc1468da177	868	/* Set the complementary output Polarity */
<>	161:2cc1468da177	869	MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
<>	161:2cc1468da177	870
<>	161:2cc1468da177	871	/* Set the complementary output State */
<>	161:2cc1468da177	872	MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
<>	161:2cc1468da177	873
<>	161:2cc1468da177	874	/* Set the Output Idle state */
<>	161:2cc1468da177	875	MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
<>	161:2cc1468da177	876
<>	161:2cc1468da177	877	/* Set the complementary output Idle state */
<>	161:2cc1468da177	878	MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
<>	161:2cc1468da177	879	}
<>	161:2cc1468da177	880
<>	161:2cc1468da177	881	/* Write to TIMx CR2 */
<>	161:2cc1468da177	882	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	883
<>	161:2cc1468da177	884	/* Write to TIMx CCMR1 */
<>	161:2cc1468da177	885	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	161:2cc1468da177	886
<>	161:2cc1468da177	887	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	888	LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	889
<>	161:2cc1468da177	890	/* Write to TIMx CCER */
<>	161:2cc1468da177	891	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	892
<>	161:2cc1468da177	893	return SUCCESS;
<>	161:2cc1468da177	894	}
<>	161:2cc1468da177	895
<>	161:2cc1468da177	896	/**
<>	161:2cc1468da177	897	* @brief Configure the TIMx output channel 2.
<>	161:2cc1468da177	898	* @param TIMx Timer Instance
<>	161:2cc1468da177	899	* @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
<>	161:2cc1468da177	900	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	901	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	902	* - ERROR: not applicable
<>	161:2cc1468da177	903	*/
<>	161:2cc1468da177	904	static ErrorStatus OC2Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	905	{
<>	161:2cc1468da177	906	uint32_t tmpccmr1 = 0U;
<>	161:2cc1468da177	907	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	908	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	909
<>	161:2cc1468da177	910	/* Check the parameters */
<>	161:2cc1468da177	911	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
<>	161:2cc1468da177	912	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	913	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	914	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	915	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	916	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	917
<>	161:2cc1468da177	918	/* Disable the Channel 2: Reset the CC2E Bit */
<>	161:2cc1468da177	919	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
<>	161:2cc1468da177	920
<>	161:2cc1468da177	921	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	922	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	923
<>	161:2cc1468da177	924	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	925	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	926
<>	161:2cc1468da177	927	/* Get the TIMx CCMR1 register value */
<>	161:2cc1468da177	928	tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
<>	161:2cc1468da177	929
<>	161:2cc1468da177	930	/* Reset Capture/Compare selection Bits */
<>	161:2cc1468da177	931	CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
<>	161:2cc1468da177	932
<>	161:2cc1468da177	933	/* Select the Output Compare Mode */
<>	161:2cc1468da177	934	MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
<>	161:2cc1468da177	935
<>	161:2cc1468da177	936	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	937	MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
<>	161:2cc1468da177	938
<>	161:2cc1468da177	939	/* Set the Output State */
<>	161:2cc1468da177	940	MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
<>	161:2cc1468da177	941
<>	161:2cc1468da177	942	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	943	{
<>	161:2cc1468da177	944	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	945	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	946
<>	161:2cc1468da177	947	/* Set the complementary output Polarity */
<>	161:2cc1468da177	948	MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
<>	161:2cc1468da177	949
<>	161:2cc1468da177	950	/* Set the complementary output State */
<>	161:2cc1468da177	951	MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
<>	161:2cc1468da177	952
<>	161:2cc1468da177	953	/* Set the Output Idle state */
<>	161:2cc1468da177	954	MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
<>	161:2cc1468da177	955
<>	161:2cc1468da177	956	/* Set the complementary output Idle state */
<>	161:2cc1468da177	957	MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
<>	161:2cc1468da177	958	}
<>	161:2cc1468da177	959
<>	161:2cc1468da177	960	/* Write to TIMx CR2 */
<>	161:2cc1468da177	961	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	962
<>	161:2cc1468da177	963	/* Write to TIMx CCMR1 */
<>	161:2cc1468da177	964	LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
<>	161:2cc1468da177	965
<>	161:2cc1468da177	966	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	967	LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	968
<>	161:2cc1468da177	969	/* Write to TIMx CCER */
<>	161:2cc1468da177	970	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	971
<>	161:2cc1468da177	972	return SUCCESS;
<>	161:2cc1468da177	973	}
<>	161:2cc1468da177	974
<>	161:2cc1468da177	975	/**
<>	161:2cc1468da177	976	* @brief Configure the TIMx output channel 3.
<>	161:2cc1468da177	977	* @param TIMx Timer Instance
<>	161:2cc1468da177	978	* @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
<>	161:2cc1468da177	979	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	980	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	981	* - ERROR: not applicable
<>	161:2cc1468da177	982	*/
<>	161:2cc1468da177	983	static ErrorStatus OC3Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	984	{
<>	161:2cc1468da177	985	uint32_t tmpccmr2 = 0U;
<>	161:2cc1468da177	986	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	987	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	988
<>	161:2cc1468da177	989	/* Check the parameters */
<>	161:2cc1468da177	990	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
<>	161:2cc1468da177	991	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	992	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	993	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	994	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	995	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	996
<>	161:2cc1468da177	997	/* Disable the Channel 3: Reset the CC3E Bit */
<>	161:2cc1468da177	998	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
<>	161:2cc1468da177	999
<>	161:2cc1468da177	1000	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	1001	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	1002
<>	161:2cc1468da177	1003	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	1004	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	1005
<>	161:2cc1468da177	1006	/* Get the TIMx CCMR2 register value */
<>	161:2cc1468da177	1007	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
<>	161:2cc1468da177	1008
<>	161:2cc1468da177	1009	/* Reset Capture/Compare selection Bits */
<>	161:2cc1468da177	1010	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
<>	161:2cc1468da177	1011
<>	161:2cc1468da177	1012	/* Select the Output Compare Mode */
<>	161:2cc1468da177	1013	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
<>	161:2cc1468da177	1014
<>	161:2cc1468da177	1015	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	1016	MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
<>	161:2cc1468da177	1017
<>	161:2cc1468da177	1018	/* Set the Output State */
<>	161:2cc1468da177	1019	MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
<>	161:2cc1468da177	1020
<>	161:2cc1468da177	1021	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	1022	{
<>	161:2cc1468da177	1023	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	1024	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	1025
<>	161:2cc1468da177	1026	/* Set the complementary output Polarity */
<>	161:2cc1468da177	1027	MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
<>	161:2cc1468da177	1028
<>	161:2cc1468da177	1029	/* Set the complementary output State */
<>	161:2cc1468da177	1030	MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
<>	161:2cc1468da177	1031
<>	161:2cc1468da177	1032	/* Set the Output Idle state */
<>	161:2cc1468da177	1033	MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
<>	161:2cc1468da177	1034
<>	161:2cc1468da177	1035	/* Set the complementary output Idle state */
<>	161:2cc1468da177	1036	MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
<>	161:2cc1468da177	1037	}
<>	161:2cc1468da177	1038
<>	161:2cc1468da177	1039	/* Write to TIMx CR2 */
<>	161:2cc1468da177	1040	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	1041
<>	161:2cc1468da177	1042	/* Write to TIMx CCMR2 */
<>	161:2cc1468da177	1043	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
<>	161:2cc1468da177	1044
<>	161:2cc1468da177	1045	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	1046	LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	1047
<>	161:2cc1468da177	1048	/* Write to TIMx CCER */
<>	161:2cc1468da177	1049	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	1050
<>	161:2cc1468da177	1051	return SUCCESS;
<>	161:2cc1468da177	1052	}
<>	161:2cc1468da177	1053
<>	161:2cc1468da177	1054	/**
<>	161:2cc1468da177	1055	* @brief Configure the TIMx output channel 4.
<>	161:2cc1468da177	1056	* @param TIMx Timer Instance
<>	161:2cc1468da177	1057	* @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
<>	161:2cc1468da177	1058	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1059	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1060	* - ERROR: not applicable
<>	161:2cc1468da177	1061	*/
<>	161:2cc1468da177	1062	static ErrorStatus OC4Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	1063	{
<>	161:2cc1468da177	1064	uint32_t tmpccmr2 = 0U;
<>	161:2cc1468da177	1065	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	1066	uint32_t tmpcr2 = 0U;
<>	161:2cc1468da177	1067
<>	161:2cc1468da177	1068	/* Check the parameters */
<>	161:2cc1468da177	1069	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<>	161:2cc1468da177	1070	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	1071	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	1072	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	1073	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	1074	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	1075
<>	161:2cc1468da177	1076	/* Disable the Channel 4: Reset the CC4E Bit */
<>	161:2cc1468da177	1077	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
<>	161:2cc1468da177	1078
<>	161:2cc1468da177	1079	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	1080	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	1081
<>	161:2cc1468da177	1082	/* Get the TIMx CR2 register value */
<>	161:2cc1468da177	1083	tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
<>	161:2cc1468da177	1084
<>	161:2cc1468da177	1085	/* Get the TIMx CCMR2 register value */
<>	161:2cc1468da177	1086	tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
<>	161:2cc1468da177	1087
<>	161:2cc1468da177	1088	/* Reset Capture/Compare selection Bits */
<>	161:2cc1468da177	1089	CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
<>	161:2cc1468da177	1090
<>	161:2cc1468da177	1091	/* Select the Output Compare Mode */
<>	161:2cc1468da177	1092	MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
<>	161:2cc1468da177	1093
<>	161:2cc1468da177	1094	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	1095	MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
<>	161:2cc1468da177	1096
<>	161:2cc1468da177	1097	/* Set the Output State */
<>	161:2cc1468da177	1098	MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
<>	161:2cc1468da177	1099
<>	161:2cc1468da177	1100	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	1101	{
<>	161:2cc1468da177	1102	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	1103	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	1104
<>	161:2cc1468da177	1105	/* Set the Output Idle state */
<>	161:2cc1468da177	1106	MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
<>	161:2cc1468da177	1107	}
<>	161:2cc1468da177	1108
<>	161:2cc1468da177	1109	/* Write to TIMx CR2 */
<>	161:2cc1468da177	1110	LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
<>	161:2cc1468da177	1111
<>	161:2cc1468da177	1112	/* Write to TIMx CCMR2 */
<>	161:2cc1468da177	1113	LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
<>	161:2cc1468da177	1114
<>	161:2cc1468da177	1115	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	1116	LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	1117
<>	161:2cc1468da177	1118	/* Write to TIMx CCER */
<>	161:2cc1468da177	1119	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	1120
<>	161:2cc1468da177	1121	return SUCCESS;
<>	161:2cc1468da177	1122	}
<>	161:2cc1468da177	1123
<>	161:2cc1468da177	1124	/**
<>	161:2cc1468da177	1125	* @brief Configure the TIMx output channel 5.
<>	161:2cc1468da177	1126	* @param TIMx Timer Instance
<>	161:2cc1468da177	1127	* @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
<>	161:2cc1468da177	1128	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1129	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1130	* - ERROR: not applicable
<>	161:2cc1468da177	1131	*/
<>	161:2cc1468da177	1132	static ErrorStatus OC5Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	1133	{
<>	161:2cc1468da177	1134	uint32_t tmpccmr3 = 0U;
<>	161:2cc1468da177	1135	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	1136
<>	161:2cc1468da177	1137	/* Check the parameters */
<>	161:2cc1468da177	1138	assert_param(IS_TIM_CC5_INSTANCE(TIMx));
<>	161:2cc1468da177	1139	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	1140	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	1141	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	1142	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	1143	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	1144
<>	161:2cc1468da177	1145	/* Disable the Channel 5: Reset the CC5E Bit */
<>	161:2cc1468da177	1146	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
<>	161:2cc1468da177	1147
<>	161:2cc1468da177	1148	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	1149	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	1150
<>	161:2cc1468da177	1151	/* Get the TIMx CCMR3 register value */
<>	161:2cc1468da177	1152	tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
<>	161:2cc1468da177	1153
<>	161:2cc1468da177	1154	/* Select the Output Compare Mode */
<>	161:2cc1468da177	1155	MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
<>	161:2cc1468da177	1156
<>	161:2cc1468da177	1157	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	1158	MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
<>	161:2cc1468da177	1159
<>	161:2cc1468da177	1160	/* Set the Output State */
<>	161:2cc1468da177	1161	MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
<>	161:2cc1468da177	1162
<>	161:2cc1468da177	1163	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	1164	{
<>	161:2cc1468da177	1165	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	1166	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	1167
<>	161:2cc1468da177	1168	/* Set the Output Idle state */
<>	161:2cc1468da177	1169	MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
<>	161:2cc1468da177	1170
<>	161:2cc1468da177	1171	}
<>	161:2cc1468da177	1172
<>	161:2cc1468da177	1173	/* Write to TIMx CCMR3 */
<>	161:2cc1468da177	1174	LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
<>	161:2cc1468da177	1175
<>	161:2cc1468da177	1176	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	1177	LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	1178
<>	161:2cc1468da177	1179	/* Write to TIMx CCER */
<>	161:2cc1468da177	1180	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	1181
<>	161:2cc1468da177	1182	return SUCCESS;
<>	161:2cc1468da177	1183	}
<>	161:2cc1468da177	1184
<>	161:2cc1468da177	1185	/**
<>	161:2cc1468da177	1186	* @brief Configure the TIMx output channel 6.
<>	161:2cc1468da177	1187	* @param TIMx Timer Instance
<>	161:2cc1468da177	1188	* @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
<>	161:2cc1468da177	1189	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1190	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1191	* - ERROR: not applicable
<>	161:2cc1468da177	1192	*/
<>	161:2cc1468da177	1193	static ErrorStatus OC6Config(TIM_TypeDef TIMx, LL_TIM_OC_InitTypeDef TIM_OCInitStruct)
<>	161:2cc1468da177	1194	{
<>	161:2cc1468da177	1195	uint32_t tmpccmr3 = 0U;
<>	161:2cc1468da177	1196	uint32_t tmpccer = 0U;
<>	161:2cc1468da177	1197
<>	161:2cc1468da177	1198	/* Check the parameters */
<>	161:2cc1468da177	1199	assert_param(IS_TIM_CC6_INSTANCE(TIMx));
<>	161:2cc1468da177	1200	assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
<>	161:2cc1468da177	1201	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
<>	161:2cc1468da177	1202	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
<>	161:2cc1468da177	1203	assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
<>	161:2cc1468da177	1204	assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
<>	161:2cc1468da177	1205
<>	161:2cc1468da177	1206	/* Disable the Channel 5: Reset the CC6E Bit */
<>	161:2cc1468da177	1207	CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
<>	161:2cc1468da177	1208
<>	161:2cc1468da177	1209	/* Get the TIMx CCER register value */
<>	161:2cc1468da177	1210	tmpccer = LL_TIM_ReadReg(TIMx, CCER);
<>	161:2cc1468da177	1211
<>	161:2cc1468da177	1212	/* Get the TIMx CCMR3 register value */
<>	161:2cc1468da177	1213	tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
<>	161:2cc1468da177	1214
<>	161:2cc1468da177	1215	/* Select the Output Compare Mode */
<>	161:2cc1468da177	1216	MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
<>	161:2cc1468da177	1217
<>	161:2cc1468da177	1218	/* Set the Output Compare Polarity */
<>	161:2cc1468da177	1219	MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
<>	161:2cc1468da177	1220
<>	161:2cc1468da177	1221	/* Set the Output State */
<>	161:2cc1468da177	1222	MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
<>	161:2cc1468da177	1223
<>	161:2cc1468da177	1224	if (IS_TIM_BREAK_INSTANCE(TIMx))
<>	161:2cc1468da177	1225	{
<>	161:2cc1468da177	1226	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
<>	161:2cc1468da177	1227	assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
<>	161:2cc1468da177	1228
<>	161:2cc1468da177	1229	/* Set the Output Idle state */
<>	161:2cc1468da177	1230	MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
<>	161:2cc1468da177	1231	}
<>	161:2cc1468da177	1232
<>	161:2cc1468da177	1233	/* Write to TIMx CCMR3 */
<>	161:2cc1468da177	1234	LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
<>	161:2cc1468da177	1235
<>	161:2cc1468da177	1236	/* Set the Capture Compare Register value */
<>	161:2cc1468da177	1237	LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
<>	161:2cc1468da177	1238
<>	161:2cc1468da177	1239	/* Write to TIMx CCER */
<>	161:2cc1468da177	1240	LL_TIM_WriteReg(TIMx, CCER, tmpccer);
<>	161:2cc1468da177	1241
<>	161:2cc1468da177	1242	return SUCCESS;
<>	161:2cc1468da177	1243	}
<>	161:2cc1468da177	1244
<>	161:2cc1468da177	1245	/**
<>	161:2cc1468da177	1246	* @brief Configure the TIMx input channel 1.
<>	161:2cc1468da177	1247	* @param TIMx Timer Instance
<>	161:2cc1468da177	1248	* @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
<>	161:2cc1468da177	1249	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1250	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1251	* - ERROR: not applicable
<>	161:2cc1468da177	1252	*/
<>	161:2cc1468da177	1253	static ErrorStatus IC1Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	161:2cc1468da177	1254	{
<>	161:2cc1468da177	1255	/* Check the parameters */
<>	161:2cc1468da177	1256	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<>	161:2cc1468da177	1257	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	161:2cc1468da177	1258	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	161:2cc1468da177	1259	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	161:2cc1468da177	1260	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	161:2cc1468da177	1261
<>	161:2cc1468da177	1262	/* Disable the Channel 1: Reset the CC1E Bit */
<>	161:2cc1468da177	1263	TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
<>	161:2cc1468da177	1264
<>	161:2cc1468da177	1265	/* Select the Input and set the filter and the prescaler value */
<>	161:2cc1468da177	1266	MODIFY_REG(TIMx->CCMR1,
<>	161:2cc1468da177	1267	(TIM_CCMR1_CC1S \| TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC),
<>	161:2cc1468da177	1268	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
<>	161:2cc1468da177	1269
<>	161:2cc1468da177	1270	/* Select the Polarity and set the CC1E Bit */
<>	161:2cc1468da177	1271	MODIFY_REG(TIMx->CCER,
<>	161:2cc1468da177	1272	(TIM_CCER_CC1P \| TIM_CCER_CC1NP),
<>	161:2cc1468da177	1273	(TIM_ICInitStruct->ICPolarity \| TIM_CCER_CC1E));
<>	161:2cc1468da177	1274
<>	161:2cc1468da177	1275	return SUCCESS;
<>	161:2cc1468da177	1276	}
<>	161:2cc1468da177	1277
<>	161:2cc1468da177	1278	/**
<>	161:2cc1468da177	1279	* @brief Configure the TIMx input channel 2.
<>	161:2cc1468da177	1280	* @param TIMx Timer Instance
<>	161:2cc1468da177	1281	* @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
<>	161:2cc1468da177	1282	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1283	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1284	* - ERROR: not applicable
<>	161:2cc1468da177	1285	*/
<>	161:2cc1468da177	1286	static ErrorStatus IC2Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	161:2cc1468da177	1287	{
<>	161:2cc1468da177	1288	/* Check the parameters */
<>	161:2cc1468da177	1289	assert_param(IS_TIM_CC2_INSTANCE(TIMx));
<>	161:2cc1468da177	1290	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	161:2cc1468da177	1291	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	161:2cc1468da177	1292	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	161:2cc1468da177	1293	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	161:2cc1468da177	1294
<>	161:2cc1468da177	1295	/* Disable the Channel 2: Reset the CC2E Bit */
<>	161:2cc1468da177	1296	TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
<>	161:2cc1468da177	1297
<>	161:2cc1468da177	1298	/* Select the Input and set the filter and the prescaler value */
<>	161:2cc1468da177	1299	MODIFY_REG(TIMx->CCMR1,
<>	161:2cc1468da177	1300	(TIM_CCMR1_CC2S \| TIM_CCMR1_IC2F \| TIM_CCMR1_IC2PSC),
<>	161:2cc1468da177	1301	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
<>	161:2cc1468da177	1302
<>	161:2cc1468da177	1303	/* Select the Polarity and set the CC2E Bit */
<>	161:2cc1468da177	1304	MODIFY_REG(TIMx->CCER,
<>	161:2cc1468da177	1305	(TIM_CCER_CC2P \| TIM_CCER_CC2NP),
<>	161:2cc1468da177	1306	((TIM_ICInitStruct->ICPolarity << 4U) \| TIM_CCER_CC2E));
<>	161:2cc1468da177	1307
<>	161:2cc1468da177	1308	return SUCCESS;
<>	161:2cc1468da177	1309	}
<>	161:2cc1468da177	1310
<>	161:2cc1468da177	1311	/**
<>	161:2cc1468da177	1312	* @brief Configure the TIMx input channel 3.
<>	161:2cc1468da177	1313	* @param TIMx Timer Instance
<>	161:2cc1468da177	1314	* @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
<>	161:2cc1468da177	1315	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1316	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1317	* - ERROR: not applicable
<>	161:2cc1468da177	1318	*/
<>	161:2cc1468da177	1319	static ErrorStatus IC3Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	161:2cc1468da177	1320	{
<>	161:2cc1468da177	1321	/* Check the parameters */
<>	161:2cc1468da177	1322	assert_param(IS_TIM_CC3_INSTANCE(TIMx));
<>	161:2cc1468da177	1323	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	161:2cc1468da177	1324	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	161:2cc1468da177	1325	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	161:2cc1468da177	1326	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	161:2cc1468da177	1327
<>	161:2cc1468da177	1328	/* Disable the Channel 3: Reset the CC3E Bit */
<>	161:2cc1468da177	1329	TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
<>	161:2cc1468da177	1330
<>	161:2cc1468da177	1331	/* Select the Input and set the filter and the prescaler value */
<>	161:2cc1468da177	1332	MODIFY_REG(TIMx->CCMR2,
<>	161:2cc1468da177	1333	(TIM_CCMR2_CC3S \| TIM_CCMR2_IC3F \| TIM_CCMR2_IC3PSC),
<>	161:2cc1468da177	1334	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 16U);
<>	161:2cc1468da177	1335
<>	161:2cc1468da177	1336	/* Select the Polarity and set the CC3E Bit */
<>	161:2cc1468da177	1337	MODIFY_REG(TIMx->CCER,
<>	161:2cc1468da177	1338	(TIM_CCER_CC3P \| TIM_CCER_CC3NP),
<>	161:2cc1468da177	1339	((TIM_ICInitStruct->ICPolarity << 8U) \| TIM_CCER_CC3E));
<>	161:2cc1468da177	1340
<>	161:2cc1468da177	1341	return SUCCESS;
<>	161:2cc1468da177	1342	}
<>	161:2cc1468da177	1343
<>	161:2cc1468da177	1344	/**
<>	161:2cc1468da177	1345	* @brief Configure the TIMx input channel 4.
<>	161:2cc1468da177	1346	* @param TIMx Timer Instance
<>	161:2cc1468da177	1347	* @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
<>	161:2cc1468da177	1348	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	1349	* - SUCCESS: TIMx registers are de-initialized
<>	161:2cc1468da177	1350	* - ERROR: not applicable
<>	161:2cc1468da177	1351	*/
<>	161:2cc1468da177	1352	static ErrorStatus IC4Config(TIM_TypeDef TIMx, LL_TIM_IC_InitTypeDef TIM_ICInitStruct)
<>	161:2cc1468da177	1353	{
<>	161:2cc1468da177	1354	/* Check the parameters */
<>	161:2cc1468da177	1355	assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<>	161:2cc1468da177	1356	assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
<>	161:2cc1468da177	1357	assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
<>	161:2cc1468da177	1358	assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
<>	161:2cc1468da177	1359	assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
<>	161:2cc1468da177	1360
<>	161:2cc1468da177	1361	/* Disable the Channel 4: Reset the CC4E Bit */
<>	161:2cc1468da177	1362	TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
<>	161:2cc1468da177	1363
<>	161:2cc1468da177	1364	/* Select the Input and set the filter and the prescaler value */
<>	161:2cc1468da177	1365	MODIFY_REG(TIMx->CCMR2,
<>	161:2cc1468da177	1366	(TIM_CCMR2_CC4S \| TIM_CCMR2_IC4F \| TIM_CCMR2_IC4PSC),
<>	161:2cc1468da177	1367	(TIM_ICInitStruct->ICActiveInput \| TIM_ICInitStruct->ICFilter \| TIM_ICInitStruct->ICPrescaler) >> 8U);
<>	161:2cc1468da177	1368
<>	161:2cc1468da177	1369	/* Select the Polarity and set the CC2E Bit */
<>	161:2cc1468da177	1370	MODIFY_REG(TIMx->CCER,
<>	161:2cc1468da177	1371	(TIM_CCER_CC4P \| TIM_CCER_CC4NP),
<>	161:2cc1468da177	1372	((TIM_ICInitStruct->ICPolarity << 12U) \| TIM_CCER_CC4E));
<>	161:2cc1468da177	1373
<>	161:2cc1468da177	1374	return SUCCESS;
<>	161:2cc1468da177	1375	}
<>	161:2cc1468da177	1376
<>	161:2cc1468da177	1377
<>	161:2cc1468da177	1378	/**
<>	161:2cc1468da177	1379	* @}
<>	161:2cc1468da177	1380	*/
<>	161:2cc1468da177	1381
<>	161:2cc1468da177	1382	/**
<>	161:2cc1468da177	1383	* @}
<>	161:2cc1468da177	1384	*/
<>	161:2cc1468da177	1385
<>	161:2cc1468da177	1386	#endif /* TIM1 \|\| TIM8 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\|TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM6 \|\| TIM7 */
<>	161:2cc1468da177	1387
<>	161:2cc1468da177	1388	/**
<>	161:2cc1468da177	1389	* @}
<>	161:2cc1468da177	1390	*/
<>	161:2cc1468da177	1391
<>	161:2cc1468da177	1392	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	1393
<>	161:2cc1468da177	1394	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/