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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_rcc.c
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	161:2cc1468da177	7	* @brief RCC LL module driver.
<>	161:2cc1468da177	8	******************************************************************************
<>	161:2cc1468da177	9	* @attention
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	12	*
<>	161:2cc1468da177	13	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	14	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	18	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	19	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	21	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	22	* without specific prior written permission.
<>	161:2cc1468da177	23	*
<>	161:2cc1468da177	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	34	*
<>	161:2cc1468da177	35	******************************************************************************
<>	161:2cc1468da177	36	*/
<>	161:2cc1468da177	37	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	38
<>	161:2cc1468da177	39	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	40	#include "stm32f7xx_ll_rcc.h"
<>	161:2cc1468da177	41	#ifdef USE_FULL_ASSERT
<>	161:2cc1468da177	42	#include "stm32_assert.h"
<>	161:2cc1468da177	43	#else
<>	161:2cc1468da177	44	#define assert_param(expr) ((void)0U)
<>	161:2cc1468da177	45	#endif
<>	161:2cc1468da177	46
<>	161:2cc1468da177	47	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	48	* @{
<>	161:2cc1468da177	49	*/
<>	161:2cc1468da177	50
<>	161:2cc1468da177	51	#if defined(RCC)
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	/** @addtogroup RCC_LL
<>	161:2cc1468da177	54	* @{
<>	161:2cc1468da177	55	*/
<>	161:2cc1468da177	56
<>	161:2cc1468da177	57	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	58	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	59	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	60	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	61	/** @addtogroup RCC_LL_Private_Macros
<>	161:2cc1468da177	62	* @{
<>	161:2cc1468da177	63	*/
<>	161:2cc1468da177	64	#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
<>	161:2cc1468da177	65	\|\| ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
<>	161:2cc1468da177	66	\|\| ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
<>	161:2cc1468da177	67	\|\| ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
<>	161:2cc1468da177	68
<>	161:2cc1468da177	69	#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
<>	161:2cc1468da177	70	\|\| ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
<>	161:2cc1468da177	71	\|\| ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
<>	161:2cc1468da177	72	\|\| ((__VALUE__) == LL_RCC_UART8_CLKSOURCE))
<>	161:2cc1468da177	73
<>	161:2cc1468da177	74	#if defined(I2C4)
<>	161:2cc1468da177	75	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<>	161:2cc1468da177	76	\|\| ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
<>	161:2cc1468da177	77	\|\| ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
<>	161:2cc1468da177	78	\|\| ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
<>	161:2cc1468da177	79	#else
<>	161:2cc1468da177	80	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<>	161:2cc1468da177	81	\|\| ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
<>	161:2cc1468da177	82	\|\| ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
<>	161:2cc1468da177	83	#endif /* I2C4 */
<>	161:2cc1468da177	84
<>	161:2cc1468da177	85	#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
<>	161:2cc1468da177	86
<>	161:2cc1468da177	87	#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
<>	161:2cc1468da177	88	\|\| ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
<>	161:2cc1468da177	89
<>	161:2cc1468da177	90	#if defined(SDMMC2)
<>	161:2cc1468da177	91	#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
<>	161:2cc1468da177	92	\|\| ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
<>	161:2cc1468da177	93	#else
<>	161:2cc1468da177	94	#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
<>	161:2cc1468da177	95	#endif /* SDMMC2 */
<>	161:2cc1468da177	96
<>	161:2cc1468da177	97	#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
<>	161:2cc1468da177	98
<>	161:2cc1468da177	99	#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
<>	161:2cc1468da177	100
<>	161:2cc1468da177	101	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	102	#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
<>	161:2cc1468da177	103
<>	161:2cc1468da177	104	#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
<>	161:2cc1468da177	105	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	106
<>	161:2cc1468da177	107	#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
<>	161:2cc1468da177	108
<>	161:2cc1468da177	109	#if defined(CEC)
<>	161:2cc1468da177	110	#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
<>	161:2cc1468da177	111	#endif /* CEC */
<>	161:2cc1468da177	112
<>	161:2cc1468da177	113	#if defined(DSI)
<>	161:2cc1468da177	114	#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
<>	161:2cc1468da177	115	#endif /* DSI */
<>	161:2cc1468da177	116
<>	161:2cc1468da177	117	#if defined(LTDC)
<>	161:2cc1468da177	118	#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
<>	161:2cc1468da177	119	#endif /* LTDC */
<>	161:2cc1468da177	120
<>	161:2cc1468da177	121	#if defined(SPDIFRX)
<>	161:2cc1468da177	122	#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
<>	161:2cc1468da177	123	#endif /* SPDIFRX */
<>	161:2cc1468da177	124
<>	161:2cc1468da177	125	/**
<>	161:2cc1468da177	126	* @}
<>	161:2cc1468da177	127	*/
<>	161:2cc1468da177	128
<>	161:2cc1468da177	129	/* Private function prototypes -----------------------------------------------*/
<>	161:2cc1468da177	130	/** @defgroup RCC_LL_Private_Functions RCC Private functions
<>	161:2cc1468da177	131	* @{
<>	161:2cc1468da177	132	*/
<>	161:2cc1468da177	133	uint32_t RCC_GetSystemClockFreq(void);
<>	161:2cc1468da177	134	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
<>	161:2cc1468da177	135	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
<>	161:2cc1468da177	136	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
<>	161:2cc1468da177	137	uint32_t RCC_PLL_GetFreqDomain_SYS(void);
<>	161:2cc1468da177	138	uint32_t RCC_PLL_GetFreqDomain_SAI(void);
<>	161:2cc1468da177	139	uint32_t RCC_PLL_GetFreqDomain_48M(void);
<>	161:2cc1468da177	140	#if defined(DSI)
<>	161:2cc1468da177	141	uint32_t RCC_PLL_GetFreqDomain_DSI(void);
<>	161:2cc1468da177	142	#endif /* DSI */
<>	161:2cc1468da177	143	uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
<>	161:2cc1468da177	144	uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
<>	161:2cc1468da177	145	#if defined(LTDC)
<>	161:2cc1468da177	146	uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
<>	161:2cc1468da177	147	#endif /* LTDC */
<>	161:2cc1468da177	148	uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
<>	161:2cc1468da177	149	uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
<>	161:2cc1468da177	150	#if defined(SPDIFRX)
<>	161:2cc1468da177	151	uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
<>	161:2cc1468da177	152	#endif /* SPDIFRX */
<>	161:2cc1468da177	153	/**
<>	161:2cc1468da177	154	* @}
<>	161:2cc1468da177	155	*/
<>	161:2cc1468da177	156
<>	161:2cc1468da177	157
<>	161:2cc1468da177	158	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	159	/** @addtogroup RCC_LL_Exported_Functions
<>	161:2cc1468da177	160	* @{
<>	161:2cc1468da177	161	*/
<>	161:2cc1468da177	162
<>	161:2cc1468da177	163	/** @addtogroup RCC_LL_EF_Init
<>	161:2cc1468da177	164	* @{
<>	161:2cc1468da177	165	*/
<>	161:2cc1468da177	166
<>	161:2cc1468da177	167	/**
<>	161:2cc1468da177	168	* @brief Reset the RCC clock configuration to the default reset state.
<>	161:2cc1468da177	169	* @note The default reset state of the clock configuration is given below:
<>	161:2cc1468da177	170	* - HSI ON and used as system clock source
<>	161:2cc1468da177	171	* - HSE and PLL OFF
<>	161:2cc1468da177	172	* - AHB, APB1 and APB2 prescaler set to 1.
<>	161:2cc1468da177	173	* - CSS, MCO OFF
<>	161:2cc1468da177	174	* - All interrupts disabled
<>	161:2cc1468da177	175	* @note This function doesn't modify the configuration of the
<>	161:2cc1468da177	176	* - Peripheral clocks
<>	161:2cc1468da177	177	* - LSI, LSE and RTC clocks
<>	161:2cc1468da177	178	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	179	* - SUCCESS: RCC registers are de-initialized
<>	161:2cc1468da177	180	* - ERROR: not applicable
<>	161:2cc1468da177	181	*/
<>	161:2cc1468da177	182	ErrorStatus LL_RCC_DeInit(void)
<>	161:2cc1468da177	183	{
<>	161:2cc1468da177	184	uint32_t vl_mask = 0U;
<>	161:2cc1468da177	185
<>	161:2cc1468da177	186	/* Set HSION bit */
<>	161:2cc1468da177	187	LL_RCC_HSI_Enable();
<>	161:2cc1468da177	188
<>	161:2cc1468da177	189	/* Reset CFGR register */
<>	161:2cc1468da177	190	LL_RCC_WriteReg(CFGR, 0x00000000U);
<>	161:2cc1468da177	191
<>	161:2cc1468da177	192	vl_mask = 0xFFFFFFFFU;
<>	161:2cc1468da177	193
<>	161:2cc1468da177	194	/* Reset HSEON, PLLSYSON bits */
<>	161:2cc1468da177	195	CLEAR_BIT(vl_mask, (RCC_CR_HSEON \| RCC_CR_HSEBYP \| RCC_CR_PLLON \| RCC_CR_CSSON));
<>	161:2cc1468da177	196
<>	161:2cc1468da177	197	/* Reset PLLSAION bit */
<>	161:2cc1468da177	198	CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
<>	161:2cc1468da177	199
<>	161:2cc1468da177	200	/* Reset PLLI2SON bit */
<>	161:2cc1468da177	201	CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
<>	161:2cc1468da177	202
<>	161:2cc1468da177	203	/* Write new mask in CR register */
<>	161:2cc1468da177	204	LL_RCC_WriteReg(CR, vl_mask);
<>	161:2cc1468da177	205
<>	161:2cc1468da177	206	/* Set HSITRIM bits to the reset value*/
<>	161:2cc1468da177	207	LL_RCC_HSI_SetCalibTrimming(0x10U);
<>	161:2cc1468da177	208
<>	161:2cc1468da177	209	/* Reset PLLCFGR register */
<>	161:2cc1468da177	210	LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
<>	161:2cc1468da177	211
<>	161:2cc1468da177	212	/* Reset PLLI2SCFGR register */
<>	161:2cc1468da177	213	LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U);
<>	161:2cc1468da177	214
<>	161:2cc1468da177	215	/* Reset PLLSAICFGR register */
<>	161:2cc1468da177	216	LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
<>	161:2cc1468da177	217
<>	161:2cc1468da177	218	/* Reset HSEBYP bit */
<>	161:2cc1468da177	219	LL_RCC_HSE_DisableBypass();
<>	161:2cc1468da177	220
<>	161:2cc1468da177	221	/* Disable all interrupts */
<>	161:2cc1468da177	222	LL_RCC_WriteReg(CIR, 0x00000000U);
<>	161:2cc1468da177	223
<>	161:2cc1468da177	224	return SUCCESS;
<>	161:2cc1468da177	225	}
<>	161:2cc1468da177	226
<>	161:2cc1468da177	227	/**
<>	161:2cc1468da177	228	* @}
<>	161:2cc1468da177	229	*/
<>	161:2cc1468da177	230
<>	161:2cc1468da177	231	/** @addtogroup RCC_LL_EF_Get_Freq
<>	161:2cc1468da177	232	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<>	161:2cc1468da177	233	* and different peripheral clocks available on the device.
<>	161:2cc1468da177	234	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
<>	161:2cc1468da177	235	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
<>	161:2cc1468da177	236	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
<>	161:2cc1468da177	237	* or HSI_VALUE(**) multiplied/divided by the PLL factors.
<>	161:2cc1468da177	238	* @note (**) HSI_VALUE is a constant defined in this file (default value
<>	161:2cc1468da177	239	* 16 MHz) but the real value may vary depending on the variations
<>	161:2cc1468da177	240	* in voltage and temperature.
<>	161:2cc1468da177	241	* @note (***) HSE_VALUE is a constant defined in this file (default value
<>	161:2cc1468da177	242	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
<>	161:2cc1468da177	243	* frequency of the crystal used. Otherwise, this function may
<>	161:2cc1468da177	244	* have wrong result.
<>	161:2cc1468da177	245	* @note The result of this function could be incorrect when using fractional
<>	161:2cc1468da177	246	* value for HSE crystal.
<>	161:2cc1468da177	247	* @note This function can be used by the user application to compute the
<>	161:2cc1468da177	248	* baud-rate for the communication peripherals or configure other parameters.
<>	161:2cc1468da177	249	* @{
<>	161:2cc1468da177	250	*/
<>	161:2cc1468da177	251
<>	161:2cc1468da177	252	/**
<>	161:2cc1468da177	253	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<>	161:2cc1468da177	254	* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
<>	161:2cc1468da177	255	* must be called to update structure fields. Otherwise, any
<>	161:2cc1468da177	256	* configuration based on this function will be incorrect.
<>	161:2cc1468da177	257	* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
<>	161:2cc1468da177	258	* @retval None
<>	161:2cc1468da177	259	*/
<>	161:2cc1468da177	260	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
<>	161:2cc1468da177	261	{
<>	161:2cc1468da177	262	/* Get SYSCLK frequency */
<>	161:2cc1468da177	263	RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	264
<>	161:2cc1468da177	265	/* HCLK clock frequency */
<>	161:2cc1468da177	266	RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
<>	161:2cc1468da177	267
<>	161:2cc1468da177	268	/* PCLK1 clock frequency */
<>	161:2cc1468da177	269	RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
<>	161:2cc1468da177	270
<>	161:2cc1468da177	271	/* PCLK2 clock frequency */
<>	161:2cc1468da177	272	RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
<>	161:2cc1468da177	273	}
<>	161:2cc1468da177	274
<>	161:2cc1468da177	275	/**
<>	161:2cc1468da177	276	* @brief Return USARTx clock frequency
<>	161:2cc1468da177	277	* @param USARTxSource This parameter can be one of the following values:
<>	161:2cc1468da177	278	* @arg @ref LL_RCC_USART1_CLKSOURCE
<>	161:2cc1468da177	279	* @arg @ref LL_RCC_USART2_CLKSOURCE
<>	161:2cc1468da177	280	* @arg @ref LL_RCC_USART3_CLKSOURCE
<>	161:2cc1468da177	281	* @arg @ref LL_RCC_USART6_CLKSOURCE
<>	161:2cc1468da177	282	* @retval USART clock frequency (in Hz)
<>	161:2cc1468da177	283	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<>	161:2cc1468da177	284	*/
<>	161:2cc1468da177	285	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
<>	161:2cc1468da177	286	{
<>	161:2cc1468da177	287	uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	288
<>	161:2cc1468da177	289	/* Check parameter */
<>	161:2cc1468da177	290	assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
<>	161:2cc1468da177	291
<>	161:2cc1468da177	292	if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
<>	161:2cc1468da177	293	{
<>	161:2cc1468da177	294	/* USART1CLK clock frequency */
<>	161:2cc1468da177	295	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	161:2cc1468da177	296	{
<>	161:2cc1468da177	297	case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
<>	161:2cc1468da177	298	usart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	299	break;
<>	161:2cc1468da177	300
<>	161:2cc1468da177	301	case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
<>	161:2cc1468da177	302	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	303	{
<>	161:2cc1468da177	304	usart_frequency = HSI_VALUE;
<>	161:2cc1468da177	305	}
<>	161:2cc1468da177	306	break;
<>	161:2cc1468da177	307
<>	161:2cc1468da177	308	case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
<>	161:2cc1468da177	309	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	310	{
<>	161:2cc1468da177	311	usart_frequency = LSE_VALUE;
<>	161:2cc1468da177	312	}
<>	161:2cc1468da177	313	break;
<>	161:2cc1468da177	314
<>	161:2cc1468da177	315	case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
<>	161:2cc1468da177	316	default:
<>	161:2cc1468da177	317	usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	318	break;
<>	161:2cc1468da177	319	}
<>	161:2cc1468da177	320	}
<>	161:2cc1468da177	321	else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
<>	161:2cc1468da177	322	{
<>	161:2cc1468da177	323	/* USART2CLK clock frequency */
<>	161:2cc1468da177	324	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	161:2cc1468da177	325	{
<>	161:2cc1468da177	326	case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
<>	161:2cc1468da177	327	usart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	328	break;
<>	161:2cc1468da177	329
<>	161:2cc1468da177	330	case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
<>	161:2cc1468da177	331	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	332	{
<>	161:2cc1468da177	333	usart_frequency = HSI_VALUE;
<>	161:2cc1468da177	334	}
<>	161:2cc1468da177	335	break;
<>	161:2cc1468da177	336
<>	161:2cc1468da177	337	case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
<>	161:2cc1468da177	338	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	339	{
<>	161:2cc1468da177	340	usart_frequency = LSE_VALUE;
<>	161:2cc1468da177	341	}
<>	161:2cc1468da177	342	break;
<>	161:2cc1468da177	343
<>	161:2cc1468da177	344	case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
<>	161:2cc1468da177	345	default:
<>	161:2cc1468da177	346	usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	347	break;
<>	161:2cc1468da177	348	}
<>	161:2cc1468da177	349	}
<>	161:2cc1468da177	350	else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
<>	161:2cc1468da177	351	{
<>	161:2cc1468da177	352	/* USART6CLK clock frequency */
<>	161:2cc1468da177	353	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	161:2cc1468da177	354	{
<>	161:2cc1468da177	355	case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */
<>	161:2cc1468da177	356	usart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	357	break;
<>	161:2cc1468da177	358
<>	161:2cc1468da177	359	case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */
<>	161:2cc1468da177	360	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	361	{
<>	161:2cc1468da177	362	usart_frequency = HSI_VALUE;
<>	161:2cc1468da177	363	}
<>	161:2cc1468da177	364	break;
<>	161:2cc1468da177	365
<>	161:2cc1468da177	366	case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */
<>	161:2cc1468da177	367	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	368	{
<>	161:2cc1468da177	369	usart_frequency = LSE_VALUE;
<>	161:2cc1468da177	370	}
<>	161:2cc1468da177	371	break;
<>	161:2cc1468da177	372
<>	161:2cc1468da177	373	case LL_RCC_USART6_CLKSOURCE_PCLK2: /* USART6 Clock is PCLK2 */
<>	161:2cc1468da177	374	default:
<>	161:2cc1468da177	375	usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	376	break;
<>	161:2cc1468da177	377	}
<>	161:2cc1468da177	378	}
<>	161:2cc1468da177	379	else
<>	161:2cc1468da177	380	{
<>	161:2cc1468da177	381	if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
<>	161:2cc1468da177	382	{
<>	161:2cc1468da177	383	/* USART3CLK clock frequency */
<>	161:2cc1468da177	384	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	161:2cc1468da177	385	{
<>	161:2cc1468da177	386	case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
<>	161:2cc1468da177	387	usart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	388	break;
<>	161:2cc1468da177	389
<>	161:2cc1468da177	390	case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
<>	161:2cc1468da177	391	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	392	{
<>	161:2cc1468da177	393	usart_frequency = HSI_VALUE;
<>	161:2cc1468da177	394	}
<>	161:2cc1468da177	395	break;
<>	161:2cc1468da177	396
<>	161:2cc1468da177	397	case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
<>	161:2cc1468da177	398	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	399	{
<>	161:2cc1468da177	400	usart_frequency = LSE_VALUE;
<>	161:2cc1468da177	401	}
<>	161:2cc1468da177	402	break;
<>	161:2cc1468da177	403
<>	161:2cc1468da177	404	case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
<>	161:2cc1468da177	405	default:
<>	161:2cc1468da177	406	usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	407	break;
<>	161:2cc1468da177	408	}
<>	161:2cc1468da177	409	}
<>	161:2cc1468da177	410	}
<>	161:2cc1468da177	411	return usart_frequency;
<>	161:2cc1468da177	412	}
<>	161:2cc1468da177	413
<>	161:2cc1468da177	414	/**
<>	161:2cc1468da177	415	* @brief Return UARTx clock frequency
<>	161:2cc1468da177	416	* @param UARTxSource This parameter can be one of the following values:
<>	161:2cc1468da177	417	* @arg @ref LL_RCC_UART4_CLKSOURCE
<>	161:2cc1468da177	418	* @arg @ref LL_RCC_UART5_CLKSOURCE
<>	161:2cc1468da177	419	* @arg @ref LL_RCC_UART7_CLKSOURCE
<>	161:2cc1468da177	420	* @arg @ref LL_RCC_UART8_CLKSOURCE
<>	161:2cc1468da177	421	* @retval UART clock frequency (in Hz)
<>	161:2cc1468da177	422	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<>	161:2cc1468da177	423	*/
<>	161:2cc1468da177	424	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
<>	161:2cc1468da177	425	{
<>	161:2cc1468da177	426	uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	427
<>	161:2cc1468da177	428	/* Check parameter */
<>	161:2cc1468da177	429	assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
<>	161:2cc1468da177	430
<>	161:2cc1468da177	431	if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
<>	161:2cc1468da177	432	{
<>	161:2cc1468da177	433	/* UART4CLK clock frequency */
<>	161:2cc1468da177	434	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	161:2cc1468da177	435	{
<>	161:2cc1468da177	436	case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
<>	161:2cc1468da177	437	uart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	438	break;
<>	161:2cc1468da177	439
<>	161:2cc1468da177	440	case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
<>	161:2cc1468da177	441	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	442	{
<>	161:2cc1468da177	443	uart_frequency = HSI_VALUE;
<>	161:2cc1468da177	444	}
<>	161:2cc1468da177	445	break;
<>	161:2cc1468da177	446
<>	161:2cc1468da177	447	case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
<>	161:2cc1468da177	448	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	449	{
<>	161:2cc1468da177	450	uart_frequency = LSE_VALUE;
<>	161:2cc1468da177	451	}
<>	161:2cc1468da177	452	break;
<>	161:2cc1468da177	453
<>	161:2cc1468da177	454	case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
<>	161:2cc1468da177	455	default:
<>	161:2cc1468da177	456	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	457	break;
<>	161:2cc1468da177	458	}
<>	161:2cc1468da177	459	}
<>	161:2cc1468da177	460	else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
<>	161:2cc1468da177	461	{
<>	161:2cc1468da177	462	/* UART5CLK clock frequency */
<>	161:2cc1468da177	463	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	161:2cc1468da177	464	{
<>	161:2cc1468da177	465	case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
<>	161:2cc1468da177	466	uart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	467	break;
<>	161:2cc1468da177	468
<>	161:2cc1468da177	469	case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
<>	161:2cc1468da177	470	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	471	{
<>	161:2cc1468da177	472	uart_frequency = HSI_VALUE;
<>	161:2cc1468da177	473	}
<>	161:2cc1468da177	474	break;
<>	161:2cc1468da177	475
<>	161:2cc1468da177	476	case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
<>	161:2cc1468da177	477	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	478	{
<>	161:2cc1468da177	479	uart_frequency = LSE_VALUE;
<>	161:2cc1468da177	480	}
<>	161:2cc1468da177	481	break;
<>	161:2cc1468da177	482
<>	161:2cc1468da177	483	case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
<>	161:2cc1468da177	484	default:
<>	161:2cc1468da177	485	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	486	break;
<>	161:2cc1468da177	487	}
<>	161:2cc1468da177	488	}
<>	161:2cc1468da177	489	else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
<>	161:2cc1468da177	490	{
<>	161:2cc1468da177	491	/* UART7CLK clock frequency */
<>	161:2cc1468da177	492	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	161:2cc1468da177	493	{
<>	161:2cc1468da177	494	case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */
<>	161:2cc1468da177	495	uart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	496	break;
<>	161:2cc1468da177	497
<>	161:2cc1468da177	498	case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */
<>	161:2cc1468da177	499	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	500	{
<>	161:2cc1468da177	501	uart_frequency = HSI_VALUE;
<>	161:2cc1468da177	502	}
<>	161:2cc1468da177	503	break;
<>	161:2cc1468da177	504
<>	161:2cc1468da177	505	case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */
<>	161:2cc1468da177	506	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	507	{
<>	161:2cc1468da177	508	uart_frequency = LSE_VALUE;
<>	161:2cc1468da177	509	}
<>	161:2cc1468da177	510	break;
<>	161:2cc1468da177	511
<>	161:2cc1468da177	512	case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */
<>	161:2cc1468da177	513	default:
<>	161:2cc1468da177	514	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	515	break;
<>	161:2cc1468da177	516	}
<>	161:2cc1468da177	517	}
<>	161:2cc1468da177	518	else
<>	161:2cc1468da177	519	{
<>	161:2cc1468da177	520	if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
<>	161:2cc1468da177	521	{
<>	161:2cc1468da177	522	/* UART8CLK clock frequency */
<>	161:2cc1468da177	523	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	161:2cc1468da177	524	{
<>	161:2cc1468da177	525	case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */
<>	161:2cc1468da177	526	uart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	527	break;
<>	161:2cc1468da177	528
<>	161:2cc1468da177	529	case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */
<>	161:2cc1468da177	530	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	531	{
<>	161:2cc1468da177	532	uart_frequency = HSI_VALUE;
<>	161:2cc1468da177	533	}
<>	161:2cc1468da177	534	break;
<>	161:2cc1468da177	535
<>	161:2cc1468da177	536	case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */
<>	161:2cc1468da177	537	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	538	{
<>	161:2cc1468da177	539	uart_frequency = LSE_VALUE;
<>	161:2cc1468da177	540	}
<>	161:2cc1468da177	541	break;
<>	161:2cc1468da177	542
<>	161:2cc1468da177	543	case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */
<>	161:2cc1468da177	544	default:
<>	161:2cc1468da177	545	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	546	break;
<>	161:2cc1468da177	547	}
<>	161:2cc1468da177	548	}
<>	161:2cc1468da177	549	}
<>	161:2cc1468da177	550	return uart_frequency;
<>	161:2cc1468da177	551	}
<>	161:2cc1468da177	552
<>	161:2cc1468da177	553	/**
<>	161:2cc1468da177	554	* @brief Return I2Cx clock frequency
<>	161:2cc1468da177	555	* @param I2CxSource This parameter can be one of the following values:
<>	161:2cc1468da177	556	* @arg @ref LL_RCC_I2C1_CLKSOURCE
<>	161:2cc1468da177	557	* @arg @ref LL_RCC_I2C2_CLKSOURCE
<>	161:2cc1468da177	558	* @arg @ref LL_RCC_I2C3_CLKSOURCE
<>	161:2cc1468da177	559	* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
<>	161:2cc1468da177	560	*
<>	161:2cc1468da177	561	* (*) value not defined in all devices.
<>	161:2cc1468da177	562	* @retval I2C clock frequency (in Hz)
<>	161:2cc1468da177	563	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
<>	161:2cc1468da177	564	*/
<>	161:2cc1468da177	565	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
<>	161:2cc1468da177	566	{
<>	161:2cc1468da177	567	uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	568
<>	161:2cc1468da177	569	/* Check parameter */
<>	161:2cc1468da177	570	assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
<>	161:2cc1468da177	571
<>	161:2cc1468da177	572	if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
<>	161:2cc1468da177	573	{
<>	161:2cc1468da177	574	/* I2C1 CLK clock frequency */
<>	161:2cc1468da177	575	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	161:2cc1468da177	576	{
<>	161:2cc1468da177	577	case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
<>	161:2cc1468da177	578	i2c_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	579	break;
<>	161:2cc1468da177	580
<>	161:2cc1468da177	581	case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
<>	161:2cc1468da177	582	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	583	{
<>	161:2cc1468da177	584	i2c_frequency = HSI_VALUE;
<>	161:2cc1468da177	585	}
<>	161:2cc1468da177	586	break;
<>	161:2cc1468da177	587
<>	161:2cc1468da177	588	case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
<>	161:2cc1468da177	589	default:
<>	161:2cc1468da177	590	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	591	break;
<>	161:2cc1468da177	592	}
<>	161:2cc1468da177	593	}
<>	161:2cc1468da177	594	else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
<>	161:2cc1468da177	595	{
<>	161:2cc1468da177	596	/* I2C2 CLK clock frequency */
<>	161:2cc1468da177	597	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	161:2cc1468da177	598	{
<>	161:2cc1468da177	599	case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
<>	161:2cc1468da177	600	i2c_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	601	break;
<>	161:2cc1468da177	602
<>	161:2cc1468da177	603	case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
<>	161:2cc1468da177	604	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	605	{
<>	161:2cc1468da177	606	i2c_frequency = HSI_VALUE;
<>	161:2cc1468da177	607	}
<>	161:2cc1468da177	608	break;
<>	161:2cc1468da177	609
<>	161:2cc1468da177	610	case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
<>	161:2cc1468da177	611	default:
<>	161:2cc1468da177	612	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	613	break;
<>	161:2cc1468da177	614	}
<>	161:2cc1468da177	615	}
<>	161:2cc1468da177	616	else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
<>	161:2cc1468da177	617	{
<>	161:2cc1468da177	618	/* I2C3 CLK clock frequency */
<>	161:2cc1468da177	619	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	161:2cc1468da177	620	{
<>	161:2cc1468da177	621	case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
<>	161:2cc1468da177	622	i2c_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	623	break;
<>	161:2cc1468da177	624
<>	161:2cc1468da177	625	case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
<>	161:2cc1468da177	626	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	627	{
<>	161:2cc1468da177	628	i2c_frequency = HSI_VALUE;
<>	161:2cc1468da177	629	}
<>	161:2cc1468da177	630	break;
<>	161:2cc1468da177	631
<>	161:2cc1468da177	632	case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
<>	161:2cc1468da177	633	default:
<>	161:2cc1468da177	634	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	635	break;
<>	161:2cc1468da177	636	}
<>	161:2cc1468da177	637	}
<>	161:2cc1468da177	638	#if defined(I2C4)
<>	161:2cc1468da177	639	else
<>	161:2cc1468da177	640	{
<>	161:2cc1468da177	641	if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
<>	161:2cc1468da177	642	{
<>	161:2cc1468da177	643	/* I2C4 CLK clock frequency */
<>	161:2cc1468da177	644	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	161:2cc1468da177	645	{
<>	161:2cc1468da177	646	case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
<>	161:2cc1468da177	647	i2c_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	648	break;
<>	161:2cc1468da177	649
<>	161:2cc1468da177	650	case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
<>	161:2cc1468da177	651	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	652	{
<>	161:2cc1468da177	653	i2c_frequency = HSI_VALUE;
<>	161:2cc1468da177	654	}
<>	161:2cc1468da177	655	break;
<>	161:2cc1468da177	656
<>	161:2cc1468da177	657	case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
<>	161:2cc1468da177	658	default:
<>	161:2cc1468da177	659	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	660	break;
<>	161:2cc1468da177	661	}
<>	161:2cc1468da177	662	}
<>	161:2cc1468da177	663	}
<>	161:2cc1468da177	664	#endif /* I2C4 */
<>	161:2cc1468da177	665
<>	161:2cc1468da177	666	return i2c_frequency;
<>	161:2cc1468da177	667	}
<>	161:2cc1468da177	668
<>	161:2cc1468da177	669	/**
<>	161:2cc1468da177	670	* @brief Return I2Sx clock frequency
<>	161:2cc1468da177	671	* @param I2SxSource This parameter can be one of the following values:
<>	161:2cc1468da177	672	* @arg @ref LL_RCC_I2S1_CLKSOURCE
<>	161:2cc1468da177	673	* @retval I2S clock frequency (in Hz)
<>	161:2cc1468da177	674	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready
<>	161:2cc1468da177	675	*/
<>	161:2cc1468da177	676	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
<>	161:2cc1468da177	677	{
<>	161:2cc1468da177	678	uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	679
<>	161:2cc1468da177	680	/* Check parameter */
<>	161:2cc1468da177	681	assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
<>	161:2cc1468da177	682
<>	161:2cc1468da177	683	if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
<>	161:2cc1468da177	684	{
<>	161:2cc1468da177	685	/* I2S1 CLK clock frequency */
<>	161:2cc1468da177	686	switch (LL_RCC_GetI2SClockSource(I2SxSource))
<>	161:2cc1468da177	687	{
<>	161:2cc1468da177	688	case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
<>	161:2cc1468da177	689	if (LL_RCC_PLLI2S_IsReady())
<>	161:2cc1468da177	690	{
<>	161:2cc1468da177	691	i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
<>	161:2cc1468da177	692	}
<>	161:2cc1468da177	693	break;
<>	161:2cc1468da177	694
<>	161:2cc1468da177	695	case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
<>	161:2cc1468da177	696	default:
<>	161:2cc1468da177	697	i2s_frequency = EXTERNAL_CLOCK_VALUE;
<>	161:2cc1468da177	698	break;
<>	161:2cc1468da177	699	}
<>	161:2cc1468da177	700	}
<>	161:2cc1468da177	701
<>	161:2cc1468da177	702	return i2s_frequency;
<>	161:2cc1468da177	703	}
<>	161:2cc1468da177	704
<>	161:2cc1468da177	705	/**
<>	161:2cc1468da177	706	* @brief Return LPTIMx clock frequency
<>	161:2cc1468da177	707	* @param LPTIMxSource This parameter can be one of the following values:
<>	161:2cc1468da177	708	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
<>	161:2cc1468da177	709	* @retval LPTIM clock frequency (in Hz)
<>	161:2cc1468da177	710	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
<>	161:2cc1468da177	711	*/
<>	161:2cc1468da177	712	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
<>	161:2cc1468da177	713	{
<>	161:2cc1468da177	714	uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	715
<>	161:2cc1468da177	716	/* Check parameter */
<>	161:2cc1468da177	717	assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
<>	161:2cc1468da177	718
<>	161:2cc1468da177	719	if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
<>	161:2cc1468da177	720	{
<>	161:2cc1468da177	721	/* LPTIM1CLK clock frequency */
<>	161:2cc1468da177	722	switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
<>	161:2cc1468da177	723	{
<>	161:2cc1468da177	724	case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
<>	161:2cc1468da177	725	if (LL_RCC_LSI_IsReady())
<>	161:2cc1468da177	726	{
<>	161:2cc1468da177	727	lptim_frequency = LSI_VALUE;
<>	161:2cc1468da177	728	}
<>	161:2cc1468da177	729	break;
<>	161:2cc1468da177	730
<>	161:2cc1468da177	731	case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
<>	161:2cc1468da177	732	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	733	{
<>	161:2cc1468da177	734	lptim_frequency = HSI_VALUE;
<>	161:2cc1468da177	735	}
<>	161:2cc1468da177	736	break;
<>	161:2cc1468da177	737
<>	161:2cc1468da177	738	case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
<>	161:2cc1468da177	739	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	740	{
<>	161:2cc1468da177	741	lptim_frequency = LSE_VALUE;
<>	161:2cc1468da177	742	}
<>	161:2cc1468da177	743	break;
<>	161:2cc1468da177	744
<>	161:2cc1468da177	745	case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
<>	161:2cc1468da177	746	default:
<>	161:2cc1468da177	747	lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	748	break;
<>	161:2cc1468da177	749	}
<>	161:2cc1468da177	750	}
<>	161:2cc1468da177	751
<>	161:2cc1468da177	752	return lptim_frequency;
<>	161:2cc1468da177	753	}
<>	161:2cc1468da177	754
<>	161:2cc1468da177	755	/**
<>	161:2cc1468da177	756	* @brief Return SAIx clock frequency
<>	161:2cc1468da177	757	* @param SAIxSource This parameter can be one of the following values:
<>	161:2cc1468da177	758	* @arg @ref LL_RCC_SAI1_CLKSOURCE
<>	161:2cc1468da177	759	* @arg @ref LL_RCC_SAI2_CLKSOURCE
<>	161:2cc1468da177	760	* @retval SAI clock frequency (in Hz)
<>	161:2cc1468da177	761	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
<>	161:2cc1468da177	762	* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
<>	161:2cc1468da177	763	*/
<>	161:2cc1468da177	764	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
<>	161:2cc1468da177	765	{
<>	161:2cc1468da177	766	uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	767
<>	161:2cc1468da177	768	/* Check parameter */
<>	161:2cc1468da177	769	assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
<>	161:2cc1468da177	770
<>	161:2cc1468da177	771	if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
<>	161:2cc1468da177	772	{
<>	161:2cc1468da177	773	/* SAI1CLK clock frequency */
<>	161:2cc1468da177	774	switch (LL_RCC_GetSAIClockSource(SAIxSource))
<>	161:2cc1468da177	775	{
<>	161:2cc1468da177	776	case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
<>	161:2cc1468da177	777	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	778	{
<>	161:2cc1468da177	779	sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
<>	161:2cc1468da177	780	}
<>	161:2cc1468da177	781	break;
<>	161:2cc1468da177	782
<>	161:2cc1468da177	783	case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
<>	161:2cc1468da177	784	if (LL_RCC_PLLI2S_IsReady())
<>	161:2cc1468da177	785	{
<>	161:2cc1468da177	786	sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
<>	161:2cc1468da177	787	}
<>	161:2cc1468da177	788	break;
<>	161:2cc1468da177	789
<>	161:2cc1468da177	790	#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
<>	161:2cc1468da177	791	case LL_RCC_SAI1_CLKSOURCE_PLLSRC:
<>	161:2cc1468da177	792	switch (LL_RCC_PLL_GetMainSource())
<>	161:2cc1468da177	793	{
<>	161:2cc1468da177	794	case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */
<>	161:2cc1468da177	795	if (LL_RCC_HSE_IsReady())
<>	161:2cc1468da177	796	{
<>	161:2cc1468da177	797	sai_frequency = HSE_VALUE;
<>	161:2cc1468da177	798	}
<>	161:2cc1468da177	799	break;
<>	161:2cc1468da177	800
<>	161:2cc1468da177	801	case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */
<>	161:2cc1468da177	802	default:
<>	161:2cc1468da177	803	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	804	{
<>	161:2cc1468da177	805	sai_frequency = HSI_VALUE;
<>	161:2cc1468da177	806	}
<>	161:2cc1468da177	807	break;
<>	161:2cc1468da177	808	}
<>	161:2cc1468da177	809	break;
<>	161:2cc1468da177	810	#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
<>	161:2cc1468da177	811	case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
<>	161:2cc1468da177	812	default:
<>	161:2cc1468da177	813	sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<>	161:2cc1468da177	814	break;
<>	161:2cc1468da177	815	}
<>	161:2cc1468da177	816	}
<>	161:2cc1468da177	817	else
<>	161:2cc1468da177	818	{
<>	161:2cc1468da177	819	if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
<>	161:2cc1468da177	820	{
<>	161:2cc1468da177	821	/* SAI2CLK clock frequency */
<>	161:2cc1468da177	822	switch (LL_RCC_GetSAIClockSource(SAIxSource))
<>	161:2cc1468da177	823	{
<>	161:2cc1468da177	824	case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
<>	161:2cc1468da177	825	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	826	{
<>	161:2cc1468da177	827	sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
<>	161:2cc1468da177	828	}
<>	161:2cc1468da177	829	break;
<>	161:2cc1468da177	830
<>	161:2cc1468da177	831	case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
<>	161:2cc1468da177	832	if (LL_RCC_PLLI2S_IsReady())
<>	161:2cc1468da177	833	{
<>	161:2cc1468da177	834	sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
<>	161:2cc1468da177	835	}
<>	161:2cc1468da177	836	break;
<>	161:2cc1468da177	837
<>	161:2cc1468da177	838	#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
<>	161:2cc1468da177	839	case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
<>	161:2cc1468da177	840	switch (LL_RCC_PLL_GetMainSource())
<>	161:2cc1468da177	841	{
<>	161:2cc1468da177	842	case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
<>	161:2cc1468da177	843	if (LL_RCC_HSE_IsReady())
<>	161:2cc1468da177	844	{
<>	161:2cc1468da177	845	sai_frequency = HSE_VALUE;
<>	161:2cc1468da177	846	}
<>	161:2cc1468da177	847	break;
<>	161:2cc1468da177	848
<>	161:2cc1468da177	849	case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
<>	161:2cc1468da177	850	default:
<>	161:2cc1468da177	851	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	852	{
<>	161:2cc1468da177	853	sai_frequency = HSI_VALUE;
<>	161:2cc1468da177	854	}
<>	161:2cc1468da177	855	break;
<>	161:2cc1468da177	856	}
<>	161:2cc1468da177	857	break;
<>	161:2cc1468da177	858	#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
<>	161:2cc1468da177	859	case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
<>	161:2cc1468da177	860	default:
<>	161:2cc1468da177	861	sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<>	161:2cc1468da177	862	break;
<>	161:2cc1468da177	863	}
<>	161:2cc1468da177	864	}
<>	161:2cc1468da177	865	}
<>	161:2cc1468da177	866
<>	161:2cc1468da177	867	return sai_frequency;
<>	161:2cc1468da177	868	}
<>	161:2cc1468da177	869
<>	161:2cc1468da177	870	/**
<>	161:2cc1468da177	871	* @brief Return SDMMCx clock frequency
<>	161:2cc1468da177	872	* @param SDMMCxSource This parameter can be one of the following values:
<>	161:2cc1468da177	873	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
<>	161:2cc1468da177	874	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
<>	161:2cc1468da177	875	*
<>	161:2cc1468da177	876	* (*) value not defined in all devices.
<>	161:2cc1468da177	877	* @retval SDMMC clock frequency (in Hz)
<>	161:2cc1468da177	878	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready
<>	161:2cc1468da177	879	*/
<>	161:2cc1468da177	880	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
<>	161:2cc1468da177	881	{
<>	161:2cc1468da177	882	uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	883
<>	161:2cc1468da177	884	/* Check parameter */
<>	161:2cc1468da177	885	assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
<>	161:2cc1468da177	886
<>	161:2cc1468da177	887	if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
<>	161:2cc1468da177	888	{
<>	161:2cc1468da177	889	/* SDMMC1CLK clock frequency */
<>	161:2cc1468da177	890	switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
<>	161:2cc1468da177	891	{
<>	161:2cc1468da177	892	case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */
<>	161:2cc1468da177	893	switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
<>	161:2cc1468da177	894	{
<>	161:2cc1468da177	895	case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
<>	161:2cc1468da177	896	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	897	{
<>	161:2cc1468da177	898	sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
<>	161:2cc1468da177	899	}
<>	161:2cc1468da177	900	break;
<>	161:2cc1468da177	901
<>	161:2cc1468da177	902	case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
<>	161:2cc1468da177	903	default:
<>	161:2cc1468da177	904	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	905	{
<>	161:2cc1468da177	906	sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
<>	161:2cc1468da177	907	}
<>	161:2cc1468da177	908	break;
<>	161:2cc1468da177	909	}
<>	161:2cc1468da177	910	break;
<>	161:2cc1468da177	911
<>	161:2cc1468da177	912	case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */
<>	161:2cc1468da177	913	default:
<>	161:2cc1468da177	914	sdmmc_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	915	break;
<>	161:2cc1468da177	916	}
<>	161:2cc1468da177	917	}
<>	161:2cc1468da177	918	#if defined(SDMMC2)
<>	161:2cc1468da177	919	else
<>	161:2cc1468da177	920	{
<>	161:2cc1468da177	921	/* SDMMC2CLK clock frequency */
<>	161:2cc1468da177	922	switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
<>	161:2cc1468da177	923	{
<>	161:2cc1468da177	924	case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */
<>	161:2cc1468da177	925	switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
<>	161:2cc1468da177	926	{
<>	161:2cc1468da177	927	case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
<>	161:2cc1468da177	928	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	929	{
<>	161:2cc1468da177	930	sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
<>	161:2cc1468da177	931	}
<>	161:2cc1468da177	932	break;
<>	161:2cc1468da177	933
<>	161:2cc1468da177	934	case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
<>	161:2cc1468da177	935	default:
<>	161:2cc1468da177	936	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	937	{
<>	161:2cc1468da177	938	sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
<>	161:2cc1468da177	939	}
<>	161:2cc1468da177	940	break;
<>	161:2cc1468da177	941	}
<>	161:2cc1468da177	942	break;
<>	161:2cc1468da177	943
<>	161:2cc1468da177	944	case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */
<>	161:2cc1468da177	945	default:
<>	161:2cc1468da177	946	sdmmc_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	947	break;
<>	161:2cc1468da177	948	}
<>	161:2cc1468da177	949	}
<>	161:2cc1468da177	950	#endif /* SDMMC2 */
<>	161:2cc1468da177	951
<>	161:2cc1468da177	952	return sdmmc_frequency;
<>	161:2cc1468da177	953	}
<>	161:2cc1468da177	954
<>	161:2cc1468da177	955	/**
<>	161:2cc1468da177	956	* @brief Return RNGx clock frequency
<>	161:2cc1468da177	957	* @param RNGxSource This parameter can be one of the following values:
<>	161:2cc1468da177	958	* @arg @ref LL_RCC_RNG_CLKSOURCE
<>	161:2cc1468da177	959	* @retval RNG clock frequency (in Hz)
<>	161:2cc1468da177	960	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
<>	161:2cc1468da177	961	*/
<>	161:2cc1468da177	962	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
<>	161:2cc1468da177	963	{
<>	161:2cc1468da177	964	uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	965
<>	161:2cc1468da177	966	/* Check parameter */
<>	161:2cc1468da177	967	assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
<>	161:2cc1468da177	968
<>	161:2cc1468da177	969	/* RNGCLK clock frequency */
<>	161:2cc1468da177	970	switch (LL_RCC_GetRNGClockSource(RNGxSource))
<>	161:2cc1468da177	971	{
<>	161:2cc1468da177	972	case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
<>	161:2cc1468da177	973	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	974	{
<>	161:2cc1468da177	975	rng_frequency = RCC_PLL_GetFreqDomain_48M();
<>	161:2cc1468da177	976	}
<>	161:2cc1468da177	977	break;
<>	161:2cc1468da177	978
<>	161:2cc1468da177	979	case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
<>	161:2cc1468da177	980	default:
<>	161:2cc1468da177	981	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	982	{
<>	161:2cc1468da177	983	rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
<>	161:2cc1468da177	984	}
<>	161:2cc1468da177	985	break;
<>	161:2cc1468da177	986	}
<>	161:2cc1468da177	987
<>	161:2cc1468da177	988	return rng_frequency;
<>	161:2cc1468da177	989	}
<>	161:2cc1468da177	990
<>	161:2cc1468da177	991	#if defined(CEC)
<>	161:2cc1468da177	992	/**
<>	161:2cc1468da177	993	* @brief Return CEC clock frequency
<>	161:2cc1468da177	994	* @param CECxSource This parameter can be one of the following values:
<>	161:2cc1468da177	995	* @arg @ref LL_RCC_CEC_CLKSOURCE
<>	161:2cc1468da177	996	* @retval CEC clock frequency (in Hz)
<>	161:2cc1468da177	997	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<>	161:2cc1468da177	998	*/
<>	161:2cc1468da177	999	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
<>	161:2cc1468da177	1000	{
<>	161:2cc1468da177	1001	uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1002
<>	161:2cc1468da177	1003	/* Check parameter */
<>	161:2cc1468da177	1004	assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
<>	161:2cc1468da177	1005
<>	161:2cc1468da177	1006	/* CECCLK clock frequency */
<>	161:2cc1468da177	1007	switch (LL_RCC_GetCECClockSource(CECxSource))
<>	161:2cc1468da177	1008	{
<>	161:2cc1468da177	1009	case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
<>	161:2cc1468da177	1010	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	1011	{
<>	161:2cc1468da177	1012	cec_frequency = LSE_VALUE;
<>	161:2cc1468da177	1013	}
<>	161:2cc1468da177	1014	break;
<>	161:2cc1468da177	1015
<>	161:2cc1468da177	1016	case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
<>	161:2cc1468da177	1017	default:
<>	161:2cc1468da177	1018	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	1019	{
<>	161:2cc1468da177	1020	cec_frequency = HSI_VALUE/488U;
<>	161:2cc1468da177	1021	}
<>	161:2cc1468da177	1022	break;
<>	161:2cc1468da177	1023	}
<>	161:2cc1468da177	1024
<>	161:2cc1468da177	1025	return cec_frequency;
<>	161:2cc1468da177	1026	}
<>	161:2cc1468da177	1027	#endif /* CEC */
<>	161:2cc1468da177	1028
<>	161:2cc1468da177	1029	/**
<>	161:2cc1468da177	1030	* @brief Return USBx clock frequency
<>	161:2cc1468da177	1031	* @param USBxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1032	* @arg @ref LL_RCC_USB_CLKSOURCE
<>	161:2cc1468da177	1033	* @retval USB clock frequency (in Hz)
<>	161:2cc1468da177	1034	*/
<>	161:2cc1468da177	1035	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
<>	161:2cc1468da177	1036	{
<>	161:2cc1468da177	1037	uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1038
<>	161:2cc1468da177	1039	/* Check parameter */
<>	161:2cc1468da177	1040	assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
<>	161:2cc1468da177	1041
<>	161:2cc1468da177	1042	/* USBCLK clock frequency */
<>	161:2cc1468da177	1043	switch (LL_RCC_GetUSBClockSource(USBxSource))
<>	161:2cc1468da177	1044	{
<>	161:2cc1468da177	1045	case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
<>	161:2cc1468da177	1046	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	1047	{
<>	161:2cc1468da177	1048	usb_frequency = RCC_PLL_GetFreqDomain_48M();
<>	161:2cc1468da177	1049	}
<>	161:2cc1468da177	1050	break;
<>	161:2cc1468da177	1051
<>	161:2cc1468da177	1052	case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
<>	161:2cc1468da177	1053	default:
<>	161:2cc1468da177	1054	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	1055	{
<>	161:2cc1468da177	1056	usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
<>	161:2cc1468da177	1057	}
<>	161:2cc1468da177	1058	break;
<>	161:2cc1468da177	1059	}
<>	161:2cc1468da177	1060
<>	161:2cc1468da177	1061	return usb_frequency;
<>	161:2cc1468da177	1062	}
<>	161:2cc1468da177	1063
<>	161:2cc1468da177	1064	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	1065	/**
<>	161:2cc1468da177	1066	* @brief Return DFSDMx clock frequency
<>	161:2cc1468da177	1067	* @param DFSDMxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1068	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
<>	161:2cc1468da177	1069	* @retval DFSDM clock frequency (in Hz)
<>	161:2cc1468da177	1070	*/
<>	161:2cc1468da177	1071	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
<>	161:2cc1468da177	1072	{
<>	161:2cc1468da177	1073	uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1074
<>	161:2cc1468da177	1075	/* Check parameter */
<>	161:2cc1468da177	1076	assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
<>	161:2cc1468da177	1077
<>	161:2cc1468da177	1078	/* DFSDM1CLK clock frequency */
<>	161:2cc1468da177	1079	switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
<>	161:2cc1468da177	1080	{
<>	161:2cc1468da177	1081	case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
<>	161:2cc1468da177	1082	dfsdm_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	1083	break;
<>	161:2cc1468da177	1084
<>	161:2cc1468da177	1085	case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
<>	161:2cc1468da177	1086	default:
<>	161:2cc1468da177	1087	dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	1088	break;
<>	161:2cc1468da177	1089	}
<>	161:2cc1468da177	1090
<>	161:2cc1468da177	1091	return dfsdm_frequency;
<>	161:2cc1468da177	1092	}
<>	161:2cc1468da177	1093
<>	161:2cc1468da177	1094	/**
<>	161:2cc1468da177	1095	* @brief Return DFSDMx Audio clock frequency
<>	161:2cc1468da177	1096	* @param DFSDMxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1097	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
<>	161:2cc1468da177	1098	* @retval DFSDM clock frequency (in Hz)
<>	161:2cc1468da177	1099	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
<>	161:2cc1468da177	1100	*/
<>	161:2cc1468da177	1101	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
<>	161:2cc1468da177	1102	{
<>	161:2cc1468da177	1103	uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1104
<>	161:2cc1468da177	1105	/* Check parameter */
<>	161:2cc1468da177	1106	assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
<>	161:2cc1468da177	1107
<>	161:2cc1468da177	1108	/* DFSDM1CLK clock frequency */
<>	161:2cc1468da177	1109	switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
<>	161:2cc1468da177	1110	{
<>	161:2cc1468da177	1111	case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
<>	161:2cc1468da177	1112	dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
<>	161:2cc1468da177	1113	break;
<>	161:2cc1468da177	1114
<>	161:2cc1468da177	1115	case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2: /* SAI2 clock used as DFSDM1 audio clock */
<>	161:2cc1468da177	1116	default:
<>	161:2cc1468da177	1117	dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
<>	161:2cc1468da177	1118	break;
<>	161:2cc1468da177	1119	}
<>	161:2cc1468da177	1120
<>	161:2cc1468da177	1121	return dfsdm_frequency;
<>	161:2cc1468da177	1122	}
<>	161:2cc1468da177	1123	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	1124
<>	161:2cc1468da177	1125	#if defined(DSI)
<>	161:2cc1468da177	1126	/**
<>	161:2cc1468da177	1127	* @brief Return DSI clock frequency
<>	161:2cc1468da177	1128	* @param DSIxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1129	* @arg @ref LL_RCC_DSI_CLKSOURCE
<>	161:2cc1468da177	1130	* @retval DSI clock frequency (in Hz)
<>	161:2cc1468da177	1131	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
<>	161:2cc1468da177	1132	* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
<>	161:2cc1468da177	1133	*/
<>	161:2cc1468da177	1134	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
<>	161:2cc1468da177	1135	{
<>	161:2cc1468da177	1136	uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1137
<>	161:2cc1468da177	1138	/* Check parameter */
<>	161:2cc1468da177	1139	assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
<>	161:2cc1468da177	1140
<>	161:2cc1468da177	1141	/* DSICLK clock frequency */
<>	161:2cc1468da177	1142	switch (LL_RCC_GetDSIClockSource(DSIxSource))
<>	161:2cc1468da177	1143	{
<>	161:2cc1468da177	1144	case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
<>	161:2cc1468da177	1145	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	1146	{
<>	161:2cc1468da177	1147	dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
<>	161:2cc1468da177	1148	}
<>	161:2cc1468da177	1149	break;
<>	161:2cc1468da177	1150
<>	161:2cc1468da177	1151	case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
<>	161:2cc1468da177	1152	default:
<>	161:2cc1468da177	1153	dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<>	161:2cc1468da177	1154	break;
<>	161:2cc1468da177	1155	}
<>	161:2cc1468da177	1156
<>	161:2cc1468da177	1157	return dsi_frequency;
<>	161:2cc1468da177	1158	}
<>	161:2cc1468da177	1159	#endif /* DSI */
<>	161:2cc1468da177	1160
<>	161:2cc1468da177	1161	#if defined(LTDC)
<>	161:2cc1468da177	1162	/**
<>	161:2cc1468da177	1163	* @brief Return LTDC clock frequency
<>	161:2cc1468da177	1164	* @param LTDCxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1165	* @arg @ref LL_RCC_LTDC_CLKSOURCE
<>	161:2cc1468da177	1166	* @retval LTDC clock frequency (in Hz)
<>	161:2cc1468da177	1167	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
<>	161:2cc1468da177	1168	*/
<>	161:2cc1468da177	1169	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
<>	161:2cc1468da177	1170	{
<>	161:2cc1468da177	1171	uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1172
<>	161:2cc1468da177	1173	/* Check parameter */
<>	161:2cc1468da177	1174	assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
<>	161:2cc1468da177	1175
<>	161:2cc1468da177	1176	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	1177	{
<>	161:2cc1468da177	1178	ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
<>	161:2cc1468da177	1179	}
<>	161:2cc1468da177	1180
<>	161:2cc1468da177	1181	return ltdc_frequency;
<>	161:2cc1468da177	1182	}
<>	161:2cc1468da177	1183	#endif /* LTDC */
<>	161:2cc1468da177	1184
<>	161:2cc1468da177	1185	#if defined(SPDIFRX)
<>	161:2cc1468da177	1186	/**
<>	161:2cc1468da177	1187	* @brief Return SPDIFRX clock frequency
<>	161:2cc1468da177	1188	* @param SPDIFRXxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1189	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
<>	161:2cc1468da177	1190	* @retval SPDIFRX clock frequency (in Hz)
<>	161:2cc1468da177	1191	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
<>	161:2cc1468da177	1192	*/
<>	161:2cc1468da177	1193	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
<>	161:2cc1468da177	1194	{
<>	161:2cc1468da177	1195	uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1196
<>	161:2cc1468da177	1197	/* Check parameter */
<>	161:2cc1468da177	1198	assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
<>	161:2cc1468da177	1199
<>	161:2cc1468da177	1200	if (LL_RCC_PLLI2S_IsReady())
<>	161:2cc1468da177	1201	{
<>	161:2cc1468da177	1202	spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
<>	161:2cc1468da177	1203	}
<>	161:2cc1468da177	1204
<>	161:2cc1468da177	1205	return spdifrx_frequency;
<>	161:2cc1468da177	1206	}
<>	161:2cc1468da177	1207	#endif /* SPDIFRX */
<>	161:2cc1468da177	1208
<>	161:2cc1468da177	1209	/**
<>	161:2cc1468da177	1210	* @}
<>	161:2cc1468da177	1211	*/
<>	161:2cc1468da177	1212
<>	161:2cc1468da177	1213	/**
<>	161:2cc1468da177	1214	* @}
<>	161:2cc1468da177	1215	*/
<>	161:2cc1468da177	1216
<>	161:2cc1468da177	1217	/** @addtogroup RCC_LL_Private_Functions
<>	161:2cc1468da177	1218	* @{
<>	161:2cc1468da177	1219	*/
<>	161:2cc1468da177	1220
<>	161:2cc1468da177	1221	/**
<>	161:2cc1468da177	1222	* @brief Return SYSTEM clock frequency
<>	161:2cc1468da177	1223	* @retval SYSTEM clock frequency (in Hz)
<>	161:2cc1468da177	1224	*/
<>	161:2cc1468da177	1225	uint32_t RCC_GetSystemClockFreq(void)
<>	161:2cc1468da177	1226	{
<>	161:2cc1468da177	1227	uint32_t frequency = 0U;
<>	161:2cc1468da177	1228
<>	161:2cc1468da177	1229	/* Get SYSCLK source -------------------------------------------------------*/
<>	161:2cc1468da177	1230	switch (LL_RCC_GetSysClkSource())
<>	161:2cc1468da177	1231	{
<>	161:2cc1468da177	1232	case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<>	161:2cc1468da177	1233	frequency = HSI_VALUE;
<>	161:2cc1468da177	1234	break;
<>	161:2cc1468da177	1235
<>	161:2cc1468da177	1236	case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
<>	161:2cc1468da177	1237	frequency = HSE_VALUE;
<>	161:2cc1468da177	1238	break;
<>	161:2cc1468da177	1239
<>	161:2cc1468da177	1240	case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
<>	161:2cc1468da177	1241	frequency = RCC_PLL_GetFreqDomain_SYS();
<>	161:2cc1468da177	1242	break;
<>	161:2cc1468da177	1243
<>	161:2cc1468da177	1244	default:
<>	161:2cc1468da177	1245	frequency = HSI_VALUE;
<>	161:2cc1468da177	1246	break;
<>	161:2cc1468da177	1247	}
<>	161:2cc1468da177	1248
<>	161:2cc1468da177	1249	return frequency;
<>	161:2cc1468da177	1250	}
<>	161:2cc1468da177	1251
<>	161:2cc1468da177	1252	/**
<>	161:2cc1468da177	1253	* @brief Return HCLK clock frequency
<>	161:2cc1468da177	1254	* @param SYSCLK_Frequency SYSCLK clock frequency
<>	161:2cc1468da177	1255	* @retval HCLK clock frequency (in Hz)
<>	161:2cc1468da177	1256	*/
<>	161:2cc1468da177	1257	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
<>	161:2cc1468da177	1258	{
<>	161:2cc1468da177	1259	/* HCLK clock frequency */
<>	161:2cc1468da177	1260	return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
<>	161:2cc1468da177	1261	}
<>	161:2cc1468da177	1262
<>	161:2cc1468da177	1263	/**
<>	161:2cc1468da177	1264	* @brief Return PCLK1 clock frequency
<>	161:2cc1468da177	1265	* @param HCLK_Frequency HCLK clock frequency
<>	161:2cc1468da177	1266	* @retval PCLK1 clock frequency (in Hz)
<>	161:2cc1468da177	1267	*/
<>	161:2cc1468da177	1268	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
<>	161:2cc1468da177	1269	{
<>	161:2cc1468da177	1270	/* PCLK1 clock frequency */
<>	161:2cc1468da177	1271	return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
<>	161:2cc1468da177	1272	}
<>	161:2cc1468da177	1273
<>	161:2cc1468da177	1274	/**
<>	161:2cc1468da177	1275	* @brief Return PCLK2 clock frequency
<>	161:2cc1468da177	1276	* @param HCLK_Frequency HCLK clock frequency
<>	161:2cc1468da177	1277	* @retval PCLK2 clock frequency (in Hz)
<>	161:2cc1468da177	1278	*/
<>	161:2cc1468da177	1279	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
<>	161:2cc1468da177	1280	{
<>	161:2cc1468da177	1281	/* PCLK2 clock frequency */
<>	161:2cc1468da177	1282	return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
<>	161:2cc1468da177	1283	}
<>	161:2cc1468da177	1284
<>	161:2cc1468da177	1285	/**
<>	161:2cc1468da177	1286	* @brief Return PLL clock frequency used for system domain
<>	161:2cc1468da177	1287	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1288	*/
<>	161:2cc1468da177	1289	uint32_t RCC_PLL_GetFreqDomain_SYS(void)
<>	161:2cc1468da177	1290	{
<>	161:2cc1468da177	1291	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1292
<>	161:2cc1468da177	1293	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
<>	161:2cc1468da177	1294	SYSCLK = PLL_VCO / PLLP
<>	161:2cc1468da177	1295	*/
<>	161:2cc1468da177	1296	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1297
<>	161:2cc1468da177	1298	switch (pllsource)
<>	161:2cc1468da177	1299	{
<>	161:2cc1468da177	1300	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<>	161:2cc1468da177	1301	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1302	break;
<>	161:2cc1468da177	1303
<>	161:2cc1468da177	1304	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<>	161:2cc1468da177	1305	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1306	break;
<>	161:2cc1468da177	1307
<>	161:2cc1468da177	1308	default:
<>	161:2cc1468da177	1309	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1310	break;
<>	161:2cc1468da177	1311	}
<>	161:2cc1468da177	1312	return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1313	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
<>	161:2cc1468da177	1314	}
<>	161:2cc1468da177	1315
<>	161:2cc1468da177	1316	/**
<>	161:2cc1468da177	1317	* @brief Return PLL clock frequency used for 48 MHz domain
<>	161:2cc1468da177	1318	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1319	*/
<>	161:2cc1468da177	1320	uint32_t RCC_PLL_GetFreqDomain_48M(void)
<>	161:2cc1468da177	1321	{
<>	161:2cc1468da177	1322	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1323
<>	161:2cc1468da177	1324	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
<>	161:2cc1468da177	1325	48M Domain clock = PLL_VCO / PLLQ
<>	161:2cc1468da177	1326	*/
<>	161:2cc1468da177	1327	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1328
<>	161:2cc1468da177	1329	switch (pllsource)
<>	161:2cc1468da177	1330	{
<>	161:2cc1468da177	1331	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<>	161:2cc1468da177	1332	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1333	break;
<>	161:2cc1468da177	1334
<>	161:2cc1468da177	1335	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<>	161:2cc1468da177	1336	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1337	break;
<>	161:2cc1468da177	1338
<>	161:2cc1468da177	1339	default:
<>	161:2cc1468da177	1340	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1341	break;
<>	161:2cc1468da177	1342	}
<>	161:2cc1468da177	1343	return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1344	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
<>	161:2cc1468da177	1345	}
<>	161:2cc1468da177	1346
<>	161:2cc1468da177	1347	#if defined(DSI)
<>	161:2cc1468da177	1348	/**
<>	161:2cc1468da177	1349	* @brief Return PLL clock frequency used for DSI clock
<>	161:2cc1468da177	1350	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1351	*/
<>	161:2cc1468da177	1352	uint32_t RCC_PLL_GetFreqDomain_DSI(void)
<>	161:2cc1468da177	1353	{
<>	161:2cc1468da177	1354	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1355
<>	161:2cc1468da177	1356	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
<>	161:2cc1468da177	1357	DSICLK = PLL_VCO / PLLR
<>	161:2cc1468da177	1358	*/
<>	161:2cc1468da177	1359	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1360
<>	161:2cc1468da177	1361	switch (pllsource)
<>	161:2cc1468da177	1362	{
<>	161:2cc1468da177	1363	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<>	161:2cc1468da177	1364	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1365	break;
<>	161:2cc1468da177	1366
<>	161:2cc1468da177	1367	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<>	161:2cc1468da177	1368	default:
<>	161:2cc1468da177	1369	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1370	break;
<>	161:2cc1468da177	1371	}
<>	161:2cc1468da177	1372	return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1373	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
<>	161:2cc1468da177	1374	}
<>	161:2cc1468da177	1375	#endif /* DSI */
<>	161:2cc1468da177	1376
<>	161:2cc1468da177	1377	/**
<>	161:2cc1468da177	1378	* @brief Return PLLSAI clock frequency used for SAI1 and SAI2 domains
<>	161:2cc1468da177	1379	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1380	*/
<>	161:2cc1468da177	1381	uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
<>	161:2cc1468da177	1382	{
<>	161:2cc1468da177	1383	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1384
<>	161:2cc1468da177	1385	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
<>	161:2cc1468da177	1386	SAI1 and SAI2 domains clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
<>	161:2cc1468da177	1387	*/
<>	161:2cc1468da177	1388	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1389
<>	161:2cc1468da177	1390	switch (pllsource)
<>	161:2cc1468da177	1391	{
<>	161:2cc1468da177	1392	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
<>	161:2cc1468da177	1393	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1394	break;
<>	161:2cc1468da177	1395
<>	161:2cc1468da177	1396	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
<>	161:2cc1468da177	1397	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1398	break;
<>	161:2cc1468da177	1399
<>	161:2cc1468da177	1400	default:
<>	161:2cc1468da177	1401	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1402	break;
<>	161:2cc1468da177	1403	}
<>	161:2cc1468da177	1404	return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1405	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
<>	161:2cc1468da177	1406	}
<>	161:2cc1468da177	1407
<>	161:2cc1468da177	1408	/**
<>	161:2cc1468da177	1409	* @brief Return PLLSAI clock frequency used for 48Mhz domain
<>	161:2cc1468da177	1410	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1411	*/
<>	161:2cc1468da177	1412	uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
<>	161:2cc1468da177	1413	{
<>	161:2cc1468da177	1414	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1415
<>	161:2cc1468da177	1416	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
<>	161:2cc1468da177	1417	48M Domain clock = PLLSAI_VCO / PLLSAIP
<>	161:2cc1468da177	1418	*/
<>	161:2cc1468da177	1419	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1420
<>	161:2cc1468da177	1421	switch (pllsource)
<>	161:2cc1468da177	1422	{
<>	161:2cc1468da177	1423	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
<>	161:2cc1468da177	1424	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1425	break;
<>	161:2cc1468da177	1426
<>	161:2cc1468da177	1427	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
<>	161:2cc1468da177	1428	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1429	break;
<>	161:2cc1468da177	1430
<>	161:2cc1468da177	1431	default:
<>	161:2cc1468da177	1432	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1433	break;
<>	161:2cc1468da177	1434	}
<>	161:2cc1468da177	1435	return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1436	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
<>	161:2cc1468da177	1437	}
<>	161:2cc1468da177	1438
<>	161:2cc1468da177	1439	#if defined(LTDC)
<>	161:2cc1468da177	1440	/**
<>	161:2cc1468da177	1441	* @brief Return PLLSAI clock frequency used for LTDC domain
<>	161:2cc1468da177	1442	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1443	*/
<>	161:2cc1468da177	1444	uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
<>	161:2cc1468da177	1445	{
<>	161:2cc1468da177	1446	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1447
<>	161:2cc1468da177	1448	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
<>	161:2cc1468da177	1449	LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
<>	161:2cc1468da177	1450	*/
<>	161:2cc1468da177	1451	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1452
<>	161:2cc1468da177	1453	switch (pllsource)
<>	161:2cc1468da177	1454	{
<>	161:2cc1468da177	1455	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
<>	161:2cc1468da177	1456	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1457	break;
<>	161:2cc1468da177	1458
<>	161:2cc1468da177	1459	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
<>	161:2cc1468da177	1460	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1461	break;
<>	161:2cc1468da177	1462
<>	161:2cc1468da177	1463	default:
<>	161:2cc1468da177	1464	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1465	break;
<>	161:2cc1468da177	1466	}
<>	161:2cc1468da177	1467	return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1468	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
<>	161:2cc1468da177	1469	}
<>	161:2cc1468da177	1470	#endif /* LTDC */
<>	161:2cc1468da177	1471
<>	161:2cc1468da177	1472	/**
<>	161:2cc1468da177	1473	* @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains
<>	161:2cc1468da177	1474	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1475	*/
<>	161:2cc1468da177	1476	uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
<>	161:2cc1468da177	1477	{
<>	161:2cc1468da177	1478	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1479
<>	161:2cc1468da177	1480	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
<>	161:2cc1468da177	1481	SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
<>	161:2cc1468da177	1482	*/
<>	161:2cc1468da177	1483	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1484
<>	161:2cc1468da177	1485	switch (pllsource)
<>	161:2cc1468da177	1486	{
<>	161:2cc1468da177	1487	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
<>	161:2cc1468da177	1488	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1489	break;
<>	161:2cc1468da177	1490
<>	161:2cc1468da177	1491	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
<>	161:2cc1468da177	1492	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1493	break;
<>	161:2cc1468da177	1494
<>	161:2cc1468da177	1495	default:
<>	161:2cc1468da177	1496	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1497	break;
<>	161:2cc1468da177	1498	}
<>	161:2cc1468da177	1499	return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1500	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
<>	161:2cc1468da177	1501	}
<>	161:2cc1468da177	1502
<>	161:2cc1468da177	1503	#if defined(SPDIFRX)
<>	161:2cc1468da177	1504	/**
<>	161:2cc1468da177	1505	* @brief Return PLLI2S clock frequency used for SPDIFRX domain
<>	161:2cc1468da177	1506	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1507	*/
<>	161:2cc1468da177	1508	uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
<>	161:2cc1468da177	1509	{
<>	161:2cc1468da177	1510	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1511
<>	161:2cc1468da177	1512	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
<>	161:2cc1468da177	1513	SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
<>	161:2cc1468da177	1514	*/
<>	161:2cc1468da177	1515	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1516
<>	161:2cc1468da177	1517	switch (pllsource)
<>	161:2cc1468da177	1518	{
<>	161:2cc1468da177	1519	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
<>	161:2cc1468da177	1520	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1521	break;
<>	161:2cc1468da177	1522
<>	161:2cc1468da177	1523	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
<>	161:2cc1468da177	1524	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1525	break;
<>	161:2cc1468da177	1526
<>	161:2cc1468da177	1527	default:
<>	161:2cc1468da177	1528	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1529	break;
<>	161:2cc1468da177	1530	}
<>	161:2cc1468da177	1531
<>	161:2cc1468da177	1532	return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1533	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
<>	161:2cc1468da177	1534	}
<>	161:2cc1468da177	1535	#endif /* SPDIFRX */
<>	161:2cc1468da177	1536
<>	161:2cc1468da177	1537	/**
<>	161:2cc1468da177	1538	* @brief Return PLLI2S clock frequency used for I2S domain
<>	161:2cc1468da177	1539	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1540	*/
<>	161:2cc1468da177	1541	uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
<>	161:2cc1468da177	1542	{
<>	161:2cc1468da177	1543	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1544
<>	161:2cc1468da177	1545	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
<>	161:2cc1468da177	1546	I2S Domain clock = PLLI2S_VCO / PLLI2SR
<>	161:2cc1468da177	1547	*/
<>	161:2cc1468da177	1548	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1549
<>	161:2cc1468da177	1550	switch (pllsource)
<>	161:2cc1468da177	1551	{
<>	161:2cc1468da177	1552	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
<>	161:2cc1468da177	1553	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1554	break;
<>	161:2cc1468da177	1555
<>	161:2cc1468da177	1556	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
<>	161:2cc1468da177	1557	default:
<>	161:2cc1468da177	1558	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1559	break;
<>	161:2cc1468da177	1560	}
<>	161:2cc1468da177	1561	return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1562	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
<>	161:2cc1468da177	1563	}
<>	161:2cc1468da177	1564
<>	161:2cc1468da177	1565	/**
<>	161:2cc1468da177	1566	* @}
<>	161:2cc1468da177	1567	*/
<>	161:2cc1468da177	1568
<>	161:2cc1468da177	1569	/**
<>	161:2cc1468da177	1570	* @}
<>	161:2cc1468da177	1571	*/
<>	161:2cc1468da177	1572
<>	161:2cc1468da177	1573	#endif /* defined(RCC) */
<>	161:2cc1468da177	1574
<>	161:2cc1468da177	1575	/**
<>	161:2cc1468da177	1576	* @}
<>	161:2cc1468da177	1577	*/
<>	161:2cc1468da177	1578
<>	161:2cc1468da177	1579	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	1580
<>	161:2cc1468da177	1581	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/