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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.c@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:: AnnaBridge
Date:: Tue Mar 20 16:56:18 2018 +0000
Revision:: 182:a56a73fd2a6f
Parent:: 161:2cc1468da177

mbed-dev library. Release version 160

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_rcc.c
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @brief RCC LL module driver.
<>	161:2cc1468da177	6	******************************************************************************
<>	161:2cc1468da177	7	* @attention
<>	161:2cc1468da177	8	*
<>	161:2cc1468da177	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	12	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	14	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	17	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	19	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	20	* without specific prior written permission.
<>	161:2cc1468da177	21	*
<>	161:2cc1468da177	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	32	*
<>	161:2cc1468da177	33	******************************************************************************
<>	161:2cc1468da177	34	*/
<>	161:2cc1468da177	35	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	36
<>	161:2cc1468da177	37	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	38	#include "stm32f7xx_ll_rcc.h"
<>	161:2cc1468da177	39	#ifdef USE_FULL_ASSERT
<>	161:2cc1468da177	40	#include "stm32_assert.h"
<>	161:2cc1468da177	41	#else
<>	161:2cc1468da177	42	#define assert_param(expr) ((void)0U)
<>	161:2cc1468da177	43	#endif
<>	161:2cc1468da177	44
<>	161:2cc1468da177	45	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	46	* @{
<>	161:2cc1468da177	47	*/
<>	161:2cc1468da177	48
<>	161:2cc1468da177	49	#if defined(RCC)
<>	161:2cc1468da177	50
<>	161:2cc1468da177	51	/** @addtogroup RCC_LL
<>	161:2cc1468da177	52	* @{
<>	161:2cc1468da177	53	*/
<>	161:2cc1468da177	54
<>	161:2cc1468da177	55	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	56	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	57	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	58	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	59	/** @addtogroup RCC_LL_Private_Macros
<>	161:2cc1468da177	60	* @{
<>	161:2cc1468da177	61	*/
<>	161:2cc1468da177	62	#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
<>	161:2cc1468da177	63	\|\| ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
<>	161:2cc1468da177	64	\|\| ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
<>	161:2cc1468da177	65	\|\| ((__VALUE__) == LL_RCC_USART6_CLKSOURCE))
<>	161:2cc1468da177	66
<>	161:2cc1468da177	67	#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
<>	161:2cc1468da177	68	\|\| ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
<>	161:2cc1468da177	69	\|\| ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
<>	161:2cc1468da177	70	\|\| ((__VALUE__) == LL_RCC_UART8_CLKSOURCE))
<>	161:2cc1468da177	71
<>	161:2cc1468da177	72	#if defined(I2C4)
<>	161:2cc1468da177	73	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<>	161:2cc1468da177	74	\|\| ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
<>	161:2cc1468da177	75	\|\| ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
<>	161:2cc1468da177	76	\|\| ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
<>	161:2cc1468da177	77	#else
<>	161:2cc1468da177	78	#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
<>	161:2cc1468da177	79	\|\| ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
<>	161:2cc1468da177	80	\|\| ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
<>	161:2cc1468da177	81	#endif /* I2C4 */
<>	161:2cc1468da177	82
<>	161:2cc1468da177	83	#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
<>	161:2cc1468da177	84
<>	161:2cc1468da177	85	#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
<>	161:2cc1468da177	86	\|\| ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
<>	161:2cc1468da177	87
<>	161:2cc1468da177	88	#if defined(SDMMC2)
<>	161:2cc1468da177	89	#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
<>	161:2cc1468da177	90	\|\| ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
<>	161:2cc1468da177	91	#else
<>	161:2cc1468da177	92	#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
<>	161:2cc1468da177	93	#endif /* SDMMC2 */
<>	161:2cc1468da177	94
<>	161:2cc1468da177	95	#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
<>	161:2cc1468da177	96
<>	161:2cc1468da177	97	#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
<>	161:2cc1468da177	98
<>	161:2cc1468da177	99	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	100	#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
<>	161:2cc1468da177	101
<>	161:2cc1468da177	102	#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
<>	161:2cc1468da177	103	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	104
<>	161:2cc1468da177	105	#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
<>	161:2cc1468da177	106
<>	161:2cc1468da177	107	#if defined(CEC)
<>	161:2cc1468da177	108	#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
<>	161:2cc1468da177	109	#endif /* CEC */
<>	161:2cc1468da177	110
<>	161:2cc1468da177	111	#if defined(DSI)
<>	161:2cc1468da177	112	#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
<>	161:2cc1468da177	113	#endif /* DSI */
<>	161:2cc1468da177	114
<>	161:2cc1468da177	115	#if defined(LTDC)
<>	161:2cc1468da177	116	#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
<>	161:2cc1468da177	117	#endif /* LTDC */
<>	161:2cc1468da177	118
<>	161:2cc1468da177	119	#if defined(SPDIFRX)
<>	161:2cc1468da177	120	#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
<>	161:2cc1468da177	121	#endif /* SPDIFRX */
<>	161:2cc1468da177	122
<>	161:2cc1468da177	123	/**
<>	161:2cc1468da177	124	* @}
<>	161:2cc1468da177	125	*/
<>	161:2cc1468da177	126
<>	161:2cc1468da177	127	/* Private function prototypes -----------------------------------------------*/
<>	161:2cc1468da177	128	/** @defgroup RCC_LL_Private_Functions RCC Private functions
<>	161:2cc1468da177	129	* @{
<>	161:2cc1468da177	130	*/
<>	161:2cc1468da177	131	uint32_t RCC_GetSystemClockFreq(void);
<>	161:2cc1468da177	132	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
<>	161:2cc1468da177	133	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
<>	161:2cc1468da177	134	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
<>	161:2cc1468da177	135	uint32_t RCC_PLL_GetFreqDomain_SYS(void);
<>	161:2cc1468da177	136	uint32_t RCC_PLL_GetFreqDomain_SAI(void);
<>	161:2cc1468da177	137	uint32_t RCC_PLL_GetFreqDomain_48M(void);
<>	161:2cc1468da177	138	#if defined(DSI)
<>	161:2cc1468da177	139	uint32_t RCC_PLL_GetFreqDomain_DSI(void);
<>	161:2cc1468da177	140	#endif /* DSI */
<>	161:2cc1468da177	141	uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
<>	161:2cc1468da177	142	uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
<>	161:2cc1468da177	143	#if defined(LTDC)
<>	161:2cc1468da177	144	uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
<>	161:2cc1468da177	145	#endif /* LTDC */
<>	161:2cc1468da177	146	uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
<>	161:2cc1468da177	147	uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
<>	161:2cc1468da177	148	#if defined(SPDIFRX)
<>	161:2cc1468da177	149	uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
<>	161:2cc1468da177	150	#endif /* SPDIFRX */
<>	161:2cc1468da177	151	/**
<>	161:2cc1468da177	152	* @}
<>	161:2cc1468da177	153	*/
<>	161:2cc1468da177	154
<>	161:2cc1468da177	155
<>	161:2cc1468da177	156	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	157	/** @addtogroup RCC_LL_Exported_Functions
<>	161:2cc1468da177	158	* @{
<>	161:2cc1468da177	159	*/
<>	161:2cc1468da177	160
<>	161:2cc1468da177	161	/** @addtogroup RCC_LL_EF_Init
<>	161:2cc1468da177	162	* @{
<>	161:2cc1468da177	163	*/
<>	161:2cc1468da177	164
<>	161:2cc1468da177	165	/**
<>	161:2cc1468da177	166	* @brief Reset the RCC clock configuration to the default reset state.
<>	161:2cc1468da177	167	* @note The default reset state of the clock configuration is given below:
<>	161:2cc1468da177	168	* - HSI ON and used as system clock source
AnnaBridge	182:a56a73fd2a6f	169	* - HSE, PLL, PLLI2S, PLLSAI OFF
<>	161:2cc1468da177	170	* - AHB, APB1 and APB2 prescaler set to 1.
<>	161:2cc1468da177	171	* - CSS, MCO OFF
<>	161:2cc1468da177	172	* - All interrupts disabled
<>	161:2cc1468da177	173	* @note This function doesn't modify the configuration of the
<>	161:2cc1468da177	174	* - Peripheral clocks
<>	161:2cc1468da177	175	* - LSI, LSE and RTC clocks
<>	161:2cc1468da177	176	* @retval An ErrorStatus enumeration value:
<>	161:2cc1468da177	177	* - SUCCESS: RCC registers are de-initialized
<>	161:2cc1468da177	178	* - ERROR: not applicable
<>	161:2cc1468da177	179	*/
<>	161:2cc1468da177	180	ErrorStatus LL_RCC_DeInit(void)
<>	161:2cc1468da177	181	{
AnnaBridge	182:a56a73fd2a6f	182	uint32_t vl_mask = 0xFFFFFFFFU;
<>	161:2cc1468da177	183
<>	161:2cc1468da177	184	/* Set HSION bit */
<>	161:2cc1468da177	185	LL_RCC_HSI_Enable();
<>	161:2cc1468da177	186
AnnaBridge	182:a56a73fd2a6f	187	/* Wait for HSI READY bit */
AnnaBridge	182:a56a73fd2a6f	188	while(LL_RCC_HSI_IsReady() != 1U)
AnnaBridge	182:a56a73fd2a6f	189	{}
AnnaBridge	182:a56a73fd2a6f	190
<>	161:2cc1468da177	191	/* Reset CFGR register */
<>	161:2cc1468da177	192	LL_RCC_WriteReg(CFGR, 0x00000000U);
<>	161:2cc1468da177	193
AnnaBridge	182:a56a73fd2a6f	194	/* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
AnnaBridge	182:a56a73fd2a6f	195	CLEAR_BIT(vl_mask, (RCC_CR_HSEON \| RCC_CR_HSEBYP \| RCC_CR_PLLON \| RCC_CR_CSSON \| RCC_CR_PLLSAION \| RCC_CR_PLLI2SON));
<>	161:2cc1468da177	196
<>	161:2cc1468da177	197	/* Write new mask in CR register */
<>	161:2cc1468da177	198	LL_RCC_WriteReg(CR, vl_mask);
<>	161:2cc1468da177	199
<>	161:2cc1468da177	200	/* Set HSITRIM bits to the reset value*/
<>	161:2cc1468da177	201	LL_RCC_HSI_SetCalibTrimming(0x10U);
<>	161:2cc1468da177	202
AnnaBridge	182:a56a73fd2a6f	203	/* Wait for PLL READY bit to be reset */
AnnaBridge	182:a56a73fd2a6f	204	while(LL_RCC_PLL_IsReady() != 0U)
AnnaBridge	182:a56a73fd2a6f	205	{}
AnnaBridge	182:a56a73fd2a6f	206
AnnaBridge	182:a56a73fd2a6f	207	/* Wait for PLLI2S READY bit to be reset */
AnnaBridge	182:a56a73fd2a6f	208	while(LL_RCC_PLLI2S_IsReady() != 0U)
AnnaBridge	182:a56a73fd2a6f	209	{}
AnnaBridge	182:a56a73fd2a6f	210
AnnaBridge	182:a56a73fd2a6f	211	/* Wait for PLLSAI READY bit to be reset */
AnnaBridge	182:a56a73fd2a6f	212	while(LL_RCC_PLLSAI_IsReady() != 0U)
AnnaBridge	182:a56a73fd2a6f	213	{}
AnnaBridge	182:a56a73fd2a6f	214
<>	161:2cc1468da177	215	/* Reset PLLCFGR register */
<>	161:2cc1468da177	216	LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
<>	161:2cc1468da177	217
<>	161:2cc1468da177	218	/* Reset PLLI2SCFGR register */
<>	161:2cc1468da177	219	LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U);
<>	161:2cc1468da177	220
<>	161:2cc1468da177	221	/* Reset PLLSAICFGR register */
<>	161:2cc1468da177	222	LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
<>	161:2cc1468da177	223
AnnaBridge	182:a56a73fd2a6f	224	/* Disable all interrupts */
AnnaBridge	182:a56a73fd2a6f	225	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE \| RCC_CIR_LSERDYIE \| RCC_CIR_HSIRDYIE \| RCC_CIR_HSERDYIE \| RCC_CIR_PLLRDYIE \| RCC_CIR_PLLI2SRDYIE \| RCC_CIR_PLLSAIRDYIE);
AnnaBridge	182:a56a73fd2a6f	226
AnnaBridge	182:a56a73fd2a6f	227	/* Clear all interrupt flags */
AnnaBridge	182:a56a73fd2a6f	228	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC \| RCC_CIR_LSERDYC \| RCC_CIR_HSIRDYC \| RCC_CIR_HSERDYC \| RCC_CIR_PLLRDYC \| RCC_CIR_PLLI2SRDYC \| RCC_CIR_PLLSAIRDYC \| RCC_CIR_CSSC);
<>	161:2cc1468da177	229
AnnaBridge	182:a56a73fd2a6f	230	/* Clear LSION bit */
AnnaBridge	182:a56a73fd2a6f	231	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	182:a56a73fd2a6f	232
AnnaBridge	182:a56a73fd2a6f	233	/* Reset all CSR flags */
AnnaBridge	182:a56a73fd2a6f	234	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
<>	161:2cc1468da177	235
<>	161:2cc1468da177	236	return SUCCESS;
<>	161:2cc1468da177	237	}
<>	161:2cc1468da177	238
<>	161:2cc1468da177	239	/**
<>	161:2cc1468da177	240	* @}
<>	161:2cc1468da177	241	*/
<>	161:2cc1468da177	242
<>	161:2cc1468da177	243	/** @addtogroup RCC_LL_EF_Get_Freq
<>	161:2cc1468da177	244	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<>	161:2cc1468da177	245	* and different peripheral clocks available on the device.
<>	161:2cc1468da177	246	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
<>	161:2cc1468da177	247	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
<>	161:2cc1468da177	248	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
<>	161:2cc1468da177	249	* or HSI_VALUE(**) multiplied/divided by the PLL factors.
<>	161:2cc1468da177	250	* @note (**) HSI_VALUE is a constant defined in this file (default value
<>	161:2cc1468da177	251	* 16 MHz) but the real value may vary depending on the variations
<>	161:2cc1468da177	252	* in voltage and temperature.
<>	161:2cc1468da177	253	* @note (***) HSE_VALUE is a constant defined in this file (default value
<>	161:2cc1468da177	254	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
<>	161:2cc1468da177	255	* frequency of the crystal used. Otherwise, this function may
<>	161:2cc1468da177	256	* have wrong result.
<>	161:2cc1468da177	257	* @note The result of this function could be incorrect when using fractional
<>	161:2cc1468da177	258	* value for HSE crystal.
<>	161:2cc1468da177	259	* @note This function can be used by the user application to compute the
<>	161:2cc1468da177	260	* baud-rate for the communication peripherals or configure other parameters.
<>	161:2cc1468da177	261	* @{
<>	161:2cc1468da177	262	*/
<>	161:2cc1468da177	263
<>	161:2cc1468da177	264	/**
<>	161:2cc1468da177	265	* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
<>	161:2cc1468da177	266	* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
<>	161:2cc1468da177	267	* must be called to update structure fields. Otherwise, any
<>	161:2cc1468da177	268	* configuration based on this function will be incorrect.
<>	161:2cc1468da177	269	* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
<>	161:2cc1468da177	270	* @retval None
<>	161:2cc1468da177	271	*/
<>	161:2cc1468da177	272	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
<>	161:2cc1468da177	273	{
<>	161:2cc1468da177	274	/* Get SYSCLK frequency */
<>	161:2cc1468da177	275	RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	276
<>	161:2cc1468da177	277	/* HCLK clock frequency */
<>	161:2cc1468da177	278	RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
<>	161:2cc1468da177	279
<>	161:2cc1468da177	280	/* PCLK1 clock frequency */
<>	161:2cc1468da177	281	RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
<>	161:2cc1468da177	282
<>	161:2cc1468da177	283	/* PCLK2 clock frequency */
<>	161:2cc1468da177	284	RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
<>	161:2cc1468da177	285	}
<>	161:2cc1468da177	286
<>	161:2cc1468da177	287	/**
<>	161:2cc1468da177	288	* @brief Return USARTx clock frequency
<>	161:2cc1468da177	289	* @param USARTxSource This parameter can be one of the following values:
<>	161:2cc1468da177	290	* @arg @ref LL_RCC_USART1_CLKSOURCE
<>	161:2cc1468da177	291	* @arg @ref LL_RCC_USART2_CLKSOURCE
<>	161:2cc1468da177	292	* @arg @ref LL_RCC_USART3_CLKSOURCE
<>	161:2cc1468da177	293	* @arg @ref LL_RCC_USART6_CLKSOURCE
<>	161:2cc1468da177	294	* @retval USART clock frequency (in Hz)
<>	161:2cc1468da177	295	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<>	161:2cc1468da177	296	*/
<>	161:2cc1468da177	297	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
<>	161:2cc1468da177	298	{
<>	161:2cc1468da177	299	uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	300
<>	161:2cc1468da177	301	/* Check parameter */
<>	161:2cc1468da177	302	assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
<>	161:2cc1468da177	303
<>	161:2cc1468da177	304	if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
<>	161:2cc1468da177	305	{
<>	161:2cc1468da177	306	/* USART1CLK clock frequency */
<>	161:2cc1468da177	307	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	161:2cc1468da177	308	{
<>	161:2cc1468da177	309	case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
<>	161:2cc1468da177	310	usart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	311	break;
<>	161:2cc1468da177	312
<>	161:2cc1468da177	313	case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
<>	161:2cc1468da177	314	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	315	{
<>	161:2cc1468da177	316	usart_frequency = HSI_VALUE;
<>	161:2cc1468da177	317	}
<>	161:2cc1468da177	318	break;
<>	161:2cc1468da177	319
<>	161:2cc1468da177	320	case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
<>	161:2cc1468da177	321	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	322	{
<>	161:2cc1468da177	323	usart_frequency = LSE_VALUE;
<>	161:2cc1468da177	324	}
<>	161:2cc1468da177	325	break;
<>	161:2cc1468da177	326
<>	161:2cc1468da177	327	case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
<>	161:2cc1468da177	328	default:
<>	161:2cc1468da177	329	usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	330	break;
<>	161:2cc1468da177	331	}
<>	161:2cc1468da177	332	}
<>	161:2cc1468da177	333	else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
<>	161:2cc1468da177	334	{
<>	161:2cc1468da177	335	/* USART2CLK clock frequency */
<>	161:2cc1468da177	336	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	161:2cc1468da177	337	{
<>	161:2cc1468da177	338	case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
<>	161:2cc1468da177	339	usart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	340	break;
<>	161:2cc1468da177	341
<>	161:2cc1468da177	342	case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
<>	161:2cc1468da177	343	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	344	{
<>	161:2cc1468da177	345	usart_frequency = HSI_VALUE;
<>	161:2cc1468da177	346	}
<>	161:2cc1468da177	347	break;
<>	161:2cc1468da177	348
<>	161:2cc1468da177	349	case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
<>	161:2cc1468da177	350	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	351	{
<>	161:2cc1468da177	352	usart_frequency = LSE_VALUE;
<>	161:2cc1468da177	353	}
<>	161:2cc1468da177	354	break;
<>	161:2cc1468da177	355
<>	161:2cc1468da177	356	case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
<>	161:2cc1468da177	357	default:
<>	161:2cc1468da177	358	usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	359	break;
<>	161:2cc1468da177	360	}
<>	161:2cc1468da177	361	}
<>	161:2cc1468da177	362	else if (USARTxSource == LL_RCC_USART6_CLKSOURCE)
<>	161:2cc1468da177	363	{
<>	161:2cc1468da177	364	/* USART6CLK clock frequency */
<>	161:2cc1468da177	365	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	161:2cc1468da177	366	{
<>	161:2cc1468da177	367	case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */
<>	161:2cc1468da177	368	usart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	369	break;
<>	161:2cc1468da177	370
<>	161:2cc1468da177	371	case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */
<>	161:2cc1468da177	372	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	373	{
<>	161:2cc1468da177	374	usart_frequency = HSI_VALUE;
<>	161:2cc1468da177	375	}
<>	161:2cc1468da177	376	break;
<>	161:2cc1468da177	377
<>	161:2cc1468da177	378	case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */
<>	161:2cc1468da177	379	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	380	{
<>	161:2cc1468da177	381	usart_frequency = LSE_VALUE;
<>	161:2cc1468da177	382	}
<>	161:2cc1468da177	383	break;
<>	161:2cc1468da177	384
<>	161:2cc1468da177	385	case LL_RCC_USART6_CLKSOURCE_PCLK2: /* USART6 Clock is PCLK2 */
<>	161:2cc1468da177	386	default:
<>	161:2cc1468da177	387	usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	388	break;
<>	161:2cc1468da177	389	}
<>	161:2cc1468da177	390	}
<>	161:2cc1468da177	391	else
<>	161:2cc1468da177	392	{
<>	161:2cc1468da177	393	if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
<>	161:2cc1468da177	394	{
<>	161:2cc1468da177	395	/* USART3CLK clock frequency */
<>	161:2cc1468da177	396	switch (LL_RCC_GetUSARTClockSource(USARTxSource))
<>	161:2cc1468da177	397	{
<>	161:2cc1468da177	398	case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
<>	161:2cc1468da177	399	usart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	400	break;
<>	161:2cc1468da177	401
<>	161:2cc1468da177	402	case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
<>	161:2cc1468da177	403	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	404	{
<>	161:2cc1468da177	405	usart_frequency = HSI_VALUE;
<>	161:2cc1468da177	406	}
<>	161:2cc1468da177	407	break;
<>	161:2cc1468da177	408
<>	161:2cc1468da177	409	case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
<>	161:2cc1468da177	410	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	411	{
<>	161:2cc1468da177	412	usart_frequency = LSE_VALUE;
<>	161:2cc1468da177	413	}
<>	161:2cc1468da177	414	break;
<>	161:2cc1468da177	415
<>	161:2cc1468da177	416	case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
<>	161:2cc1468da177	417	default:
<>	161:2cc1468da177	418	usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	419	break;
<>	161:2cc1468da177	420	}
<>	161:2cc1468da177	421	}
<>	161:2cc1468da177	422	}
<>	161:2cc1468da177	423	return usart_frequency;
<>	161:2cc1468da177	424	}
<>	161:2cc1468da177	425
<>	161:2cc1468da177	426	/**
<>	161:2cc1468da177	427	* @brief Return UARTx clock frequency
<>	161:2cc1468da177	428	* @param UARTxSource This parameter can be one of the following values:
<>	161:2cc1468da177	429	* @arg @ref LL_RCC_UART4_CLKSOURCE
<>	161:2cc1468da177	430	* @arg @ref LL_RCC_UART5_CLKSOURCE
<>	161:2cc1468da177	431	* @arg @ref LL_RCC_UART7_CLKSOURCE
<>	161:2cc1468da177	432	* @arg @ref LL_RCC_UART8_CLKSOURCE
<>	161:2cc1468da177	433	* @retval UART clock frequency (in Hz)
<>	161:2cc1468da177	434	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<>	161:2cc1468da177	435	*/
<>	161:2cc1468da177	436	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
<>	161:2cc1468da177	437	{
<>	161:2cc1468da177	438	uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	439
<>	161:2cc1468da177	440	/* Check parameter */
<>	161:2cc1468da177	441	assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
<>	161:2cc1468da177	442
<>	161:2cc1468da177	443	if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
<>	161:2cc1468da177	444	{
<>	161:2cc1468da177	445	/* UART4CLK clock frequency */
<>	161:2cc1468da177	446	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	161:2cc1468da177	447	{
<>	161:2cc1468da177	448	case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
<>	161:2cc1468da177	449	uart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	450	break;
<>	161:2cc1468da177	451
<>	161:2cc1468da177	452	case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
<>	161:2cc1468da177	453	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	454	{
<>	161:2cc1468da177	455	uart_frequency = HSI_VALUE;
<>	161:2cc1468da177	456	}
<>	161:2cc1468da177	457	break;
<>	161:2cc1468da177	458
<>	161:2cc1468da177	459	case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
<>	161:2cc1468da177	460	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	461	{
<>	161:2cc1468da177	462	uart_frequency = LSE_VALUE;
<>	161:2cc1468da177	463	}
<>	161:2cc1468da177	464	break;
<>	161:2cc1468da177	465
<>	161:2cc1468da177	466	case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
<>	161:2cc1468da177	467	default:
<>	161:2cc1468da177	468	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	469	break;
<>	161:2cc1468da177	470	}
<>	161:2cc1468da177	471	}
<>	161:2cc1468da177	472	else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
<>	161:2cc1468da177	473	{
<>	161:2cc1468da177	474	/* UART5CLK clock frequency */
<>	161:2cc1468da177	475	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	161:2cc1468da177	476	{
<>	161:2cc1468da177	477	case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
<>	161:2cc1468da177	478	uart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	479	break;
<>	161:2cc1468da177	480
<>	161:2cc1468da177	481	case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
<>	161:2cc1468da177	482	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	483	{
<>	161:2cc1468da177	484	uart_frequency = HSI_VALUE;
<>	161:2cc1468da177	485	}
<>	161:2cc1468da177	486	break;
<>	161:2cc1468da177	487
<>	161:2cc1468da177	488	case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
<>	161:2cc1468da177	489	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	490	{
<>	161:2cc1468da177	491	uart_frequency = LSE_VALUE;
<>	161:2cc1468da177	492	}
<>	161:2cc1468da177	493	break;
<>	161:2cc1468da177	494
<>	161:2cc1468da177	495	case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
<>	161:2cc1468da177	496	default:
<>	161:2cc1468da177	497	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	498	break;
<>	161:2cc1468da177	499	}
<>	161:2cc1468da177	500	}
<>	161:2cc1468da177	501	else if (UARTxSource == LL_RCC_UART7_CLKSOURCE)
<>	161:2cc1468da177	502	{
<>	161:2cc1468da177	503	/* UART7CLK clock frequency */
<>	161:2cc1468da177	504	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	161:2cc1468da177	505	{
<>	161:2cc1468da177	506	case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */
<>	161:2cc1468da177	507	uart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	508	break;
<>	161:2cc1468da177	509
<>	161:2cc1468da177	510	case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */
<>	161:2cc1468da177	511	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	512	{
<>	161:2cc1468da177	513	uart_frequency = HSI_VALUE;
<>	161:2cc1468da177	514	}
<>	161:2cc1468da177	515	break;
<>	161:2cc1468da177	516
<>	161:2cc1468da177	517	case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */
<>	161:2cc1468da177	518	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	519	{
<>	161:2cc1468da177	520	uart_frequency = LSE_VALUE;
<>	161:2cc1468da177	521	}
<>	161:2cc1468da177	522	break;
<>	161:2cc1468da177	523
<>	161:2cc1468da177	524	case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */
<>	161:2cc1468da177	525	default:
<>	161:2cc1468da177	526	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	527	break;
<>	161:2cc1468da177	528	}
<>	161:2cc1468da177	529	}
<>	161:2cc1468da177	530	else
<>	161:2cc1468da177	531	{
<>	161:2cc1468da177	532	if (UARTxSource == LL_RCC_UART8_CLKSOURCE)
<>	161:2cc1468da177	533	{
<>	161:2cc1468da177	534	/* UART8CLK clock frequency */
<>	161:2cc1468da177	535	switch (LL_RCC_GetUARTClockSource(UARTxSource))
<>	161:2cc1468da177	536	{
<>	161:2cc1468da177	537	case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */
<>	161:2cc1468da177	538	uart_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	539	break;
<>	161:2cc1468da177	540
<>	161:2cc1468da177	541	case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */
<>	161:2cc1468da177	542	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	543	{
<>	161:2cc1468da177	544	uart_frequency = HSI_VALUE;
<>	161:2cc1468da177	545	}
<>	161:2cc1468da177	546	break;
<>	161:2cc1468da177	547
<>	161:2cc1468da177	548	case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */
<>	161:2cc1468da177	549	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	550	{
<>	161:2cc1468da177	551	uart_frequency = LSE_VALUE;
<>	161:2cc1468da177	552	}
<>	161:2cc1468da177	553	break;
<>	161:2cc1468da177	554
<>	161:2cc1468da177	555	case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */
<>	161:2cc1468da177	556	default:
<>	161:2cc1468da177	557	uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	558	break;
<>	161:2cc1468da177	559	}
<>	161:2cc1468da177	560	}
<>	161:2cc1468da177	561	}
<>	161:2cc1468da177	562	return uart_frequency;
<>	161:2cc1468da177	563	}
<>	161:2cc1468da177	564
<>	161:2cc1468da177	565	/**
<>	161:2cc1468da177	566	* @brief Return I2Cx clock frequency
<>	161:2cc1468da177	567	* @param I2CxSource This parameter can be one of the following values:
<>	161:2cc1468da177	568	* @arg @ref LL_RCC_I2C1_CLKSOURCE
<>	161:2cc1468da177	569	* @arg @ref LL_RCC_I2C2_CLKSOURCE
<>	161:2cc1468da177	570	* @arg @ref LL_RCC_I2C3_CLKSOURCE
<>	161:2cc1468da177	571	* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
<>	161:2cc1468da177	572	*
<>	161:2cc1468da177	573	* (*) value not defined in all devices.
<>	161:2cc1468da177	574	* @retval I2C clock frequency (in Hz)
<>	161:2cc1468da177	575	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
<>	161:2cc1468da177	576	*/
<>	161:2cc1468da177	577	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
<>	161:2cc1468da177	578	{
<>	161:2cc1468da177	579	uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	580
<>	161:2cc1468da177	581	/* Check parameter */
<>	161:2cc1468da177	582	assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
<>	161:2cc1468da177	583
<>	161:2cc1468da177	584	if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
<>	161:2cc1468da177	585	{
<>	161:2cc1468da177	586	/* I2C1 CLK clock frequency */
<>	161:2cc1468da177	587	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	161:2cc1468da177	588	{
<>	161:2cc1468da177	589	case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
<>	161:2cc1468da177	590	i2c_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	591	break;
<>	161:2cc1468da177	592
<>	161:2cc1468da177	593	case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
<>	161:2cc1468da177	594	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	595	{
<>	161:2cc1468da177	596	i2c_frequency = HSI_VALUE;
<>	161:2cc1468da177	597	}
<>	161:2cc1468da177	598	break;
<>	161:2cc1468da177	599
<>	161:2cc1468da177	600	case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
<>	161:2cc1468da177	601	default:
<>	161:2cc1468da177	602	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	603	break;
<>	161:2cc1468da177	604	}
<>	161:2cc1468da177	605	}
<>	161:2cc1468da177	606	else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
<>	161:2cc1468da177	607	{
<>	161:2cc1468da177	608	/* I2C2 CLK clock frequency */
<>	161:2cc1468da177	609	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	161:2cc1468da177	610	{
<>	161:2cc1468da177	611	case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
<>	161:2cc1468da177	612	i2c_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	613	break;
<>	161:2cc1468da177	614
<>	161:2cc1468da177	615	case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
<>	161:2cc1468da177	616	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	617	{
<>	161:2cc1468da177	618	i2c_frequency = HSI_VALUE;
<>	161:2cc1468da177	619	}
<>	161:2cc1468da177	620	break;
<>	161:2cc1468da177	621
<>	161:2cc1468da177	622	case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
<>	161:2cc1468da177	623	default:
<>	161:2cc1468da177	624	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	625	break;
<>	161:2cc1468da177	626	}
<>	161:2cc1468da177	627	}
<>	161:2cc1468da177	628	else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
<>	161:2cc1468da177	629	{
<>	161:2cc1468da177	630	/* I2C3 CLK clock frequency */
<>	161:2cc1468da177	631	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	161:2cc1468da177	632	{
<>	161:2cc1468da177	633	case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
<>	161:2cc1468da177	634	i2c_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	635	break;
<>	161:2cc1468da177	636
<>	161:2cc1468da177	637	case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
<>	161:2cc1468da177	638	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	639	{
<>	161:2cc1468da177	640	i2c_frequency = HSI_VALUE;
<>	161:2cc1468da177	641	}
<>	161:2cc1468da177	642	break;
<>	161:2cc1468da177	643
<>	161:2cc1468da177	644	case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
<>	161:2cc1468da177	645	default:
<>	161:2cc1468da177	646	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	647	break;
<>	161:2cc1468da177	648	}
<>	161:2cc1468da177	649	}
<>	161:2cc1468da177	650	#if defined(I2C4)
<>	161:2cc1468da177	651	else
<>	161:2cc1468da177	652	{
<>	161:2cc1468da177	653	if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
<>	161:2cc1468da177	654	{
<>	161:2cc1468da177	655	/* I2C4 CLK clock frequency */
<>	161:2cc1468da177	656	switch (LL_RCC_GetI2CClockSource(I2CxSource))
<>	161:2cc1468da177	657	{
<>	161:2cc1468da177	658	case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
<>	161:2cc1468da177	659	i2c_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	660	break;
<>	161:2cc1468da177	661
<>	161:2cc1468da177	662	case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
<>	161:2cc1468da177	663	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	664	{
<>	161:2cc1468da177	665	i2c_frequency = HSI_VALUE;
<>	161:2cc1468da177	666	}
<>	161:2cc1468da177	667	break;
<>	161:2cc1468da177	668
<>	161:2cc1468da177	669	case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
<>	161:2cc1468da177	670	default:
<>	161:2cc1468da177	671	i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	672	break;
<>	161:2cc1468da177	673	}
<>	161:2cc1468da177	674	}
<>	161:2cc1468da177	675	}
<>	161:2cc1468da177	676	#endif /* I2C4 */
<>	161:2cc1468da177	677
<>	161:2cc1468da177	678	return i2c_frequency;
<>	161:2cc1468da177	679	}
<>	161:2cc1468da177	680
<>	161:2cc1468da177	681	/**
<>	161:2cc1468da177	682	* @brief Return I2Sx clock frequency
<>	161:2cc1468da177	683	* @param I2SxSource This parameter can be one of the following values:
<>	161:2cc1468da177	684	* @arg @ref LL_RCC_I2S1_CLKSOURCE
<>	161:2cc1468da177	685	* @retval I2S clock frequency (in Hz)
<>	161:2cc1468da177	686	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready
<>	161:2cc1468da177	687	*/
<>	161:2cc1468da177	688	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
<>	161:2cc1468da177	689	{
<>	161:2cc1468da177	690	uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	691
<>	161:2cc1468da177	692	/* Check parameter */
<>	161:2cc1468da177	693	assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
<>	161:2cc1468da177	694
<>	161:2cc1468da177	695	if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
<>	161:2cc1468da177	696	{
<>	161:2cc1468da177	697	/* I2S1 CLK clock frequency */
<>	161:2cc1468da177	698	switch (LL_RCC_GetI2SClockSource(I2SxSource))
<>	161:2cc1468da177	699	{
<>	161:2cc1468da177	700	case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
<>	161:2cc1468da177	701	if (LL_RCC_PLLI2S_IsReady())
<>	161:2cc1468da177	702	{
<>	161:2cc1468da177	703	i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
<>	161:2cc1468da177	704	}
<>	161:2cc1468da177	705	break;
<>	161:2cc1468da177	706
<>	161:2cc1468da177	707	case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
<>	161:2cc1468da177	708	default:
<>	161:2cc1468da177	709	i2s_frequency = EXTERNAL_CLOCK_VALUE;
<>	161:2cc1468da177	710	break;
<>	161:2cc1468da177	711	}
<>	161:2cc1468da177	712	}
<>	161:2cc1468da177	713
<>	161:2cc1468da177	714	return i2s_frequency;
<>	161:2cc1468da177	715	}
<>	161:2cc1468da177	716
<>	161:2cc1468da177	717	/**
<>	161:2cc1468da177	718	* @brief Return LPTIMx clock frequency
<>	161:2cc1468da177	719	* @param LPTIMxSource This parameter can be one of the following values:
<>	161:2cc1468da177	720	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
<>	161:2cc1468da177	721	* @retval LPTIM clock frequency (in Hz)
<>	161:2cc1468da177	722	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
<>	161:2cc1468da177	723	*/
<>	161:2cc1468da177	724	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
<>	161:2cc1468da177	725	{
<>	161:2cc1468da177	726	uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	727
<>	161:2cc1468da177	728	/* Check parameter */
<>	161:2cc1468da177	729	assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
<>	161:2cc1468da177	730
<>	161:2cc1468da177	731	if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
<>	161:2cc1468da177	732	{
<>	161:2cc1468da177	733	/* LPTIM1CLK clock frequency */
<>	161:2cc1468da177	734	switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
<>	161:2cc1468da177	735	{
<>	161:2cc1468da177	736	case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
<>	161:2cc1468da177	737	if (LL_RCC_LSI_IsReady())
<>	161:2cc1468da177	738	{
<>	161:2cc1468da177	739	lptim_frequency = LSI_VALUE;
<>	161:2cc1468da177	740	}
<>	161:2cc1468da177	741	break;
<>	161:2cc1468da177	742
<>	161:2cc1468da177	743	case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
<>	161:2cc1468da177	744	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	745	{
<>	161:2cc1468da177	746	lptim_frequency = HSI_VALUE;
<>	161:2cc1468da177	747	}
<>	161:2cc1468da177	748	break;
<>	161:2cc1468da177	749
<>	161:2cc1468da177	750	case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
<>	161:2cc1468da177	751	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	752	{
<>	161:2cc1468da177	753	lptim_frequency = LSE_VALUE;
<>	161:2cc1468da177	754	}
<>	161:2cc1468da177	755	break;
<>	161:2cc1468da177	756
<>	161:2cc1468da177	757	case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
<>	161:2cc1468da177	758	default:
<>	161:2cc1468da177	759	lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	760	break;
<>	161:2cc1468da177	761	}
<>	161:2cc1468da177	762	}
<>	161:2cc1468da177	763
<>	161:2cc1468da177	764	return lptim_frequency;
<>	161:2cc1468da177	765	}
<>	161:2cc1468da177	766
<>	161:2cc1468da177	767	/**
<>	161:2cc1468da177	768	* @brief Return SAIx clock frequency
<>	161:2cc1468da177	769	* @param SAIxSource This parameter can be one of the following values:
<>	161:2cc1468da177	770	* @arg @ref LL_RCC_SAI1_CLKSOURCE
<>	161:2cc1468da177	771	* @arg @ref LL_RCC_SAI2_CLKSOURCE
<>	161:2cc1468da177	772	* @retval SAI clock frequency (in Hz)
<>	161:2cc1468da177	773	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
<>	161:2cc1468da177	774	* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
<>	161:2cc1468da177	775	*/
<>	161:2cc1468da177	776	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
<>	161:2cc1468da177	777	{
<>	161:2cc1468da177	778	uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	779
<>	161:2cc1468da177	780	/* Check parameter */
<>	161:2cc1468da177	781	assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
<>	161:2cc1468da177	782
<>	161:2cc1468da177	783	if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
<>	161:2cc1468da177	784	{
<>	161:2cc1468da177	785	/* SAI1CLK clock frequency */
<>	161:2cc1468da177	786	switch (LL_RCC_GetSAIClockSource(SAIxSource))
<>	161:2cc1468da177	787	{
<>	161:2cc1468da177	788	case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
<>	161:2cc1468da177	789	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	790	{
<>	161:2cc1468da177	791	sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
<>	161:2cc1468da177	792	}
<>	161:2cc1468da177	793	break;
<>	161:2cc1468da177	794
<>	161:2cc1468da177	795	case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
<>	161:2cc1468da177	796	if (LL_RCC_PLLI2S_IsReady())
<>	161:2cc1468da177	797	{
<>	161:2cc1468da177	798	sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
<>	161:2cc1468da177	799	}
<>	161:2cc1468da177	800	break;
<>	161:2cc1468da177	801
<>	161:2cc1468da177	802	#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
<>	161:2cc1468da177	803	case LL_RCC_SAI1_CLKSOURCE_PLLSRC:
<>	161:2cc1468da177	804	switch (LL_RCC_PLL_GetMainSource())
<>	161:2cc1468da177	805	{
<>	161:2cc1468da177	806	case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */
<>	161:2cc1468da177	807	if (LL_RCC_HSE_IsReady())
<>	161:2cc1468da177	808	{
<>	161:2cc1468da177	809	sai_frequency = HSE_VALUE;
<>	161:2cc1468da177	810	}
<>	161:2cc1468da177	811	break;
<>	161:2cc1468da177	812
<>	161:2cc1468da177	813	case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */
<>	161:2cc1468da177	814	default:
<>	161:2cc1468da177	815	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	816	{
<>	161:2cc1468da177	817	sai_frequency = HSI_VALUE;
<>	161:2cc1468da177	818	}
<>	161:2cc1468da177	819	break;
<>	161:2cc1468da177	820	}
<>	161:2cc1468da177	821	break;
<>	161:2cc1468da177	822	#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
<>	161:2cc1468da177	823	case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
<>	161:2cc1468da177	824	default:
<>	161:2cc1468da177	825	sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<>	161:2cc1468da177	826	break;
<>	161:2cc1468da177	827	}
<>	161:2cc1468da177	828	}
<>	161:2cc1468da177	829	else
<>	161:2cc1468da177	830	{
<>	161:2cc1468da177	831	if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
<>	161:2cc1468da177	832	{
<>	161:2cc1468da177	833	/* SAI2CLK clock frequency */
<>	161:2cc1468da177	834	switch (LL_RCC_GetSAIClockSource(SAIxSource))
<>	161:2cc1468da177	835	{
<>	161:2cc1468da177	836	case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
<>	161:2cc1468da177	837	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	838	{
<>	161:2cc1468da177	839	sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
<>	161:2cc1468da177	840	}
<>	161:2cc1468da177	841	break;
<>	161:2cc1468da177	842
<>	161:2cc1468da177	843	case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
<>	161:2cc1468da177	844	if (LL_RCC_PLLI2S_IsReady())
<>	161:2cc1468da177	845	{
<>	161:2cc1468da177	846	sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
<>	161:2cc1468da177	847	}
<>	161:2cc1468da177	848	break;
<>	161:2cc1468da177	849
<>	161:2cc1468da177	850	#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
<>	161:2cc1468da177	851	case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
<>	161:2cc1468da177	852	switch (LL_RCC_PLL_GetMainSource())
<>	161:2cc1468da177	853	{
<>	161:2cc1468da177	854	case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
<>	161:2cc1468da177	855	if (LL_RCC_HSE_IsReady())
<>	161:2cc1468da177	856	{
<>	161:2cc1468da177	857	sai_frequency = HSE_VALUE;
<>	161:2cc1468da177	858	}
<>	161:2cc1468da177	859	break;
<>	161:2cc1468da177	860
<>	161:2cc1468da177	861	case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
<>	161:2cc1468da177	862	default:
<>	161:2cc1468da177	863	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	864	{
<>	161:2cc1468da177	865	sai_frequency = HSI_VALUE;
<>	161:2cc1468da177	866	}
<>	161:2cc1468da177	867	break;
<>	161:2cc1468da177	868	}
<>	161:2cc1468da177	869	break;
<>	161:2cc1468da177	870	#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
<>	161:2cc1468da177	871	case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
<>	161:2cc1468da177	872	default:
<>	161:2cc1468da177	873	sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<>	161:2cc1468da177	874	break;
<>	161:2cc1468da177	875	}
<>	161:2cc1468da177	876	}
<>	161:2cc1468da177	877	}
<>	161:2cc1468da177	878
<>	161:2cc1468da177	879	return sai_frequency;
<>	161:2cc1468da177	880	}
<>	161:2cc1468da177	881
<>	161:2cc1468da177	882	/**
<>	161:2cc1468da177	883	* @brief Return SDMMCx clock frequency
<>	161:2cc1468da177	884	* @param SDMMCxSource This parameter can be one of the following values:
<>	161:2cc1468da177	885	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
<>	161:2cc1468da177	886	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*)
<>	161:2cc1468da177	887	*
<>	161:2cc1468da177	888	* (*) value not defined in all devices.
<>	161:2cc1468da177	889	* @retval SDMMC clock frequency (in Hz)
<>	161:2cc1468da177	890	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready
<>	161:2cc1468da177	891	*/
<>	161:2cc1468da177	892	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
<>	161:2cc1468da177	893	{
<>	161:2cc1468da177	894	uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	895
<>	161:2cc1468da177	896	/* Check parameter */
<>	161:2cc1468da177	897	assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
<>	161:2cc1468da177	898
<>	161:2cc1468da177	899	if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE)
<>	161:2cc1468da177	900	{
<>	161:2cc1468da177	901	/* SDMMC1CLK clock frequency */
<>	161:2cc1468da177	902	switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
<>	161:2cc1468da177	903	{
<>	161:2cc1468da177	904	case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */
<>	161:2cc1468da177	905	switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
<>	161:2cc1468da177	906	{
<>	161:2cc1468da177	907	case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
<>	161:2cc1468da177	908	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	909	{
<>	161:2cc1468da177	910	sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
<>	161:2cc1468da177	911	}
<>	161:2cc1468da177	912	break;
<>	161:2cc1468da177	913
<>	161:2cc1468da177	914	case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
<>	161:2cc1468da177	915	default:
<>	161:2cc1468da177	916	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	917	{
<>	161:2cc1468da177	918	sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
<>	161:2cc1468da177	919	}
<>	161:2cc1468da177	920	break;
<>	161:2cc1468da177	921	}
<>	161:2cc1468da177	922	break;
<>	161:2cc1468da177	923
<>	161:2cc1468da177	924	case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */
<>	161:2cc1468da177	925	default:
<>	161:2cc1468da177	926	sdmmc_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	927	break;
<>	161:2cc1468da177	928	}
<>	161:2cc1468da177	929	}
<>	161:2cc1468da177	930	#if defined(SDMMC2)
<>	161:2cc1468da177	931	else
<>	161:2cc1468da177	932	{
<>	161:2cc1468da177	933	/* SDMMC2CLK clock frequency */
<>	161:2cc1468da177	934	switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
<>	161:2cc1468da177	935	{
<>	161:2cc1468da177	936	case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */
<>	161:2cc1468da177	937	switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
<>	161:2cc1468da177	938	{
<>	161:2cc1468da177	939	case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
<>	161:2cc1468da177	940	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	941	{
<>	161:2cc1468da177	942	sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
<>	161:2cc1468da177	943	}
<>	161:2cc1468da177	944	break;
<>	161:2cc1468da177	945
<>	161:2cc1468da177	946	case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
<>	161:2cc1468da177	947	default:
<>	161:2cc1468da177	948	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	949	{
<>	161:2cc1468da177	950	sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M();
<>	161:2cc1468da177	951	}
<>	161:2cc1468da177	952	break;
<>	161:2cc1468da177	953	}
<>	161:2cc1468da177	954	break;
<>	161:2cc1468da177	955
<>	161:2cc1468da177	956	case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */
<>	161:2cc1468da177	957	default:
<>	161:2cc1468da177	958	sdmmc_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	959	break;
<>	161:2cc1468da177	960	}
<>	161:2cc1468da177	961	}
<>	161:2cc1468da177	962	#endif /* SDMMC2 */
<>	161:2cc1468da177	963
<>	161:2cc1468da177	964	return sdmmc_frequency;
<>	161:2cc1468da177	965	}
<>	161:2cc1468da177	966
<>	161:2cc1468da177	967	/**
<>	161:2cc1468da177	968	* @brief Return RNGx clock frequency
<>	161:2cc1468da177	969	* @param RNGxSource This parameter can be one of the following values:
<>	161:2cc1468da177	970	* @arg @ref LL_RCC_RNG_CLKSOURCE
<>	161:2cc1468da177	971	* @retval RNG clock frequency (in Hz)
<>	161:2cc1468da177	972	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
<>	161:2cc1468da177	973	*/
<>	161:2cc1468da177	974	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
<>	161:2cc1468da177	975	{
<>	161:2cc1468da177	976	uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	977
<>	161:2cc1468da177	978	/* Check parameter */
<>	161:2cc1468da177	979	assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
<>	161:2cc1468da177	980
<>	161:2cc1468da177	981	/* RNGCLK clock frequency */
<>	161:2cc1468da177	982	switch (LL_RCC_GetRNGClockSource(RNGxSource))
<>	161:2cc1468da177	983	{
<>	161:2cc1468da177	984	case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
<>	161:2cc1468da177	985	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	986	{
<>	161:2cc1468da177	987	rng_frequency = RCC_PLL_GetFreqDomain_48M();
<>	161:2cc1468da177	988	}
<>	161:2cc1468da177	989	break;
<>	161:2cc1468da177	990
<>	161:2cc1468da177	991	case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
<>	161:2cc1468da177	992	default:
<>	161:2cc1468da177	993	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	994	{
<>	161:2cc1468da177	995	rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
<>	161:2cc1468da177	996	}
<>	161:2cc1468da177	997	break;
<>	161:2cc1468da177	998	}
<>	161:2cc1468da177	999
<>	161:2cc1468da177	1000	return rng_frequency;
<>	161:2cc1468da177	1001	}
<>	161:2cc1468da177	1002
<>	161:2cc1468da177	1003	#if defined(CEC)
<>	161:2cc1468da177	1004	/**
<>	161:2cc1468da177	1005	* @brief Return CEC clock frequency
<>	161:2cc1468da177	1006	* @param CECxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1007	* @arg @ref LL_RCC_CEC_CLKSOURCE
<>	161:2cc1468da177	1008	* @retval CEC clock frequency (in Hz)
<>	161:2cc1468da177	1009	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
<>	161:2cc1468da177	1010	*/
<>	161:2cc1468da177	1011	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
<>	161:2cc1468da177	1012	{
<>	161:2cc1468da177	1013	uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1014
<>	161:2cc1468da177	1015	/* Check parameter */
<>	161:2cc1468da177	1016	assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
<>	161:2cc1468da177	1017
<>	161:2cc1468da177	1018	/* CECCLK clock frequency */
<>	161:2cc1468da177	1019	switch (LL_RCC_GetCECClockSource(CECxSource))
<>	161:2cc1468da177	1020	{
<>	161:2cc1468da177	1021	case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
<>	161:2cc1468da177	1022	if (LL_RCC_LSE_IsReady())
<>	161:2cc1468da177	1023	{
<>	161:2cc1468da177	1024	cec_frequency = LSE_VALUE;
<>	161:2cc1468da177	1025	}
<>	161:2cc1468da177	1026	break;
<>	161:2cc1468da177	1027
<>	161:2cc1468da177	1028	case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
<>	161:2cc1468da177	1029	default:
<>	161:2cc1468da177	1030	if (LL_RCC_HSI_IsReady())
<>	161:2cc1468da177	1031	{
<>	161:2cc1468da177	1032	cec_frequency = HSI_VALUE/488U;
<>	161:2cc1468da177	1033	}
<>	161:2cc1468da177	1034	break;
<>	161:2cc1468da177	1035	}
<>	161:2cc1468da177	1036
<>	161:2cc1468da177	1037	return cec_frequency;
<>	161:2cc1468da177	1038	}
<>	161:2cc1468da177	1039	#endif /* CEC */
<>	161:2cc1468da177	1040
<>	161:2cc1468da177	1041	/**
<>	161:2cc1468da177	1042	* @brief Return USBx clock frequency
<>	161:2cc1468da177	1043	* @param USBxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1044	* @arg @ref LL_RCC_USB_CLKSOURCE
<>	161:2cc1468da177	1045	* @retval USB clock frequency (in Hz)
<>	161:2cc1468da177	1046	*/
<>	161:2cc1468da177	1047	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
<>	161:2cc1468da177	1048	{
<>	161:2cc1468da177	1049	uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1050
<>	161:2cc1468da177	1051	/* Check parameter */
<>	161:2cc1468da177	1052	assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
<>	161:2cc1468da177	1053
<>	161:2cc1468da177	1054	/* USBCLK clock frequency */
<>	161:2cc1468da177	1055	switch (LL_RCC_GetUSBClockSource(USBxSource))
<>	161:2cc1468da177	1056	{
<>	161:2cc1468da177	1057	case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
<>	161:2cc1468da177	1058	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	1059	{
<>	161:2cc1468da177	1060	usb_frequency = RCC_PLL_GetFreqDomain_48M();
<>	161:2cc1468da177	1061	}
<>	161:2cc1468da177	1062	break;
<>	161:2cc1468da177	1063
<>	161:2cc1468da177	1064	case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
<>	161:2cc1468da177	1065	default:
<>	161:2cc1468da177	1066	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	1067	{
<>	161:2cc1468da177	1068	usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
<>	161:2cc1468da177	1069	}
<>	161:2cc1468da177	1070	break;
<>	161:2cc1468da177	1071	}
<>	161:2cc1468da177	1072
<>	161:2cc1468da177	1073	return usb_frequency;
<>	161:2cc1468da177	1074	}
<>	161:2cc1468da177	1075
<>	161:2cc1468da177	1076	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	1077	/**
<>	161:2cc1468da177	1078	* @brief Return DFSDMx clock frequency
<>	161:2cc1468da177	1079	* @param DFSDMxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1080	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
<>	161:2cc1468da177	1081	* @retval DFSDM clock frequency (in Hz)
<>	161:2cc1468da177	1082	*/
<>	161:2cc1468da177	1083	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
<>	161:2cc1468da177	1084	{
<>	161:2cc1468da177	1085	uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1086
<>	161:2cc1468da177	1087	/* Check parameter */
<>	161:2cc1468da177	1088	assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
<>	161:2cc1468da177	1089
<>	161:2cc1468da177	1090	/* DFSDM1CLK clock frequency */
<>	161:2cc1468da177	1091	switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
<>	161:2cc1468da177	1092	{
<>	161:2cc1468da177	1093	case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
<>	161:2cc1468da177	1094	dfsdm_frequency = RCC_GetSystemClockFreq();
<>	161:2cc1468da177	1095	break;
<>	161:2cc1468da177	1096
<>	161:2cc1468da177	1097	case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
<>	161:2cc1468da177	1098	default:
<>	161:2cc1468da177	1099	dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
<>	161:2cc1468da177	1100	break;
<>	161:2cc1468da177	1101	}
<>	161:2cc1468da177	1102
<>	161:2cc1468da177	1103	return dfsdm_frequency;
<>	161:2cc1468da177	1104	}
<>	161:2cc1468da177	1105
<>	161:2cc1468da177	1106	/**
<>	161:2cc1468da177	1107	* @brief Return DFSDMx Audio clock frequency
<>	161:2cc1468da177	1108	* @param DFSDMxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1109	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
<>	161:2cc1468da177	1110	* @retval DFSDM clock frequency (in Hz)
<>	161:2cc1468da177	1111	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
<>	161:2cc1468da177	1112	*/
<>	161:2cc1468da177	1113	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
<>	161:2cc1468da177	1114	{
<>	161:2cc1468da177	1115	uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1116
<>	161:2cc1468da177	1117	/* Check parameter */
<>	161:2cc1468da177	1118	assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
<>	161:2cc1468da177	1119
<>	161:2cc1468da177	1120	/* DFSDM1CLK clock frequency */
<>	161:2cc1468da177	1121	switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
<>	161:2cc1468da177	1122	{
<>	161:2cc1468da177	1123	case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
<>	161:2cc1468da177	1124	dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
<>	161:2cc1468da177	1125	break;
<>	161:2cc1468da177	1126
<>	161:2cc1468da177	1127	case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2: /* SAI2 clock used as DFSDM1 audio clock */
<>	161:2cc1468da177	1128	default:
<>	161:2cc1468da177	1129	dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE);
<>	161:2cc1468da177	1130	break;
<>	161:2cc1468da177	1131	}
<>	161:2cc1468da177	1132
<>	161:2cc1468da177	1133	return dfsdm_frequency;
<>	161:2cc1468da177	1134	}
<>	161:2cc1468da177	1135	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	1136
<>	161:2cc1468da177	1137	#if defined(DSI)
<>	161:2cc1468da177	1138	/**
<>	161:2cc1468da177	1139	* @brief Return DSI clock frequency
<>	161:2cc1468da177	1140	* @param DSIxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1141	* @arg @ref LL_RCC_DSI_CLKSOURCE
<>	161:2cc1468da177	1142	* @retval DSI clock frequency (in Hz)
<>	161:2cc1468da177	1143	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
<>	161:2cc1468da177	1144	* - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
<>	161:2cc1468da177	1145	*/
<>	161:2cc1468da177	1146	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
<>	161:2cc1468da177	1147	{
<>	161:2cc1468da177	1148	uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1149
<>	161:2cc1468da177	1150	/* Check parameter */
<>	161:2cc1468da177	1151	assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
<>	161:2cc1468da177	1152
<>	161:2cc1468da177	1153	/* DSICLK clock frequency */
<>	161:2cc1468da177	1154	switch (LL_RCC_GetDSIClockSource(DSIxSource))
<>	161:2cc1468da177	1155	{
<>	161:2cc1468da177	1156	case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
<>	161:2cc1468da177	1157	if (LL_RCC_PLL_IsReady())
<>	161:2cc1468da177	1158	{
<>	161:2cc1468da177	1159	dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
<>	161:2cc1468da177	1160	}
<>	161:2cc1468da177	1161	break;
<>	161:2cc1468da177	1162
<>	161:2cc1468da177	1163	case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
<>	161:2cc1468da177	1164	default:
<>	161:2cc1468da177	1165	dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
<>	161:2cc1468da177	1166	break;
<>	161:2cc1468da177	1167	}
<>	161:2cc1468da177	1168
<>	161:2cc1468da177	1169	return dsi_frequency;
<>	161:2cc1468da177	1170	}
<>	161:2cc1468da177	1171	#endif /* DSI */
<>	161:2cc1468da177	1172
<>	161:2cc1468da177	1173	#if defined(LTDC)
<>	161:2cc1468da177	1174	/**
<>	161:2cc1468da177	1175	* @brief Return LTDC clock frequency
<>	161:2cc1468da177	1176	* @param LTDCxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1177	* @arg @ref LL_RCC_LTDC_CLKSOURCE
<>	161:2cc1468da177	1178	* @retval LTDC clock frequency (in Hz)
<>	161:2cc1468da177	1179	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
<>	161:2cc1468da177	1180	*/
<>	161:2cc1468da177	1181	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
<>	161:2cc1468da177	1182	{
<>	161:2cc1468da177	1183	uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1184
<>	161:2cc1468da177	1185	/* Check parameter */
<>	161:2cc1468da177	1186	assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
<>	161:2cc1468da177	1187
<>	161:2cc1468da177	1188	if (LL_RCC_PLLSAI_IsReady())
<>	161:2cc1468da177	1189	{
<>	161:2cc1468da177	1190	ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
<>	161:2cc1468da177	1191	}
<>	161:2cc1468da177	1192
<>	161:2cc1468da177	1193	return ltdc_frequency;
<>	161:2cc1468da177	1194	}
<>	161:2cc1468da177	1195	#endif /* LTDC */
<>	161:2cc1468da177	1196
<>	161:2cc1468da177	1197	#if defined(SPDIFRX)
<>	161:2cc1468da177	1198	/**
<>	161:2cc1468da177	1199	* @brief Return SPDIFRX clock frequency
<>	161:2cc1468da177	1200	* @param SPDIFRXxSource This parameter can be one of the following values:
<>	161:2cc1468da177	1201	* @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
<>	161:2cc1468da177	1202	* @retval SPDIFRX clock frequency (in Hz)
<>	161:2cc1468da177	1203	* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
<>	161:2cc1468da177	1204	*/
<>	161:2cc1468da177	1205	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
<>	161:2cc1468da177	1206	{
<>	161:2cc1468da177	1207	uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
<>	161:2cc1468da177	1208
<>	161:2cc1468da177	1209	/* Check parameter */
<>	161:2cc1468da177	1210	assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
<>	161:2cc1468da177	1211
<>	161:2cc1468da177	1212	if (LL_RCC_PLLI2S_IsReady())
<>	161:2cc1468da177	1213	{
<>	161:2cc1468da177	1214	spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
<>	161:2cc1468da177	1215	}
<>	161:2cc1468da177	1216
<>	161:2cc1468da177	1217	return spdifrx_frequency;
<>	161:2cc1468da177	1218	}
<>	161:2cc1468da177	1219	#endif /* SPDIFRX */
<>	161:2cc1468da177	1220
<>	161:2cc1468da177	1221	/**
<>	161:2cc1468da177	1222	* @}
<>	161:2cc1468da177	1223	*/
<>	161:2cc1468da177	1224
<>	161:2cc1468da177	1225	/**
<>	161:2cc1468da177	1226	* @}
<>	161:2cc1468da177	1227	*/
<>	161:2cc1468da177	1228
<>	161:2cc1468da177	1229	/** @addtogroup RCC_LL_Private_Functions
<>	161:2cc1468da177	1230	* @{
<>	161:2cc1468da177	1231	*/
<>	161:2cc1468da177	1232
<>	161:2cc1468da177	1233	/**
<>	161:2cc1468da177	1234	* @brief Return SYSTEM clock frequency
<>	161:2cc1468da177	1235	* @retval SYSTEM clock frequency (in Hz)
<>	161:2cc1468da177	1236	*/
<>	161:2cc1468da177	1237	uint32_t RCC_GetSystemClockFreq(void)
<>	161:2cc1468da177	1238	{
<>	161:2cc1468da177	1239	uint32_t frequency = 0U;
<>	161:2cc1468da177	1240
<>	161:2cc1468da177	1241	/* Get SYSCLK source -------------------------------------------------------*/
<>	161:2cc1468da177	1242	switch (LL_RCC_GetSysClkSource())
<>	161:2cc1468da177	1243	{
<>	161:2cc1468da177	1244	case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<>	161:2cc1468da177	1245	frequency = HSI_VALUE;
<>	161:2cc1468da177	1246	break;
<>	161:2cc1468da177	1247
<>	161:2cc1468da177	1248	case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
<>	161:2cc1468da177	1249	frequency = HSE_VALUE;
<>	161:2cc1468da177	1250	break;
<>	161:2cc1468da177	1251
<>	161:2cc1468da177	1252	case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
<>	161:2cc1468da177	1253	frequency = RCC_PLL_GetFreqDomain_SYS();
<>	161:2cc1468da177	1254	break;
<>	161:2cc1468da177	1255
<>	161:2cc1468da177	1256	default:
<>	161:2cc1468da177	1257	frequency = HSI_VALUE;
<>	161:2cc1468da177	1258	break;
<>	161:2cc1468da177	1259	}
<>	161:2cc1468da177	1260
<>	161:2cc1468da177	1261	return frequency;
<>	161:2cc1468da177	1262	}
<>	161:2cc1468da177	1263
<>	161:2cc1468da177	1264	/**
<>	161:2cc1468da177	1265	* @brief Return HCLK clock frequency
<>	161:2cc1468da177	1266	* @param SYSCLK_Frequency SYSCLK clock frequency
<>	161:2cc1468da177	1267	* @retval HCLK clock frequency (in Hz)
<>	161:2cc1468da177	1268	*/
<>	161:2cc1468da177	1269	uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
<>	161:2cc1468da177	1270	{
<>	161:2cc1468da177	1271	/* HCLK clock frequency */
<>	161:2cc1468da177	1272	return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
<>	161:2cc1468da177	1273	}
<>	161:2cc1468da177	1274
<>	161:2cc1468da177	1275	/**
<>	161:2cc1468da177	1276	* @brief Return PCLK1 clock frequency
<>	161:2cc1468da177	1277	* @param HCLK_Frequency HCLK clock frequency
<>	161:2cc1468da177	1278	* @retval PCLK1 clock frequency (in Hz)
<>	161:2cc1468da177	1279	*/
<>	161:2cc1468da177	1280	uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
<>	161:2cc1468da177	1281	{
<>	161:2cc1468da177	1282	/* PCLK1 clock frequency */
<>	161:2cc1468da177	1283	return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
<>	161:2cc1468da177	1284	}
<>	161:2cc1468da177	1285
<>	161:2cc1468da177	1286	/**
<>	161:2cc1468da177	1287	* @brief Return PCLK2 clock frequency
<>	161:2cc1468da177	1288	* @param HCLK_Frequency HCLK clock frequency
<>	161:2cc1468da177	1289	* @retval PCLK2 clock frequency (in Hz)
<>	161:2cc1468da177	1290	*/
<>	161:2cc1468da177	1291	uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
<>	161:2cc1468da177	1292	{
<>	161:2cc1468da177	1293	/* PCLK2 clock frequency */
<>	161:2cc1468da177	1294	return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
<>	161:2cc1468da177	1295	}
<>	161:2cc1468da177	1296
<>	161:2cc1468da177	1297	/**
<>	161:2cc1468da177	1298	* @brief Return PLL clock frequency used for system domain
<>	161:2cc1468da177	1299	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1300	*/
<>	161:2cc1468da177	1301	uint32_t RCC_PLL_GetFreqDomain_SYS(void)
<>	161:2cc1468da177	1302	{
<>	161:2cc1468da177	1303	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1304
<>	161:2cc1468da177	1305	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
<>	161:2cc1468da177	1306	SYSCLK = PLL_VCO / PLLP
<>	161:2cc1468da177	1307	*/
<>	161:2cc1468da177	1308	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1309
<>	161:2cc1468da177	1310	switch (pllsource)
<>	161:2cc1468da177	1311	{
<>	161:2cc1468da177	1312	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<>	161:2cc1468da177	1313	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1314	break;
<>	161:2cc1468da177	1315
<>	161:2cc1468da177	1316	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<>	161:2cc1468da177	1317	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1318	break;
<>	161:2cc1468da177	1319
<>	161:2cc1468da177	1320	default:
<>	161:2cc1468da177	1321	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1322	break;
<>	161:2cc1468da177	1323	}
<>	161:2cc1468da177	1324	return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1325	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
<>	161:2cc1468da177	1326	}
<>	161:2cc1468da177	1327
<>	161:2cc1468da177	1328	/**
<>	161:2cc1468da177	1329	* @brief Return PLL clock frequency used for 48 MHz domain
<>	161:2cc1468da177	1330	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1331	*/
<>	161:2cc1468da177	1332	uint32_t RCC_PLL_GetFreqDomain_48M(void)
<>	161:2cc1468da177	1333	{
<>	161:2cc1468da177	1334	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1335
<>	161:2cc1468da177	1336	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
<>	161:2cc1468da177	1337	48M Domain clock = PLL_VCO / PLLQ
<>	161:2cc1468da177	1338	*/
<>	161:2cc1468da177	1339	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1340
<>	161:2cc1468da177	1341	switch (pllsource)
<>	161:2cc1468da177	1342	{
<>	161:2cc1468da177	1343	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<>	161:2cc1468da177	1344	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1345	break;
<>	161:2cc1468da177	1346
<>	161:2cc1468da177	1347	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<>	161:2cc1468da177	1348	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1349	break;
<>	161:2cc1468da177	1350
<>	161:2cc1468da177	1351	default:
<>	161:2cc1468da177	1352	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1353	break;
<>	161:2cc1468da177	1354	}
<>	161:2cc1468da177	1355	return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1356	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
<>	161:2cc1468da177	1357	}
<>	161:2cc1468da177	1358
<>	161:2cc1468da177	1359	#if defined(DSI)
<>	161:2cc1468da177	1360	/**
<>	161:2cc1468da177	1361	* @brief Return PLL clock frequency used for DSI clock
<>	161:2cc1468da177	1362	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1363	*/
<>	161:2cc1468da177	1364	uint32_t RCC_PLL_GetFreqDomain_DSI(void)
<>	161:2cc1468da177	1365	{
<>	161:2cc1468da177	1366	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1367
<>	161:2cc1468da177	1368	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
<>	161:2cc1468da177	1369	DSICLK = PLL_VCO / PLLR
<>	161:2cc1468da177	1370	*/
<>	161:2cc1468da177	1371	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1372
<>	161:2cc1468da177	1373	switch (pllsource)
<>	161:2cc1468da177	1374	{
<>	161:2cc1468da177	1375	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
<>	161:2cc1468da177	1376	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1377	break;
<>	161:2cc1468da177	1378
<>	161:2cc1468da177	1379	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
<>	161:2cc1468da177	1380	default:
<>	161:2cc1468da177	1381	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1382	break;
<>	161:2cc1468da177	1383	}
<>	161:2cc1468da177	1384	return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1385	LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
<>	161:2cc1468da177	1386	}
<>	161:2cc1468da177	1387	#endif /* DSI */
<>	161:2cc1468da177	1388
<>	161:2cc1468da177	1389	/**
<>	161:2cc1468da177	1390	* @brief Return PLLSAI clock frequency used for SAI1 and SAI2 domains
<>	161:2cc1468da177	1391	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1392	*/
<>	161:2cc1468da177	1393	uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
<>	161:2cc1468da177	1394	{
<>	161:2cc1468da177	1395	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1396
<>	161:2cc1468da177	1397	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
<>	161:2cc1468da177	1398	SAI1 and SAI2 domains clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
<>	161:2cc1468da177	1399	*/
<>	161:2cc1468da177	1400	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1401
<>	161:2cc1468da177	1402	switch (pllsource)
<>	161:2cc1468da177	1403	{
<>	161:2cc1468da177	1404	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
<>	161:2cc1468da177	1405	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1406	break;
<>	161:2cc1468da177	1407
<>	161:2cc1468da177	1408	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
<>	161:2cc1468da177	1409	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1410	break;
<>	161:2cc1468da177	1411
<>	161:2cc1468da177	1412	default:
<>	161:2cc1468da177	1413	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1414	break;
<>	161:2cc1468da177	1415	}
<>	161:2cc1468da177	1416	return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1417	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
<>	161:2cc1468da177	1418	}
<>	161:2cc1468da177	1419
<>	161:2cc1468da177	1420	/**
<>	161:2cc1468da177	1421	* @brief Return PLLSAI clock frequency used for 48Mhz domain
<>	161:2cc1468da177	1422	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1423	*/
<>	161:2cc1468da177	1424	uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
<>	161:2cc1468da177	1425	{
<>	161:2cc1468da177	1426	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1427
<>	161:2cc1468da177	1428	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
<>	161:2cc1468da177	1429	48M Domain clock = PLLSAI_VCO / PLLSAIP
<>	161:2cc1468da177	1430	*/
<>	161:2cc1468da177	1431	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1432
<>	161:2cc1468da177	1433	switch (pllsource)
<>	161:2cc1468da177	1434	{
<>	161:2cc1468da177	1435	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
<>	161:2cc1468da177	1436	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1437	break;
<>	161:2cc1468da177	1438
<>	161:2cc1468da177	1439	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
<>	161:2cc1468da177	1440	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1441	break;
<>	161:2cc1468da177	1442
<>	161:2cc1468da177	1443	default:
<>	161:2cc1468da177	1444	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1445	break;
<>	161:2cc1468da177	1446	}
<>	161:2cc1468da177	1447	return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1448	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
<>	161:2cc1468da177	1449	}
<>	161:2cc1468da177	1450
<>	161:2cc1468da177	1451	#if defined(LTDC)
<>	161:2cc1468da177	1452	/**
<>	161:2cc1468da177	1453	* @brief Return PLLSAI clock frequency used for LTDC domain
<>	161:2cc1468da177	1454	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1455	*/
<>	161:2cc1468da177	1456	uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
<>	161:2cc1468da177	1457	{
<>	161:2cc1468da177	1458	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1459
<>	161:2cc1468da177	1460	/* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN
<>	161:2cc1468da177	1461	LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
<>	161:2cc1468da177	1462	*/
<>	161:2cc1468da177	1463	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1464
<>	161:2cc1468da177	1465	switch (pllsource)
<>	161:2cc1468da177	1466	{
<>	161:2cc1468da177	1467	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
<>	161:2cc1468da177	1468	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1469	break;
<>	161:2cc1468da177	1470
<>	161:2cc1468da177	1471	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
<>	161:2cc1468da177	1472	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1473	break;
<>	161:2cc1468da177	1474
<>	161:2cc1468da177	1475	default:
<>	161:2cc1468da177	1476	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1477	break;
<>	161:2cc1468da177	1478	}
<>	161:2cc1468da177	1479	return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1480	LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
<>	161:2cc1468da177	1481	}
<>	161:2cc1468da177	1482	#endif /* LTDC */
<>	161:2cc1468da177	1483
<>	161:2cc1468da177	1484	/**
<>	161:2cc1468da177	1485	* @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains
<>	161:2cc1468da177	1486	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1487	*/
<>	161:2cc1468da177	1488	uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
<>	161:2cc1468da177	1489	{
<>	161:2cc1468da177	1490	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1491
<>	161:2cc1468da177	1492	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
<>	161:2cc1468da177	1493	SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
<>	161:2cc1468da177	1494	*/
<>	161:2cc1468da177	1495	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1496
<>	161:2cc1468da177	1497	switch (pllsource)
<>	161:2cc1468da177	1498	{
<>	161:2cc1468da177	1499	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
<>	161:2cc1468da177	1500	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1501	break;
<>	161:2cc1468da177	1502
<>	161:2cc1468da177	1503	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
<>	161:2cc1468da177	1504	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1505	break;
<>	161:2cc1468da177	1506
<>	161:2cc1468da177	1507	default:
<>	161:2cc1468da177	1508	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1509	break;
<>	161:2cc1468da177	1510	}
<>	161:2cc1468da177	1511	return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1512	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
<>	161:2cc1468da177	1513	}
<>	161:2cc1468da177	1514
<>	161:2cc1468da177	1515	#if defined(SPDIFRX)
<>	161:2cc1468da177	1516	/**
<>	161:2cc1468da177	1517	* @brief Return PLLI2S clock frequency used for SPDIFRX domain
<>	161:2cc1468da177	1518	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1519	*/
<>	161:2cc1468da177	1520	uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
<>	161:2cc1468da177	1521	{
<>	161:2cc1468da177	1522	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1523
<>	161:2cc1468da177	1524	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
<>	161:2cc1468da177	1525	SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
<>	161:2cc1468da177	1526	*/
<>	161:2cc1468da177	1527	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1528
<>	161:2cc1468da177	1529	switch (pllsource)
<>	161:2cc1468da177	1530	{
<>	161:2cc1468da177	1531	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
<>	161:2cc1468da177	1532	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1533	break;
<>	161:2cc1468da177	1534
<>	161:2cc1468da177	1535	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
<>	161:2cc1468da177	1536	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1537	break;
<>	161:2cc1468da177	1538
<>	161:2cc1468da177	1539	default:
<>	161:2cc1468da177	1540	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1541	break;
<>	161:2cc1468da177	1542	}
<>	161:2cc1468da177	1543
<>	161:2cc1468da177	1544	return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1545	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
<>	161:2cc1468da177	1546	}
<>	161:2cc1468da177	1547	#endif /* SPDIFRX */
<>	161:2cc1468da177	1548
<>	161:2cc1468da177	1549	/**
<>	161:2cc1468da177	1550	* @brief Return PLLI2S clock frequency used for I2S domain
<>	161:2cc1468da177	1551	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1552	*/
<>	161:2cc1468da177	1553	uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
<>	161:2cc1468da177	1554	{
<>	161:2cc1468da177	1555	uint32_t pllinputfreq = 0U, pllsource = 0U;
<>	161:2cc1468da177	1556
<>	161:2cc1468da177	1557	/* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN
<>	161:2cc1468da177	1558	I2S Domain clock = PLLI2S_VCO / PLLI2SR
<>	161:2cc1468da177	1559	*/
<>	161:2cc1468da177	1560	pllsource = LL_RCC_PLL_GetMainSource();
<>	161:2cc1468da177	1561
<>	161:2cc1468da177	1562	switch (pllsource)
<>	161:2cc1468da177	1563	{
<>	161:2cc1468da177	1564	case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
<>	161:2cc1468da177	1565	pllinputfreq = HSE_VALUE;
<>	161:2cc1468da177	1566	break;
<>	161:2cc1468da177	1567
<>	161:2cc1468da177	1568	case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
<>	161:2cc1468da177	1569	default:
<>	161:2cc1468da177	1570	pllinputfreq = HSI_VALUE;
<>	161:2cc1468da177	1571	break;
<>	161:2cc1468da177	1572	}
<>	161:2cc1468da177	1573	return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
<>	161:2cc1468da177	1574	LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
<>	161:2cc1468da177	1575	}
<>	161:2cc1468da177	1576
<>	161:2cc1468da177	1577	/**
<>	161:2cc1468da177	1578	* @}
<>	161:2cc1468da177	1579	*/
<>	161:2cc1468da177	1580
<>	161:2cc1468da177	1581	/**
<>	161:2cc1468da177	1582	* @}
<>	161:2cc1468da177	1583	*/
<>	161:2cc1468da177	1584
<>	161:2cc1468da177	1585	#endif /* defined(RCC) */
<>	161:2cc1468da177	1586
<>	161:2cc1468da177	1587	/**
<>	161:2cc1468da177	1588	* @}
<>	161:2cc1468da177	1589	*/
<>	161:2cc1468da177	1590
<>	161:2cc1468da177	1591	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	1592
<>	161:2cc1468da177	1593	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/