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TARGET_LPC1549/LPC15xx.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
86:04dd9b1680ae
Child:
105:8ed44a420e5c
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 79:0c05e21ae27e 1
emilmont 79:0c05e21ae27e 2 /****************************************************************************************************//**
emilmont 79:0c05e21ae27e 3 * @file LPC15xx.h
emilmont 79:0c05e21ae27e 4 *
emilmont 79:0c05e21ae27e 5 * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
emilmont 79:0c05e21ae27e 6 * LPC15xx from .
emilmont 79:0c05e21ae27e 7 *
emilmont 79:0c05e21ae27e 8 * @version V0.3
emilmont 79:0c05e21ae27e 9 * @date 17. July 2013
emilmont 79:0c05e21ae27e 10 *
emilmont 79:0c05e21ae27e 11 * @note Generated with SVDConv V2.80
emilmont 79:0c05e21ae27e 12 * from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
emilmont 79:0c05e21ae27e 13 *
emilmont 79:0c05e21ae27e 14 * modified by Keil
emilmont 79:0c05e21ae27e 15 * modified by ytsuboi
emilmont 79:0c05e21ae27e 16 *******************************************************************************************************/
emilmont 79:0c05e21ae27e 17
emilmont 79:0c05e21ae27e 18
emilmont 79:0c05e21ae27e 19
emilmont 79:0c05e21ae27e 20 /** @addtogroup (null)
emilmont 79:0c05e21ae27e 21 * @{
emilmont 79:0c05e21ae27e 22 */
emilmont 79:0c05e21ae27e 23
emilmont 79:0c05e21ae27e 24 /** @addtogroup LPC15xx
emilmont 79:0c05e21ae27e 25 * @{
emilmont 79:0c05e21ae27e 26 */
emilmont 79:0c05e21ae27e 27
emilmont 79:0c05e21ae27e 28 #ifndef LPC15XX_H
emilmont 79:0c05e21ae27e 29 #define LPC15XX_H
emilmont 79:0c05e21ae27e 30
emilmont 79:0c05e21ae27e 31 #ifdef __cplusplus
emilmont 79:0c05e21ae27e 32 extern "C" {
emilmont 79:0c05e21ae27e 33 #endif
emilmont 79:0c05e21ae27e 34
emilmont 79:0c05e21ae27e 35
emilmont 79:0c05e21ae27e 36 /* ------------------------- Interrupt Number Definition ------------------------ */
emilmont 79:0c05e21ae27e 37
emilmont 79:0c05e21ae27e 38 typedef enum {
emilmont 79:0c05e21ae27e 39 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
emilmont 79:0c05e21ae27e 40 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
emilmont 79:0c05e21ae27e 41 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
emilmont 79:0c05e21ae27e 42 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
emilmont 79:0c05e21ae27e 43 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
emilmont 79:0c05e21ae27e 44 and No Match */
emilmont 79:0c05e21ae27e 45 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
emilmont 79:0c05e21ae27e 46 related Fault */
emilmont 79:0c05e21ae27e 47 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
emilmont 79:0c05e21ae27e 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
emilmont 79:0c05e21ae27e 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
emilmont 79:0c05e21ae27e 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
emilmont 79:0c05e21ae27e 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
emilmont 79:0c05e21ae27e 52 /* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
emilmont 79:0c05e21ae27e 53 WDT_IRQn = 0, /*!< 0 WDT */
emilmont 79:0c05e21ae27e 54 BOD_IRQn = 1, /*!< 1 BOD */
emilmont 79:0c05e21ae27e 55 FLASH_IRQn = 2, /*!< 2 FLASH */
emilmont 79:0c05e21ae27e 56 EE_IRQn = 3, /*!< 3 EE */
emilmont 79:0c05e21ae27e 57 DMA_IRQn = 4, /*!< 4 DMA */
emilmont 79:0c05e21ae27e 58 GINT0_IRQn = 5, /*!< 5 GINT0 */
emilmont 79:0c05e21ae27e 59 GINT1_IRQn = 6, /*!< 6 GINT1 */
emilmont 79:0c05e21ae27e 60 PIN_INT0_IRQn = 7, /*!< 7 PIN_INT0 */
emilmont 79:0c05e21ae27e 61 PIN_INT1_IRQn = 8, /*!< 8 PIN_INT1 */
emilmont 79:0c05e21ae27e 62 PIN_INT2_IRQn = 9, /*!< 9 PIN_INT2 */
emilmont 79:0c05e21ae27e 63 PIN_INT3_IRQn = 10, /*!< 10 PIN_INT3 */
emilmont 79:0c05e21ae27e 64 PIN_INT4_IRQn = 11, /*!< 11 PIN_INT4 */
emilmont 79:0c05e21ae27e 65 PIN_INT5_IRQn = 12, /*!< 12 PIN_INT5 */
emilmont 79:0c05e21ae27e 66 PIN_INT6_IRQn = 13, /*!< 13 PIN_INT6 */
emilmont 79:0c05e21ae27e 67 PIN_INT7_IRQn = 14, /*!< 14 PIN_INT7 */
emilmont 79:0c05e21ae27e 68 RIT_IRQn = 15, /*!< 15 RIT */
emilmont 79:0c05e21ae27e 69 SCT0_IRQn = 16, /*!< 16 SCT0 */
emilmont 79:0c05e21ae27e 70 SCT1_IRQn = 17, /*!< 17 SCT1 */
emilmont 79:0c05e21ae27e 71 SCT2_IRQn = 18, /*!< 18 SCT2 */
emilmont 79:0c05e21ae27e 72 SCT3_IRQn = 19, /*!< 19 SCT3 */
emilmont 79:0c05e21ae27e 73 MRT_IRQn = 20, /*!< 20 MRT */
emilmont 79:0c05e21ae27e 74 UART0_IRQn = 21, /*!< 21 UART0 */
emilmont 79:0c05e21ae27e 75 UART1_IRQn = 22, /*!< 22 UART1 */
emilmont 79:0c05e21ae27e 76 UART2_IRQn = 23, /*!< 23 UART2 */
emilmont 79:0c05e21ae27e 77 I2C0_IRQn = 24, /*!< 24 I2C0 */
emilmont 79:0c05e21ae27e 78 SPI0_IRQn = 25, /*!< 25 SPI0 */
emilmont 79:0c05e21ae27e 79 SPI1_IRQn = 26, /*!< 26 SPI1 */
emilmont 79:0c05e21ae27e 80 C_CAN0_IRQn = 27, /*!< 27 C_CAN0 */
emilmont 79:0c05e21ae27e 81 USB_IRQ_IRQn = 28, /*!< 28 USB_IRQ */
emilmont 79:0c05e21ae27e 82 USB_FIQ_IRQn = 29, /*!< 29 USB_FIQ */
emilmont 79:0c05e21ae27e 83 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
emilmont 79:0c05e21ae27e 84 ADC0_SEQA_IRQn = 31, /*!< 31 ADC0_SEQA */
emilmont 79:0c05e21ae27e 85 ADC0_SEQB_IRQn = 32, /*!< 32 ADC0_SEQB */
emilmont 79:0c05e21ae27e 86 ADC0_THCMP_IRQn = 33, /*!< 33 ADC0_THCMP */
emilmont 79:0c05e21ae27e 87 ADC0_OVR_IRQn = 34, /*!< 34 ADC0_OVR */
emilmont 79:0c05e21ae27e 88 ADC1_SEQA_IRQn = 35, /*!< 35 ADC1_SEQA */
emilmont 79:0c05e21ae27e 89 ADC1_SEQB_IRQn = 36, /*!< 36 ADC1_SEQB */
emilmont 79:0c05e21ae27e 90 ADC1_THCMP_IRQn = 37, /*!< 37 ADC1_THCMP */
emilmont 79:0c05e21ae27e 91 ADC1_OVR_IRQn = 38, /*!< 38 ADC1_OVR */
emilmont 79:0c05e21ae27e 92 DAC_IRQn = 39, /*!< 39 DAC */
emilmont 79:0c05e21ae27e 93 CMP0_IRQn = 40, /*!< 40 CMP0 */
emilmont 79:0c05e21ae27e 94 CMP1_IRQn = 41, /*!< 41 CMP1 */
emilmont 79:0c05e21ae27e 95 CMP2_IRQn = 42, /*!< 42 CMP2 */
emilmont 79:0c05e21ae27e 96 CMP3_IRQn = 43, /*!< 43 CMP3 */
emilmont 79:0c05e21ae27e 97 QEI_IRQn = 44, /*!< 44 QEI */
emilmont 79:0c05e21ae27e 98 RTC_ALARM_IRQn = 45, /*!< 45 RTC_ALARM */
emilmont 79:0c05e21ae27e 99 RTC_WAKE_IRQn = 46 /*!< 46 RTC_WAKE */
emilmont 79:0c05e21ae27e 100 } IRQn_Type;
emilmont 79:0c05e21ae27e 101
emilmont 79:0c05e21ae27e 102
emilmont 79:0c05e21ae27e 103 /** @addtogroup Configuration_of_CMSIS
emilmont 79:0c05e21ae27e 104 * @{
emilmont 79:0c05e21ae27e 105 */
emilmont 79:0c05e21ae27e 106
emilmont 79:0c05e21ae27e 107
emilmont 79:0c05e21ae27e 108 /* ================================================================================ */
emilmont 79:0c05e21ae27e 109 /* ================ Processor and Core Peripheral Section ================ */
emilmont 79:0c05e21ae27e 110 /* ================================================================================ */
emilmont 79:0c05e21ae27e 111
emilmont 79:0c05e21ae27e 112 /* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
emilmont 79:0c05e21ae27e 113 #define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */
emilmont 79:0c05e21ae27e 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
emilmont 79:0c05e21ae27e 115 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
emilmont 79:0c05e21ae27e 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 79:0c05e21ae27e 117 /** @} */ /* End of group Configuration_of_CMSIS */
emilmont 79:0c05e21ae27e 118
emilmont 79:0c05e21ae27e 119 #include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
emilmont 79:0c05e21ae27e 120 #include "system_LPC15xx.h" /*!< LPC15xx System */
emilmont 79:0c05e21ae27e 121
emilmont 79:0c05e21ae27e 122
emilmont 79:0c05e21ae27e 123 /* ================================================================================ */
emilmont 79:0c05e21ae27e 124 /* ================ Device Specific Peripheral Section ================ */
emilmont 79:0c05e21ae27e 125 /* ================================================================================ */
emilmont 79:0c05e21ae27e 126
emilmont 79:0c05e21ae27e 127
emilmont 79:0c05e21ae27e 128 /** @addtogroup Device_Peripheral_Registers
emilmont 79:0c05e21ae27e 129 * @{
emilmont 79:0c05e21ae27e 130 */
emilmont 79:0c05e21ae27e 131
emilmont 79:0c05e21ae27e 132
emilmont 79:0c05e21ae27e 133 /* ------------------- Start of section using anonymous unions ------------------ */
emilmont 79:0c05e21ae27e 134 #if defined(__CC_ARM)
emilmont 79:0c05e21ae27e 135 #pragma push
emilmont 79:0c05e21ae27e 136 #pragma anon_unions
emilmont 79:0c05e21ae27e 137 #elif defined(__ICCARM__)
emilmont 79:0c05e21ae27e 138 #pragma language=extended
emilmont 79:0c05e21ae27e 139 #elif defined(__GNUC__)
emilmont 79:0c05e21ae27e 140 /* anonymous unions are enabled by default */
emilmont 79:0c05e21ae27e 141 #elif defined(__TMS470__)
emilmont 79:0c05e21ae27e 142 /* anonymous unions are enabled by default */
emilmont 79:0c05e21ae27e 143 #elif defined(__TASKING__)
emilmont 79:0c05e21ae27e 144 #pragma warning 586
emilmont 79:0c05e21ae27e 145 #else
emilmont 79:0c05e21ae27e 146 #warning Not supported compiler type
emilmont 79:0c05e21ae27e 147 #endif
emilmont 79:0c05e21ae27e 148
emilmont 79:0c05e21ae27e 149
emilmont 79:0c05e21ae27e 150
emilmont 79:0c05e21ae27e 151 /* ================================================================================ */
emilmont 79:0c05e21ae27e 152 /* ================ GPIO_PORT ================ */
emilmont 79:0c05e21ae27e 153 /* ================================================================================ */
emilmont 79:0c05e21ae27e 154
emilmont 79:0c05e21ae27e 155
emilmont 79:0c05e21ae27e 156 /**
emilmont 79:0c05e21ae27e 157 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
emilmont 79:0c05e21ae27e 158 */
emilmont 79:0c05e21ae27e 159
emilmont 79:0c05e21ae27e 160 typedef struct { /*!< GPIO_PORT Structure */
emilmont 79:0c05e21ae27e 161 __IO uint8_t B[76]; /*!< Byte pin registers */
emilmont 79:0c05e21ae27e 162 __I uint32_t RESERVED0[45];
emilmont 79:0c05e21ae27e 163 __IO uint32_t W[76]; /*!< Word pin registers */
emilmont 79:0c05e21ae27e 164 __I uint32_t RESERVED1[1908];
emilmont 79:0c05e21ae27e 165 __IO uint32_t DIR[3]; /*!< Port Direction registers */
emilmont 79:0c05e21ae27e 166 __I uint32_t RESERVED2[29];
emilmont 79:0c05e21ae27e 167 __IO uint32_t MASK[3]; /*!< Port Mask register */
emilmont 79:0c05e21ae27e 168 __I uint32_t RESERVED3[29];
emilmont 79:0c05e21ae27e 169 __IO uint32_t PIN[3]; /*!< Port pin register */
emilmont 79:0c05e21ae27e 170 __I uint32_t RESERVED4[29];
emilmont 79:0c05e21ae27e 171 __IO uint32_t MPIN[3]; /*!< Masked port register */
emilmont 79:0c05e21ae27e 172 __I uint32_t RESERVED5[29];
emilmont 79:0c05e21ae27e 173 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
emilmont 79:0c05e21ae27e 174 __I uint32_t RESERVED6[29];
emilmont 79:0c05e21ae27e 175 __O uint32_t CLR[3]; /*!< Clear port */
emilmont 79:0c05e21ae27e 176 __I uint32_t RESERVED7[29];
emilmont 79:0c05e21ae27e 177 __O uint32_t NOT[3]; /*!< Toggle port */
emilmont 79:0c05e21ae27e 178 } LPC_GPIO_PORT_Type;
emilmont 79:0c05e21ae27e 179
emilmont 79:0c05e21ae27e 180
emilmont 79:0c05e21ae27e 181 /* ================================================================================ */
emilmont 79:0c05e21ae27e 182 /* ================ DMA ================ */
emilmont 79:0c05e21ae27e 183 /* ================================================================================ */
emilmont 79:0c05e21ae27e 184
emilmont 79:0c05e21ae27e 185
emilmont 79:0c05e21ae27e 186 /**
emilmont 79:0c05e21ae27e 187 * @brief DMA controller (DMA)
emilmont 79:0c05e21ae27e 188 */
emilmont 79:0c05e21ae27e 189
emilmont 79:0c05e21ae27e 190 typedef struct { /*!< DMA Structure */
emilmont 79:0c05e21ae27e 191 __IO uint32_t CTRL; /*!< DMA control. */
emilmont 79:0c05e21ae27e 192 __I uint32_t INTSTAT; /*!< Interrupt status. */
emilmont 79:0c05e21ae27e 193 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
emilmont 79:0c05e21ae27e 194 __I uint32_t RESERVED0[5];
emilmont 79:0c05e21ae27e 195 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
emilmont 79:0c05e21ae27e 196 __I uint32_t RESERVED1;
emilmont 79:0c05e21ae27e 197 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
emilmont 79:0c05e21ae27e 198 __I uint32_t RESERVED2;
emilmont 79:0c05e21ae27e 199 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
emilmont 79:0c05e21ae27e 200 __I uint32_t RESERVED3;
emilmont 79:0c05e21ae27e 201 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
emilmont 79:0c05e21ae27e 202 __I uint32_t RESERVED4;
emilmont 79:0c05e21ae27e 203 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
emilmont 79:0c05e21ae27e 204 __I uint32_t RESERVED5;
emilmont 79:0c05e21ae27e 205 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
emilmont 79:0c05e21ae27e 206 __I uint32_t RESERVED6;
emilmont 79:0c05e21ae27e 207 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
emilmont 79:0c05e21ae27e 208 __I uint32_t RESERVED7;
emilmont 79:0c05e21ae27e 209 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
emilmont 79:0c05e21ae27e 210 __I uint32_t RESERVED8;
emilmont 79:0c05e21ae27e 211 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
emilmont 79:0c05e21ae27e 212 __I uint32_t RESERVED9;
emilmont 79:0c05e21ae27e 213 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
emilmont 79:0c05e21ae27e 214 __I uint32_t RESERVED10;
emilmont 79:0c05e21ae27e 215 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
emilmont 79:0c05e21ae27e 216 __I uint32_t RESERVED11;
emilmont 79:0c05e21ae27e 217 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
emilmont 79:0c05e21ae27e 218 __I uint32_t RESERVED12[225];
emilmont 79:0c05e21ae27e 219 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 220 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 221 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 222 __I uint32_t RESERVED13;
emilmont 79:0c05e21ae27e 223 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 224 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 225 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 226 __I uint32_t RESERVED14;
emilmont 79:0c05e21ae27e 227 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 228 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 229 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 230 __I uint32_t RESERVED15;
emilmont 79:0c05e21ae27e 231 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 232 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 233 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 234 __I uint32_t RESERVED16;
emilmont 79:0c05e21ae27e 235 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 236 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 237 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 238 __I uint32_t RESERVED17;
emilmont 79:0c05e21ae27e 239 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 240 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 241 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 242 __I uint32_t RESERVED18;
emilmont 79:0c05e21ae27e 243 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 244 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 245 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 246 __I uint32_t RESERVED19;
emilmont 79:0c05e21ae27e 247 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 248 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 249 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 250 __I uint32_t RESERVED20;
emilmont 79:0c05e21ae27e 251 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 252 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 253 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 254 __I uint32_t RESERVED21;
emilmont 79:0c05e21ae27e 255 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 256 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 257 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 258 __I uint32_t RESERVED22;
emilmont 79:0c05e21ae27e 259 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 260 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 261 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 262 __I uint32_t RESERVED23;
emilmont 79:0c05e21ae27e 263 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 264 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 265 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 266 __I uint32_t RESERVED24;
emilmont 79:0c05e21ae27e 267 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 268 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 269 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 270 __I uint32_t RESERVED25;
emilmont 79:0c05e21ae27e 271 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 272 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 273 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 274 __I uint32_t RESERVED26;
emilmont 79:0c05e21ae27e 275 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 276 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 277 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 278 __I uint32_t RESERVED27;
emilmont 79:0c05e21ae27e 279 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 280 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 281 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 282 __I uint32_t RESERVED28;
emilmont 79:0c05e21ae27e 283 __IO uint32_t CFG16; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 284 __I uint32_t CTLSTAT16; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 285 __IO uint32_t XFERCFG16; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 286 __I uint32_t RESERVED29;
emilmont 79:0c05e21ae27e 287 __IO uint32_t CFG17; /*!< Configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 288 __I uint32_t CTLSTAT17; /*!< Control and status register for DMA channel 0. */
emilmont 79:0c05e21ae27e 289 __IO uint32_t XFERCFG17; /*!< Transfer configuration register for DMA channel 0. */
emilmont 79:0c05e21ae27e 290 } LPC_DMA_Type;
emilmont 79:0c05e21ae27e 291
emilmont 79:0c05e21ae27e 292
emilmont 79:0c05e21ae27e 293 /* ================================================================================ */
emilmont 79:0c05e21ae27e 294 /* ================ USB ================ */
emilmont 79:0c05e21ae27e 295 /* ================================================================================ */
emilmont 79:0c05e21ae27e 296
emilmont 79:0c05e21ae27e 297
emilmont 79:0c05e21ae27e 298 /**
emilmont 79:0c05e21ae27e 299 * @brief USB device controller (USB)
emilmont 79:0c05e21ae27e 300 */
emilmont 79:0c05e21ae27e 301
emilmont 79:0c05e21ae27e 302 typedef struct { /*!< USB Structure */
emilmont 79:0c05e21ae27e 303 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
emilmont 79:0c05e21ae27e 304 __IO uint32_t INFO; /*!< USB Info register */
emilmont 79:0c05e21ae27e 305 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
emilmont 79:0c05e21ae27e 306 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
emilmont 79:0c05e21ae27e 307 __IO uint32_t LPM; /*!< Link Power Management register */
emilmont 79:0c05e21ae27e 308 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
emilmont 79:0c05e21ae27e 309 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
emilmont 79:0c05e21ae27e 310 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
emilmont 79:0c05e21ae27e 311 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
emilmont 79:0c05e21ae27e 312 __IO uint32_t INTEN; /*!< USB interrupt enable register */
emilmont 79:0c05e21ae27e 313 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
emilmont 79:0c05e21ae27e 314 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
emilmont 79:0c05e21ae27e 315 __I uint32_t RESERVED0;
emilmont 79:0c05e21ae27e 316 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
emilmont 79:0c05e21ae27e 317 } LPC_USB_Type;
emilmont 79:0c05e21ae27e 318
emilmont 79:0c05e21ae27e 319
emilmont 79:0c05e21ae27e 320 /* ================================================================================ */
emilmont 79:0c05e21ae27e 321 /* ================ CRC ================ */
emilmont 79:0c05e21ae27e 322 /* ================================================================================ */
emilmont 79:0c05e21ae27e 323
emilmont 79:0c05e21ae27e 324
emilmont 79:0c05e21ae27e 325 /**
emilmont 79:0c05e21ae27e 326 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
emilmont 79:0c05e21ae27e 327 */
emilmont 79:0c05e21ae27e 328
emilmont 79:0c05e21ae27e 329 typedef struct { /*!< CRC Structure */
emilmont 79:0c05e21ae27e 330 __IO uint32_t MODE; /*!< CRC mode register */
emilmont 79:0c05e21ae27e 331 __IO uint32_t SEED; /*!< CRC seed register */
emilmont 79:0c05e21ae27e 332
emilmont 79:0c05e21ae27e 333 union {
emilmont 79:0c05e21ae27e 334 __O uint32_t WR_DATA; /*!< CRC data register */
emilmont 79:0c05e21ae27e 335 __I uint32_t SUM; /*!< CRC checksum register */
emilmont 79:0c05e21ae27e 336 };
emilmont 79:0c05e21ae27e 337 } LPC_CRC_Type;
emilmont 79:0c05e21ae27e 338
emilmont 79:0c05e21ae27e 339
emilmont 79:0c05e21ae27e 340 /* ================================================================================ */
emilmont 79:0c05e21ae27e 341 /* ================ SCT0 ================ */
emilmont 79:0c05e21ae27e 342 /* ================================================================================ */
emilmont 79:0c05e21ae27e 343
emilmont 79:0c05e21ae27e 344
emilmont 79:0c05e21ae27e 345 /**
emilmont 79:0c05e21ae27e 346 * @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
emilmont 79:0c05e21ae27e 347 */
emilmont 79:0c05e21ae27e 348
emilmont 79:0c05e21ae27e 349 typedef struct { /*!< SCT0 Structure */
emilmont 79:0c05e21ae27e 350 __IO uint32_t CONFIG; /*!< SCT configuration register */
emilmont 79:0c05e21ae27e 351 __IO uint32_t CTRL; /*!< SCT control register */
emilmont 79:0c05e21ae27e 352 __IO uint32_t LIMIT; /*!< SCT limit register */
emilmont 79:0c05e21ae27e 353 __IO uint32_t HALT; /*!< SCT halt condition register */
emilmont 79:0c05e21ae27e 354 __IO uint32_t STOP; /*!< SCT stop condition register */
emilmont 79:0c05e21ae27e 355 __IO uint32_t START; /*!< SCT start condition register */
emilmont 79:0c05e21ae27e 356 __IO uint32_t DITHER; /*!< SCT dither condition register */
emilmont 79:0c05e21ae27e 357 __I uint32_t RESERVED0[9];
emilmont 79:0c05e21ae27e 358 __IO uint32_t COUNT; /*!< SCT counter register */
emilmont 79:0c05e21ae27e 359 __IO uint32_t STATE; /*!< SCT state register */
emilmont 79:0c05e21ae27e 360 __I uint32_t INPUT; /*!< SCT input register */
emilmont 79:0c05e21ae27e 361 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
emilmont 79:0c05e21ae27e 362 __IO uint32_t OUTPUT; /*!< SCT output register */
emilmont 79:0c05e21ae27e 363 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
emilmont 79:0c05e21ae27e 364 __IO uint32_t RES; /*!< SCT conflict resolution register */
emilmont 79:0c05e21ae27e 365 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
emilmont 79:0c05e21ae27e 366 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
emilmont 79:0c05e21ae27e 367 __I uint32_t RESERVED1[35];
emilmont 79:0c05e21ae27e 368 __IO uint32_t EVEN; /*!< SCT event enable register */
emilmont 79:0c05e21ae27e 369 __IO uint32_t EVFLAG; /*!< SCT event flag register */
emilmont 79:0c05e21ae27e 370 __IO uint32_t CONEN; /*!< SCT conflict enable register */
emilmont 79:0c05e21ae27e 371 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
emilmont 79:0c05e21ae27e 372
emilmont 79:0c05e21ae27e 373 union {
emilmont 79:0c05e21ae27e 374 __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 375 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 376 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 377 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 378 };
emilmont 79:0c05e21ae27e 379
emilmont 79:0c05e21ae27e 380 union {
emilmont 79:0c05e21ae27e 381 __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 382 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 383 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 384 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 385 };
emilmont 79:0c05e21ae27e 386
emilmont 79:0c05e21ae27e 387 union {
emilmont 79:0c05e21ae27e 388 __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 389 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 390 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 391 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 392 };
emilmont 79:0c05e21ae27e 393
emilmont 79:0c05e21ae27e 394 union {
emilmont 79:0c05e21ae27e 395 __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 396 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 397 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 398 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 399 };
emilmont 79:0c05e21ae27e 400
emilmont 79:0c05e21ae27e 401 union {
emilmont 79:0c05e21ae27e 402 __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 403 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 404 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 405 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 406 };
emilmont 79:0c05e21ae27e 407
emilmont 79:0c05e21ae27e 408 union {
emilmont 79:0c05e21ae27e 409 __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 410 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 411 __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 412 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 413 };
emilmont 79:0c05e21ae27e 414
emilmont 79:0c05e21ae27e 415 union {
emilmont 79:0c05e21ae27e 416 __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 417 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 418 __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 419 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 420 };
emilmont 79:0c05e21ae27e 421
emilmont 79:0c05e21ae27e 422 union {
emilmont 79:0c05e21ae27e 423 __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 424 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 425 __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 426 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 427 };
emilmont 79:0c05e21ae27e 428
emilmont 79:0c05e21ae27e 429 union {
emilmont 79:0c05e21ae27e 430 __I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 431 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 432 __IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 433 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 434 };
emilmont 79:0c05e21ae27e 435
emilmont 79:0c05e21ae27e 436 union {
emilmont 79:0c05e21ae27e 437 __IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 438 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 439 __I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 440 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 441 };
emilmont 79:0c05e21ae27e 442
emilmont 79:0c05e21ae27e 443 union {
emilmont 79:0c05e21ae27e 444 __IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 445 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 446 __I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 447 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 448 };
emilmont 79:0c05e21ae27e 449
emilmont 79:0c05e21ae27e 450 union {
emilmont 79:0c05e21ae27e 451 __IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 452 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 453 __I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 454 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 455 };
emilmont 79:0c05e21ae27e 456
emilmont 79:0c05e21ae27e 457 union {
emilmont 79:0c05e21ae27e 458 __IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 459 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 460 __I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 461 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 462 };
emilmont 79:0c05e21ae27e 463
emilmont 79:0c05e21ae27e 464 union {
emilmont 79:0c05e21ae27e 465 __IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 466 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 467 __I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 468 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 469 };
emilmont 79:0c05e21ae27e 470
emilmont 79:0c05e21ae27e 471 union {
emilmont 79:0c05e21ae27e 472 __I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 473 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 474 __IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 475 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 476 };
emilmont 79:0c05e21ae27e 477
emilmont 79:0c05e21ae27e 478 union {
emilmont 79:0c05e21ae27e 479 __IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
emilmont 79:0c05e21ae27e 480 to REGMODE15 = 0 */
emilmont 79:0c05e21ae27e 481 __I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
emilmont 79:0c05e21ae27e 482 REGMODE15 = 1 */
emilmont 79:0c05e21ae27e 483 };
emilmont 79:0c05e21ae27e 484 __IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
emilmont 79:0c05e21ae27e 485 0 to 5. */
emilmont 79:0c05e21ae27e 486 __IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
emilmont 79:0c05e21ae27e 487 0 to 5. */
emilmont 79:0c05e21ae27e 488 __IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
emilmont 79:0c05e21ae27e 489 0 to 5. */
emilmont 79:0c05e21ae27e 490 __IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
emilmont 79:0c05e21ae27e 491 0 to 5. */
emilmont 79:0c05e21ae27e 492 __IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
emilmont 79:0c05e21ae27e 493 0 to 5. */
emilmont 79:0c05e21ae27e 494 __IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
emilmont 79:0c05e21ae27e 495 0 to 5. */
emilmont 79:0c05e21ae27e 496 __I uint32_t RESERVED2[42];
emilmont 79:0c05e21ae27e 497
emilmont 79:0c05e21ae27e 498 union {
emilmont 79:0c05e21ae27e 499 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 500 = 1 */
emilmont 79:0c05e21ae27e 501 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 502 = 0 */
emilmont 79:0c05e21ae27e 503 };
emilmont 79:0c05e21ae27e 504
emilmont 79:0c05e21ae27e 505 union {
emilmont 79:0c05e21ae27e 506 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 507 = 0 */
emilmont 79:0c05e21ae27e 508 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 509 = 1 */
emilmont 79:0c05e21ae27e 510 };
emilmont 79:0c05e21ae27e 511
emilmont 79:0c05e21ae27e 512 union {
emilmont 79:0c05e21ae27e 513 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 514 = 0 */
emilmont 79:0c05e21ae27e 515 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 516 = 1 */
emilmont 79:0c05e21ae27e 517 };
emilmont 79:0c05e21ae27e 518
emilmont 79:0c05e21ae27e 519 union {
emilmont 79:0c05e21ae27e 520 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 521 = 1 */
emilmont 79:0c05e21ae27e 522 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 523 = 0 */
emilmont 79:0c05e21ae27e 524 };
emilmont 79:0c05e21ae27e 525
emilmont 79:0c05e21ae27e 526 union {
emilmont 79:0c05e21ae27e 527 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 528 = 1 */
emilmont 79:0c05e21ae27e 529 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 530 = 0 */
emilmont 79:0c05e21ae27e 531 };
emilmont 79:0c05e21ae27e 532
emilmont 79:0c05e21ae27e 533 union {
emilmont 79:0c05e21ae27e 534 __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 535 = 1 */
emilmont 79:0c05e21ae27e 536 __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 537 = 0 */
emilmont 79:0c05e21ae27e 538 };
emilmont 79:0c05e21ae27e 539
emilmont 79:0c05e21ae27e 540 union {
emilmont 79:0c05e21ae27e 541 __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 542 = 0 */
emilmont 79:0c05e21ae27e 543 __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 544 = 1 */
emilmont 79:0c05e21ae27e 545 };
emilmont 79:0c05e21ae27e 546
emilmont 79:0c05e21ae27e 547 union {
emilmont 79:0c05e21ae27e 548 __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 549 = 0 */
emilmont 79:0c05e21ae27e 550 __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 551 = 1 */
emilmont 79:0c05e21ae27e 552 };
emilmont 79:0c05e21ae27e 553
emilmont 79:0c05e21ae27e 554 union {
emilmont 79:0c05e21ae27e 555 __IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 556 = 1 */
emilmont 79:0c05e21ae27e 557 __IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 558 = 0 */
emilmont 79:0c05e21ae27e 559 };
emilmont 79:0c05e21ae27e 560
emilmont 79:0c05e21ae27e 561 union {
emilmont 79:0c05e21ae27e 562 __IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 563 = 1 */
emilmont 79:0c05e21ae27e 564 __IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 565 = 0 */
emilmont 79:0c05e21ae27e 566 };
emilmont 79:0c05e21ae27e 567
emilmont 79:0c05e21ae27e 568 union {
emilmont 79:0c05e21ae27e 569 __IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 570 = 1 */
emilmont 79:0c05e21ae27e 571 __IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 572 = 0 */
emilmont 79:0c05e21ae27e 573 };
emilmont 79:0c05e21ae27e 574
emilmont 79:0c05e21ae27e 575 union {
emilmont 79:0c05e21ae27e 576 __IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 577 = 1 */
emilmont 79:0c05e21ae27e 578 __IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 579 = 0 */
emilmont 79:0c05e21ae27e 580 };
emilmont 79:0c05e21ae27e 581
emilmont 79:0c05e21ae27e 582 union {
emilmont 79:0c05e21ae27e 583 __IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 584 = 0 */
emilmont 79:0c05e21ae27e 585 __IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 586 = 1 */
emilmont 79:0c05e21ae27e 587 };
emilmont 79:0c05e21ae27e 588
emilmont 79:0c05e21ae27e 589 union {
emilmont 79:0c05e21ae27e 590 __IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 591 = 0 */
emilmont 79:0c05e21ae27e 592 __IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 593 = 1 */
emilmont 79:0c05e21ae27e 594 };
emilmont 79:0c05e21ae27e 595
emilmont 79:0c05e21ae27e 596 union {
emilmont 79:0c05e21ae27e 597 __IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 598 = 1 */
emilmont 79:0c05e21ae27e 599 __IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 600 = 0 */
emilmont 79:0c05e21ae27e 601 };
emilmont 79:0c05e21ae27e 602
emilmont 79:0c05e21ae27e 603 union {
emilmont 79:0c05e21ae27e 604 __IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
emilmont 79:0c05e21ae27e 605 = 1 */
emilmont 79:0c05e21ae27e 606 __IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
emilmont 79:0c05e21ae27e 607 = 0 */
emilmont 79:0c05e21ae27e 608 };
emilmont 79:0c05e21ae27e 609 __IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
emilmont 79:0c05e21ae27e 610 registers 0 to 5. */
emilmont 79:0c05e21ae27e 611 __IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
emilmont 79:0c05e21ae27e 612 registers 0 to 5. */
emilmont 79:0c05e21ae27e 613 __IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
emilmont 79:0c05e21ae27e 614 registers 0 to 5. */
emilmont 79:0c05e21ae27e 615 __IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
emilmont 79:0c05e21ae27e 616 registers 0 to 5. */
emilmont 79:0c05e21ae27e 617 __IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
emilmont 79:0c05e21ae27e 618 registers 0 to 5. */
emilmont 79:0c05e21ae27e 619 __IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
emilmont 79:0c05e21ae27e 620 registers 0 to 5. */
emilmont 79:0c05e21ae27e 621 __I uint32_t RESERVED3[42];
emilmont 79:0c05e21ae27e 622 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 623 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 624 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 625 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 626 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 627 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 628 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 629 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 630 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 631 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 632 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 633 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 634 __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 635 __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 636 __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 637 __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 638 __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 639 __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 640 __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 641 __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 642 __IO uint32_t EV10_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 643 __IO uint32_t EV10_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 644 __IO uint32_t EV11_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 645 __IO uint32_t EV11_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 646 __IO uint32_t EV12_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 647 __IO uint32_t EV12_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 648 __IO uint32_t EV13_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 649 __IO uint32_t EV13_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 650 __IO uint32_t EV14_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 651 __IO uint32_t EV14_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 652 __IO uint32_t EV15_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 653 __IO uint32_t EV15_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 654 __I uint32_t RESERVED4[96];
emilmont 79:0c05e21ae27e 655 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 656 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 657 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 658 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 659 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 660 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 661 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 662 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 663 __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 664 __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 665 __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 666 __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 667 __IO uint32_t OUT6_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 668 __IO uint32_t OUT6_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 669 __IO uint32_t OUT7_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 670 __IO uint32_t OUT7_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 671 __IO uint32_t OUT8_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 672 __IO uint32_t OUT8_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 673 __IO uint32_t OUT9_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 674 __IO uint32_t OUT9_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 675 } LPC_SCT0_Type;
emilmont 79:0c05e21ae27e 676
emilmont 79:0c05e21ae27e 677
emilmont 79:0c05e21ae27e 678 /* ================================================================================ */
emilmont 79:0c05e21ae27e 679 /* ================ SCT2 ================ */
emilmont 79:0c05e21ae27e 680 /* ================================================================================ */
emilmont 79:0c05e21ae27e 681
emilmont 79:0c05e21ae27e 682
emilmont 79:0c05e21ae27e 683 /**
emilmont 79:0c05e21ae27e 684 * @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
emilmont 79:0c05e21ae27e 685 */
emilmont 79:0c05e21ae27e 686
emilmont 79:0c05e21ae27e 687 typedef struct { /*!< SCT2 Structure */
emilmont 79:0c05e21ae27e 688 __IO uint32_t CONFIG; /*!< SCT configuration register */
emilmont 79:0c05e21ae27e 689 __IO uint32_t CTRL; /*!< SCT control register */
emilmont 79:0c05e21ae27e 690 __IO uint32_t LIMIT; /*!< SCT limit register */
emilmont 79:0c05e21ae27e 691 __IO uint32_t HALT; /*!< SCT halt condition register */
emilmont 79:0c05e21ae27e 692 __IO uint32_t STOP; /*!< SCT stop condition register */
emilmont 79:0c05e21ae27e 693 __IO uint32_t START; /*!< SCT start condition register */
emilmont 79:0c05e21ae27e 694 __I uint32_t RESERVED0[10];
emilmont 79:0c05e21ae27e 695 __IO uint32_t COUNT; /*!< SCT counter register */
emilmont 79:0c05e21ae27e 696 __IO uint32_t STATE; /*!< SCT state register */
emilmont 79:0c05e21ae27e 697 __I uint32_t INPUT; /*!< SCT input register */
emilmont 79:0c05e21ae27e 698 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
emilmont 79:0c05e21ae27e 699 __IO uint32_t OUTPUT; /*!< SCT output register */
emilmont 79:0c05e21ae27e 700 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
emilmont 79:0c05e21ae27e 701 __IO uint32_t RES; /*!< SCT conflict resolution register */
emilmont 79:0c05e21ae27e 702 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
emilmont 79:0c05e21ae27e 703 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
emilmont 79:0c05e21ae27e 704 __I uint32_t RESERVED1[35];
emilmont 79:0c05e21ae27e 705 __IO uint32_t EVEN; /*!< SCT event enable register */
emilmont 79:0c05e21ae27e 706 __IO uint32_t EVFLAG; /*!< SCT event flag register */
emilmont 79:0c05e21ae27e 707 __IO uint32_t CONEN; /*!< SCT conflict enable register */
emilmont 79:0c05e21ae27e 708 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
emilmont 79:0c05e21ae27e 709
emilmont 79:0c05e21ae27e 710 union {
emilmont 79:0c05e21ae27e 711 __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
emilmont 79:0c05e21ae27e 712 = 1 */
emilmont 79:0c05e21ae27e 713 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
emilmont 79:0c05e21ae27e 714 REGMODE7 = 0 */
emilmont 79:0c05e21ae27e 715 };
emilmont 79:0c05e21ae27e 716
emilmont 79:0c05e21ae27e 717 union {
emilmont 79:0c05e21ae27e 718 __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
emilmont 79:0c05e21ae27e 719 = 1 */
emilmont 79:0c05e21ae27e 720 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
emilmont 79:0c05e21ae27e 721 REGMODE7 = 0 */
emilmont 79:0c05e21ae27e 722 };
emilmont 79:0c05e21ae27e 723
emilmont 79:0c05e21ae27e 724 union {
emilmont 79:0c05e21ae27e 725 __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
emilmont 79:0c05e21ae27e 726 = 1 */
emilmont 79:0c05e21ae27e 727 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
emilmont 79:0c05e21ae27e 728 REGMODE7 = 0 */
emilmont 79:0c05e21ae27e 729 };
emilmont 79:0c05e21ae27e 730
emilmont 79:0c05e21ae27e 731 union {
emilmont 79:0c05e21ae27e 732 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
emilmont 79:0c05e21ae27e 733 REGMODE7 = 0 */
emilmont 79:0c05e21ae27e 734 __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
emilmont 79:0c05e21ae27e 735 = 1 */
emilmont 79:0c05e21ae27e 736 };
emilmont 79:0c05e21ae27e 737
emilmont 79:0c05e21ae27e 738 union {
emilmont 79:0c05e21ae27e 739 __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
emilmont 79:0c05e21ae27e 740 = 1 */
emilmont 79:0c05e21ae27e 741 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
emilmont 79:0c05e21ae27e 742 REGMODE7 = 0 */
emilmont 79:0c05e21ae27e 743 };
emilmont 79:0c05e21ae27e 744
emilmont 79:0c05e21ae27e 745 union {
emilmont 79:0c05e21ae27e 746 __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
emilmont 79:0c05e21ae27e 747 REGMODE7 = 0 */
emilmont 79:0c05e21ae27e 748 __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
emilmont 79:0c05e21ae27e 749 = 1 */
emilmont 79:0c05e21ae27e 750 };
emilmont 79:0c05e21ae27e 751
emilmont 79:0c05e21ae27e 752 union {
emilmont 79:0c05e21ae27e 753 __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
emilmont 79:0c05e21ae27e 754 = 1 */
emilmont 79:0c05e21ae27e 755 __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
emilmont 79:0c05e21ae27e 756 REGMODE7 = 0 */
emilmont 79:0c05e21ae27e 757 };
emilmont 79:0c05e21ae27e 758
emilmont 79:0c05e21ae27e 759 union {
emilmont 79:0c05e21ae27e 760 __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
emilmont 79:0c05e21ae27e 761 = 1 */
emilmont 79:0c05e21ae27e 762 __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
emilmont 79:0c05e21ae27e 763 REGMODE7 = 0 */
emilmont 79:0c05e21ae27e 764 };
emilmont 79:0c05e21ae27e 765 __I uint32_t RESERVED2[56];
emilmont 79:0c05e21ae27e 766
emilmont 79:0c05e21ae27e 767 union {
emilmont 79:0c05e21ae27e 768 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
emilmont 79:0c05e21ae27e 769 = 1 */
emilmont 79:0c05e21ae27e 770 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
emilmont 79:0c05e21ae27e 771 = 0 */
emilmont 79:0c05e21ae27e 772 };
emilmont 79:0c05e21ae27e 773
emilmont 79:0c05e21ae27e 774 union {
emilmont 79:0c05e21ae27e 775 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
emilmont 79:0c05e21ae27e 776 = 1 */
emilmont 79:0c05e21ae27e 777 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
emilmont 79:0c05e21ae27e 778 = 0 */
emilmont 79:0c05e21ae27e 779 };
emilmont 79:0c05e21ae27e 780
emilmont 79:0c05e21ae27e 781 union {
emilmont 79:0c05e21ae27e 782 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
emilmont 79:0c05e21ae27e 783 = 1 */
emilmont 79:0c05e21ae27e 784 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
emilmont 79:0c05e21ae27e 785 = 0 */
emilmont 79:0c05e21ae27e 786 };
emilmont 79:0c05e21ae27e 787
emilmont 79:0c05e21ae27e 788 union {
emilmont 79:0c05e21ae27e 789 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
emilmont 79:0c05e21ae27e 790 = 0 */
emilmont 79:0c05e21ae27e 791 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
emilmont 79:0c05e21ae27e 792 = 1 */
emilmont 79:0c05e21ae27e 793 };
emilmont 79:0c05e21ae27e 794
emilmont 79:0c05e21ae27e 795 union {
emilmont 79:0c05e21ae27e 796 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
emilmont 79:0c05e21ae27e 797 = 1 */
emilmont 79:0c05e21ae27e 798 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
emilmont 79:0c05e21ae27e 799 = 0 */
emilmont 79:0c05e21ae27e 800 };
emilmont 79:0c05e21ae27e 801
emilmont 79:0c05e21ae27e 802 union {
emilmont 79:0c05e21ae27e 803 __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
emilmont 79:0c05e21ae27e 804 = 0 */
emilmont 79:0c05e21ae27e 805 __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
emilmont 79:0c05e21ae27e 806 = 1 */
emilmont 79:0c05e21ae27e 807 };
emilmont 79:0c05e21ae27e 808
emilmont 79:0c05e21ae27e 809 union {
emilmont 79:0c05e21ae27e 810 __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
emilmont 79:0c05e21ae27e 811 = 1 */
emilmont 79:0c05e21ae27e 812 __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
emilmont 79:0c05e21ae27e 813 = 0 */
emilmont 79:0c05e21ae27e 814 };
emilmont 79:0c05e21ae27e 815
emilmont 79:0c05e21ae27e 816 union {
emilmont 79:0c05e21ae27e 817 __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
emilmont 79:0c05e21ae27e 818 = 1 */
emilmont 79:0c05e21ae27e 819 __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
emilmont 79:0c05e21ae27e 820 = 0 */
emilmont 79:0c05e21ae27e 821 };
emilmont 79:0c05e21ae27e 822 __I uint32_t RESERVED3[56];
emilmont 79:0c05e21ae27e 823 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 824 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 825 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 826 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 827 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 828 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 829 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 830 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 831 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 832 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 833 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 834 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 835 __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 836 __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 837 __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 838 __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 839 __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 840 __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 841 __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
emilmont 79:0c05e21ae27e 842 __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
emilmont 79:0c05e21ae27e 843 __I uint32_t RESERVED4[108];
emilmont 79:0c05e21ae27e 844 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 845 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 846 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 847 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 848 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 849 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 850 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 851 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 852 __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 853 __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 854 __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
emilmont 79:0c05e21ae27e 855 __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
emilmont 79:0c05e21ae27e 856 } LPC_SCT2_Type;
emilmont 79:0c05e21ae27e 857
emilmont 79:0c05e21ae27e 858
emilmont 79:0c05e21ae27e 859 /* ================================================================================ */
emilmont 79:0c05e21ae27e 860 /* ================ ADC0 ================ */
emilmont 79:0c05e21ae27e 861 /* ================================================================================ */
emilmont 79:0c05e21ae27e 862
emilmont 79:0c05e21ae27e 863
emilmont 79:0c05e21ae27e 864 /**
emilmont 79:0c05e21ae27e 865 * @brief 12-bit ADC controller ADC0/1 (ADC0)
emilmont 79:0c05e21ae27e 866 */
emilmont 79:0c05e21ae27e 867
emilmont 79:0c05e21ae27e 868 typedef struct { /*!< ADC0 Structure */
emilmont 79:0c05e21ae27e 869 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
emilmont 79:0c05e21ae27e 870 bits for each sequence and the A/D power-down bit. */
emilmont 79:0c05e21ae27e 871 __IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
emilmont 79:0c05e21ae27e 872 internal source for various channels */
emilmont 79:0c05e21ae27e 873 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
emilmont 79:0c05e21ae27e 874 and channel selection for conversion sequence-A. Also specifies
emilmont 79:0c05e21ae27e 875 interrupt mode for sequence-A. */
emilmont 79:0c05e21ae27e 876 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
emilmont 79:0c05e21ae27e 877 and channel selection for conversion sequence-B. Also specifies
emilmont 79:0c05e21ae27e 878 interrupt mode for sequence-B. */
emilmont 79:0c05e21ae27e 879 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
emilmont 79:0c05e21ae27e 880 the result of the most recent A/D conversion performed under
emilmont 79:0c05e21ae27e 881 sequence-A */
emilmont 79:0c05e21ae27e 882 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
emilmont 79:0c05e21ae27e 883 the result of the most recent A/D conversion performed under
emilmont 79:0c05e21ae27e 884 sequence-B */
emilmont 79:0c05e21ae27e 885 __I uint32_t RESERVED0[2];
emilmont 79:0c05e21ae27e 886 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
emilmont 79:0c05e21ae27e 887 of the most recent conversion completed on channel 0. */
emilmont 79:0c05e21ae27e 888 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
emilmont 79:0c05e21ae27e 889 level for automatic threshold comparison for any channels linked
emilmont 79:0c05e21ae27e 890 to threshold pair 0. */
emilmont 79:0c05e21ae27e 891 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
emilmont 79:0c05e21ae27e 892 level for automatic threshold comparison for any channels linked
emilmont 79:0c05e21ae27e 893 to threshold pair 1. */
emilmont 79:0c05e21ae27e 894 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
emilmont 79:0c05e21ae27e 895 level for automatic threshold comparison for any channels linked
emilmont 79:0c05e21ae27e 896 to threshold pair 0. */
emilmont 79:0c05e21ae27e 897 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
emilmont 79:0c05e21ae27e 898 level for automatic threshold comparison for any channels linked
emilmont 79:0c05e21ae27e 899 to threshold pair 1. */
emilmont 79:0c05e21ae27e 900 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
emilmont 79:0c05e21ae27e 901 threshold compare registers are to be used for each channel */
emilmont 79:0c05e21ae27e 902 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
emilmont 79:0c05e21ae27e 903 bits that enable the sequence-A, sequence-B, threshold compare
emilmont 79:0c05e21ae27e 904 and data overrun interrupts to be generated. */
emilmont 79:0c05e21ae27e 905 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
emilmont 79:0c05e21ae27e 906 and the individual component overrun and threshold-compare flags.
emilmont 79:0c05e21ae27e 907 (The overrun bits replicate information stored in the result
emilmont 79:0c05e21ae27e 908 registers). */
emilmont 79:0c05e21ae27e 909 __IO uint32_t TRM; /*!< ADC trim register. */
emilmont 79:0c05e21ae27e 910 } LPC_ADC0_Type;
emilmont 79:0c05e21ae27e 911
emilmont 79:0c05e21ae27e 912
emilmont 79:0c05e21ae27e 913 /* ================================================================================ */
emilmont 79:0c05e21ae27e 914 /* ================ DAC ================ */
emilmont 79:0c05e21ae27e 915 /* ================================================================================ */
emilmont 79:0c05e21ae27e 916
emilmont 79:0c05e21ae27e 917
emilmont 79:0c05e21ae27e 918 /**
emilmont 79:0c05e21ae27e 919 * @brief 12-bit DAC Modification (DAC)
emilmont 79:0c05e21ae27e 920 */
emilmont 79:0c05e21ae27e 921
emilmont 79:0c05e21ae27e 922 typedef struct { /*!< DAC Structure */
emilmont 79:0c05e21ae27e 923 __IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
emilmont 79:0c05e21ae27e 924 value to be converted to analog. */
emilmont 79:0c05e21ae27e 925 __IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
emilmont 79:0c05e21ae27e 926 DAC operation and the interrupt/dma request flag. */
emilmont 79:0c05e21ae27e 927 __IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
emilmont 79:0c05e21ae27e 928 value for the internal DAC DMA/Interrupt timer. */
emilmont 79:0c05e21ae27e 929 } LPC_DAC_Type;
emilmont 79:0c05e21ae27e 930
emilmont 79:0c05e21ae27e 931
emilmont 79:0c05e21ae27e 932 /* ================================================================================ */
emilmont 79:0c05e21ae27e 933 /* ================ ACMP ================ */
emilmont 79:0c05e21ae27e 934 /* ================================================================================ */
emilmont 79:0c05e21ae27e 935
emilmont 79:0c05e21ae27e 936
emilmont 79:0c05e21ae27e 937 /**
emilmont 79:0c05e21ae27e 938 * @brief Analog comparators ACMP0/1/2/3 (ACMP)
emilmont 79:0c05e21ae27e 939 */
emilmont 79:0c05e21ae27e 940
emilmont 79:0c05e21ae27e 941 typedef struct { /*!< ACMP Structure */
emilmont 79:0c05e21ae27e 942 __IO uint32_t CTRL; /*!< Comparator block control register */
emilmont 79:0c05e21ae27e 943 __IO uint32_t CMP0; /*!< Comparator 0 source control */
emilmont 79:0c05e21ae27e 944 __IO uint32_t CMPFILTR0; /*!< Comparator 0 pin filter set-up */
emilmont 79:0c05e21ae27e 945 __IO uint32_t CMP1; /*!< Comparator 1 source control */
emilmont 79:0c05e21ae27e 946 __IO uint32_t CMPFILTR1; /*!< Comparator 0 pin filter set-up */
emilmont 79:0c05e21ae27e 947 __IO uint32_t CMP2; /*!< Comparator 2 source control */
emilmont 79:0c05e21ae27e 948 __IO uint32_t CMPFILTR2; /*!< Comparator 0 pin filter set-up */
emilmont 79:0c05e21ae27e 949 __IO uint32_t CMP3; /*!< Comparator 3 source control */
emilmont 79:0c05e21ae27e 950 __IO uint32_t CMPFILTR3; /*!< Comparator 0 pin filter set-up */
emilmont 79:0c05e21ae27e 951 } LPC_ACMP_Type;
emilmont 79:0c05e21ae27e 952
emilmont 79:0c05e21ae27e 953
emilmont 79:0c05e21ae27e 954 /* ================================================================================ */
emilmont 79:0c05e21ae27e 955 /* ================ INMUX ================ */
emilmont 79:0c05e21ae27e 956 /* ================================================================================ */
emilmont 79:0c05e21ae27e 957
emilmont 79:0c05e21ae27e 958
emilmont 79:0c05e21ae27e 959 /**
emilmont 79:0c05e21ae27e 960 * @brief Input multiplexing (INMUX) (INMUX)
emilmont 79:0c05e21ae27e 961 */
emilmont 79:0c05e21ae27e 962
emilmont 79:0c05e21ae27e 963 typedef struct { /*!< INMUX Structure */
emilmont 79:0c05e21ae27e 964 __IO uint32_t SCT0_INMUX[7]; /*!< Pinmux register for SCT0 input 0 */
emilmont 79:0c05e21ae27e 965 __I uint32_t RESERVED0;
emilmont 79:0c05e21ae27e 966 __IO uint32_t SCT1_INMUX[7]; /*!< Pinmux register for SCT1 input 0 */
emilmont 79:0c05e21ae27e 967 __I uint32_t RESERVED1;
emilmont 79:0c05e21ae27e 968 __IO uint32_t SCT2_INMUX[3]; /*!< Pinmux register for SCT2 input 0 */
emilmont 79:0c05e21ae27e 969 __I uint32_t RESERVED2[5];
emilmont 79:0c05e21ae27e 970 __IO uint32_t SCT3_INMUX[3]; /*!< Pinmux register for SCT3 input 0 */
emilmont 79:0c05e21ae27e 971 __I uint32_t RESERVED3[21];
emilmont 79:0c05e21ae27e 972 __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select register 0 */
emilmont 79:0c05e21ae27e 973 __IO uint32_t DMA_ITRIG_INMUX[18]; /*!< Trigger input for DMA channel 0 select register. */
emilmont 79:0c05e21ae27e 974 __I uint32_t RESERVED4[14];
emilmont 79:0c05e21ae27e 975 __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
emilmont 79:0c05e21ae27e 976 clock */
emilmont 79:0c05e21ae27e 977 __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement function target clock */
emilmont 79:0c05e21ae27e 978 } LPC_INMUX_Type;
emilmont 79:0c05e21ae27e 979
emilmont 79:0c05e21ae27e 980
emilmont 79:0c05e21ae27e 981 /* ================================================================================ */
emilmont 79:0c05e21ae27e 982 /* ================ RTC ================ */
emilmont 79:0c05e21ae27e 983 /* ================================================================================ */
emilmont 79:0c05e21ae27e 984
emilmont 79:0c05e21ae27e 985
emilmont 79:0c05e21ae27e 986 /**
emilmont 79:0c05e21ae27e 987 * @brief Real-Time Clock (RTC) (RTC)
emilmont 79:0c05e21ae27e 988 */
emilmont 79:0c05e21ae27e 989
emilmont 79:0c05e21ae27e 990 typedef struct { /*!< RTC Structure */
emilmont 79:0c05e21ae27e 991 __IO uint32_t CTRL; /*!< RTC control register */
emilmont 79:0c05e21ae27e 992 __IO uint32_t MATCH; /*!< RTC match register */
emilmont 79:0c05e21ae27e 993 __IO uint32_t COUNT; /*!< RTC counter register */
emilmont 79:0c05e21ae27e 994 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
emilmont 79:0c05e21ae27e 995 } LPC_RTC_Type;
emilmont 79:0c05e21ae27e 996
emilmont 79:0c05e21ae27e 997
emilmont 79:0c05e21ae27e 998 /* ================================================================================ */
emilmont 79:0c05e21ae27e 999 /* ================ WWDT ================ */
emilmont 79:0c05e21ae27e 1000 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1001
emilmont 79:0c05e21ae27e 1002
emilmont 79:0c05e21ae27e 1003 /**
emilmont 79:0c05e21ae27e 1004 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
emilmont 79:0c05e21ae27e 1005 */
emilmont 79:0c05e21ae27e 1006
emilmont 79:0c05e21ae27e 1007 typedef struct { /*!< WWDT Structure */
emilmont 79:0c05e21ae27e 1008 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
emilmont 79:0c05e21ae27e 1009 and status of the Watchdog Timer. */
emilmont 79:0c05e21ae27e 1010 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
emilmont 79:0c05e21ae27e 1011 the time-out value. */
emilmont 79:0c05e21ae27e 1012 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
emilmont 79:0c05e21ae27e 1013 to this register reloads the Watchdog timer with the value contained
emilmont 79:0c05e21ae27e 1014 in WDTC. */
emilmont 79:0c05e21ae27e 1015 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
emilmont 79:0c05e21ae27e 1016 the current value of the Watchdog timer. */
emilmont 79:0c05e21ae27e 1017 __I uint32_t RESERVED0;
emilmont 79:0c05e21ae27e 1018 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
emilmont 79:0c05e21ae27e 1019 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
emilmont 79:0c05e21ae27e 1020 } LPC_WWDT_Type;
emilmont 79:0c05e21ae27e 1021
emilmont 79:0c05e21ae27e 1022
emilmont 79:0c05e21ae27e 1023 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1024 /* ================ SWM ================ */
emilmont 79:0c05e21ae27e 1025 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1026
emilmont 79:0c05e21ae27e 1027
emilmont 79:0c05e21ae27e 1028 /**
emilmont 79:0c05e21ae27e 1029 * @brief Switch Matrix (SWM) (SWM)
emilmont 79:0c05e21ae27e 1030 */
emilmont 79:0c05e21ae27e 1031
emilmont 79:0c05e21ae27e 1032 typedef struct { /*!< SWM Structure */
emilmont 79:0c05e21ae27e 1033 union {
emilmont 79:0c05e21ae27e 1034 __IO uint32_t PINASSIGN[16];
emilmont 79:0c05e21ae27e 1035 struct {
emilmont 79:0c05e21ae27e 1036 __IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
emilmont 79:0c05e21ae27e 1037 U0_RTS, U0_CTS. */
emilmont 79:0c05e21ae27e 1038 __IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
emilmont 79:0c05e21ae27e 1039 U1_RXD, U1_RTS. */
emilmont 79:0c05e21ae27e 1040 __IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
emilmont 79:0c05e21ae27e 1041 U2_TXD, U2_RXD. */
emilmont 79:0c05e21ae27e 1042 __IO uint32_t PINASSIGN3; /*!< Pin assign register 3. Assign movable function . */
emilmont 79:0c05e21ae27e 1043 __IO uint32_t PINASSIGN4; /*!< Pin assign register 4. Assign movable functions */
emilmont 79:0c05e21ae27e 1044 __IO uint32_t PINASSIGN5; /*!< Pin assign register 5. Assign movable functions */
emilmont 79:0c05e21ae27e 1045 __IO uint32_t PINASSIGN6; /*!< Pin assign register 6. Assign movable functions */
emilmont 79:0c05e21ae27e 1046 __IO uint32_t PINASSIGN7; /*!< Pin assign register 7. Assign movable functions */
emilmont 79:0c05e21ae27e 1047 __IO uint32_t PINASSIGN8; /*!< Pin assign register 8. Assign movable functions */
emilmont 79:0c05e21ae27e 1048 __IO uint32_t PINASSIGN9; /*!< Pin assign register 9. Assign movable functions */
emilmont 79:0c05e21ae27e 1049 __IO uint32_t PINASSIGN10; /*!< Pin assign register 10. Assign movable functions */
emilmont 79:0c05e21ae27e 1050 __IO uint32_t PINASSIGN11; /*!< Pin assign register 11. Assign movable functions */
emilmont 79:0c05e21ae27e 1051 __IO uint32_t PINASSIGN12; /*!< Pin assign register 12. Assign movable functions */
emilmont 79:0c05e21ae27e 1052 __IO uint32_t PINASSIGN13; /*!< Pin assign register 13. Assign movable functions */
emilmont 79:0c05e21ae27e 1053 __IO uint32_t PINASSIGN14; /*!< Pin assign register 14. Assign movable functions */
emilmont 79:0c05e21ae27e 1054 __IO uint32_t PINASSIGN15; /*!< Pin assign register 15. Assign movable functions */
emilmont 79:0c05e21ae27e 1055 };
emilmont 79:0c05e21ae27e 1056 };
emilmont 79:0c05e21ae27e 1057 __I uint32_t RESERVED0[96];
emilmont 79:0c05e21ae27e 1058 __IO uint32_t PINENABLE0; /*!< Pin enable register 0. Enables fixed-pin functions */
emilmont 79:0c05e21ae27e 1059 __IO uint32_t PINENABLE1; /*!< Pin enable register 0. Enables fixed-pin functions */
emilmont 79:0c05e21ae27e 1060 } LPC_SWM_Type;
emilmont 79:0c05e21ae27e 1061
emilmont 79:0c05e21ae27e 1062
emilmont 79:0c05e21ae27e 1063 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1064 /* ================ PMU ================ */
emilmont 79:0c05e21ae27e 1065 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1066
emilmont 79:0c05e21ae27e 1067
emilmont 79:0c05e21ae27e 1068 /**
emilmont 79:0c05e21ae27e 1069 * @brief Power Management Unit (PMU) (PMU)
emilmont 79:0c05e21ae27e 1070 */
emilmont 79:0c05e21ae27e 1071
emilmont 79:0c05e21ae27e 1072 typedef struct { /*!< PMU Structure */
emilmont 79:0c05e21ae27e 1073 __IO uint32_t PCON; /*!< Power control register */
emilmont 79:0c05e21ae27e 1074 __IO uint32_t GPREG0; /*!< General purpose register 0 */
emilmont 79:0c05e21ae27e 1075 __IO uint32_t GPREG1; /*!< General purpose register 0 */
emilmont 79:0c05e21ae27e 1076 __IO uint32_t GPREG2; /*!< General purpose register 0 */
emilmont 79:0c05e21ae27e 1077 __IO uint32_t GPREG3; /*!< General purpose register 0 */
emilmont 79:0c05e21ae27e 1078 __IO uint32_t DPDCTRL; /*!< Deep power-down control register */
emilmont 79:0c05e21ae27e 1079 } LPC_PMU_Type;
emilmont 79:0c05e21ae27e 1080
emilmont 79:0c05e21ae27e 1081
emilmont 79:0c05e21ae27e 1082 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1083 /* ================ USART0 ================ */
emilmont 79:0c05e21ae27e 1084 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1085
emilmont 79:0c05e21ae27e 1086
emilmont 79:0c05e21ae27e 1087 /**
emilmont 79:0c05e21ae27e 1088 * @brief USART0 (USART0)
emilmont 79:0c05e21ae27e 1089 */
emilmont 79:0c05e21ae27e 1090
emilmont 79:0c05e21ae27e 1091 typedef struct { /*!< USART0 Structure */
emilmont 79:0c05e21ae27e 1092 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
emilmont 79:0c05e21ae27e 1093 that typically are not changed during operation. */
emilmont 79:0c05e21ae27e 1094 __IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
emilmont 79:0c05e21ae27e 1095 likely to change during operation. */
emilmont 79:0c05e21ae27e 1096 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
emilmont 79:0c05e21ae27e 1097 here. Writing ones clears some bits in the register. Some bits
emilmont 79:0c05e21ae27e 1098 can be cleared by writing a 1 to them. */
emilmont 79:0c05e21ae27e 1099 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
emilmont 79:0c05e21ae27e 1100 interrupt enable bit for each potential USART interrupt. A complete
emilmont 79:0c05e21ae27e 1101 value may be read from this register. Writing a 1 to any implemented
emilmont 79:0c05e21ae27e 1102 bit position causes that bit to be set. */
emilmont 79:0c05e21ae27e 1103 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
emilmont 79:0c05e21ae27e 1104 of bits in the INTENSET register. Writing a 1 to any implemented
emilmont 79:0c05e21ae27e 1105 bit position causes the corresponding bit to be cleared. */
emilmont 79:0c05e21ae27e 1106 __I uint32_t RXDATA; /*!< Receiver Data register. Contains the last character received. */
emilmont 79:0c05e21ae27e 1107 __I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
emilmont 79:0c05e21ae27e 1108 received with the current USART receive status. Allows DMA or
emilmont 79:0c05e21ae27e 1109 software to recover incoming data and status together. */
emilmont 79:0c05e21ae27e 1110 __IO uint32_t TXDATA; /*!< Transmit Data register. Data to be transmitted is written here. */
emilmont 79:0c05e21ae27e 1111 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
emilmont 79:0c05e21ae27e 1112 value. */
emilmont 79:0c05e21ae27e 1113 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
emilmont 79:0c05e21ae27e 1114 enabled. */
emilmont 79:0c05e21ae27e 1115 } LPC_USART0_Type;
emilmont 79:0c05e21ae27e 1116
emilmont 79:0c05e21ae27e 1117
emilmont 79:0c05e21ae27e 1118 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1119 /* ================ SPI0 ================ */
emilmont 79:0c05e21ae27e 1120 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1121
emilmont 79:0c05e21ae27e 1122
emilmont 79:0c05e21ae27e 1123 /**
emilmont 79:0c05e21ae27e 1124 * @brief SPI0 (SPI0)
emilmont 79:0c05e21ae27e 1125 */
emilmont 79:0c05e21ae27e 1126
emilmont 79:0c05e21ae27e 1127 typedef struct { /*!< SPI0 Structure */
emilmont 79:0c05e21ae27e 1128 __IO uint32_t CFG; /*!< SPI Configuration register */
emilmont 79:0c05e21ae27e 1129 __IO uint32_t DLY; /*!< SPI Delay register */
emilmont 79:0c05e21ae27e 1130 __IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
emilmont 79:0c05e21ae27e 1131 to that bit position */
emilmont 79:0c05e21ae27e 1132 __IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
emilmont 79:0c05e21ae27e 1133 from this register. Writing a 1 to any implemented bit position
emilmont 79:0c05e21ae27e 1134 causes that bit to be set. */
emilmont 79:0c05e21ae27e 1135 __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
emilmont 79:0c05e21ae27e 1136 position causes the corresponding bit in INTENSET to be cleared. */
emilmont 79:0c05e21ae27e 1137 __I uint32_t RXDAT; /*!< SPI Receive Data */
emilmont 79:0c05e21ae27e 1138 __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control */
emilmont 79:0c05e21ae27e 1139 __IO uint32_t TXDAT; /*!< SPI Transmit Data with Control */
emilmont 79:0c05e21ae27e 1140 __IO uint32_t TXCTL; /*!< SPI Transmit Control */
emilmont 79:0c05e21ae27e 1141 __IO uint32_t DIV; /*!< SPI clock Divider */
emilmont 79:0c05e21ae27e 1142 __I uint32_t INTSTAT; /*!< SPI Interrupt Status */
emilmont 79:0c05e21ae27e 1143 } LPC_SPI0_Type;
emilmont 79:0c05e21ae27e 1144
emilmont 79:0c05e21ae27e 1145
emilmont 79:0c05e21ae27e 1146 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1147 /* ================ I2C0 ================ */
emilmont 79:0c05e21ae27e 1148 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1149
emilmont 79:0c05e21ae27e 1150
emilmont 79:0c05e21ae27e 1151 /**
emilmont 79:0c05e21ae27e 1152 * @brief I2C-bus interface (I2C0)
emilmont 79:0c05e21ae27e 1153 */
emilmont 79:0c05e21ae27e 1154
emilmont 79:0c05e21ae27e 1155 typedef struct { /*!< I2C0 Structure */
emilmont 79:0c05e21ae27e 1156 __IO uint32_t CFG; /*!< Configuration for shared functions. */
emilmont 79:0c05e21ae27e 1157 __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */
emilmont 79:0c05e21ae27e 1158 __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */
emilmont 79:0c05e21ae27e 1159 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */
emilmont 79:0c05e21ae27e 1160 __IO uint32_t TIMEOUT; /*!< Time-out value register. */
emilmont 79:0c05e21ae27e 1161 __IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
emilmont 79:0c05e21ae27e 1162 what time increments are used for the MSTTIME and SLVTIME registers. */
emilmont 79:0c05e21ae27e 1163 __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */
emilmont 79:0c05e21ae27e 1164 __I uint32_t RESERVED0;
emilmont 79:0c05e21ae27e 1165 __IO uint32_t MSTCTL; /*!< Master control register. */
emilmont 79:0c05e21ae27e 1166 __IO uint32_t MSTTIME; /*!< Master timing configuration. */
emilmont 79:0c05e21ae27e 1167 __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */
emilmont 79:0c05e21ae27e 1168 __I uint32_t RESERVED1[5];
emilmont 79:0c05e21ae27e 1169 __IO uint32_t SLVCTL; /*!< Slave control register. */
emilmont 79:0c05e21ae27e 1170 __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */
emilmont 79:0c05e21ae27e 1171 __IO uint32_t SLVADR0; /*!< Slave address 0. */
emilmont 79:0c05e21ae27e 1172 __IO uint32_t SLVADR1; /*!< Slave address 0. */
emilmont 79:0c05e21ae27e 1173 __IO uint32_t SLVADR2; /*!< Slave address 0. */
emilmont 79:0c05e21ae27e 1174 __IO uint32_t SLVADR3; /*!< Slave address 0. */
emilmont 79:0c05e21ae27e 1175 __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */
emilmont 79:0c05e21ae27e 1176 __I uint32_t RESERVED2[9];
emilmont 79:0c05e21ae27e 1177 __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */
emilmont 79:0c05e21ae27e 1178 } LPC_I2C0_Type;
emilmont 79:0c05e21ae27e 1179
emilmont 79:0c05e21ae27e 1180
emilmont 79:0c05e21ae27e 1181 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1182 /* ================ QEI ================ */
emilmont 79:0c05e21ae27e 1183 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1184
emilmont 79:0c05e21ae27e 1185
emilmont 79:0c05e21ae27e 1186 /**
emilmont 79:0c05e21ae27e 1187 * @brief Quadrature Encoder Interface (QEI) (QEI)
emilmont 79:0c05e21ae27e 1188 */
emilmont 79:0c05e21ae27e 1189
emilmont 79:0c05e21ae27e 1190 typedef struct { /*!< QEI Structure */
emilmont 79:0c05e21ae27e 1191 __O uint32_t CON; /*!< Control register */
emilmont 79:0c05e21ae27e 1192 __I uint32_t STAT; /*!< Encoder status register */
emilmont 79:0c05e21ae27e 1193 __IO uint32_t CONF; /*!< Configuration register */
emilmont 79:0c05e21ae27e 1194 __I uint32_t POS; /*!< Position register */
emilmont 79:0c05e21ae27e 1195 __IO uint32_t MAXPOS; /*!< Maximum position register */
emilmont 79:0c05e21ae27e 1196 __IO uint32_t CMPOS0; /*!< position compare register 0 */
emilmont 79:0c05e21ae27e 1197 __IO uint32_t CMPOS1; /*!< position compare register 1 */
emilmont 79:0c05e21ae27e 1198 __IO uint32_t CMPOS2; /*!< position compare register 2 */
emilmont 79:0c05e21ae27e 1199 __I uint32_t INXCNT; /*!< Index count register */
emilmont 79:0c05e21ae27e 1200 __IO uint32_t INXCMP0; /*!< Index compare register 0 */
emilmont 79:0c05e21ae27e 1201 __IO uint32_t LOAD; /*!< Velocity timer reload register */
emilmont 79:0c05e21ae27e 1202 __I uint32_t TIME; /*!< Velocity timer register */
emilmont 79:0c05e21ae27e 1203 __I uint32_t VEL; /*!< Velocity counter register */
emilmont 79:0c05e21ae27e 1204 __I uint32_t CAP; /*!< Velocity capture register */
emilmont 79:0c05e21ae27e 1205 __IO uint32_t VELCOMP; /*!< Velocity compare register */
emilmont 79:0c05e21ae27e 1206 __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */
emilmont 79:0c05e21ae27e 1207 __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */
emilmont 79:0c05e21ae27e 1208 __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */
emilmont 79:0c05e21ae27e 1209 __IO uint32_t WINDOW; /*!< Index acceptance window register */
emilmont 79:0c05e21ae27e 1210 __IO uint32_t INXCMP1; /*!< Index compare register 1 */
emilmont 79:0c05e21ae27e 1211 __IO uint32_t INXCMP2; /*!< Index compare register 2 */
emilmont 79:0c05e21ae27e 1212 __I uint32_t RESERVED0[993];
emilmont 79:0c05e21ae27e 1213 __O uint32_t IEC; /*!< Interrupt enable clear register */
emilmont 79:0c05e21ae27e 1214 __O uint32_t IES; /*!< Interrupt enable set register */
emilmont 79:0c05e21ae27e 1215 __I uint32_t INTSTAT; /*!< Interrupt status register */
emilmont 79:0c05e21ae27e 1216 __O uint32_t IE; /*!< Interrupt enable clear register */
emilmont 79:0c05e21ae27e 1217 __O uint32_t CLR; /*!< Interrupt status clear register */
emilmont 79:0c05e21ae27e 1218 __O uint32_t SET; /*!< Interrupt status set register */
emilmont 79:0c05e21ae27e 1219 } LPC_QEI_Type;
emilmont 79:0c05e21ae27e 1220
emilmont 79:0c05e21ae27e 1221
emilmont 79:0c05e21ae27e 1222 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1223 /* ================ SYSCON ================ */
emilmont 79:0c05e21ae27e 1224 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1225
emilmont 79:0c05e21ae27e 1226
emilmont 79:0c05e21ae27e 1227 /**
emilmont 79:0c05e21ae27e 1228 * @brief System configuration (SYSCON) (SYSCON)
emilmont 79:0c05e21ae27e 1229 */
emilmont 79:0c05e21ae27e 1230
emilmont 79:0c05e21ae27e 1231 typedef struct { /*!< SYSCON Structure */
emilmont 79:0c05e21ae27e 1232 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
emilmont 79:0c05e21ae27e 1233 __I uint32_t RESERVED0[4];
emilmont 79:0c05e21ae27e 1234 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
emilmont 79:0c05e21ae27e 1235 __I uint32_t RESERVED1;
emilmont 79:0c05e21ae27e 1236 __IO uint32_t NMISRC; /*!< NMI Source Control */
emilmont 79:0c05e21ae27e 1237 __I uint32_t RESERVED2[8];
emilmont 79:0c05e21ae27e 1238 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
emilmont 79:0c05e21ae27e 1239 __IO uint32_t PRESETCTRL0; /*!< Peripheral reset control 0 */
emilmont 79:0c05e21ae27e 1240 __IO uint32_t PRESETCTRL1; /*!< Peripheral reset control 1 */
emilmont 79:0c05e21ae27e 1241 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
emilmont 79:0c05e21ae27e 1242 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
emilmont 79:0c05e21ae27e 1243 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 2 */
emilmont 79:0c05e21ae27e 1244 __I uint32_t RESERVED3[10];
emilmont 79:0c05e21ae27e 1245 __IO uint32_t MAINCLKSELA; /*!< Main clock source select A */
emilmont 79:0c05e21ae27e 1246 __IO uint32_t MAINCLKSELB; /*!< Main clock source select B */
emilmont 79:0c05e21ae27e 1247 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
emilmont 79:0c05e21ae27e 1248 __IO uint32_t ADCASYNCCLKSEL; /*!< ADC asynchronous clock source select */
emilmont 79:0c05e21ae27e 1249 __I uint32_t RESERVED4;
emilmont 79:0c05e21ae27e 1250 __IO uint32_t CLKOUTSELA; /*!< CLKOUT clock source select A */
emilmont 79:0c05e21ae27e 1251 __IO uint32_t CLKOUTSELB; /*!< CLKOUT clock source select B */
emilmont 79:0c05e21ae27e 1252 __I uint32_t RESERVED5;
emilmont 79:0c05e21ae27e 1253 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
emilmont 79:0c05e21ae27e 1254 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
emilmont 79:0c05e21ae27e 1255 __IO uint32_t SCTPLLCLKSEL; /*!< SCT PLL clock source select */
emilmont 79:0c05e21ae27e 1256 __I uint32_t RESERVED6[5];
emilmont 79:0c05e21ae27e 1257 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
emilmont 79:0c05e21ae27e 1258 __IO uint32_t SYSAHBCLKCTRL0; /*!< System clock control 0 */
emilmont 79:0c05e21ae27e 1259 __IO uint32_t SYSAHBCLKCTRL1; /*!< System clock control 1 */
emilmont 79:0c05e21ae27e 1260 __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */
emilmont 79:0c05e21ae27e 1261 __IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
emilmont 79:0c05e21ae27e 1262 baud rate generator. */
emilmont 79:0c05e21ae27e 1263 __IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
emilmont 79:0c05e21ae27e 1264 filter */
emilmont 79:0c05e21ae27e 1265 __IO uint32_t TRACECLKDIV; /*!< ARM trace clock divider */
emilmont 79:0c05e21ae27e 1266 __I uint32_t RESERVED7[4];
emilmont 79:0c05e21ae27e 1267 __IO uint32_t USBCLKDIV; /*!< USB clock divider */
emilmont 79:0c05e21ae27e 1268 __IO uint32_t ADCASYNCCLKDIV; /*!< Asynchronous ADC clock divider */
emilmont 79:0c05e21ae27e 1269 __I uint32_t RESERVED8;
emilmont 79:0c05e21ae27e 1270 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
emilmont 79:0c05e21ae27e 1271 __I uint32_t RESERVED9[11];
emilmont 79:0c05e21ae27e 1272 __IO uint32_t FRGCTRL; /*!< USART fractional baud rate generator control */
emilmont 79:0c05e21ae27e 1273 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
emilmont 79:0c05e21ae27e 1274 __IO uint32_t USBCLKST; /*!< USB clock status */
emilmont 79:0c05e21ae27e 1275 __I uint32_t RESERVED10[19];
emilmont 79:0c05e21ae27e 1276 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
emilmont 79:0c05e21ae27e 1277 __I uint32_t RESERVED11;
emilmont 79:0c05e21ae27e 1278 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
emilmont 79:0c05e21ae27e 1279 __I uint32_t RESERVED12;
emilmont 79:0c05e21ae27e 1280 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator control */
emilmont 79:0c05e21ae27e 1281 __I uint32_t RESERVED13;
emilmont 79:0c05e21ae27e 1282 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
emilmont 79:0c05e21ae27e 1283 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
emilmont 79:0c05e21ae27e 1284 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
emilmont 79:0c05e21ae27e 1285 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
emilmont 79:0c05e21ae27e 1286 __IO uint32_t SCTPLLCTRL; /*!< SCT PLL control */
emilmont 79:0c05e21ae27e 1287 __I uint32_t SCTPLLSTAT; /*!< SCT PLL status */
emilmont 79:0c05e21ae27e 1288 __I uint32_t RESERVED14[21];
emilmont 79:0c05e21ae27e 1289 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
emilmont 79:0c05e21ae27e 1290 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
emilmont 79:0c05e21ae27e 1291 __I uint32_t RESERVED15[3];
emilmont 79:0c05e21ae27e 1292 __IO uint32_t STARTERP0; /*!< Start logic 0 wake-up enable register */
emilmont 79:0c05e21ae27e 1293 __IO uint32_t STARTERP1; /*!< Start logic 1 wake-up enable register */
emilmont 79:0c05e21ae27e 1294 } LPC_SYSCON_Type;
emilmont 79:0c05e21ae27e 1295
emilmont 79:0c05e21ae27e 1296
emilmont 79:0c05e21ae27e 1297 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1298 /* ================ MRT ================ */
emilmont 79:0c05e21ae27e 1299 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1300
emilmont 79:0c05e21ae27e 1301
emilmont 79:0c05e21ae27e 1302 /**
emilmont 79:0c05e21ae27e 1303 * @brief Multi-Rate Timer (MRT) (MRT)
emilmont 79:0c05e21ae27e 1304 */
emilmont 79:0c05e21ae27e 1305
emilmont 79:0c05e21ae27e 1306 typedef struct { /*!< MRT Structure */
emilmont 79:0c05e21ae27e 1307 __IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
emilmont 79:0c05e21ae27e 1308 the TIMER0 register. */
emilmont 79:0c05e21ae27e 1309 __I uint32_t TIMER0; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
emilmont 79:0c05e21ae27e 1310 __IO uint32_t CTRL0; /*!< MRT0 Control register. This register controls the MRT0 modes. */
emilmont 79:0c05e21ae27e 1311 __IO uint32_t STAT0; /*!< MRT0 Status register. */
emilmont 79:0c05e21ae27e 1312 __IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
emilmont 79:0c05e21ae27e 1313 the TIMER0 register. */
emilmont 79:0c05e21ae27e 1314 __I uint32_t TIMER1; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
emilmont 79:0c05e21ae27e 1315 __IO uint32_t CTRL1; /*!< MRT0 Control register. This register controls the MRT0 modes. */
emilmont 79:0c05e21ae27e 1316 __IO uint32_t STAT1; /*!< MRT0 Status register. */
emilmont 79:0c05e21ae27e 1317 __IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
emilmont 79:0c05e21ae27e 1318 the TIMER0 register. */
emilmont 79:0c05e21ae27e 1319 __I uint32_t TIMER2; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
emilmont 79:0c05e21ae27e 1320 __IO uint32_t CTRL2; /*!< MRT0 Control register. This register controls the MRT0 modes. */
emilmont 79:0c05e21ae27e 1321 __IO uint32_t STAT2; /*!< MRT0 Status register. */
emilmont 79:0c05e21ae27e 1322 __IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
emilmont 79:0c05e21ae27e 1323 the TIMER0 register. */
emilmont 79:0c05e21ae27e 1324 __I uint32_t TIMER3; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
emilmont 79:0c05e21ae27e 1325 __IO uint32_t CTRL3; /*!< MRT0 Control register. This register controls the MRT0 modes. */
emilmont 79:0c05e21ae27e 1326 __IO uint32_t STAT3; /*!< MRT0 Status register. */
emilmont 79:0c05e21ae27e 1327 __I uint32_t RESERVED0[45];
emilmont 79:0c05e21ae27e 1328 __I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
emilmont 79:0c05e21ae27e 1329 first idle channel. */
emilmont 79:0c05e21ae27e 1330 __IO uint32_t IRQ_FLAG; /*!< Global interrupt flag register */
emilmont 79:0c05e21ae27e 1331 } LPC_MRT_Type;
emilmont 79:0c05e21ae27e 1332
emilmont 79:0c05e21ae27e 1333
emilmont 79:0c05e21ae27e 1334 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1335 /* ================ PINT ================ */
emilmont 79:0c05e21ae27e 1336 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1337
emilmont 79:0c05e21ae27e 1338
emilmont 79:0c05e21ae27e 1339 /**
emilmont 79:0c05e21ae27e 1340 * @brief Pin interruptand pattern match (PINT) (PINT)
emilmont 79:0c05e21ae27e 1341 */
emilmont 79:0c05e21ae27e 1342
emilmont 79:0c05e21ae27e 1343 typedef struct { /*!< PINT Structure */
emilmont 79:0c05e21ae27e 1344 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
emilmont 79:0c05e21ae27e 1345 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
emilmont 79:0c05e21ae27e 1346 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
emilmont 79:0c05e21ae27e 1347 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
emilmont 79:0c05e21ae27e 1348 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
emilmont 79:0c05e21ae27e 1349 register */
emilmont 79:0c05e21ae27e 1350 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
emilmont 79:0c05e21ae27e 1351 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
emilmont 79:0c05e21ae27e 1352 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
emilmont 79:0c05e21ae27e 1353 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
emilmont 79:0c05e21ae27e 1354 __IO uint32_t IST; /*!< Pin interrupt status register */
emilmont 79:0c05e21ae27e 1355 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
emilmont 79:0c05e21ae27e 1356 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
emilmont 79:0c05e21ae27e 1357 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
emilmont 79:0c05e21ae27e 1358 } LPC_PINT_Type;
emilmont 79:0c05e21ae27e 1359
emilmont 79:0c05e21ae27e 1360
emilmont 79:0c05e21ae27e 1361 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1362 /* ================ GINT0 ================ */
emilmont 79:0c05e21ae27e 1363 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1364
emilmont 79:0c05e21ae27e 1365
emilmont 79:0c05e21ae27e 1366 /**
emilmont 79:0c05e21ae27e 1367 * @brief Group interrupt 0/1 (GINT0/1) (GINT0)
emilmont 79:0c05e21ae27e 1368 */
emilmont 79:0c05e21ae27e 1369
emilmont 79:0c05e21ae27e 1370 typedef struct { /*!< GINT0 Structure */
emilmont 79:0c05e21ae27e 1371 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
emilmont 79:0c05e21ae27e 1372 __I uint32_t RESERVED0[7];
emilmont 79:0c05e21ae27e 1373 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
emilmont 79:0c05e21ae27e 1374 __I uint32_t RESERVED1[5];
emilmont 79:0c05e21ae27e 1375 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port 0 enable register */
emilmont 79:0c05e21ae27e 1376 } LPC_GINT0_Type;
emilmont 79:0c05e21ae27e 1377
emilmont 79:0c05e21ae27e 1378
emilmont 79:0c05e21ae27e 1379 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1380 /* ================ RIT ================ */
emilmont 79:0c05e21ae27e 1381 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1382
emilmont 79:0c05e21ae27e 1383
emilmont 79:0c05e21ae27e 1384 /**
emilmont 79:0c05e21ae27e 1385 * @brief Repetitive Interrupt Timer (RIT) (RIT)
emilmont 79:0c05e21ae27e 1386 */
emilmont 79:0c05e21ae27e 1387
emilmont 79:0c05e21ae27e 1388 typedef struct { /*!< RIT Structure */
emilmont 79:0c05e21ae27e 1389 __IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
emilmont 79:0c05e21ae27e 1390 value. */
emilmont 79:0c05e21ae27e 1391 __IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
emilmont 79:0c05e21ae27e 1392 value. A 1 written to any bit will force a compare on the corresponding
emilmont 79:0c05e21ae27e 1393 bit of the counter and compare register. */
emilmont 79:0c05e21ae27e 1394 __IO uint32_t CTRL; /*!< Control register. */
emilmont 79:0c05e21ae27e 1395 __IO uint32_t COUNTER; /*!< Counter LSB register. 32 LSBs of the counter. */
emilmont 79:0c05e21ae27e 1396 __IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
emilmont 79:0c05e21ae27e 1397 value. */
emilmont 79:0c05e21ae27e 1398 __IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
emilmont 79:0c05e21ae27e 1399 value. A 1 written to any bit will force a compare on the corresponding
emilmont 79:0c05e21ae27e 1400 bit of the counter and compare register. */
emilmont 79:0c05e21ae27e 1401 __I uint32_t RESERVED0;
emilmont 79:0c05e21ae27e 1402 __IO uint32_t COUNTER_H; /*!< Counter MSB register. 16 MSBs of the counter. */
emilmont 79:0c05e21ae27e 1403 } LPC_RIT_Type;
emilmont 79:0c05e21ae27e 1404
emilmont 79:0c05e21ae27e 1405
emilmont 79:0c05e21ae27e 1406 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1407 /* ================ SCTIPU ================ */
emilmont 79:0c05e21ae27e 1408 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1409
emilmont 79:0c05e21ae27e 1410
emilmont 79:0c05e21ae27e 1411 /**
emilmont 79:0c05e21ae27e 1412 * @brief SCT Input Processing Unit (IPU) (SCTIPU)
emilmont 79:0c05e21ae27e 1413 */
emilmont 79:0c05e21ae27e 1414
emilmont 79:0c05e21ae27e 1415 typedef struct { /*!< SCTIPU Structure */
emilmont 79:0c05e21ae27e 1416 __IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
emilmont 79:0c05e21ae27e 1417 latch/sample-enable mux selects, and sample overrride bits for
emilmont 79:0c05e21ae27e 1418 the SAMPLE module. */
emilmont 79:0c05e21ae27e 1419 __I uint32_t RESERVED0[7];
emilmont 79:0c05e21ae27e 1420 __IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
emilmont 79:0c05e21ae27e 1421 to ORed Abort Output 0. */
emilmont 79:0c05e21ae27e 1422 __IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
emilmont 79:0c05e21ae27e 1423 input source caused abort output 0. */
emilmont 79:0c05e21ae27e 1424 __I uint32_t RESERVED1[6];
emilmont 79:0c05e21ae27e 1425 __IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
emilmont 79:0c05e21ae27e 1426 to ORed Abort Output 0. */
emilmont 79:0c05e21ae27e 1427 __IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
emilmont 79:0c05e21ae27e 1428 input source caused abort output 0. */
emilmont 79:0c05e21ae27e 1429 __I uint32_t RESERVED2[6];
emilmont 79:0c05e21ae27e 1430 __IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
emilmont 79:0c05e21ae27e 1431 to ORed Abort Output 0. */
emilmont 79:0c05e21ae27e 1432 __IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
emilmont 79:0c05e21ae27e 1433 input source caused abort output 0. */
emilmont 79:0c05e21ae27e 1434 __I uint32_t RESERVED3[6];
emilmont 79:0c05e21ae27e 1435 __IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
emilmont 79:0c05e21ae27e 1436 to ORed Abort Output 0. */
emilmont 79:0c05e21ae27e 1437 __IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
emilmont 79:0c05e21ae27e 1438 input source caused abort output 0. */
emilmont 79:0c05e21ae27e 1439 } LPC_SCTIPU_Type;
emilmont 79:0c05e21ae27e 1440
emilmont 79:0c05e21ae27e 1441
emilmont 79:0c05e21ae27e 1442 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1443 /* ================ FLASHCTRL ================ */
emilmont 79:0c05e21ae27e 1444 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1445
emilmont 79:0c05e21ae27e 1446
emilmont 79:0c05e21ae27e 1447 /**
emilmont 79:0c05e21ae27e 1448 * @brief Flash controller (FLASHCTRL)
emilmont 79:0c05e21ae27e 1449 */
emilmont 79:0c05e21ae27e 1450
emilmont 79:0c05e21ae27e 1451 typedef struct { /*!< FLASHCTRL Structure */
emilmont 79:0c05e21ae27e 1452 __I uint32_t RESERVED0[8];
emilmont 79:0c05e21ae27e 1453 __IO uint32_t FMSSTART; /*!< Signature start address register */
emilmont 79:0c05e21ae27e 1454 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
emilmont 79:0c05e21ae27e 1455 __I uint32_t RESERVED1;
emilmont 79:0c05e21ae27e 1456 __I uint32_t FMSW0; /*!< Signature word */
emilmont 79:0c05e21ae27e 1457 } LPC_FLASHCTRL_Type;
emilmont 79:0c05e21ae27e 1458
emilmont 79:0c05e21ae27e 1459
emilmont 79:0c05e21ae27e 1460 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1461 /* ================ C_CAN0 ================ */
emilmont 79:0c05e21ae27e 1462 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1463
emilmont 79:0c05e21ae27e 1464
emilmont 79:0c05e21ae27e 1465 /**
emilmont 79:0c05e21ae27e 1466 * @brief Controller Area Network C_CAN0 (C_CAN0)
emilmont 79:0c05e21ae27e 1467 */
emilmont 79:0c05e21ae27e 1468
emilmont 79:0c05e21ae27e 1469 typedef struct { /*!< C_CAN0 Structure */
emilmont 79:0c05e21ae27e 1470 __IO uint32_t CANCNTL; /*!< CAN control */
emilmont 79:0c05e21ae27e 1471 __IO uint32_t CANSTAT; /*!< Status register */
emilmont 79:0c05e21ae27e 1472 __I uint32_t CANEC; /*!< Error counter */
emilmont 79:0c05e21ae27e 1473 __IO uint32_t CANBT; /*!< Bit timing register */
emilmont 79:0c05e21ae27e 1474 __I uint32_t CANINT; /*!< Interrupt register */
emilmont 79:0c05e21ae27e 1475 __IO uint32_t CANTEST; /*!< Test register */
emilmont 79:0c05e21ae27e 1476 __IO uint32_t CANBRPE; /*!< Baud rate prescaler extension register */
emilmont 79:0c05e21ae27e 1477 __I uint32_t RESERVED0;
emilmont 79:0c05e21ae27e 1478 __IO uint32_t CANIF1_CMDREQ; /*!< Message interface 1 command request */
emilmont 79:0c05e21ae27e 1479
emilmont 79:0c05e21ae27e 1480 union {
emilmont 79:0c05e21ae27e 1481 __IO uint32_t CANIF1_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
emilmont 79:0c05e21ae27e 1482 __IO uint32_t CANIF1_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
emilmont 79:0c05e21ae27e 1483 };
emilmont 79:0c05e21ae27e 1484 __IO uint32_t CANIF1_MSK1; /*!< Message interface 1 mask 1 */
emilmont 79:0c05e21ae27e 1485 __IO uint32_t CANIF1_MSK2; /*!< Message interface 1 mask 2 */
emilmont 79:0c05e21ae27e 1486 __IO uint32_t CANIF1_ARB1; /*!< Message interface 1 arbitration 1 */
emilmont 79:0c05e21ae27e 1487 __IO uint32_t CANIF1_ARB2; /*!< Message interface 1 arbitration 2 */
emilmont 79:0c05e21ae27e 1488 __IO uint32_t CANIF1_MCTRL; /*!< Message interface 1 message control */
emilmont 79:0c05e21ae27e 1489 __IO uint32_t CANIF1_DA1; /*!< Message interface 1 data A1 */
emilmont 79:0c05e21ae27e 1490 __IO uint32_t CANIF1_DA2; /*!< Message interface 1 data A2 */
emilmont 79:0c05e21ae27e 1491 __IO uint32_t CANIF1_DB1; /*!< Message interface 1 data B1 */
emilmont 79:0c05e21ae27e 1492 __IO uint32_t CANIF1_DB2; /*!< Message interface 1 data B2 */
emilmont 79:0c05e21ae27e 1493 __I uint32_t RESERVED1[13];
emilmont 79:0c05e21ae27e 1494 __IO uint32_t CANIF2_CMDREQ; /*!< Message interface 1 command request */
emilmont 79:0c05e21ae27e 1495
emilmont 79:0c05e21ae27e 1496 union {
emilmont 79:0c05e21ae27e 1497 __IO uint32_t CANIF2_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
emilmont 79:0c05e21ae27e 1498 __IO uint32_t CANIF2_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
emilmont 79:0c05e21ae27e 1499 };
emilmont 79:0c05e21ae27e 1500 __IO uint32_t CANIF2_MSK1; /*!< Message interface 1 mask 1 */
emilmont 79:0c05e21ae27e 1501 __IO uint32_t CANIF2_MSK2; /*!< Message interface 1 mask 2 */
emilmont 79:0c05e21ae27e 1502 __IO uint32_t CANIF2_ARB1; /*!< Message interface 1 arbitration 1 */
emilmont 79:0c05e21ae27e 1503 __IO uint32_t CANIF2_ARB2; /*!< Message interface 1 arbitration 2 */
emilmont 79:0c05e21ae27e 1504 __IO uint32_t CANIF2_MCTRL; /*!< Message interface 1 message control */
bogdanm 86:04dd9b1680ae 1505 __IO uint32_t CANIF2_DA1; /*!< Message interface 2 data A1 */
bogdanm 86:04dd9b1680ae 1506 __IO uint32_t CANIF2_DA2; /*!< Message interface 2 data A2 */
bogdanm 86:04dd9b1680ae 1507 __IO uint32_t CANIF2_DB1; /*!< Message interface 2 data B1 */
bogdanm 86:04dd9b1680ae 1508 __IO uint32_t CANIF2_DB2; /*!< Message interface 2 data B2 */
bogdanm 86:04dd9b1680ae 1509 __I uint32_t RESERVED2[21];
emilmont 79:0c05e21ae27e 1510 __I uint32_t CANTXREQ1; /*!< Transmission request 1 */
emilmont 79:0c05e21ae27e 1511 __I uint32_t CANTXREQ2; /*!< Transmission request 2 */
emilmont 79:0c05e21ae27e 1512 __I uint32_t RESERVED3[6];
emilmont 79:0c05e21ae27e 1513 __I uint32_t CANND1; /*!< New data 1 */
emilmont 79:0c05e21ae27e 1514 __I uint32_t CANND2; /*!< New data 2 */
emilmont 79:0c05e21ae27e 1515 __I uint32_t RESERVED4[6];
emilmont 79:0c05e21ae27e 1516 __I uint32_t CANIR1; /*!< Interrupt pending 1 */
emilmont 79:0c05e21ae27e 1517 __I uint32_t CANIR2; /*!< Interrupt pending 2 */
emilmont 79:0c05e21ae27e 1518 __I uint32_t RESERVED5[6];
emilmont 79:0c05e21ae27e 1519 __I uint32_t CANMSGV1; /*!< Message valid 1 */
emilmont 79:0c05e21ae27e 1520 __I uint32_t CANMSGV2; /*!< Message valid 2 */
emilmont 79:0c05e21ae27e 1521 __I uint32_t RESERVED6[6];
emilmont 79:0c05e21ae27e 1522 __IO uint32_t CANCLKDIV; /*!< Can clock divider register */
emilmont 79:0c05e21ae27e 1523 } LPC_C_CAN0_Type;
emilmont 79:0c05e21ae27e 1524
emilmont 79:0c05e21ae27e 1525
emilmont 79:0c05e21ae27e 1526 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1527 /* ================ IOCON ================ */
emilmont 79:0c05e21ae27e 1528 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1529
emilmont 79:0c05e21ae27e 1530
emilmont 79:0c05e21ae27e 1531 /**
emilmont 79:0c05e21ae27e 1532 * @brief I/O pin configuration (IOCON) (IOCON)
emilmont 79:0c05e21ae27e 1533 */
emilmont 79:0c05e21ae27e 1534
emilmont 79:0c05e21ae27e 1535 typedef struct { /*!< IOCON Structure */
emilmont 79:0c05e21ae27e 1536 __IO uint32_t PIO0_0; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1537 __IO uint32_t PIO0_1; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1538 __IO uint32_t PIO0_2; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1539 __IO uint32_t PIO0_3; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1540 __IO uint32_t PIO0_4; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1541 __IO uint32_t PIO0_5; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1542 __IO uint32_t PIO0_6; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1543 __IO uint32_t PIO0_7; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1544 __IO uint32_t PIO0_8; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1545 __IO uint32_t PIO0_9; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1546 __IO uint32_t PIO0_10; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1547 __IO uint32_t PIO0_11; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1548 __IO uint32_t PIO0_12; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1549 __IO uint32_t PIO0_13; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1550 __IO uint32_t PIO0_14; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1551 __IO uint32_t PIO0_15; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1552 __IO uint32_t PIO0_16; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1553 __IO uint32_t PIO0_17; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1554 __IO uint32_t PIO0_18; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1555 __IO uint32_t PIO0_19; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1556 __IO uint32_t PIO0_20; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1557 __IO uint32_t PIO0_21; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
emilmont 79:0c05e21ae27e 1558 __IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
emilmont 79:0c05e21ae27e 1559 the I2C-bus SCL function. */
emilmont 79:0c05e21ae27e 1560 __IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
emilmont 79:0c05e21ae27e 1561 the I2C-bus SCL function. */
emilmont 79:0c05e21ae27e 1562 __IO uint32_t PIO0_24; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
emilmont 79:0c05e21ae27e 1563 __IO uint32_t PIO0_25; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
emilmont 79:0c05e21ae27e 1564 __IO uint32_t PIO0_26; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
emilmont 79:0c05e21ae27e 1565 __IO uint32_t PIO0_27; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
emilmont 79:0c05e21ae27e 1566 __IO uint32_t PIO0_28; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
emilmont 79:0c05e21ae27e 1567 __IO uint32_t PIO0_29; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
emilmont 79:0c05e21ae27e 1568 __IO uint32_t PIO0_30; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
emilmont 79:0c05e21ae27e 1569 __IO uint32_t PIO0_31; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
emilmont 79:0c05e21ae27e 1570 __IO uint32_t PIO1_0; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1571 __IO uint32_t PIO1_1; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1572 __IO uint32_t PIO1_2; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1573 __IO uint32_t PIO1_3; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1574 __IO uint32_t PIO1_4; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1575 __IO uint32_t PIO1_5; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1576 __IO uint32_t PIO1_6; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1577 __IO uint32_t PIO1_7; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1578 __IO uint32_t PIO1_8; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1579 __IO uint32_t PIO1_9; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1580 __IO uint32_t PIO1_10; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1581 __IO uint32_t PIO1_11; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1582 __IO uint32_t PIO1_12; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1583 __IO uint32_t PIO1_13; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1584 __IO uint32_t PIO1_14; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1585 __IO uint32_t PIO1_15; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1586 __IO uint32_t PIO1_16; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1587 __IO uint32_t PIO1_17; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1588 __IO uint32_t PIO1_18; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1589 __IO uint32_t PIO1_19; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1590 __IO uint32_t PIO1_20; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1591 __IO uint32_t PIO1_21; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1592 __IO uint32_t PIO1_22; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1593 __IO uint32_t PIO1_23; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1594 __IO uint32_t PIO1_24; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1595 __IO uint32_t PIO1_25; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1596 __IO uint32_t PIO1_26; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1597 __IO uint32_t PIO1_27; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1598 __IO uint32_t PIO1_28; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1599 __IO uint32_t PIO1_29; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1600 __IO uint32_t PIO1_30; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1601 __IO uint32_t PIO1_31; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
emilmont 79:0c05e21ae27e 1602 __IO uint32_t PIO2_0; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1603 __IO uint32_t PIO2_1; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1604 __IO uint32_t PIO2_2; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1605 __IO uint32_t PIO2_3; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1606 __IO uint32_t PIO2_4; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1607 __IO uint32_t PIO2_5; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1608 __IO uint32_t PIO2_6; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1609 __IO uint32_t PIO2_7; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1610 __IO uint32_t PIO2_8; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1611 __IO uint32_t PIO2_9; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1612 __IO uint32_t PIO2_10; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1613 __IO uint32_t PIO2_11; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
emilmont 79:0c05e21ae27e 1614 } LPC_IOCON_Type;
emilmont 79:0c05e21ae27e 1615
emilmont 79:0c05e21ae27e 1616
emilmont 79:0c05e21ae27e 1617 /* -------------------- End of section using anonymous unions ------------------- */
emilmont 79:0c05e21ae27e 1618 #if defined(__CC_ARM)
emilmont 79:0c05e21ae27e 1619 #pragma pop
emilmont 79:0c05e21ae27e 1620 #elif defined(__ICCARM__)
emilmont 79:0c05e21ae27e 1621 /* leave anonymous unions enabled */
emilmont 79:0c05e21ae27e 1622 #elif defined(__GNUC__)
emilmont 79:0c05e21ae27e 1623 /* anonymous unions are enabled by default */
emilmont 79:0c05e21ae27e 1624 #elif defined(__TMS470__)
emilmont 79:0c05e21ae27e 1625 /* anonymous unions are enabled by default */
emilmont 79:0c05e21ae27e 1626 #elif defined(__TASKING__)
emilmont 79:0c05e21ae27e 1627 #pragma warning restore
emilmont 79:0c05e21ae27e 1628 #else
emilmont 79:0c05e21ae27e 1629 #warning Not supported compiler type
emilmont 79:0c05e21ae27e 1630 #endif
emilmont 79:0c05e21ae27e 1631
emilmont 79:0c05e21ae27e 1632
emilmont 79:0c05e21ae27e 1633
emilmont 79:0c05e21ae27e 1634
emilmont 79:0c05e21ae27e 1635 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1636 /* ================ Peripheral memory map ================ */
emilmont 79:0c05e21ae27e 1637 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1638
emilmont 79:0c05e21ae27e 1639 #define LPC_GPIO_PORT_BASE 0x1C000000UL
emilmont 79:0c05e21ae27e 1640 #define LPC_DMA_BASE 0x1C004000UL
emilmont 79:0c05e21ae27e 1641 #define LPC_USB_BASE 0x1C00C000UL
emilmont 79:0c05e21ae27e 1642 #define LPC_CRC_BASE 0x1C010000UL
emilmont 79:0c05e21ae27e 1643 #define LPC_SCT0_BASE 0x1C018000UL
emilmont 79:0c05e21ae27e 1644 #define LPC_SCT1_BASE 0x1C01C000UL
emilmont 79:0c05e21ae27e 1645 #define LPC_SCT2_BASE 0x1C020000UL
emilmont 79:0c05e21ae27e 1646 #define LPC_SCT3_BASE 0x1C024000UL
emilmont 79:0c05e21ae27e 1647 #define LPC_ADC0_BASE 0x40000000UL
emilmont 79:0c05e21ae27e 1648 #define LPC_DAC_BASE 0x40004000UL
emilmont 79:0c05e21ae27e 1649 #define LPC_ACMP_BASE 0x40008000UL
emilmont 79:0c05e21ae27e 1650 #define LPC_INMUX_BASE 0x40014000UL
emilmont 79:0c05e21ae27e 1651 #define LPC_RTC_BASE 0x40028000UL
emilmont 79:0c05e21ae27e 1652 #define LPC_WWDT_BASE 0x4002C000UL
emilmont 79:0c05e21ae27e 1653 #define LPC_SWM_BASE 0x40038000UL
emilmont 79:0c05e21ae27e 1654 #define LPC_PMU_BASE 0x4003C000UL
emilmont 79:0c05e21ae27e 1655 #define LPC_USART0_BASE 0x40040000UL
emilmont 79:0c05e21ae27e 1656 #define LPC_USART1_BASE 0x40044000UL
emilmont 79:0c05e21ae27e 1657 #define LPC_SPI0_BASE 0x40048000UL
emilmont 79:0c05e21ae27e 1658 #define LPC_SPI1_BASE 0x4004C000UL
emilmont 79:0c05e21ae27e 1659 #define LPC_I2C0_BASE 0x40050000UL
emilmont 79:0c05e21ae27e 1660 #define LPC_QEI_BASE 0x40058000UL
emilmont 79:0c05e21ae27e 1661 #define LPC_SYSCON_BASE 0x40074000UL
emilmont 79:0c05e21ae27e 1662 #define LPC_ADC1_BASE 0x40080000UL
emilmont 79:0c05e21ae27e 1663 #define LPC_MRT_BASE 0x400A0000UL
emilmont 79:0c05e21ae27e 1664 #define LPC_PINT_BASE 0x400A4000UL
emilmont 79:0c05e21ae27e 1665 #define LPC_GINT0_BASE 0x400A8000UL
emilmont 79:0c05e21ae27e 1666 #define LPC_GINT1_BASE 0x400AC000UL
emilmont 79:0c05e21ae27e 1667 #define LPC_RIT_BASE 0x400B4000UL
emilmont 79:0c05e21ae27e 1668 #define LPC_SCTIPU_BASE 0x400B8000UL
emilmont 79:0c05e21ae27e 1669 #define LPC_FLASHCTRL_BASE 0x400BC000UL
emilmont 79:0c05e21ae27e 1670 #define LPC_USART2_BASE 0x400C0000UL
emilmont 79:0c05e21ae27e 1671 #define LPC_C_CAN0_BASE 0x400F0000UL
emilmont 79:0c05e21ae27e 1672 #define LPC_IOCON_BASE 0x400F8000UL
emilmont 79:0c05e21ae27e 1673
emilmont 79:0c05e21ae27e 1674
emilmont 79:0c05e21ae27e 1675 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1676 /* ================ Peripheral declaration ================ */
emilmont 79:0c05e21ae27e 1677 /* ================================================================================ */
emilmont 79:0c05e21ae27e 1678
emilmont 79:0c05e21ae27e 1679 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
emilmont 79:0c05e21ae27e 1680 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
emilmont 79:0c05e21ae27e 1681 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
emilmont 79:0c05e21ae27e 1682 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
emilmont 79:0c05e21ae27e 1683 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
emilmont 79:0c05e21ae27e 1684 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
emilmont 79:0c05e21ae27e 1685 #define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
emilmont 79:0c05e21ae27e 1686 #define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
emilmont 79:0c05e21ae27e 1687 #define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
emilmont 79:0c05e21ae27e 1688 #define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
emilmont 79:0c05e21ae27e 1689 #define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
emilmont 79:0c05e21ae27e 1690 #define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
emilmont 79:0c05e21ae27e 1691 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
emilmont 79:0c05e21ae27e 1692 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
emilmont 79:0c05e21ae27e 1693 #define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
emilmont 79:0c05e21ae27e 1694 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
emilmont 79:0c05e21ae27e 1695 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
emilmont 79:0c05e21ae27e 1696 #define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
emilmont 79:0c05e21ae27e 1697 #define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
emilmont 79:0c05e21ae27e 1698 #define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
emilmont 79:0c05e21ae27e 1699 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
emilmont 79:0c05e21ae27e 1700 #define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
emilmont 79:0c05e21ae27e 1701 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
emilmont 79:0c05e21ae27e 1702 #define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
emilmont 79:0c05e21ae27e 1703 #define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
emilmont 79:0c05e21ae27e 1704 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
emilmont 79:0c05e21ae27e 1705 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
emilmont 79:0c05e21ae27e 1706 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
emilmont 79:0c05e21ae27e 1707 #define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
emilmont 79:0c05e21ae27e 1708 #define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
emilmont 79:0c05e21ae27e 1709 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
emilmont 79:0c05e21ae27e 1710 #define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
emilmont 79:0c05e21ae27e 1711 #define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
emilmont 79:0c05e21ae27e 1712 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
emilmont 79:0c05e21ae27e 1713
emilmont 79:0c05e21ae27e 1714
emilmont 79:0c05e21ae27e 1715 /** @} */ /* End of group Device_Peripheral_Registers */
emilmont 79:0c05e21ae27e 1716 /** @} */ /* End of group LPC15xx */
emilmont 79:0c05e21ae27e 1717 /** @} */ /* End of group (null) */
emilmont 79:0c05e21ae27e 1718
emilmont 79:0c05e21ae27e 1719 #ifdef __cplusplus
emilmont 79:0c05e21ae27e 1720 }
emilmont 79:0c05e21ae27e 1721 #endif
emilmont 79:0c05e21ae27e 1722
emilmont 79:0c05e21ae27e 1723
emilmont 79:0c05e21ae27e 1724 #endif /* LPC15XX_H */
emilmont 79:0c05e21ae27e 1725