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TARGET_ARM_MPS2_M7/TOOLCHAIN_ARM_STD/MPS2.sct

Committer:
<>
Date:
2017-01-16
Revision:
134:ad3be0349dc5
Parent:
116:c0f6e94411f5

File content as of revision 134:ad3be0349dc5:

;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2016 ARM Limited
;* All rights reserved.
;* 
;* Redistribution and use in source and binary forms, with or without 
;* modification, are permitted provided that the following conditions are met:
;* 
;* 1. Redistributions of source code must retain the above copyright notice, 
;* this list of conditions and the following disclaimer.
;* 
;* 2. Redistributions in binary form must reproduce the above copyright notice, 
;* this list of conditions and the following disclaimer in the documentation 
;* and/or other materials provided with the distribution.
;* 
;* 3. Neither the name of the copyright holder nor the names of its contributors 
;* may be used to endorse or promote products derived from this software without 
;* specific prior written permission.
;* 
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
;* POSSIBILITY OF SUCH DAMAGE. 
;*
; *************************************************************
; *** Scatter-Loading Description File                      ***
; *************************************************************

LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
  ER_IROM1 0x00000000 0x00400000  {  ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
  RW_IRAM1 (0x20000000+0x100) (0x400000-0x100)  {  ; RW data
   .ANY (+RW +ZI)
  }
}