mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_IOTSS_BEID/core_cm7.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:: Kojto
Date:: Thu Jul 07 14:34:11 2016 +0100
Revision:: 122:f9eeca106725
Child:: 128:9bcdf88f62b0

Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/************************************************************************//
Kojto	122:f9eeca106725	2	* @file core_cm7.h
Kojto	122:f9eeca106725	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Kojto	122:f9eeca106725	4	* @version V4.10
Kojto	122:f9eeca106725	5	* @date 18. March 2015
Kojto	122:f9eeca106725	6	*
Kojto	122:f9eeca106725	7	* @note
Kojto	122:f9eeca106725	8	*
Kojto	122:f9eeca106725	9	******************************************************************************/
Kojto	122:f9eeca106725	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto	122:f9eeca106725	11
Kojto	122:f9eeca106725	12	All rights reserved.
Kojto	122:f9eeca106725	13	Redistribution and use in source and binary forms, with or without
Kojto	122:f9eeca106725	14	modification, are permitted provided that the following conditions are met:
Kojto	122:f9eeca106725	15	- Redistributions of source code must retain the above copyright
Kojto	122:f9eeca106725	16	notice, this list of conditions and the following disclaimer.
Kojto	122:f9eeca106725	17	- Redistributions in binary form must reproduce the above copyright
Kojto	122:f9eeca106725	18	notice, this list of conditions and the following disclaimer in the
Kojto	122:f9eeca106725	19	documentation and/or other materials provided with the distribution.
Kojto	122:f9eeca106725	20	- Neither the name of ARM nor the names of its contributors may be used
Kojto	122:f9eeca106725	21	to endorse or promote products derived from this software without
Kojto	122:f9eeca106725	22	specific prior written permission.
Kojto	122:f9eeca106725	23	*
Kojto	122:f9eeca106725	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	122:f9eeca106725	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	122:f9eeca106725	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto	122:f9eeca106725	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto	122:f9eeca106725	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto	122:f9eeca106725	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto	122:f9eeca106725	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto	122:f9eeca106725	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto	122:f9eeca106725	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto	122:f9eeca106725	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto	122:f9eeca106725	34	POSSIBILITY OF SUCH DAMAGE.
Kojto	122:f9eeca106725	35	---------------------------------------------------------------------------*/
Kojto	122:f9eeca106725	36
Kojto	122:f9eeca106725	37
Kojto	122:f9eeca106725	38	#if defined ( __ICCARM__ )
Kojto	122:f9eeca106725	39	#pragma system_include /* treat file as system include file for MISRA check */
Kojto	122:f9eeca106725	40	#endif
Kojto	122:f9eeca106725	41
Kojto	122:f9eeca106725	42	#ifndef __CORE_CM7_H_GENERIC
Kojto	122:f9eeca106725	43	#define __CORE_CM7_H_GENERIC
Kojto	122:f9eeca106725	44
Kojto	122:f9eeca106725	45	#ifdef __cplusplus
Kojto	122:f9eeca106725	46	extern "C" {
Kojto	122:f9eeca106725	47	#endif
Kojto	122:f9eeca106725	48
Kojto	122:f9eeca106725	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto	122:f9eeca106725	50	CMSIS violates the following MISRA-C:2004 rules:
Kojto	122:f9eeca106725	51
Kojto	122:f9eeca106725	52	\li Required Rule 8.5, object/function definition in header file.<br>
Kojto	122:f9eeca106725	53	Function definitions in header files are used to allow 'inlining'.
Kojto	122:f9eeca106725	54
Kojto	122:f9eeca106725	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto	122:f9eeca106725	56	Unions are used for effective representation of core registers.
Kojto	122:f9eeca106725	57
Kojto	122:f9eeca106725	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto	122:f9eeca106725	59	Function-like macros are used to allow more efficient code.
Kojto	122:f9eeca106725	60	*/
Kojto	122:f9eeca106725	61
Kojto	122:f9eeca106725	62
Kojto	122:f9eeca106725	63	/*******************************************************************************
Kojto	122:f9eeca106725	64	* CMSIS definitions
Kojto	122:f9eeca106725	65	******************************************************************************/
Kojto	122:f9eeca106725	66	/** \ingroup Cortex_M7
Kojto	122:f9eeca106725	67	@{
Kojto	122:f9eeca106725	68	*/
Kojto	122:f9eeca106725	69
Kojto	122:f9eeca106725	70	/* CMSIS CM7 definitions */
Kojto	122:f9eeca106725	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
Kojto	122:f9eeca106725	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
Kojto	122:f9eeca106725	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
Kojto	122:f9eeca106725	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Kojto	122:f9eeca106725	75
Kojto	122:f9eeca106725	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
Kojto	122:f9eeca106725	77
Kojto	122:f9eeca106725	78
Kojto	122:f9eeca106725	79	#if defined ( __CC_ARM )
Kojto	122:f9eeca106725	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Kojto	122:f9eeca106725	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Kojto	122:f9eeca106725	82	#define __STATIC_INLINE static __inline
Kojto	122:f9eeca106725	83
Kojto	122:f9eeca106725	84	#elif defined ( __GNUC__ )
Kojto	122:f9eeca106725	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	122:f9eeca106725	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	122:f9eeca106725	87	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	88
Kojto	122:f9eeca106725	89	#elif defined ( __ICCARM__ )
Kojto	122:f9eeca106725	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
Kojto	122:f9eeca106725	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Kojto	122:f9eeca106725	92	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	93
Kojto	122:f9eeca106725	94	#elif defined ( __TMS470__ )
Kojto	122:f9eeca106725	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Kojto	122:f9eeca106725	96	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	97
Kojto	122:f9eeca106725	98	#elif defined ( __TASKING__ )
Kojto	122:f9eeca106725	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Kojto	122:f9eeca106725	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Kojto	122:f9eeca106725	101	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	102
Kojto	122:f9eeca106725	103	#elif defined ( __CSMC__ )
Kojto	122:f9eeca106725	104	#define __packed
Kojto	122:f9eeca106725	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
Kojto	122:f9eeca106725	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
Kojto	122:f9eeca106725	107	#define __STATIC_INLINE static inline
Kojto	122:f9eeca106725	108
Kojto	122:f9eeca106725	109	#endif
Kojto	122:f9eeca106725	110
Kojto	122:f9eeca106725	111	/** __FPU_USED indicates whether an FPU is used or not.
Kojto	122:f9eeca106725	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Kojto	122:f9eeca106725	113	*/
Kojto	122:f9eeca106725	114	#if defined ( __CC_ARM )
Kojto	122:f9eeca106725	115	#if defined __TARGET_FPU_VFP
Kojto	122:f9eeca106725	116	#if (__FPU_PRESENT == 1)
Kojto	122:f9eeca106725	117	#define __FPU_USED 1
Kojto	122:f9eeca106725	118	#else
Kojto	122:f9eeca106725	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	120	#define __FPU_USED 0
Kojto	122:f9eeca106725	121	#endif
Kojto	122:f9eeca106725	122	#else
Kojto	122:f9eeca106725	123	#define __FPU_USED 0
Kojto	122:f9eeca106725	124	#endif
Kojto	122:f9eeca106725	125
Kojto	122:f9eeca106725	126	#elif defined ( __GNUC__ )
Kojto	122:f9eeca106725	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	122:f9eeca106725	128	#if (__FPU_PRESENT == 1)
Kojto	122:f9eeca106725	129	#define __FPU_USED 1
Kojto	122:f9eeca106725	130	#else
Kojto	122:f9eeca106725	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	132	#define __FPU_USED 0
Kojto	122:f9eeca106725	133	#endif
Kojto	122:f9eeca106725	134	#else
Kojto	122:f9eeca106725	135	#define __FPU_USED 0
Kojto	122:f9eeca106725	136	#endif
Kojto	122:f9eeca106725	137
Kojto	122:f9eeca106725	138	#elif defined ( __ICCARM__ )
Kojto	122:f9eeca106725	139	#if defined __ARMVFP__
Kojto	122:f9eeca106725	140	#if (__FPU_PRESENT == 1)
Kojto	122:f9eeca106725	141	#define __FPU_USED 1
Kojto	122:f9eeca106725	142	#else
Kojto	122:f9eeca106725	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	144	#define __FPU_USED 0
Kojto	122:f9eeca106725	145	#endif
Kojto	122:f9eeca106725	146	#else
Kojto	122:f9eeca106725	147	#define __FPU_USED 0
Kojto	122:f9eeca106725	148	#endif
Kojto	122:f9eeca106725	149
Kojto	122:f9eeca106725	150	#elif defined ( __TMS470__ )
Kojto	122:f9eeca106725	151	#if defined __TI_VFP_SUPPORT__
Kojto	122:f9eeca106725	152	#if (__FPU_PRESENT == 1)
Kojto	122:f9eeca106725	153	#define __FPU_USED 1
Kojto	122:f9eeca106725	154	#else
Kojto	122:f9eeca106725	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	156	#define __FPU_USED 0
Kojto	122:f9eeca106725	157	#endif
Kojto	122:f9eeca106725	158	#else
Kojto	122:f9eeca106725	159	#define __FPU_USED 0
Kojto	122:f9eeca106725	160	#endif
Kojto	122:f9eeca106725	161
Kojto	122:f9eeca106725	162	#elif defined ( __TASKING__ )
Kojto	122:f9eeca106725	163	#if defined __FPU_VFP__
Kojto	122:f9eeca106725	164	#if (__FPU_PRESENT == 1)
Kojto	122:f9eeca106725	165	#define __FPU_USED 1
Kojto	122:f9eeca106725	166	#else
Kojto	122:f9eeca106725	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	168	#define __FPU_USED 0
Kojto	122:f9eeca106725	169	#endif
Kojto	122:f9eeca106725	170	#else
Kojto	122:f9eeca106725	171	#define __FPU_USED 0
Kojto	122:f9eeca106725	172	#endif
Kojto	122:f9eeca106725	173
Kojto	122:f9eeca106725	174	#elif defined ( __CSMC__ ) /* Cosmic */
Kojto	122:f9eeca106725	175	#if ( __CSMC__ & 0x400) // FPU present for parser
Kojto	122:f9eeca106725	176	#if (__FPU_PRESENT == 1)
Kojto	122:f9eeca106725	177	#define __FPU_USED 1
Kojto	122:f9eeca106725	178	#else
Kojto	122:f9eeca106725	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	122:f9eeca106725	180	#define __FPU_USED 0
Kojto	122:f9eeca106725	181	#endif
Kojto	122:f9eeca106725	182	#else
Kojto	122:f9eeca106725	183	#define __FPU_USED 0
Kojto	122:f9eeca106725	184	#endif
Kojto	122:f9eeca106725	185	#endif
Kojto	122:f9eeca106725	186
Kojto	122:f9eeca106725	187	#include <stdint.h> /* standard types definitions */
Kojto	122:f9eeca106725	188	#include <core_cmInstr.h> /* Core Instruction Access */
Kojto	122:f9eeca106725	189	#include <core_cmFunc.h> /* Core Function Access */
Kojto	122:f9eeca106725	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Kojto	122:f9eeca106725	191
Kojto	122:f9eeca106725	192	#ifdef __cplusplus
Kojto	122:f9eeca106725	193	}
Kojto	122:f9eeca106725	194	#endif
Kojto	122:f9eeca106725	195
Kojto	122:f9eeca106725	196	#endif /* __CORE_CM7_H_GENERIC */
Kojto	122:f9eeca106725	197
Kojto	122:f9eeca106725	198	#ifndef __CMSIS_GENERIC
Kojto	122:f9eeca106725	199
Kojto	122:f9eeca106725	200	#ifndef __CORE_CM7_H_DEPENDANT
Kojto	122:f9eeca106725	201	#define __CORE_CM7_H_DEPENDANT
Kojto	122:f9eeca106725	202
Kojto	122:f9eeca106725	203	#ifdef __cplusplus
Kojto	122:f9eeca106725	204	extern "C" {
Kojto	122:f9eeca106725	205	#endif
Kojto	122:f9eeca106725	206
Kojto	122:f9eeca106725	207	/* check device defines and use defaults */
Kojto	122:f9eeca106725	208	#if defined __CHECK_DEVICE_DEFINES
Kojto	122:f9eeca106725	209	#ifndef __CM7_REV
Kojto	122:f9eeca106725	210	#define __CM7_REV 0x0000
Kojto	122:f9eeca106725	211	#warning "__CM7_REV not defined in device header file; using default!"
Kojto	122:f9eeca106725	212	#endif
Kojto	122:f9eeca106725	213
Kojto	122:f9eeca106725	214	#ifndef __FPU_PRESENT
Kojto	122:f9eeca106725	215	#define __FPU_PRESENT 0
Kojto	122:f9eeca106725	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
Kojto	122:f9eeca106725	217	#endif
Kojto	122:f9eeca106725	218
Kojto	122:f9eeca106725	219	#ifndef __MPU_PRESENT
Kojto	122:f9eeca106725	220	#define __MPU_PRESENT 0
Kojto	122:f9eeca106725	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto	122:f9eeca106725	222	#endif
Kojto	122:f9eeca106725	223
Kojto	122:f9eeca106725	224	#ifndef __ICACHE_PRESENT
Kojto	122:f9eeca106725	225	#define __ICACHE_PRESENT 0
Kojto	122:f9eeca106725	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
Kojto	122:f9eeca106725	227	#endif
Kojto	122:f9eeca106725	228
Kojto	122:f9eeca106725	229	#ifndef __DCACHE_PRESENT
Kojto	122:f9eeca106725	230	#define __DCACHE_PRESENT 0
Kojto	122:f9eeca106725	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
Kojto	122:f9eeca106725	232	#endif
Kojto	122:f9eeca106725	233
Kojto	122:f9eeca106725	234	#ifndef __DTCM_PRESENT
Kojto	122:f9eeca106725	235	#define __DTCM_PRESENT 0
Kojto	122:f9eeca106725	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
Kojto	122:f9eeca106725	237	#endif
Kojto	122:f9eeca106725	238
Kojto	122:f9eeca106725	239	#ifndef __NVIC_PRIO_BITS
Kojto	122:f9eeca106725	240	#define __NVIC_PRIO_BITS 3
Kojto	122:f9eeca106725	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto	122:f9eeca106725	242	#endif
Kojto	122:f9eeca106725	243
Kojto	122:f9eeca106725	244	#ifndef __Vendor_SysTickConfig
Kojto	122:f9eeca106725	245	#define __Vendor_SysTickConfig 0
Kojto	122:f9eeca106725	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto	122:f9eeca106725	247	#endif
Kojto	122:f9eeca106725	248	#endif
Kojto	122:f9eeca106725	249
Kojto	122:f9eeca106725	250	/* IO definitions (access restrictions to peripheral registers) */
Kojto	122:f9eeca106725	251	/**
Kojto	122:f9eeca106725	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto	122:f9eeca106725	253
Kojto	122:f9eeca106725	254	<strong>IO Type Qualifiers</strong> are used
Kojto	122:f9eeca106725	255	\li to specify the access to peripheral variables.
Kojto	122:f9eeca106725	256	\li for automatic generation of peripheral register debug information.
Kojto	122:f9eeca106725	257	*/
Kojto	122:f9eeca106725	258	#ifdef __cplusplus
Kojto	122:f9eeca106725	259	#define __I volatile /!< Defines 'read only' permissions /
Kojto	122:f9eeca106725	260	#else
Kojto	122:f9eeca106725	261	#define __I volatile const /!< Defines 'read only' permissions /
Kojto	122:f9eeca106725	262	#endif
Kojto	122:f9eeca106725	263	#define __O volatile /!< Defines 'write only' permissions /
Kojto	122:f9eeca106725	264	#define __IO volatile /!< Defines 'read / write' permissions /
Kojto	122:f9eeca106725	265
Kojto	122:f9eeca106725	266	/@} end of group Cortex_M7 /
Kojto	122:f9eeca106725	267
Kojto	122:f9eeca106725	268
Kojto	122:f9eeca106725	269
Kojto	122:f9eeca106725	270	/*******************************************************************************
Kojto	122:f9eeca106725	271	* Register Abstraction
Kojto	122:f9eeca106725	272	Core Register contain:
Kojto	122:f9eeca106725	273	- Core Register
Kojto	122:f9eeca106725	274	- Core NVIC Register
Kojto	122:f9eeca106725	275	- Core SCB Register
Kojto	122:f9eeca106725	276	- Core SysTick Register
Kojto	122:f9eeca106725	277	- Core Debug Register
Kojto	122:f9eeca106725	278	- Core MPU Register
Kojto	122:f9eeca106725	279	- Core FPU Register
Kojto	122:f9eeca106725	280	******************************************************************************/
Kojto	122:f9eeca106725	281	/** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto	122:f9eeca106725	282	\brief Type definitions and defines for Cortex-M processor based devices.
Kojto	122:f9eeca106725	283	*/
Kojto	122:f9eeca106725	284
Kojto	122:f9eeca106725	285	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	286	\defgroup CMSIS_CORE Status and Control Registers
Kojto	122:f9eeca106725	287	\brief Core Register type definitions.
Kojto	122:f9eeca106725	288	@{
Kojto	122:f9eeca106725	289	*/
Kojto	122:f9eeca106725	290
Kojto	122:f9eeca106725	291	/** \brief Union type to access the Application Program Status Register (APSR).
Kojto	122:f9eeca106725	292	*/
Kojto	122:f9eeca106725	293	typedef union
Kojto	122:f9eeca106725	294	{
Kojto	122:f9eeca106725	295	struct
Kojto	122:f9eeca106725	296	{
Kojto	122:f9eeca106725	297	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Kojto	122:f9eeca106725	298	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	122:f9eeca106725	299	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Kojto	122:f9eeca106725	300	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	122:f9eeca106725	301	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	122:f9eeca106725	302	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	122:f9eeca106725	303	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	122:f9eeca106725	304	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	122:f9eeca106725	305	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	306	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	307	} APSR_Type;
Kojto	122:f9eeca106725	308
Kojto	122:f9eeca106725	309	/* APSR Register Definitions */
Kojto	122:f9eeca106725	310	#define APSR_N_Pos 31 /!< APSR: N Position /
Kojto	122:f9eeca106725	311	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
Kojto	122:f9eeca106725	312
Kojto	122:f9eeca106725	313	#define APSR_Z_Pos 30 /!< APSR: Z Position /
Kojto	122:f9eeca106725	314	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
Kojto	122:f9eeca106725	315
Kojto	122:f9eeca106725	316	#define APSR_C_Pos 29 /!< APSR: C Position /
Kojto	122:f9eeca106725	317	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
Kojto	122:f9eeca106725	318
Kojto	122:f9eeca106725	319	#define APSR_V_Pos 28 /!< APSR: V Position /
Kojto	122:f9eeca106725	320	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
Kojto	122:f9eeca106725	321
Kojto	122:f9eeca106725	322	#define APSR_Q_Pos 27 /!< APSR: Q Position /
Kojto	122:f9eeca106725	323	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
Kojto	122:f9eeca106725	324
Kojto	122:f9eeca106725	325	#define APSR_GE_Pos 16 /!< APSR: GE Position /
Kojto	122:f9eeca106725	326	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
Kojto	122:f9eeca106725	327
Kojto	122:f9eeca106725	328
Kojto	122:f9eeca106725	329	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto	122:f9eeca106725	330	*/
Kojto	122:f9eeca106725	331	typedef union
Kojto	122:f9eeca106725	332	{
Kojto	122:f9eeca106725	333	struct
Kojto	122:f9eeca106725	334	{
Kojto	122:f9eeca106725	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	122:f9eeca106725	336	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Kojto	122:f9eeca106725	337	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	338	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	339	} IPSR_Type;
Kojto	122:f9eeca106725	340
Kojto	122:f9eeca106725	341	/* IPSR Register Definitions */
Kojto	122:f9eeca106725	342	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
Kojto	122:f9eeca106725	343	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
Kojto	122:f9eeca106725	344
Kojto	122:f9eeca106725	345
Kojto	122:f9eeca106725	346	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto	122:f9eeca106725	347	*/
Kojto	122:f9eeca106725	348	typedef union
Kojto	122:f9eeca106725	349	{
Kojto	122:f9eeca106725	350	struct
Kojto	122:f9eeca106725	351	{
Kojto	122:f9eeca106725	352	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	122:f9eeca106725	353	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Kojto	122:f9eeca106725	354	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	122:f9eeca106725	355	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Kojto	122:f9eeca106725	356	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Kojto	122:f9eeca106725	357	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Kojto	122:f9eeca106725	358	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	122:f9eeca106725	359	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	122:f9eeca106725	360	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	122:f9eeca106725	361	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	122:f9eeca106725	362	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	122:f9eeca106725	363	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	364	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	365	} xPSR_Type;
Kojto	122:f9eeca106725	366
Kojto	122:f9eeca106725	367	/* xPSR Register Definitions */
Kojto	122:f9eeca106725	368	#define xPSR_N_Pos 31 /!< xPSR: N Position /
Kojto	122:f9eeca106725	369	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
Kojto	122:f9eeca106725	370
Kojto	122:f9eeca106725	371	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
Kojto	122:f9eeca106725	372	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
Kojto	122:f9eeca106725	373
Kojto	122:f9eeca106725	374	#define xPSR_C_Pos 29 /!< xPSR: C Position /
Kojto	122:f9eeca106725	375	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
Kojto	122:f9eeca106725	376
Kojto	122:f9eeca106725	377	#define xPSR_V_Pos 28 /!< xPSR: V Position /
Kojto	122:f9eeca106725	378	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
Kojto	122:f9eeca106725	379
Kojto	122:f9eeca106725	380	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
Kojto	122:f9eeca106725	381	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
Kojto	122:f9eeca106725	382
Kojto	122:f9eeca106725	383	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
Kojto	122:f9eeca106725	384	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
Kojto	122:f9eeca106725	385
Kojto	122:f9eeca106725	386	#define xPSR_T_Pos 24 /!< xPSR: T Position /
Kojto	122:f9eeca106725	387	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
Kojto	122:f9eeca106725	388
Kojto	122:f9eeca106725	389	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
Kojto	122:f9eeca106725	390	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
Kojto	122:f9eeca106725	391
Kojto	122:f9eeca106725	392	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
Kojto	122:f9eeca106725	393	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
Kojto	122:f9eeca106725	394
Kojto	122:f9eeca106725	395
Kojto	122:f9eeca106725	396	/** \brief Union type to access the Control Registers (CONTROL).
Kojto	122:f9eeca106725	397	*/
Kojto	122:f9eeca106725	398	typedef union
Kojto	122:f9eeca106725	399	{
Kojto	122:f9eeca106725	400	struct
Kojto	122:f9eeca106725	401	{
Kojto	122:f9eeca106725	402	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Kojto	122:f9eeca106725	403	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Kojto	122:f9eeca106725	404	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Kojto	122:f9eeca106725	405	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Kojto	122:f9eeca106725	406	} b; /!< Structure used for bit access /
Kojto	122:f9eeca106725	407	uint32_t w; /!< Type used for word access /
Kojto	122:f9eeca106725	408	} CONTROL_Type;
Kojto	122:f9eeca106725	409
Kojto	122:f9eeca106725	410	/* CONTROL Register Definitions */
Kojto	122:f9eeca106725	411	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
Kojto	122:f9eeca106725	412	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
Kojto	122:f9eeca106725	413
Kojto	122:f9eeca106725	414	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
Kojto	122:f9eeca106725	415	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
Kojto	122:f9eeca106725	416
Kojto	122:f9eeca106725	417	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
Kojto	122:f9eeca106725	418	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
Kojto	122:f9eeca106725	419
Kojto	122:f9eeca106725	420	/@} end of group CMSIS_CORE /
Kojto	122:f9eeca106725	421
Kojto	122:f9eeca106725	422
Kojto	122:f9eeca106725	423	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	424	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto	122:f9eeca106725	425	\brief Type definitions for the NVIC Registers
Kojto	122:f9eeca106725	426	@{
Kojto	122:f9eeca106725	427	*/
Kojto	122:f9eeca106725	428
Kojto	122:f9eeca106725	429	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto	122:f9eeca106725	430	*/
Kojto	122:f9eeca106725	431	typedef struct
Kojto	122:f9eeca106725	432	{
Kojto	122:f9eeca106725	433	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Kojto	122:f9eeca106725	434	uint32_t RESERVED0[24];
Kojto	122:f9eeca106725	435	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Kojto	122:f9eeca106725	436	uint32_t RSERVED1[24];
Kojto	122:f9eeca106725	437	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Kojto	122:f9eeca106725	438	uint32_t RESERVED2[24];
Kojto	122:f9eeca106725	439	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Kojto	122:f9eeca106725	440	uint32_t RESERVED3[24];
Kojto	122:f9eeca106725	441	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Kojto	122:f9eeca106725	442	uint32_t RESERVED4[56];
Kojto	122:f9eeca106725	443	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Kojto	122:f9eeca106725	444	uint32_t RESERVED5[644];
Kojto	122:f9eeca106725	445	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Kojto	122:f9eeca106725	446	} NVIC_Type;
Kojto	122:f9eeca106725	447
Kojto	122:f9eeca106725	448	/* Software Triggered Interrupt Register Definitions */
Kojto	122:f9eeca106725	449	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	122:f9eeca106725	450	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
Kojto	122:f9eeca106725	451
Kojto	122:f9eeca106725	452	/@} end of group CMSIS_NVIC /
Kojto	122:f9eeca106725	453
Kojto	122:f9eeca106725	454
Kojto	122:f9eeca106725	455	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	456	\defgroup CMSIS_SCB System Control Block (SCB)
Kojto	122:f9eeca106725	457	\brief Type definitions for the System Control Block Registers
Kojto	122:f9eeca106725	458	@{
Kojto	122:f9eeca106725	459	*/
Kojto	122:f9eeca106725	460
Kojto	122:f9eeca106725	461	/** \brief Structure type to access the System Control Block (SCB).
Kojto	122:f9eeca106725	462	*/
Kojto	122:f9eeca106725	463	typedef struct
Kojto	122:f9eeca106725	464	{
Kojto	122:f9eeca106725	465	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Kojto	122:f9eeca106725	466	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Kojto	122:f9eeca106725	467	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Kojto	122:f9eeca106725	468	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Kojto	122:f9eeca106725	469	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Kojto	122:f9eeca106725	470	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Kojto	122:f9eeca106725	471	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Kojto	122:f9eeca106725	472	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Kojto	122:f9eeca106725	473	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Kojto	122:f9eeca106725	474	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Kojto	122:f9eeca106725	475	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Kojto	122:f9eeca106725	476	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Kojto	122:f9eeca106725	477	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Kojto	122:f9eeca106725	478	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Kojto	122:f9eeca106725	479	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Kojto	122:f9eeca106725	480	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Kojto	122:f9eeca106725	481	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Kojto	122:f9eeca106725	482	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Kojto	122:f9eeca106725	483	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Kojto	122:f9eeca106725	484	uint32_t RESERVED0[1];
Kojto	122:f9eeca106725	485	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
Kojto	122:f9eeca106725	486	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
Kojto	122:f9eeca106725	487	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
Kojto	122:f9eeca106725	488	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
Kojto	122:f9eeca106725	489	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Kojto	122:f9eeca106725	490	uint32_t RESERVED3[93];
Kojto	122:f9eeca106725	491	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
Kojto	122:f9eeca106725	492	uint32_t RESERVED4[15];
Kojto	122:f9eeca106725	493	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
Kojto	122:f9eeca106725	494	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
Kojto	122:f9eeca106725	495	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
Kojto	122:f9eeca106725	496	uint32_t RESERVED5[1];
Kojto	122:f9eeca106725	497	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
Kojto	122:f9eeca106725	498	uint32_t RESERVED6[1];
Kojto	122:f9eeca106725	499	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
Kojto	122:f9eeca106725	500	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
Kojto	122:f9eeca106725	501	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
Kojto	122:f9eeca106725	502	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
Kojto	122:f9eeca106725	503	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
Kojto	122:f9eeca106725	504	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
Kojto	122:f9eeca106725	505	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
Kojto	122:f9eeca106725	506	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
Kojto	122:f9eeca106725	507	uint32_t RESERVED7[6];
Kojto	122:f9eeca106725	508	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
Kojto	122:f9eeca106725	509	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
Kojto	122:f9eeca106725	510	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
Kojto	122:f9eeca106725	511	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
Kojto	122:f9eeca106725	512	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
Kojto	122:f9eeca106725	513	uint32_t RESERVED8[1];
Kojto	122:f9eeca106725	514	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
Kojto	122:f9eeca106725	515	} SCB_Type;
Kojto	122:f9eeca106725	516
Kojto	122:f9eeca106725	517	/* SCB CPUID Register Definitions */
Kojto	122:f9eeca106725	518	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Kojto	122:f9eeca106725	519	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Kojto	122:f9eeca106725	520
Kojto	122:f9eeca106725	521	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Kojto	122:f9eeca106725	522	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Kojto	122:f9eeca106725	523
Kojto	122:f9eeca106725	524	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Kojto	122:f9eeca106725	525	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Kojto	122:f9eeca106725	526
Kojto	122:f9eeca106725	527	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Kojto	122:f9eeca106725	528	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Kojto	122:f9eeca106725	529
Kojto	122:f9eeca106725	530	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	122:f9eeca106725	531	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
Kojto	122:f9eeca106725	532
Kojto	122:f9eeca106725	533	/* SCB Interrupt Control State Register Definitions */
Kojto	122:f9eeca106725	534	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Kojto	122:f9eeca106725	535	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Kojto	122:f9eeca106725	536
Kojto	122:f9eeca106725	537	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Kojto	122:f9eeca106725	538	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Kojto	122:f9eeca106725	539
Kojto	122:f9eeca106725	540	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Kojto	122:f9eeca106725	541	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Kojto	122:f9eeca106725	542
Kojto	122:f9eeca106725	543	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Kojto	122:f9eeca106725	544	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Kojto	122:f9eeca106725	545
Kojto	122:f9eeca106725	546	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Kojto	122:f9eeca106725	547	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Kojto	122:f9eeca106725	548
Kojto	122:f9eeca106725	549	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Kojto	122:f9eeca106725	550	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Kojto	122:f9eeca106725	551
Kojto	122:f9eeca106725	552	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Kojto	122:f9eeca106725	553	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Kojto	122:f9eeca106725	554
Kojto	122:f9eeca106725	555	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Kojto	122:f9eeca106725	556	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Kojto	122:f9eeca106725	557
Kojto	122:f9eeca106725	558	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Kojto	122:f9eeca106725	559	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Kojto	122:f9eeca106725	560
Kojto	122:f9eeca106725	561	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	122:f9eeca106725	562	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
Kojto	122:f9eeca106725	563
Kojto	122:f9eeca106725	564	/* SCB Vector Table Offset Register Definitions */
Kojto	122:f9eeca106725	565	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Kojto	122:f9eeca106725	566	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	122:f9eeca106725	567
Kojto	122:f9eeca106725	568	/* SCB Application Interrupt and Reset Control Register Definitions */
Kojto	122:f9eeca106725	569	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Kojto	122:f9eeca106725	570	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Kojto	122:f9eeca106725	571
Kojto	122:f9eeca106725	572	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Kojto	122:f9eeca106725	573	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Kojto	122:f9eeca106725	574
Kojto	122:f9eeca106725	575	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Kojto	122:f9eeca106725	576	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Kojto	122:f9eeca106725	577
Kojto	122:f9eeca106725	578	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Kojto	122:f9eeca106725	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Kojto	122:f9eeca106725	580
Kojto	122:f9eeca106725	581	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Kojto	122:f9eeca106725	582	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Kojto	122:f9eeca106725	583
Kojto	122:f9eeca106725	584	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Kojto	122:f9eeca106725	585	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Kojto	122:f9eeca106725	586
Kojto	122:f9eeca106725	587	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	122:f9eeca106725	588	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
Kojto	122:f9eeca106725	589
Kojto	122:f9eeca106725	590	/* SCB System Control Register Definitions */
Kojto	122:f9eeca106725	591	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Kojto	122:f9eeca106725	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Kojto	122:f9eeca106725	593
Kojto	122:f9eeca106725	594	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Kojto	122:f9eeca106725	595	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Kojto	122:f9eeca106725	596
Kojto	122:f9eeca106725	597	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Kojto	122:f9eeca106725	598	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Kojto	122:f9eeca106725	599
Kojto	122:f9eeca106725	600	/* SCB Configuration Control Register Definitions */
Kojto	122:f9eeca106725	601	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
Kojto	122:f9eeca106725	602	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
Kojto	122:f9eeca106725	603
Kojto	122:f9eeca106725	604	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
Kojto	122:f9eeca106725	605	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
Kojto	122:f9eeca106725	606
Kojto	122:f9eeca106725	607	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
Kojto	122:f9eeca106725	608	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
Kojto	122:f9eeca106725	609
Kojto	122:f9eeca106725	610	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Kojto	122:f9eeca106725	611	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Kojto	122:f9eeca106725	612
Kojto	122:f9eeca106725	613	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Kojto	122:f9eeca106725	614	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Kojto	122:f9eeca106725	615
Kojto	122:f9eeca106725	616	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Kojto	122:f9eeca106725	617	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Kojto	122:f9eeca106725	618
Kojto	122:f9eeca106725	619	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Kojto	122:f9eeca106725	620	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Kojto	122:f9eeca106725	621
Kojto	122:f9eeca106725	622	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Kojto	122:f9eeca106725	623	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Kojto	122:f9eeca106725	624
Kojto	122:f9eeca106725	625	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	122:f9eeca106725	626	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
Kojto	122:f9eeca106725	627
Kojto	122:f9eeca106725	628	/* SCB System Handler Control and State Register Definitions */
Kojto	122:f9eeca106725	629	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Kojto	122:f9eeca106725	630	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Kojto	122:f9eeca106725	631
Kojto	122:f9eeca106725	632	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Kojto	122:f9eeca106725	633	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Kojto	122:f9eeca106725	634
Kojto	122:f9eeca106725	635	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Kojto	122:f9eeca106725	636	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Kojto	122:f9eeca106725	637
Kojto	122:f9eeca106725	638	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Kojto	122:f9eeca106725	639	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Kojto	122:f9eeca106725	640
Kojto	122:f9eeca106725	641	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Kojto	122:f9eeca106725	642	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Kojto	122:f9eeca106725	643
Kojto	122:f9eeca106725	644	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Kojto	122:f9eeca106725	645	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Kojto	122:f9eeca106725	646
Kojto	122:f9eeca106725	647	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Kojto	122:f9eeca106725	648	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Kojto	122:f9eeca106725	649
Kojto	122:f9eeca106725	650	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Kojto	122:f9eeca106725	651	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Kojto	122:f9eeca106725	652
Kojto	122:f9eeca106725	653	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Kojto	122:f9eeca106725	654	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Kojto	122:f9eeca106725	655
Kojto	122:f9eeca106725	656	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Kojto	122:f9eeca106725	657	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Kojto	122:f9eeca106725	658
Kojto	122:f9eeca106725	659	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Kojto	122:f9eeca106725	660	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Kojto	122:f9eeca106725	661
Kojto	122:f9eeca106725	662	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Kojto	122:f9eeca106725	663	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Kojto	122:f9eeca106725	664
Kojto	122:f9eeca106725	665	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Kojto	122:f9eeca106725	666	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Kojto	122:f9eeca106725	667
Kojto	122:f9eeca106725	668	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	122:f9eeca106725	669	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
Kojto	122:f9eeca106725	670
Kojto	122:f9eeca106725	671	/* SCB Configurable Fault Status Registers Definitions */
Kojto	122:f9eeca106725	672	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Kojto	122:f9eeca106725	673	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Kojto	122:f9eeca106725	674
Kojto	122:f9eeca106725	675	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Kojto	122:f9eeca106725	676	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Kojto	122:f9eeca106725	677
Kojto	122:f9eeca106725	678	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	122:f9eeca106725	679	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Kojto	122:f9eeca106725	680
Kojto	122:f9eeca106725	681	/* SCB Hard Fault Status Registers Definitions */
Kojto	122:f9eeca106725	682	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Kojto	122:f9eeca106725	683	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Kojto	122:f9eeca106725	684
Kojto	122:f9eeca106725	685	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Kojto	122:f9eeca106725	686	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Kojto	122:f9eeca106725	687
Kojto	122:f9eeca106725	688	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Kojto	122:f9eeca106725	689	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Kojto	122:f9eeca106725	690
Kojto	122:f9eeca106725	691	/* SCB Debug Fault Status Register Definitions */
Kojto	122:f9eeca106725	692	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Kojto	122:f9eeca106725	693	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Kojto	122:f9eeca106725	694
Kojto	122:f9eeca106725	695	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Kojto	122:f9eeca106725	696	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Kojto	122:f9eeca106725	697
Kojto	122:f9eeca106725	698	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Kojto	122:f9eeca106725	699	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Kojto	122:f9eeca106725	700
Kojto	122:f9eeca106725	701	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Kojto	122:f9eeca106725	702	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Kojto	122:f9eeca106725	703
Kojto	122:f9eeca106725	704	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	122:f9eeca106725	705	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
Kojto	122:f9eeca106725	706
Kojto	122:f9eeca106725	707	/* Cache Level ID register */
Kojto	122:f9eeca106725	708	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
Kojto	122:f9eeca106725	709	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
Kojto	122:f9eeca106725	710
Kojto	122:f9eeca106725	711	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
Kojto	122:f9eeca106725	712	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
Kojto	122:f9eeca106725	713
Kojto	122:f9eeca106725	714	/* Cache Type register */
Kojto	122:f9eeca106725	715	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
Kojto	122:f9eeca106725	716	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
Kojto	122:f9eeca106725	717
Kojto	122:f9eeca106725	718	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
Kojto	122:f9eeca106725	719	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
Kojto	122:f9eeca106725	720
Kojto	122:f9eeca106725	721	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
Kojto	122:f9eeca106725	722	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
Kojto	122:f9eeca106725	723
Kojto	122:f9eeca106725	724	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
Kojto	122:f9eeca106725	725	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
Kojto	122:f9eeca106725	726
Kojto	122:f9eeca106725	727	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
Kojto	122:f9eeca106725	728	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
Kojto	122:f9eeca106725	729
Kojto	122:f9eeca106725	730	/* Cache Size ID Register */
Kojto	122:f9eeca106725	731	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
Kojto	122:f9eeca106725	732	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
Kojto	122:f9eeca106725	733
Kojto	122:f9eeca106725	734	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
Kojto	122:f9eeca106725	735	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
Kojto	122:f9eeca106725	736
Kojto	122:f9eeca106725	737	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
Kojto	122:f9eeca106725	738	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
Kojto	122:f9eeca106725	739
Kojto	122:f9eeca106725	740	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
Kojto	122:f9eeca106725	741	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
Kojto	122:f9eeca106725	742
Kojto	122:f9eeca106725	743	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
Kojto	122:f9eeca106725	744	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
Kojto	122:f9eeca106725	745
Kojto	122:f9eeca106725	746	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
Kojto	122:f9eeca106725	747	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
Kojto	122:f9eeca106725	748
Kojto	122:f9eeca106725	749	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
Kojto	122:f9eeca106725	750	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
Kojto	122:f9eeca106725	751
Kojto	122:f9eeca106725	752	/* Cache Size Selection Register */
Kojto	122:f9eeca106725	753	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
Kojto	122:f9eeca106725	754	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
Kojto	122:f9eeca106725	755
Kojto	122:f9eeca106725	756	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
Kojto	122:f9eeca106725	757	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
Kojto	122:f9eeca106725	758
Kojto	122:f9eeca106725	759	/* SCB Software Triggered Interrupt Register */
Kojto	122:f9eeca106725	760	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
Kojto	122:f9eeca106725	761	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
Kojto	122:f9eeca106725	762
Kojto	122:f9eeca106725	763	/* Instruction Tightly-Coupled Memory Control Register*/
Kojto	122:f9eeca106725	764	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
Kojto	122:f9eeca106725	765	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
Kojto	122:f9eeca106725	766
Kojto	122:f9eeca106725	767	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
Kojto	122:f9eeca106725	768	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
Kojto	122:f9eeca106725	769
Kojto	122:f9eeca106725	770	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
Kojto	122:f9eeca106725	771	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
Kojto	122:f9eeca106725	772
Kojto	122:f9eeca106725	773	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
Kojto	122:f9eeca106725	774	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
Kojto	122:f9eeca106725	775
Kojto	122:f9eeca106725	776	/* Data Tightly-Coupled Memory Control Registers */
Kojto	122:f9eeca106725	777	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
Kojto	122:f9eeca106725	778	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
Kojto	122:f9eeca106725	779
Kojto	122:f9eeca106725	780	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
Kojto	122:f9eeca106725	781	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
Kojto	122:f9eeca106725	782
Kojto	122:f9eeca106725	783	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
Kojto	122:f9eeca106725	784	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
Kojto	122:f9eeca106725	785
Kojto	122:f9eeca106725	786	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
Kojto	122:f9eeca106725	787	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
Kojto	122:f9eeca106725	788
Kojto	122:f9eeca106725	789	/* AHBP Control Register */
Kojto	122:f9eeca106725	790	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
Kojto	122:f9eeca106725	791	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
Kojto	122:f9eeca106725	792
Kojto	122:f9eeca106725	793	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
Kojto	122:f9eeca106725	794	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
Kojto	122:f9eeca106725	795
Kojto	122:f9eeca106725	796	/* L1 Cache Control Register */
Kojto	122:f9eeca106725	797	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
Kojto	122:f9eeca106725	798	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
Kojto	122:f9eeca106725	799
Kojto	122:f9eeca106725	800	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
Kojto	122:f9eeca106725	801	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
Kojto	122:f9eeca106725	802
Kojto	122:f9eeca106725	803	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
Kojto	122:f9eeca106725	804	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
Kojto	122:f9eeca106725	805
Kojto	122:f9eeca106725	806	/* AHBS control register */
Kojto	122:f9eeca106725	807	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
Kojto	122:f9eeca106725	808	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
Kojto	122:f9eeca106725	809
Kojto	122:f9eeca106725	810	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
Kojto	122:f9eeca106725	811	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
Kojto	122:f9eeca106725	812
Kojto	122:f9eeca106725	813	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
Kojto	122:f9eeca106725	814	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
Kojto	122:f9eeca106725	815
Kojto	122:f9eeca106725	816	/* Auxiliary Bus Fault Status Register */
Kojto	122:f9eeca106725	817	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
Kojto	122:f9eeca106725	818	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
Kojto	122:f9eeca106725	819
Kojto	122:f9eeca106725	820	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
Kojto	122:f9eeca106725	821	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
Kojto	122:f9eeca106725	822
Kojto	122:f9eeca106725	823	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
Kojto	122:f9eeca106725	824	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
Kojto	122:f9eeca106725	825
Kojto	122:f9eeca106725	826	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
Kojto	122:f9eeca106725	827	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
Kojto	122:f9eeca106725	828
Kojto	122:f9eeca106725	829	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
Kojto	122:f9eeca106725	830	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
Kojto	122:f9eeca106725	831
Kojto	122:f9eeca106725	832	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
Kojto	122:f9eeca106725	833	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
Kojto	122:f9eeca106725	834
Kojto	122:f9eeca106725	835	/@} end of group CMSIS_SCB /
Kojto	122:f9eeca106725	836
Kojto	122:f9eeca106725	837
Kojto	122:f9eeca106725	838	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	839	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto	122:f9eeca106725	840	\brief Type definitions for the System Control and ID Register not in the SCB
Kojto	122:f9eeca106725	841	@{
Kojto	122:f9eeca106725	842	*/
Kojto	122:f9eeca106725	843
Kojto	122:f9eeca106725	844	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto	122:f9eeca106725	845	*/
Kojto	122:f9eeca106725	846	typedef struct
Kojto	122:f9eeca106725	847	{
Kojto	122:f9eeca106725	848	uint32_t RESERVED0[1];
Kojto	122:f9eeca106725	849	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Kojto	122:f9eeca106725	850	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Kojto	122:f9eeca106725	851	} SCnSCB_Type;
Kojto	122:f9eeca106725	852
Kojto	122:f9eeca106725	853	/* Interrupt Controller Type Register Definitions */
Kojto	122:f9eeca106725	854	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	122:f9eeca106725	855	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
Kojto	122:f9eeca106725	856
Kojto	122:f9eeca106725	857	/* Auxiliary Control Register Definitions */
Kojto	122:f9eeca106725	858	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
Kojto	122:f9eeca106725	859	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
Kojto	122:f9eeca106725	860
Kojto	122:f9eeca106725	861	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
Kojto	122:f9eeca106725	862	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
Kojto	122:f9eeca106725	863
Kojto	122:f9eeca106725	864	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
Kojto	122:f9eeca106725	865	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
Kojto	122:f9eeca106725	866
Kojto	122:f9eeca106725	867	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Kojto	122:f9eeca106725	868	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Kojto	122:f9eeca106725	869
Kojto	122:f9eeca106725	870	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Kojto	122:f9eeca106725	871	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
Kojto	122:f9eeca106725	872
Kojto	122:f9eeca106725	873	/@} end of group CMSIS_SCnotSCB /
Kojto	122:f9eeca106725	874
Kojto	122:f9eeca106725	875
Kojto	122:f9eeca106725	876	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	877	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto	122:f9eeca106725	878	\brief Type definitions for the System Timer Registers.
Kojto	122:f9eeca106725	879	@{
Kojto	122:f9eeca106725	880	*/
Kojto	122:f9eeca106725	881
Kojto	122:f9eeca106725	882	/** \brief Structure type to access the System Timer (SysTick).
Kojto	122:f9eeca106725	883	*/
Kojto	122:f9eeca106725	884	typedef struct
Kojto	122:f9eeca106725	885	{
Kojto	122:f9eeca106725	886	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Kojto	122:f9eeca106725	887	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Kojto	122:f9eeca106725	888	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Kojto	122:f9eeca106725	889	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Kojto	122:f9eeca106725	890	} SysTick_Type;
Kojto	122:f9eeca106725	891
Kojto	122:f9eeca106725	892	/* SysTick Control / Status Register Definitions */
Kojto	122:f9eeca106725	893	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Kojto	122:f9eeca106725	894	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Kojto	122:f9eeca106725	895
Kojto	122:f9eeca106725	896	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Kojto	122:f9eeca106725	897	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Kojto	122:f9eeca106725	898
Kojto	122:f9eeca106725	899	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Kojto	122:f9eeca106725	900	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Kojto	122:f9eeca106725	901
Kojto	122:f9eeca106725	902	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	122:f9eeca106725	903	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
Kojto	122:f9eeca106725	904
Kojto	122:f9eeca106725	905	/* SysTick Reload Register Definitions */
Kojto	122:f9eeca106725	906	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	122:f9eeca106725	907	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
Kojto	122:f9eeca106725	908
Kojto	122:f9eeca106725	909	/* SysTick Current Register Definitions */
Kojto	122:f9eeca106725	910	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	122:f9eeca106725	911	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
Kojto	122:f9eeca106725	912
Kojto	122:f9eeca106725	913	/* SysTick Calibration Register Definitions */
Kojto	122:f9eeca106725	914	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Kojto	122:f9eeca106725	915	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Kojto	122:f9eeca106725	916
Kojto	122:f9eeca106725	917	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Kojto	122:f9eeca106725	918	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Kojto	122:f9eeca106725	919
Kojto	122:f9eeca106725	920	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	122:f9eeca106725	921	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
Kojto	122:f9eeca106725	922
Kojto	122:f9eeca106725	923	/@} end of group CMSIS_SysTick /
Kojto	122:f9eeca106725	924
Kojto	122:f9eeca106725	925
Kojto	122:f9eeca106725	926	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	927	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto	122:f9eeca106725	928	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto	122:f9eeca106725	929	@{
Kojto	122:f9eeca106725	930	*/
Kojto	122:f9eeca106725	931
Kojto	122:f9eeca106725	932	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto	122:f9eeca106725	933	*/
Kojto	122:f9eeca106725	934	typedef struct
Kojto	122:f9eeca106725	935	{
Kojto	122:f9eeca106725	936	__O union
Kojto	122:f9eeca106725	937	{
Kojto	122:f9eeca106725	938	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Kojto	122:f9eeca106725	939	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Kojto	122:f9eeca106725	940	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Kojto	122:f9eeca106725	941	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Kojto	122:f9eeca106725	942	uint32_t RESERVED0[864];
Kojto	122:f9eeca106725	943	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Kojto	122:f9eeca106725	944	uint32_t RESERVED1[15];
Kojto	122:f9eeca106725	945	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Kojto	122:f9eeca106725	946	uint32_t RESERVED2[15];
Kojto	122:f9eeca106725	947	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Kojto	122:f9eeca106725	948	uint32_t RESERVED3[29];
Kojto	122:f9eeca106725	949	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Kojto	122:f9eeca106725	950	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Kojto	122:f9eeca106725	951	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Kojto	122:f9eeca106725	952	uint32_t RESERVED4[43];
Kojto	122:f9eeca106725	953	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Kojto	122:f9eeca106725	954	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Kojto	122:f9eeca106725	955	uint32_t RESERVED5[6];
Kojto	122:f9eeca106725	956	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Kojto	122:f9eeca106725	957	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Kojto	122:f9eeca106725	958	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Kojto	122:f9eeca106725	959	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Kojto	122:f9eeca106725	960	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Kojto	122:f9eeca106725	961	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Kojto	122:f9eeca106725	962	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Kojto	122:f9eeca106725	963	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Kojto	122:f9eeca106725	964	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Kojto	122:f9eeca106725	965	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Kojto	122:f9eeca106725	966	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Kojto	122:f9eeca106725	967	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Kojto	122:f9eeca106725	968	} ITM_Type;
Kojto	122:f9eeca106725	969
Kojto	122:f9eeca106725	970	/* ITM Trace Privilege Register Definitions */
Kojto	122:f9eeca106725	971	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	122:f9eeca106725	972	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
Kojto	122:f9eeca106725	973
Kojto	122:f9eeca106725	974	/* ITM Trace Control Register Definitions */
Kojto	122:f9eeca106725	975	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Kojto	122:f9eeca106725	976	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Kojto	122:f9eeca106725	977
Kojto	122:f9eeca106725	978	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Kojto	122:f9eeca106725	979	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Kojto	122:f9eeca106725	980
Kojto	122:f9eeca106725	981	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Kojto	122:f9eeca106725	982	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Kojto	122:f9eeca106725	983
Kojto	122:f9eeca106725	984	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Kojto	122:f9eeca106725	985	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Kojto	122:f9eeca106725	986
Kojto	122:f9eeca106725	987	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Kojto	122:f9eeca106725	988	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Kojto	122:f9eeca106725	989
Kojto	122:f9eeca106725	990	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Kojto	122:f9eeca106725	991	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Kojto	122:f9eeca106725	992
Kojto	122:f9eeca106725	993	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Kojto	122:f9eeca106725	994	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Kojto	122:f9eeca106725	995
Kojto	122:f9eeca106725	996	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Kojto	122:f9eeca106725	997	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Kojto	122:f9eeca106725	998
Kojto	122:f9eeca106725	999	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	122:f9eeca106725	1000	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
Kojto	122:f9eeca106725	1001
Kojto	122:f9eeca106725	1002	/* ITM Integration Write Register Definitions */
Kojto	122:f9eeca106725	1003	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	122:f9eeca106725	1004	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
Kojto	122:f9eeca106725	1005
Kojto	122:f9eeca106725	1006	/* ITM Integration Read Register Definitions */
Kojto	122:f9eeca106725	1007	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	122:f9eeca106725	1008	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
Kojto	122:f9eeca106725	1009
Kojto	122:f9eeca106725	1010	/* ITM Integration Mode Control Register Definitions */
Kojto	122:f9eeca106725	1011	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	122:f9eeca106725	1012	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
Kojto	122:f9eeca106725	1013
Kojto	122:f9eeca106725	1014	/* ITM Lock Status Register Definitions */
Kojto	122:f9eeca106725	1015	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Kojto	122:f9eeca106725	1016	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Kojto	122:f9eeca106725	1017
Kojto	122:f9eeca106725	1018	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Kojto	122:f9eeca106725	1019	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Kojto	122:f9eeca106725	1020
Kojto	122:f9eeca106725	1021	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	122:f9eeca106725	1022	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
Kojto	122:f9eeca106725	1023
Kojto	122:f9eeca106725	1024	/@}/ /* end of group CMSIS_ITM */
Kojto	122:f9eeca106725	1025
Kojto	122:f9eeca106725	1026
Kojto	122:f9eeca106725	1027	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1028	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto	122:f9eeca106725	1029	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto	122:f9eeca106725	1030	@{
Kojto	122:f9eeca106725	1031	*/
Kojto	122:f9eeca106725	1032
Kojto	122:f9eeca106725	1033	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto	122:f9eeca106725	1034	*/
Kojto	122:f9eeca106725	1035	typedef struct
Kojto	122:f9eeca106725	1036	{
Kojto	122:f9eeca106725	1037	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Kojto	122:f9eeca106725	1038	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Kojto	122:f9eeca106725	1039	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Kojto	122:f9eeca106725	1040	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Kojto	122:f9eeca106725	1041	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Kojto	122:f9eeca106725	1042	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Kojto	122:f9eeca106725	1043	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Kojto	122:f9eeca106725	1044	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Kojto	122:f9eeca106725	1045	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Kojto	122:f9eeca106725	1046	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Kojto	122:f9eeca106725	1047	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Kojto	122:f9eeca106725	1048	uint32_t RESERVED0[1];
Kojto	122:f9eeca106725	1049	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Kojto	122:f9eeca106725	1050	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Kojto	122:f9eeca106725	1051	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Kojto	122:f9eeca106725	1052	uint32_t RESERVED1[1];
Kojto	122:f9eeca106725	1053	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Kojto	122:f9eeca106725	1054	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Kojto	122:f9eeca106725	1055	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Kojto	122:f9eeca106725	1056	uint32_t RESERVED2[1];
Kojto	122:f9eeca106725	1057	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Kojto	122:f9eeca106725	1058	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Kojto	122:f9eeca106725	1059	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Kojto	122:f9eeca106725	1060	uint32_t RESERVED3[981];
Kojto	122:f9eeca106725	1061	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
Kojto	122:f9eeca106725	1062	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
Kojto	122:f9eeca106725	1063	} DWT_Type;
Kojto	122:f9eeca106725	1064
Kojto	122:f9eeca106725	1065	/* DWT Control Register Definitions */
Kojto	122:f9eeca106725	1066	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Kojto	122:f9eeca106725	1067	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Kojto	122:f9eeca106725	1068
Kojto	122:f9eeca106725	1069	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Kojto	122:f9eeca106725	1070	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Kojto	122:f9eeca106725	1071
Kojto	122:f9eeca106725	1072	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Kojto	122:f9eeca106725	1073	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Kojto	122:f9eeca106725	1074
Kojto	122:f9eeca106725	1075	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Kojto	122:f9eeca106725	1076	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Kojto	122:f9eeca106725	1077
Kojto	122:f9eeca106725	1078	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Kojto	122:f9eeca106725	1079	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Kojto	122:f9eeca106725	1080
Kojto	122:f9eeca106725	1081	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Kojto	122:f9eeca106725	1082	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Kojto	122:f9eeca106725	1083
Kojto	122:f9eeca106725	1084	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Kojto	122:f9eeca106725	1085	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Kojto	122:f9eeca106725	1086
Kojto	122:f9eeca106725	1087	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Kojto	122:f9eeca106725	1088	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Kojto	122:f9eeca106725	1089
Kojto	122:f9eeca106725	1090	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Kojto	122:f9eeca106725	1091	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Kojto	122:f9eeca106725	1092
Kojto	122:f9eeca106725	1093	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Kojto	122:f9eeca106725	1094	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Kojto	122:f9eeca106725	1095
Kojto	122:f9eeca106725	1096	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Kojto	122:f9eeca106725	1097	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Kojto	122:f9eeca106725	1098
Kojto	122:f9eeca106725	1099	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Kojto	122:f9eeca106725	1100	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Kojto	122:f9eeca106725	1101
Kojto	122:f9eeca106725	1102	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Kojto	122:f9eeca106725	1103	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Kojto	122:f9eeca106725	1104
Kojto	122:f9eeca106725	1105	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Kojto	122:f9eeca106725	1106	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Kojto	122:f9eeca106725	1107
Kojto	122:f9eeca106725	1108	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Kojto	122:f9eeca106725	1109	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Kojto	122:f9eeca106725	1110
Kojto	122:f9eeca106725	1111	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Kojto	122:f9eeca106725	1112	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Kojto	122:f9eeca106725	1113
Kojto	122:f9eeca106725	1114	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Kojto	122:f9eeca106725	1115	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Kojto	122:f9eeca106725	1116
Kojto	122:f9eeca106725	1117	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	122:f9eeca106725	1118	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
Kojto	122:f9eeca106725	1119
Kojto	122:f9eeca106725	1120	/* DWT CPI Count Register Definitions */
Kojto	122:f9eeca106725	1121	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	122:f9eeca106725	1122	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
Kojto	122:f9eeca106725	1123
Kojto	122:f9eeca106725	1124	/* DWT Exception Overhead Count Register Definitions */
Kojto	122:f9eeca106725	1125	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	122:f9eeca106725	1126	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
Kojto	122:f9eeca106725	1127
Kojto	122:f9eeca106725	1128	/* DWT Sleep Count Register Definitions */
Kojto	122:f9eeca106725	1129	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	122:f9eeca106725	1130	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Kojto	122:f9eeca106725	1131
Kojto	122:f9eeca106725	1132	/* DWT LSU Count Register Definitions */
Kojto	122:f9eeca106725	1133	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	122:f9eeca106725	1134	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
Kojto	122:f9eeca106725	1135
Kojto	122:f9eeca106725	1136	/* DWT Folded-instruction Count Register Definitions */
Kojto	122:f9eeca106725	1137	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	122:f9eeca106725	1138	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
Kojto	122:f9eeca106725	1139
Kojto	122:f9eeca106725	1140	/* DWT Comparator Mask Register Definitions */
Kojto	122:f9eeca106725	1141	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	122:f9eeca106725	1142	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
Kojto	122:f9eeca106725	1143
Kojto	122:f9eeca106725	1144	/* DWT Comparator Function Register Definitions */
Kojto	122:f9eeca106725	1145	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Kojto	122:f9eeca106725	1146	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Kojto	122:f9eeca106725	1147
Kojto	122:f9eeca106725	1148	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Kojto	122:f9eeca106725	1149	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Kojto	122:f9eeca106725	1150
Kojto	122:f9eeca106725	1151	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Kojto	122:f9eeca106725	1152	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Kojto	122:f9eeca106725	1153
Kojto	122:f9eeca106725	1154	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Kojto	122:f9eeca106725	1155	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Kojto	122:f9eeca106725	1156
Kojto	122:f9eeca106725	1157	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Kojto	122:f9eeca106725	1158	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Kojto	122:f9eeca106725	1159
Kojto	122:f9eeca106725	1160	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Kojto	122:f9eeca106725	1161	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Kojto	122:f9eeca106725	1162
Kojto	122:f9eeca106725	1163	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Kojto	122:f9eeca106725	1164	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Kojto	122:f9eeca106725	1165
Kojto	122:f9eeca106725	1166	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Kojto	122:f9eeca106725	1167	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Kojto	122:f9eeca106725	1168
Kojto	122:f9eeca106725	1169	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	122:f9eeca106725	1170	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
Kojto	122:f9eeca106725	1171
Kojto	122:f9eeca106725	1172	/@}/ /* end of group CMSIS_DWT */
Kojto	122:f9eeca106725	1173
Kojto	122:f9eeca106725	1174
Kojto	122:f9eeca106725	1175	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1176	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto	122:f9eeca106725	1177	\brief Type definitions for the Trace Port Interface (TPI)
Kojto	122:f9eeca106725	1178	@{
Kojto	122:f9eeca106725	1179	*/
Kojto	122:f9eeca106725	1180
Kojto	122:f9eeca106725	1181	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto	122:f9eeca106725	1182	*/
Kojto	122:f9eeca106725	1183	typedef struct
Kojto	122:f9eeca106725	1184	{
Kojto	122:f9eeca106725	1185	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Kojto	122:f9eeca106725	1186	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Kojto	122:f9eeca106725	1187	uint32_t RESERVED0[2];
Kojto	122:f9eeca106725	1188	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Kojto	122:f9eeca106725	1189	uint32_t RESERVED1[55];
Kojto	122:f9eeca106725	1190	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Kojto	122:f9eeca106725	1191	uint32_t RESERVED2[131];
Kojto	122:f9eeca106725	1192	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Kojto	122:f9eeca106725	1193	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Kojto	122:f9eeca106725	1194	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Kojto	122:f9eeca106725	1195	uint32_t RESERVED3[759];
Kojto	122:f9eeca106725	1196	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Kojto	122:f9eeca106725	1197	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Kojto	122:f9eeca106725	1198	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Kojto	122:f9eeca106725	1199	uint32_t RESERVED4[1];
Kojto	122:f9eeca106725	1200	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Kojto	122:f9eeca106725	1201	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Kojto	122:f9eeca106725	1202	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Kojto	122:f9eeca106725	1203	uint32_t RESERVED5[39];
Kojto	122:f9eeca106725	1204	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Kojto	122:f9eeca106725	1205	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Kojto	122:f9eeca106725	1206	uint32_t RESERVED7[8];
Kojto	122:f9eeca106725	1207	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Kojto	122:f9eeca106725	1208	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Kojto	122:f9eeca106725	1209	} TPI_Type;
Kojto	122:f9eeca106725	1210
Kojto	122:f9eeca106725	1211	/* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto	122:f9eeca106725	1212	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	122:f9eeca106725	1213	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
Kojto	122:f9eeca106725	1214
Kojto	122:f9eeca106725	1215	/* TPI Selected Pin Protocol Register Definitions */
Kojto	122:f9eeca106725	1216	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	122:f9eeca106725	1217	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
Kojto	122:f9eeca106725	1218
Kojto	122:f9eeca106725	1219	/* TPI Formatter and Flush Status Register Definitions */
Kojto	122:f9eeca106725	1220	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Kojto	122:f9eeca106725	1221	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Kojto	122:f9eeca106725	1222
Kojto	122:f9eeca106725	1223	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Kojto	122:f9eeca106725	1224	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Kojto	122:f9eeca106725	1225
Kojto	122:f9eeca106725	1226	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Kojto	122:f9eeca106725	1227	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Kojto	122:f9eeca106725	1228
Kojto	122:f9eeca106725	1229	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	122:f9eeca106725	1230	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
Kojto	122:f9eeca106725	1231
Kojto	122:f9eeca106725	1232	/* TPI Formatter and Flush Control Register Definitions */
Kojto	122:f9eeca106725	1233	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Kojto	122:f9eeca106725	1234	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Kojto	122:f9eeca106725	1235
Kojto	122:f9eeca106725	1236	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Kojto	122:f9eeca106725	1237	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Kojto	122:f9eeca106725	1238
Kojto	122:f9eeca106725	1239	/* TPI TRIGGER Register Definitions */
Kojto	122:f9eeca106725	1240	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	122:f9eeca106725	1241	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
Kojto	122:f9eeca106725	1242
Kojto	122:f9eeca106725	1243	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto	122:f9eeca106725	1244	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Kojto	122:f9eeca106725	1245	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Kojto	122:f9eeca106725	1246
Kojto	122:f9eeca106725	1247	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Kojto	122:f9eeca106725	1248	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Kojto	122:f9eeca106725	1249
Kojto	122:f9eeca106725	1250	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Kojto	122:f9eeca106725	1251	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Kojto	122:f9eeca106725	1252
Kojto	122:f9eeca106725	1253	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Kojto	122:f9eeca106725	1254	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Kojto	122:f9eeca106725	1255
Kojto	122:f9eeca106725	1256	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Kojto	122:f9eeca106725	1257	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Kojto	122:f9eeca106725	1258
Kojto	122:f9eeca106725	1259	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Kojto	122:f9eeca106725	1260	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Kojto	122:f9eeca106725	1261
Kojto	122:f9eeca106725	1262	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	122:f9eeca106725	1263	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
Kojto	122:f9eeca106725	1264
Kojto	122:f9eeca106725	1265	/* TPI ITATBCTR2 Register Definitions */
Kojto	122:f9eeca106725	1266	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	122:f9eeca106725	1267	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
Kojto	122:f9eeca106725	1268
Kojto	122:f9eeca106725	1269	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto	122:f9eeca106725	1270	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Kojto	122:f9eeca106725	1271	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Kojto	122:f9eeca106725	1272
Kojto	122:f9eeca106725	1273	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Kojto	122:f9eeca106725	1274	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Kojto	122:f9eeca106725	1275
Kojto	122:f9eeca106725	1276	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Kojto	122:f9eeca106725	1277	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Kojto	122:f9eeca106725	1278
Kojto	122:f9eeca106725	1279	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Kojto	122:f9eeca106725	1280	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Kojto	122:f9eeca106725	1281
Kojto	122:f9eeca106725	1282	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Kojto	122:f9eeca106725	1283	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Kojto	122:f9eeca106725	1284
Kojto	122:f9eeca106725	1285	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Kojto	122:f9eeca106725	1286	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Kojto	122:f9eeca106725	1287
Kojto	122:f9eeca106725	1288	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	122:f9eeca106725	1289	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
Kojto	122:f9eeca106725	1290
Kojto	122:f9eeca106725	1291	/* TPI ITATBCTR0 Register Definitions */
Kojto	122:f9eeca106725	1292	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	122:f9eeca106725	1293	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
Kojto	122:f9eeca106725	1294
Kojto	122:f9eeca106725	1295	/* TPI Integration Mode Control Register Definitions */
Kojto	122:f9eeca106725	1296	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	122:f9eeca106725	1297	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
Kojto	122:f9eeca106725	1298
Kojto	122:f9eeca106725	1299	/* TPI DEVID Register Definitions */
Kojto	122:f9eeca106725	1300	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Kojto	122:f9eeca106725	1301	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Kojto	122:f9eeca106725	1302
Kojto	122:f9eeca106725	1303	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Kojto	122:f9eeca106725	1304	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Kojto	122:f9eeca106725	1305
Kojto	122:f9eeca106725	1306	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Kojto	122:f9eeca106725	1307	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Kojto	122:f9eeca106725	1308
Kojto	122:f9eeca106725	1309	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Kojto	122:f9eeca106725	1310	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Kojto	122:f9eeca106725	1311
Kojto	122:f9eeca106725	1312	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Kojto	122:f9eeca106725	1313	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Kojto	122:f9eeca106725	1314
Kojto	122:f9eeca106725	1315	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	122:f9eeca106725	1316	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
Kojto	122:f9eeca106725	1317
Kojto	122:f9eeca106725	1318	/* TPI DEVTYPE Register Definitions */
Kojto	122:f9eeca106725	1319	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Kojto	122:f9eeca106725	1320	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Kojto	122:f9eeca106725	1321
Kojto	122:f9eeca106725	1322	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	122:f9eeca106725	1323	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
Kojto	122:f9eeca106725	1324
Kojto	122:f9eeca106725	1325	/@}/ /* end of group CMSIS_TPI */
Kojto	122:f9eeca106725	1326
Kojto	122:f9eeca106725	1327
Kojto	122:f9eeca106725	1328	#if (__MPU_PRESENT == 1)
Kojto	122:f9eeca106725	1329	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1330	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto	122:f9eeca106725	1331	\brief Type definitions for the Memory Protection Unit (MPU)
Kojto	122:f9eeca106725	1332	@{
Kojto	122:f9eeca106725	1333	*/
Kojto	122:f9eeca106725	1334
Kojto	122:f9eeca106725	1335	/** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto	122:f9eeca106725	1336	*/
Kojto	122:f9eeca106725	1337	typedef struct
Kojto	122:f9eeca106725	1338	{
Kojto	122:f9eeca106725	1339	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Kojto	122:f9eeca106725	1340	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Kojto	122:f9eeca106725	1341	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Kojto	122:f9eeca106725	1342	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Kojto	122:f9eeca106725	1343	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Kojto	122:f9eeca106725	1344	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Kojto	122:f9eeca106725	1345	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1346	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Kojto	122:f9eeca106725	1347	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1348	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Kojto	122:f9eeca106725	1349	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Kojto	122:f9eeca106725	1350	} MPU_Type;
Kojto	122:f9eeca106725	1351
Kojto	122:f9eeca106725	1352	/* MPU Type Register */
Kojto	122:f9eeca106725	1353	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Kojto	122:f9eeca106725	1354	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Kojto	122:f9eeca106725	1355
Kojto	122:f9eeca106725	1356	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Kojto	122:f9eeca106725	1357	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Kojto	122:f9eeca106725	1358
Kojto	122:f9eeca106725	1359	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	122:f9eeca106725	1360	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
Kojto	122:f9eeca106725	1361
Kojto	122:f9eeca106725	1362	/* MPU Control Register */
Kojto	122:f9eeca106725	1363	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Kojto	122:f9eeca106725	1364	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Kojto	122:f9eeca106725	1365
Kojto	122:f9eeca106725	1366	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Kojto	122:f9eeca106725	1367	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Kojto	122:f9eeca106725	1368
Kojto	122:f9eeca106725	1369	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	122:f9eeca106725	1370	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
Kojto	122:f9eeca106725	1371
Kojto	122:f9eeca106725	1372	/* MPU Region Number Register */
Kojto	122:f9eeca106725	1373	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	122:f9eeca106725	1374	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
Kojto	122:f9eeca106725	1375
Kojto	122:f9eeca106725	1376	/* MPU Region Base Address Register */
Kojto	122:f9eeca106725	1377	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Kojto	122:f9eeca106725	1378	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Kojto	122:f9eeca106725	1379
Kojto	122:f9eeca106725	1380	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Kojto	122:f9eeca106725	1381	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Kojto	122:f9eeca106725	1382
Kojto	122:f9eeca106725	1383	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	122:f9eeca106725	1384	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
Kojto	122:f9eeca106725	1385
Kojto	122:f9eeca106725	1386	/* MPU Region Attribute and Size Register */
Kojto	122:f9eeca106725	1387	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Kojto	122:f9eeca106725	1388	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Kojto	122:f9eeca106725	1389
Kojto	122:f9eeca106725	1390	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Kojto	122:f9eeca106725	1391	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Kojto	122:f9eeca106725	1392
Kojto	122:f9eeca106725	1393	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Kojto	122:f9eeca106725	1394	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Kojto	122:f9eeca106725	1395
Kojto	122:f9eeca106725	1396	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Kojto	122:f9eeca106725	1397	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Kojto	122:f9eeca106725	1398
Kojto	122:f9eeca106725	1399	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Kojto	122:f9eeca106725	1400	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Kojto	122:f9eeca106725	1401
Kojto	122:f9eeca106725	1402	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Kojto	122:f9eeca106725	1403	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Kojto	122:f9eeca106725	1404
Kojto	122:f9eeca106725	1405	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Kojto	122:f9eeca106725	1406	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Kojto	122:f9eeca106725	1407
Kojto	122:f9eeca106725	1408	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Kojto	122:f9eeca106725	1409	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Kojto	122:f9eeca106725	1410
Kojto	122:f9eeca106725	1411	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Kojto	122:f9eeca106725	1412	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Kojto	122:f9eeca106725	1413
Kojto	122:f9eeca106725	1414	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	122:f9eeca106725	1415	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
Kojto	122:f9eeca106725	1416
Kojto	122:f9eeca106725	1417	/@} end of group CMSIS_MPU /
Kojto	122:f9eeca106725	1418	#endif
Kojto	122:f9eeca106725	1419
Kojto	122:f9eeca106725	1420
Kojto	122:f9eeca106725	1421	#if (__FPU_PRESENT == 1)
Kojto	122:f9eeca106725	1422	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1423	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Kojto	122:f9eeca106725	1424	\brief Type definitions for the Floating Point Unit (FPU)
Kojto	122:f9eeca106725	1425	@{
Kojto	122:f9eeca106725	1426	*/
Kojto	122:f9eeca106725	1427
Kojto	122:f9eeca106725	1428	/** \brief Structure type to access the Floating Point Unit (FPU).
Kojto	122:f9eeca106725	1429	*/
Kojto	122:f9eeca106725	1430	typedef struct
Kojto	122:f9eeca106725	1431	{
Kojto	122:f9eeca106725	1432	uint32_t RESERVED0[1];
Kojto	122:f9eeca106725	1433	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Kojto	122:f9eeca106725	1434	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Kojto	122:f9eeca106725	1435	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Kojto	122:f9eeca106725	1436	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Kojto	122:f9eeca106725	1437	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Kojto	122:f9eeca106725	1438	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
Kojto	122:f9eeca106725	1439	} FPU_Type;
Kojto	122:f9eeca106725	1440
Kojto	122:f9eeca106725	1441	/* Floating-Point Context Control Register */
Kojto	122:f9eeca106725	1442	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
Kojto	122:f9eeca106725	1443	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Kojto	122:f9eeca106725	1444
Kojto	122:f9eeca106725	1445	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
Kojto	122:f9eeca106725	1446	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Kojto	122:f9eeca106725	1447
Kojto	122:f9eeca106725	1448	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
Kojto	122:f9eeca106725	1449	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Kojto	122:f9eeca106725	1450
Kojto	122:f9eeca106725	1451	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
Kojto	122:f9eeca106725	1452	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Kojto	122:f9eeca106725	1453
Kojto	122:f9eeca106725	1454	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
Kojto	122:f9eeca106725	1455	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Kojto	122:f9eeca106725	1456
Kojto	122:f9eeca106725	1457	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
Kojto	122:f9eeca106725	1458	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Kojto	122:f9eeca106725	1459
Kojto	122:f9eeca106725	1460	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
Kojto	122:f9eeca106725	1461	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Kojto	122:f9eeca106725	1462
Kojto	122:f9eeca106725	1463	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
Kojto	122:f9eeca106725	1464	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Kojto	122:f9eeca106725	1465
Kojto	122:f9eeca106725	1466	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Kojto	122:f9eeca106725	1467	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
Kojto	122:f9eeca106725	1468
Kojto	122:f9eeca106725	1469	/* Floating-Point Context Address Register */
Kojto	122:f9eeca106725	1470	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
Kojto	122:f9eeca106725	1471	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Kojto	122:f9eeca106725	1472
Kojto	122:f9eeca106725	1473	/* Floating-Point Default Status Control Register */
Kojto	122:f9eeca106725	1474	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
Kojto	122:f9eeca106725	1475	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Kojto	122:f9eeca106725	1476
Kojto	122:f9eeca106725	1477	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
Kojto	122:f9eeca106725	1478	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Kojto	122:f9eeca106725	1479
Kojto	122:f9eeca106725	1480	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
Kojto	122:f9eeca106725	1481	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Kojto	122:f9eeca106725	1482
Kojto	122:f9eeca106725	1483	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
Kojto	122:f9eeca106725	1484	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Kojto	122:f9eeca106725	1485
Kojto	122:f9eeca106725	1486	/* Media and FP Feature Register 0 */
Kojto	122:f9eeca106725	1487	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
Kojto	122:f9eeca106725	1488	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Kojto	122:f9eeca106725	1489
Kojto	122:f9eeca106725	1490	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
Kojto	122:f9eeca106725	1491	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Kojto	122:f9eeca106725	1492
Kojto	122:f9eeca106725	1493	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
Kojto	122:f9eeca106725	1494	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Kojto	122:f9eeca106725	1495
Kojto	122:f9eeca106725	1496	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
Kojto	122:f9eeca106725	1497	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Kojto	122:f9eeca106725	1498
Kojto	122:f9eeca106725	1499	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
Kojto	122:f9eeca106725	1500	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Kojto	122:f9eeca106725	1501
Kojto	122:f9eeca106725	1502	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
Kojto	122:f9eeca106725	1503	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Kojto	122:f9eeca106725	1504
Kojto	122:f9eeca106725	1505	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
Kojto	122:f9eeca106725	1506	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Kojto	122:f9eeca106725	1507
Kojto	122:f9eeca106725	1508	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Kojto	122:f9eeca106725	1509	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
Kojto	122:f9eeca106725	1510
Kojto	122:f9eeca106725	1511	/* Media and FP Feature Register 1 */
Kojto	122:f9eeca106725	1512	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
Kojto	122:f9eeca106725	1513	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Kojto	122:f9eeca106725	1514
Kojto	122:f9eeca106725	1515	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
Kojto	122:f9eeca106725	1516	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Kojto	122:f9eeca106725	1517
Kojto	122:f9eeca106725	1518	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
Kojto	122:f9eeca106725	1519	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Kojto	122:f9eeca106725	1520
Kojto	122:f9eeca106725	1521	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Kojto	122:f9eeca106725	1522	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
Kojto	122:f9eeca106725	1523
Kojto	122:f9eeca106725	1524	/* Media and FP Feature Register 2 */
Kojto	122:f9eeca106725	1525
Kojto	122:f9eeca106725	1526	/@} end of group CMSIS_FPU /
Kojto	122:f9eeca106725	1527	#endif
Kojto	122:f9eeca106725	1528
Kojto	122:f9eeca106725	1529
Kojto	122:f9eeca106725	1530	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1531	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto	122:f9eeca106725	1532	\brief Type definitions for the Core Debug Registers
Kojto	122:f9eeca106725	1533	@{
Kojto	122:f9eeca106725	1534	*/
Kojto	122:f9eeca106725	1535
Kojto	122:f9eeca106725	1536	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto	122:f9eeca106725	1537	*/
Kojto	122:f9eeca106725	1538	typedef struct
Kojto	122:f9eeca106725	1539	{
Kojto	122:f9eeca106725	1540	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Kojto	122:f9eeca106725	1541	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Kojto	122:f9eeca106725	1542	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Kojto	122:f9eeca106725	1543	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Kojto	122:f9eeca106725	1544	} CoreDebug_Type;
Kojto	122:f9eeca106725	1545
Kojto	122:f9eeca106725	1546	/* Debug Halting Control and Status Register */
Kojto	122:f9eeca106725	1547	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Kojto	122:f9eeca106725	1548	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Kojto	122:f9eeca106725	1549
Kojto	122:f9eeca106725	1550	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Kojto	122:f9eeca106725	1551	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Kojto	122:f9eeca106725	1552
Kojto	122:f9eeca106725	1553	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Kojto	122:f9eeca106725	1554	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Kojto	122:f9eeca106725	1555
Kojto	122:f9eeca106725	1556	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Kojto	122:f9eeca106725	1557	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Kojto	122:f9eeca106725	1558
Kojto	122:f9eeca106725	1559	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Kojto	122:f9eeca106725	1560	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Kojto	122:f9eeca106725	1561
Kojto	122:f9eeca106725	1562	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Kojto	122:f9eeca106725	1563	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Kojto	122:f9eeca106725	1564
Kojto	122:f9eeca106725	1565	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Kojto	122:f9eeca106725	1566	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Kojto	122:f9eeca106725	1567
Kojto	122:f9eeca106725	1568	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Kojto	122:f9eeca106725	1569	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Kojto	122:f9eeca106725	1570
Kojto	122:f9eeca106725	1571	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Kojto	122:f9eeca106725	1572	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Kojto	122:f9eeca106725	1573
Kojto	122:f9eeca106725	1574	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Kojto	122:f9eeca106725	1575	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Kojto	122:f9eeca106725	1576
Kojto	122:f9eeca106725	1577	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Kojto	122:f9eeca106725	1578	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Kojto	122:f9eeca106725	1579
Kojto	122:f9eeca106725	1580	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	122:f9eeca106725	1581	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Kojto	122:f9eeca106725	1582
Kojto	122:f9eeca106725	1583	/* Debug Core Register Selector Register */
Kojto	122:f9eeca106725	1584	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Kojto	122:f9eeca106725	1585	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Kojto	122:f9eeca106725	1586
Kojto	122:f9eeca106725	1587	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	122:f9eeca106725	1588	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
Kojto	122:f9eeca106725	1589
Kojto	122:f9eeca106725	1590	/* Debug Exception and Monitor Control Register */
Kojto	122:f9eeca106725	1591	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Kojto	122:f9eeca106725	1592	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Kojto	122:f9eeca106725	1593
Kojto	122:f9eeca106725	1594	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Kojto	122:f9eeca106725	1595	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Kojto	122:f9eeca106725	1596
Kojto	122:f9eeca106725	1597	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Kojto	122:f9eeca106725	1598	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Kojto	122:f9eeca106725	1599
Kojto	122:f9eeca106725	1600	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Kojto	122:f9eeca106725	1601	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Kojto	122:f9eeca106725	1602
Kojto	122:f9eeca106725	1603	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Kojto	122:f9eeca106725	1604	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Kojto	122:f9eeca106725	1605
Kojto	122:f9eeca106725	1606	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Kojto	122:f9eeca106725	1607	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Kojto	122:f9eeca106725	1608
Kojto	122:f9eeca106725	1609	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Kojto	122:f9eeca106725	1610	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Kojto	122:f9eeca106725	1611
Kojto	122:f9eeca106725	1612	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Kojto	122:f9eeca106725	1613	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Kojto	122:f9eeca106725	1614
Kojto	122:f9eeca106725	1615	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Kojto	122:f9eeca106725	1616	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Kojto	122:f9eeca106725	1617
Kojto	122:f9eeca106725	1618	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Kojto	122:f9eeca106725	1619	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Kojto	122:f9eeca106725	1620
Kojto	122:f9eeca106725	1621	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Kojto	122:f9eeca106725	1622	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Kojto	122:f9eeca106725	1623
Kojto	122:f9eeca106725	1624	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Kojto	122:f9eeca106725	1625	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Kojto	122:f9eeca106725	1626
Kojto	122:f9eeca106725	1627	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	122:f9eeca106725	1628	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Kojto	122:f9eeca106725	1629
Kojto	122:f9eeca106725	1630	/@} end of group CMSIS_CoreDebug /
Kojto	122:f9eeca106725	1631
Kojto	122:f9eeca106725	1632
Kojto	122:f9eeca106725	1633	/** \ingroup CMSIS_core_register
Kojto	122:f9eeca106725	1634	\defgroup CMSIS_core_base Core Definitions
Kojto	122:f9eeca106725	1635	\brief Definitions for base addresses, unions, and structures.
Kojto	122:f9eeca106725	1636	@{
Kojto	122:f9eeca106725	1637	*/
Kojto	122:f9eeca106725	1638
Kojto	122:f9eeca106725	1639	/* Memory mapping of Cortex-M4 Hardware */
Kojto	122:f9eeca106725	1640	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Kojto	122:f9eeca106725	1641	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Kojto	122:f9eeca106725	1642	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Kojto	122:f9eeca106725	1643	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Kojto	122:f9eeca106725	1644	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Kojto	122:f9eeca106725	1645	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Kojto	122:f9eeca106725	1646	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Kojto	122:f9eeca106725	1647	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Kojto	122:f9eeca106725	1648
Kojto	122:f9eeca106725	1649	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Kojto	122:f9eeca106725	1650	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Kojto	122:f9eeca106725	1651	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Kojto	122:f9eeca106725	1652	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Kojto	122:f9eeca106725	1653	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Kojto	122:f9eeca106725	1654	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Kojto	122:f9eeca106725	1655	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Kojto	122:f9eeca106725	1656	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Kojto	122:f9eeca106725	1657
Kojto	122:f9eeca106725	1658	#if (__MPU_PRESENT == 1)
Kojto	122:f9eeca106725	1659	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Kojto	122:f9eeca106725	1660	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Kojto	122:f9eeca106725	1661	#endif
Kojto	122:f9eeca106725	1662
Kojto	122:f9eeca106725	1663	#if (__FPU_PRESENT == 1)
Kojto	122:f9eeca106725	1664	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Kojto	122:f9eeca106725	1665	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Kojto	122:f9eeca106725	1666	#endif
Kojto	122:f9eeca106725	1667
Kojto	122:f9eeca106725	1668	/@} /
Kojto	122:f9eeca106725	1669
Kojto	122:f9eeca106725	1670
Kojto	122:f9eeca106725	1671
Kojto	122:f9eeca106725	1672	/*******************************************************************************
Kojto	122:f9eeca106725	1673	* Hardware Abstraction Layer
Kojto	122:f9eeca106725	1674	Core Function Interface contains:
Kojto	122:f9eeca106725	1675	- Core NVIC Functions
Kojto	122:f9eeca106725	1676	- Core SysTick Functions
Kojto	122:f9eeca106725	1677	- Core Debug Functions
Kojto	122:f9eeca106725	1678	- Core Register Access Functions
Kojto	122:f9eeca106725	1679	******************************************************************************/
Kojto	122:f9eeca106725	1680	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto	122:f9eeca106725	1681	*/
Kojto	122:f9eeca106725	1682
Kojto	122:f9eeca106725	1683
Kojto	122:f9eeca106725	1684
Kojto	122:f9eeca106725	1685	/* ########################## NVIC functions #################################### */
Kojto	122:f9eeca106725	1686	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1687	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto	122:f9eeca106725	1688	\brief Functions that manage interrupts and exceptions via the NVIC.
Kojto	122:f9eeca106725	1689	@{
Kojto	122:f9eeca106725	1690	*/
Kojto	122:f9eeca106725	1691
Kojto	122:f9eeca106725	1692	/** \brief Set Priority Grouping
Kojto	122:f9eeca106725	1693
Kojto	122:f9eeca106725	1694	The function sets the priority grouping field using the required unlock sequence.
Kojto	122:f9eeca106725	1695	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto	122:f9eeca106725	1696	Only values from 0..7 are used.
Kojto	122:f9eeca106725	1697	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1698	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	122:f9eeca106725	1699
Kojto	122:f9eeca106725	1700	\param [in] PriorityGroup Priority grouping field.
Kojto	122:f9eeca106725	1701	*/
Kojto	122:f9eeca106725	1702	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto	122:f9eeca106725	1703	{
Kojto	122:f9eeca106725	1704	uint32_t reg_value;
Kojto	122:f9eeca106725	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1706
Kojto	122:f9eeca106725	1707	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	122:f9eeca106725	1708	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto	122:f9eeca106725	1709	reg_value = (reg_value \|
Kojto	122:f9eeca106725	1710	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	122:f9eeca106725	1711	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto	122:f9eeca106725	1712	SCB->AIRCR = reg_value;
Kojto	122:f9eeca106725	1713	}
Kojto	122:f9eeca106725	1714
Kojto	122:f9eeca106725	1715
Kojto	122:f9eeca106725	1716	/** \brief Get Priority Grouping
Kojto	122:f9eeca106725	1717
Kojto	122:f9eeca106725	1718	The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto	122:f9eeca106725	1719
Kojto	122:f9eeca106725	1720	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto	122:f9eeca106725	1721	*/
Kojto	122:f9eeca106725	1722	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto	122:f9eeca106725	1723	{
Kojto	122:f9eeca106725	1724	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto	122:f9eeca106725	1725	}
Kojto	122:f9eeca106725	1726
Kojto	122:f9eeca106725	1727
Kojto	122:f9eeca106725	1728	/** \brief Enable External Interrupt
Kojto	122:f9eeca106725	1729
Kojto	122:f9eeca106725	1730	The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto	122:f9eeca106725	1731
Kojto	122:f9eeca106725	1732	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1733	*/
Kojto	122:f9eeca106725	1734	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1735	{
Kojto	122:f9eeca106725	1736	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1737	}
Kojto	122:f9eeca106725	1738
Kojto	122:f9eeca106725	1739
Kojto	122:f9eeca106725	1740	/** \brief Disable External Interrupt
Kojto	122:f9eeca106725	1741
Kojto	122:f9eeca106725	1742	The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto	122:f9eeca106725	1743
Kojto	122:f9eeca106725	1744	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1745	*/
Kojto	122:f9eeca106725	1746	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1747	{
Kojto	122:f9eeca106725	1748	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1749	}
Kojto	122:f9eeca106725	1750
Kojto	122:f9eeca106725	1751
Kojto	122:f9eeca106725	1752	/** \brief Get Pending Interrupt
Kojto	122:f9eeca106725	1753
Kojto	122:f9eeca106725	1754	The function reads the pending register in the NVIC and returns the pending bit
Kojto	122:f9eeca106725	1755	for the specified interrupt.
Kojto	122:f9eeca106725	1756
Kojto	122:f9eeca106725	1757	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1758
Kojto	122:f9eeca106725	1759	\return 0 Interrupt status is not pending.
Kojto	122:f9eeca106725	1760	\return 1 Interrupt status is pending.
Kojto	122:f9eeca106725	1761	*/
Kojto	122:f9eeca106725	1762	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1763	{
Kojto	122:f9eeca106725	1764	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	122:f9eeca106725	1765	}
Kojto	122:f9eeca106725	1766
Kojto	122:f9eeca106725	1767
Kojto	122:f9eeca106725	1768	/** \brief Set Pending Interrupt
Kojto	122:f9eeca106725	1769
Kojto	122:f9eeca106725	1770	The function sets the pending bit of an external interrupt.
Kojto	122:f9eeca106725	1771
Kojto	122:f9eeca106725	1772	\param [in] IRQn Interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1773	*/
Kojto	122:f9eeca106725	1774	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1775	{
Kojto	122:f9eeca106725	1776	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1777	}
Kojto	122:f9eeca106725	1778
Kojto	122:f9eeca106725	1779
Kojto	122:f9eeca106725	1780	/** \brief Clear Pending Interrupt
Kojto	122:f9eeca106725	1781
Kojto	122:f9eeca106725	1782	The function clears the pending bit of an external interrupt.
Kojto	122:f9eeca106725	1783
Kojto	122:f9eeca106725	1784	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	122:f9eeca106725	1785	*/
Kojto	122:f9eeca106725	1786	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1787	{
Kojto	122:f9eeca106725	1788	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto	122:f9eeca106725	1789	}
Kojto	122:f9eeca106725	1790
Kojto	122:f9eeca106725	1791
Kojto	122:f9eeca106725	1792	/** \brief Get Active Interrupt
Kojto	122:f9eeca106725	1793
Kojto	122:f9eeca106725	1794	The function reads the active register in NVIC and returns the active bit.
Kojto	122:f9eeca106725	1795
Kojto	122:f9eeca106725	1796	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1797
Kojto	122:f9eeca106725	1798	\return 0 Interrupt status is not active.
Kojto	122:f9eeca106725	1799	\return 1 Interrupt status is active.
Kojto	122:f9eeca106725	1800	*/
Kojto	122:f9eeca106725	1801	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1802	{
Kojto	122:f9eeca106725	1803	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto	122:f9eeca106725	1804	}
Kojto	122:f9eeca106725	1805
Kojto	122:f9eeca106725	1806
Kojto	122:f9eeca106725	1807	/** \brief Set Interrupt Priority
Kojto	122:f9eeca106725	1808
Kojto	122:f9eeca106725	1809	The function sets the priority of an interrupt.
Kojto	122:f9eeca106725	1810
Kojto	122:f9eeca106725	1811	\note The priority cannot be set for every core interrupt.
Kojto	122:f9eeca106725	1812
Kojto	122:f9eeca106725	1813	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1814	\param [in] priority Priority to set.
Kojto	122:f9eeca106725	1815	*/
Kojto	122:f9eeca106725	1816	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto	122:f9eeca106725	1817	{
Kojto	122:f9eeca106725	1818	if((int32_t)IRQn < 0) {
Kojto	122:f9eeca106725	1819	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	122:f9eeca106725	1820	}
Kojto	122:f9eeca106725	1821	else {
Kojto	122:f9eeca106725	1822	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto	122:f9eeca106725	1823	}
Kojto	122:f9eeca106725	1824	}
Kojto	122:f9eeca106725	1825
Kojto	122:f9eeca106725	1826
Kojto	122:f9eeca106725	1827	/** \brief Get Interrupt Priority
Kojto	122:f9eeca106725	1828
Kojto	122:f9eeca106725	1829	The function reads the priority of an interrupt. The interrupt
Kojto	122:f9eeca106725	1830	number can be positive to specify an external (device specific)
Kojto	122:f9eeca106725	1831	interrupt, or negative to specify an internal (core) interrupt.
Kojto	122:f9eeca106725	1832
Kojto	122:f9eeca106725	1833
Kojto	122:f9eeca106725	1834	\param [in] IRQn Interrupt number.
Kojto	122:f9eeca106725	1835	\return Interrupt Priority. Value is aligned automatically to the implemented
Kojto	122:f9eeca106725	1836	priority bits of the microcontroller.
Kojto	122:f9eeca106725	1837	*/
Kojto	122:f9eeca106725	1838	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto	122:f9eeca106725	1839	{
Kojto	122:f9eeca106725	1840
Kojto	122:f9eeca106725	1841	if((int32_t)IRQn < 0) {
Kojto	122:f9eeca106725	1842	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto	122:f9eeca106725	1843	}
Kojto	122:f9eeca106725	1844	else {
Kojto	122:f9eeca106725	1845	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto	122:f9eeca106725	1846	}
Kojto	122:f9eeca106725	1847	}
Kojto	122:f9eeca106725	1848
Kojto	122:f9eeca106725	1849
Kojto	122:f9eeca106725	1850	/** \brief Encode Priority
Kojto	122:f9eeca106725	1851
Kojto	122:f9eeca106725	1852	The function encodes the priority for an interrupt with the given priority group,
Kojto	122:f9eeca106725	1853	preemptive priority value, and subpriority value.
Kojto	122:f9eeca106725	1854	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1855	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	122:f9eeca106725	1856
Kojto	122:f9eeca106725	1857	\param [in] PriorityGroup Used priority group.
Kojto	122:f9eeca106725	1858	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto	122:f9eeca106725	1859	\param [in] SubPriority Subpriority value (starting from 0).
Kojto	122:f9eeca106725	1860	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto	122:f9eeca106725	1861	*/
Kojto	122:f9eeca106725	1862	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto	122:f9eeca106725	1863	{
Kojto	122:f9eeca106725	1864	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1865	uint32_t PreemptPriorityBits;
Kojto	122:f9eeca106725	1866	uint32_t SubPriorityBits;
Kojto	122:f9eeca106725	1867
Kojto	122:f9eeca106725	1868	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	122:f9eeca106725	1869	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	122:f9eeca106725	1870
Kojto	122:f9eeca106725	1871	return (
Kojto	122:f9eeca106725	1872	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
Kojto	122:f9eeca106725	1873	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto	122:f9eeca106725	1874	);
Kojto	122:f9eeca106725	1875	}
Kojto	122:f9eeca106725	1876
Kojto	122:f9eeca106725	1877
Kojto	122:f9eeca106725	1878	/** \brief Decode Priority
Kojto	122:f9eeca106725	1879
Kojto	122:f9eeca106725	1880	The function decodes an interrupt priority value with a given priority group to
Kojto	122:f9eeca106725	1881	preemptive priority value and subpriority value.
Kojto	122:f9eeca106725	1882	In case of a conflict between priority grouping and available
Kojto	122:f9eeca106725	1883	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto	122:f9eeca106725	1884
Kojto	122:f9eeca106725	1885	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto	122:f9eeca106725	1886	\param [in] PriorityGroup Used priority group.
Kojto	122:f9eeca106725	1887	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto	122:f9eeca106725	1888	\param [out] pSubPriority Subpriority value (starting from 0).
Kojto	122:f9eeca106725	1889	*/
Kojto	122:f9eeca106725	1890	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto	122:f9eeca106725	1891	{
Kojto	122:f9eeca106725	1892	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto	122:f9eeca106725	1893	uint32_t PreemptPriorityBits;
Kojto	122:f9eeca106725	1894	uint32_t SubPriorityBits;
Kojto	122:f9eeca106725	1895
Kojto	122:f9eeca106725	1896	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto	122:f9eeca106725	1897	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto	122:f9eeca106725	1898
Kojto	122:f9eeca106725	1899	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto	122:f9eeca106725	1900	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto	122:f9eeca106725	1901	}
Kojto	122:f9eeca106725	1902
Kojto	122:f9eeca106725	1903
Kojto	122:f9eeca106725	1904	/** \brief System Reset
Kojto	122:f9eeca106725	1905
Kojto	122:f9eeca106725	1906	The function initiates a system reset request to reset the MCU.
Kojto	122:f9eeca106725	1907	*/
Kojto	122:f9eeca106725	1908	__STATIC_INLINE void NVIC_SystemReset(void)
Kojto	122:f9eeca106725	1909	{
Kojto	122:f9eeca106725	1910	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	122:f9eeca106725	1911	buffered write are completed before reset */
Kojto	122:f9eeca106725	1912	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	122:f9eeca106725	1913	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	122:f9eeca106725	1914	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto	122:f9eeca106725	1915	__DSB(); /* Ensure completion of memory access */
Kojto	122:f9eeca106725	1916	while(1) { __NOP(); } /* wait until reset */
Kojto	122:f9eeca106725	1917	}
Kojto	122:f9eeca106725	1918
Kojto	122:f9eeca106725	1919	/@} end of CMSIS_Core_NVICFunctions /
Kojto	122:f9eeca106725	1920
Kojto	122:f9eeca106725	1921
Kojto	122:f9eeca106725	1922	/* ########################## FPU functions #################################### */
Kojto	122:f9eeca106725	1923	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1924	\defgroup CMSIS_Core_FpuFunctions FPU Functions
Kojto	122:f9eeca106725	1925	\brief Function that provides FPU type.
Kojto	122:f9eeca106725	1926	@{
Kojto	122:f9eeca106725	1927	*/
Kojto	122:f9eeca106725	1928
Kojto	122:f9eeca106725	1929	/**
Kojto	122:f9eeca106725	1930	\fn uint32_t SCB_GetFPUType(void)
Kojto	122:f9eeca106725	1931	\brief get FPU type
Kojto	122:f9eeca106725	1932	\returns
Kojto	122:f9eeca106725	1933	- \b 0: No FPU
Kojto	122:f9eeca106725	1934	- \b 1: Single precision FPU
Kojto	122:f9eeca106725	1935	- \b 2: Double + Single precision FPU
Kojto	122:f9eeca106725	1936	*/
Kojto	122:f9eeca106725	1937	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
Kojto	122:f9eeca106725	1938	{
Kojto	122:f9eeca106725	1939	uint32_t mvfr0;
Kojto	122:f9eeca106725	1940
Kojto	122:f9eeca106725	1941	mvfr0 = SCB->MVFR0;
Kojto	122:f9eeca106725	1942	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
Kojto	122:f9eeca106725	1943	return 2UL; // Double + Single precision FPU
Kojto	122:f9eeca106725	1944	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
Kojto	122:f9eeca106725	1945	return 1UL; // Single precision FPU
Kojto	122:f9eeca106725	1946	} else {
Kojto	122:f9eeca106725	1947	return 0UL; // No FPU
Kojto	122:f9eeca106725	1948	}
Kojto	122:f9eeca106725	1949	}
Kojto	122:f9eeca106725	1950
Kojto	122:f9eeca106725	1951
Kojto	122:f9eeca106725	1952	/@} end of CMSIS_Core_FpuFunctions /
Kojto	122:f9eeca106725	1953
Kojto	122:f9eeca106725	1954
Kojto	122:f9eeca106725	1955
Kojto	122:f9eeca106725	1956	/* ########################## Cache functions #################################### */
Kojto	122:f9eeca106725	1957	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	1958	\defgroup CMSIS_Core_CacheFunctions Cache Functions
Kojto	122:f9eeca106725	1959	\brief Functions that configure Instruction and Data cache.
Kojto	122:f9eeca106725	1960	@{
Kojto	122:f9eeca106725	1961	*/
Kojto	122:f9eeca106725	1962
Kojto	122:f9eeca106725	1963	/* Cache Size ID Register Macros */
Kojto	122:f9eeca106725	1964	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
Kojto	122:f9eeca106725	1965	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
Kojto	122:f9eeca106725	1966	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
Kojto	122:f9eeca106725	1967
Kojto	122:f9eeca106725	1968
Kojto	122:f9eeca106725	1969	/** \brief Enable I-Cache
Kojto	122:f9eeca106725	1970
Kojto	122:f9eeca106725	1971	The function turns on I-Cache
Kojto	122:f9eeca106725	1972	*/
Kojto	122:f9eeca106725	1973	__STATIC_INLINE void SCB_EnableICache (void)
Kojto	122:f9eeca106725	1974	{
Kojto	122:f9eeca106725	1975	#if (__ICACHE_PRESENT == 1)
Kojto	122:f9eeca106725	1976	__DSB();
Kojto	122:f9eeca106725	1977	__ISB();
Kojto	122:f9eeca106725	1978	SCB->ICIALLU = 0UL; // invalidate I-Cache
Kojto	122:f9eeca106725	1979	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
Kojto	122:f9eeca106725	1980	__DSB();
Kojto	122:f9eeca106725	1981	__ISB();
Kojto	122:f9eeca106725	1982	#endif
Kojto	122:f9eeca106725	1983	}
Kojto	122:f9eeca106725	1984
Kojto	122:f9eeca106725	1985
Kojto	122:f9eeca106725	1986	/** \brief Disable I-Cache
Kojto	122:f9eeca106725	1987
Kojto	122:f9eeca106725	1988	The function turns off I-Cache
Kojto	122:f9eeca106725	1989	*/
Kojto	122:f9eeca106725	1990	__STATIC_INLINE void SCB_DisableICache (void)
Kojto	122:f9eeca106725	1991	{
Kojto	122:f9eeca106725	1992	#if (__ICACHE_PRESENT == 1)
Kojto	122:f9eeca106725	1993	__DSB();
Kojto	122:f9eeca106725	1994	__ISB();
Kojto	122:f9eeca106725	1995	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
Kojto	122:f9eeca106725	1996	SCB->ICIALLU = 0UL; // invalidate I-Cache
Kojto	122:f9eeca106725	1997	__DSB();
Kojto	122:f9eeca106725	1998	__ISB();
Kojto	122:f9eeca106725	1999	#endif
Kojto	122:f9eeca106725	2000	}
Kojto	122:f9eeca106725	2001
Kojto	122:f9eeca106725	2002
Kojto	122:f9eeca106725	2003	/** \brief Invalidate I-Cache
Kojto	122:f9eeca106725	2004
Kojto	122:f9eeca106725	2005	The function invalidates I-Cache
Kojto	122:f9eeca106725	2006	*/
Kojto	122:f9eeca106725	2007	__STATIC_INLINE void SCB_InvalidateICache (void)
Kojto	122:f9eeca106725	2008	{
Kojto	122:f9eeca106725	2009	#if (__ICACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2010	__DSB();
Kojto	122:f9eeca106725	2011	__ISB();
Kojto	122:f9eeca106725	2012	SCB->ICIALLU = 0UL;
Kojto	122:f9eeca106725	2013	__DSB();
Kojto	122:f9eeca106725	2014	__ISB();
Kojto	122:f9eeca106725	2015	#endif
Kojto	122:f9eeca106725	2016	}
Kojto	122:f9eeca106725	2017
Kojto	122:f9eeca106725	2018
Kojto	122:f9eeca106725	2019	/** \brief Enable D-Cache
Kojto	122:f9eeca106725	2020
Kojto	122:f9eeca106725	2021	The function turns on D-Cache
Kojto	122:f9eeca106725	2022	*/
Kojto	122:f9eeca106725	2023	__STATIC_INLINE void SCB_EnableDCache (void)
Kojto	122:f9eeca106725	2024	{
Kojto	122:f9eeca106725	2025	#if (__DCACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2026	uint32_t ccsidr, sshift, wshift, sw;
Kojto	122:f9eeca106725	2027	uint32_t sets, ways;
Kojto	122:f9eeca106725	2028
Kojto	122:f9eeca106725	2029	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Kojto	122:f9eeca106725	2030	ccsidr = SCB->CCSIDR;
Kojto	122:f9eeca106725	2031	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto	122:f9eeca106725	2032	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto	122:f9eeca106725	2033	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto	122:f9eeca106725	2034	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto	122:f9eeca106725	2035
Kojto	122:f9eeca106725	2036	__DSB();
Kojto	122:f9eeca106725	2037
Kojto	122:f9eeca106725	2038	do { // invalidate D-Cache
Kojto	122:f9eeca106725	2039	uint32_t tmpways = ways;
Kojto	122:f9eeca106725	2040	do {
Kojto	122:f9eeca106725	2041	sw = ((tmpways << wshift) \| (sets << sshift));
Kojto	122:f9eeca106725	2042	SCB->DCISW = sw;
Kojto	122:f9eeca106725	2043	} while(tmpways--);
Kojto	122:f9eeca106725	2044	} while(sets--);
Kojto	122:f9eeca106725	2045	__DSB();
Kojto	122:f9eeca106725	2046
Kojto	122:f9eeca106725	2047	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
Kojto	122:f9eeca106725	2048
Kojto	122:f9eeca106725	2049	__DSB();
Kojto	122:f9eeca106725	2050	__ISB();
Kojto	122:f9eeca106725	2051	#endif
Kojto	122:f9eeca106725	2052	}
Kojto	122:f9eeca106725	2053
Kojto	122:f9eeca106725	2054
Kojto	122:f9eeca106725	2055	/** \brief Disable D-Cache
Kojto	122:f9eeca106725	2056
Kojto	122:f9eeca106725	2057	The function turns off D-Cache
Kojto	122:f9eeca106725	2058	*/
Kojto	122:f9eeca106725	2059	__STATIC_INLINE void SCB_DisableDCache (void)
Kojto	122:f9eeca106725	2060	{
Kojto	122:f9eeca106725	2061	#if (__DCACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2062	uint32_t ccsidr, sshift, wshift, sw;
Kojto	122:f9eeca106725	2063	uint32_t sets, ways;
Kojto	122:f9eeca106725	2064
Kojto	122:f9eeca106725	2065	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Kojto	122:f9eeca106725	2066	ccsidr = SCB->CCSIDR;
Kojto	122:f9eeca106725	2067	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto	122:f9eeca106725	2068	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto	122:f9eeca106725	2069	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto	122:f9eeca106725	2070	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto	122:f9eeca106725	2071
Kojto	122:f9eeca106725	2072	__DSB();
Kojto	122:f9eeca106725	2073
Kojto	122:f9eeca106725	2074	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
Kojto	122:f9eeca106725	2075
Kojto	122:f9eeca106725	2076	do { // clean & invalidate D-Cache
Kojto	122:f9eeca106725	2077	uint32_t tmpways = ways;
Kojto	122:f9eeca106725	2078	do {
Kojto	122:f9eeca106725	2079	sw = ((tmpways << wshift) \| (sets << sshift));
Kojto	122:f9eeca106725	2080	SCB->DCCISW = sw;
Kojto	122:f9eeca106725	2081	} while(tmpways--);
Kojto	122:f9eeca106725	2082	} while(sets--);
Kojto	122:f9eeca106725	2083
Kojto	122:f9eeca106725	2084
Kojto	122:f9eeca106725	2085	__DSB();
Kojto	122:f9eeca106725	2086	__ISB();
Kojto	122:f9eeca106725	2087	#endif
Kojto	122:f9eeca106725	2088	}
Kojto	122:f9eeca106725	2089
Kojto	122:f9eeca106725	2090
Kojto	122:f9eeca106725	2091	/** \brief Invalidate D-Cache
Kojto	122:f9eeca106725	2092
Kojto	122:f9eeca106725	2093	The function invalidates D-Cache
Kojto	122:f9eeca106725	2094	*/
Kojto	122:f9eeca106725	2095	__STATIC_INLINE void SCB_InvalidateDCache (void)
Kojto	122:f9eeca106725	2096	{
Kojto	122:f9eeca106725	2097	#if (__DCACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2098	uint32_t ccsidr, sshift, wshift, sw;
Kojto	122:f9eeca106725	2099	uint32_t sets, ways;
Kojto	122:f9eeca106725	2100
Kojto	122:f9eeca106725	2101	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Kojto	122:f9eeca106725	2102	ccsidr = SCB->CCSIDR;
Kojto	122:f9eeca106725	2103	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto	122:f9eeca106725	2104	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto	122:f9eeca106725	2105	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto	122:f9eeca106725	2106	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto	122:f9eeca106725	2107
Kojto	122:f9eeca106725	2108	__DSB();
Kojto	122:f9eeca106725	2109
Kojto	122:f9eeca106725	2110	do { // invalidate D-Cache
Kojto	122:f9eeca106725	2111	uint32_t tmpways = ways;
Kojto	122:f9eeca106725	2112	do {
Kojto	122:f9eeca106725	2113	sw = ((tmpways << wshift) \| (sets << sshift));
Kojto	122:f9eeca106725	2114	SCB->DCISW = sw;
Kojto	122:f9eeca106725	2115	} while(tmpways--);
Kojto	122:f9eeca106725	2116	} while(sets--);
Kojto	122:f9eeca106725	2117
Kojto	122:f9eeca106725	2118	__DSB();
Kojto	122:f9eeca106725	2119	__ISB();
Kojto	122:f9eeca106725	2120	#endif
Kojto	122:f9eeca106725	2121	}
Kojto	122:f9eeca106725	2122
Kojto	122:f9eeca106725	2123
Kojto	122:f9eeca106725	2124	/** \brief Clean D-Cache
Kojto	122:f9eeca106725	2125
Kojto	122:f9eeca106725	2126	The function cleans D-Cache
Kojto	122:f9eeca106725	2127	*/
Kojto	122:f9eeca106725	2128	__STATIC_INLINE void SCB_CleanDCache (void)
Kojto	122:f9eeca106725	2129	{
Kojto	122:f9eeca106725	2130	#if (__DCACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2131	uint32_t ccsidr, sshift, wshift, sw;
Kojto	122:f9eeca106725	2132	uint32_t sets, ways;
Kojto	122:f9eeca106725	2133
Kojto	122:f9eeca106725	2134	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Kojto	122:f9eeca106725	2135	ccsidr = SCB->CCSIDR;
Kojto	122:f9eeca106725	2136	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto	122:f9eeca106725	2137	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto	122:f9eeca106725	2138	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto	122:f9eeca106725	2139	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto	122:f9eeca106725	2140
Kojto	122:f9eeca106725	2141	__DSB();
Kojto	122:f9eeca106725	2142
Kojto	122:f9eeca106725	2143	do { // clean D-Cache
Kojto	122:f9eeca106725	2144	uint32_t tmpways = ways;
Kojto	122:f9eeca106725	2145	do {
Kojto	122:f9eeca106725	2146	sw = ((tmpways << wshift) \| (sets << sshift));
Kojto	122:f9eeca106725	2147	SCB->DCCSW = sw;
Kojto	122:f9eeca106725	2148	} while(tmpways--);
Kojto	122:f9eeca106725	2149	} while(sets--);
Kojto	122:f9eeca106725	2150
Kojto	122:f9eeca106725	2151	__DSB();
Kojto	122:f9eeca106725	2152	__ISB();
Kojto	122:f9eeca106725	2153	#endif
Kojto	122:f9eeca106725	2154	}
Kojto	122:f9eeca106725	2155
Kojto	122:f9eeca106725	2156
Kojto	122:f9eeca106725	2157	/** \brief Clean & Invalidate D-Cache
Kojto	122:f9eeca106725	2158
Kojto	122:f9eeca106725	2159	The function cleans and Invalidates D-Cache
Kojto	122:f9eeca106725	2160	*/
Kojto	122:f9eeca106725	2161	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
Kojto	122:f9eeca106725	2162	{
Kojto	122:f9eeca106725	2163	#if (__DCACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2164	uint32_t ccsidr, sshift, wshift, sw;
Kojto	122:f9eeca106725	2165	uint32_t sets, ways;
Kojto	122:f9eeca106725	2166
Kojto	122:f9eeca106725	2167	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
Kojto	122:f9eeca106725	2168	ccsidr = SCB->CCSIDR;
Kojto	122:f9eeca106725	2169	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto	122:f9eeca106725	2170	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto	122:f9eeca106725	2171	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto	122:f9eeca106725	2172	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto	122:f9eeca106725	2173
Kojto	122:f9eeca106725	2174	__DSB();
Kojto	122:f9eeca106725	2175
Kojto	122:f9eeca106725	2176	do { // clean & invalidate D-Cache
Kojto	122:f9eeca106725	2177	uint32_t tmpways = ways;
Kojto	122:f9eeca106725	2178	do {
Kojto	122:f9eeca106725	2179	sw = ((tmpways << wshift) \| (sets << sshift));
Kojto	122:f9eeca106725	2180	SCB->DCCISW = sw;
Kojto	122:f9eeca106725	2181	} while(tmpways--);
Kojto	122:f9eeca106725	2182	} while(sets--);
Kojto	122:f9eeca106725	2183
Kojto	122:f9eeca106725	2184	__DSB();
Kojto	122:f9eeca106725	2185	__ISB();
Kojto	122:f9eeca106725	2186	#endif
Kojto	122:f9eeca106725	2187	}
Kojto	122:f9eeca106725	2188
Kojto	122:f9eeca106725	2189
Kojto	122:f9eeca106725	2190	/**
Kojto	122:f9eeca106725	2191	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto	122:f9eeca106725	2192	\brief D-Cache Invalidate by address
Kojto	122:f9eeca106725	2193	\param[in] addr address (aligned to 32-byte boundary)
Kojto	122:f9eeca106725	2194	\param[in] dsize size of memory block (in number of bytes)
Kojto	122:f9eeca106725	2195	*/
Kojto	122:f9eeca106725	2196	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto	122:f9eeca106725	2197	{
Kojto	122:f9eeca106725	2198	#if (__DCACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2199	int32_t op_size = dsize;
Kojto	122:f9eeca106725	2200	uint32_t op_addr = (uint32_t)addr;
Kojto	122:f9eeca106725	2201	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto	122:f9eeca106725	2202
Kojto	122:f9eeca106725	2203	__DSB();
Kojto	122:f9eeca106725	2204
Kojto	122:f9eeca106725	2205	while (op_size > 0) {
Kojto	122:f9eeca106725	2206	SCB->DCIMVAC = op_addr;
Kojto	122:f9eeca106725	2207	op_addr += linesize;
Kojto	122:f9eeca106725	2208	op_size -= (int32_t)linesize;
Kojto	122:f9eeca106725	2209	}
Kojto	122:f9eeca106725	2210
Kojto	122:f9eeca106725	2211	__DSB();
Kojto	122:f9eeca106725	2212	__ISB();
Kojto	122:f9eeca106725	2213	#endif
Kojto	122:f9eeca106725	2214	}
Kojto	122:f9eeca106725	2215
Kojto	122:f9eeca106725	2216
Kojto	122:f9eeca106725	2217	/**
Kojto	122:f9eeca106725	2218	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto	122:f9eeca106725	2219	\brief D-Cache Clean by address
Kojto	122:f9eeca106725	2220	\param[in] addr address (aligned to 32-byte boundary)
Kojto	122:f9eeca106725	2221	\param[in] dsize size of memory block (in number of bytes)
Kojto	122:f9eeca106725	2222	*/
Kojto	122:f9eeca106725	2223	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto	122:f9eeca106725	2224	{
Kojto	122:f9eeca106725	2225	#if (__DCACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2226	int32_t op_size = dsize;
Kojto	122:f9eeca106725	2227	uint32_t op_addr = (uint32_t) addr;
Kojto	122:f9eeca106725	2228	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto	122:f9eeca106725	2229
Kojto	122:f9eeca106725	2230	__DSB();
Kojto	122:f9eeca106725	2231
Kojto	122:f9eeca106725	2232	while (op_size > 0) {
Kojto	122:f9eeca106725	2233	SCB->DCCMVAC = op_addr;
Kojto	122:f9eeca106725	2234	op_addr += linesize;
Kojto	122:f9eeca106725	2235	op_size -= (int32_t)linesize;
Kojto	122:f9eeca106725	2236	}
Kojto	122:f9eeca106725	2237
Kojto	122:f9eeca106725	2238	__DSB();
Kojto	122:f9eeca106725	2239	__ISB();
Kojto	122:f9eeca106725	2240	#endif
Kojto	122:f9eeca106725	2241	}
Kojto	122:f9eeca106725	2242
Kojto	122:f9eeca106725	2243
Kojto	122:f9eeca106725	2244	/**
Kojto	122:f9eeca106725	2245	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto	122:f9eeca106725	2246	\brief D-Cache Clean and Invalidate by address
Kojto	122:f9eeca106725	2247	\param[in] addr address (aligned to 32-byte boundary)
Kojto	122:f9eeca106725	2248	\param[in] dsize size of memory block (in number of bytes)
Kojto	122:f9eeca106725	2249	*/
Kojto	122:f9eeca106725	2250	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto	122:f9eeca106725	2251	{
Kojto	122:f9eeca106725	2252	#if (__DCACHE_PRESENT == 1)
Kojto	122:f9eeca106725	2253	int32_t op_size = dsize;
Kojto	122:f9eeca106725	2254	uint32_t op_addr = (uint32_t) addr;
Kojto	122:f9eeca106725	2255	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto	122:f9eeca106725	2256
Kojto	122:f9eeca106725	2257	__DSB();
Kojto	122:f9eeca106725	2258
Kojto	122:f9eeca106725	2259	while (op_size > 0) {
Kojto	122:f9eeca106725	2260	SCB->DCCIMVAC = op_addr;
Kojto	122:f9eeca106725	2261	op_addr += linesize;
Kojto	122:f9eeca106725	2262	op_size -= (int32_t)linesize;
Kojto	122:f9eeca106725	2263	}
Kojto	122:f9eeca106725	2264
Kojto	122:f9eeca106725	2265	__DSB();
Kojto	122:f9eeca106725	2266	__ISB();
Kojto	122:f9eeca106725	2267	#endif
Kojto	122:f9eeca106725	2268	}
Kojto	122:f9eeca106725	2269
Kojto	122:f9eeca106725	2270
Kojto	122:f9eeca106725	2271	/@} end of CMSIS_Core_CacheFunctions /
Kojto	122:f9eeca106725	2272
Kojto	122:f9eeca106725	2273
Kojto	122:f9eeca106725	2274
Kojto	122:f9eeca106725	2275	/* ################################## SysTick function ############################################ */
Kojto	122:f9eeca106725	2276	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	2277	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto	122:f9eeca106725	2278	\brief Functions that configure the System.
Kojto	122:f9eeca106725	2279	@{
Kojto	122:f9eeca106725	2280	*/
Kojto	122:f9eeca106725	2281
Kojto	122:f9eeca106725	2282	#if (__Vendor_SysTickConfig == 0)
Kojto	122:f9eeca106725	2283
Kojto	122:f9eeca106725	2284	/** \brief System Tick Configuration
Kojto	122:f9eeca106725	2285
Kojto	122:f9eeca106725	2286	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto	122:f9eeca106725	2287	Counter is in free running mode to generate periodic interrupts.
Kojto	122:f9eeca106725	2288
Kojto	122:f9eeca106725	2289	\param [in] ticks Number of ticks between two interrupts.
Kojto	122:f9eeca106725	2290
Kojto	122:f9eeca106725	2291	\return 0 Function succeeded.
Kojto	122:f9eeca106725	2292	\return 1 Function failed.
Kojto	122:f9eeca106725	2293
Kojto	122:f9eeca106725	2294	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	122:f9eeca106725	2295	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	122:f9eeca106725	2296	must contain a vendor-specific implementation of this function.
Kojto	122:f9eeca106725	2297
Kojto	122:f9eeca106725	2298	*/
Kojto	122:f9eeca106725	2299	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto	122:f9eeca106725	2300	{
Kojto	122:f9eeca106725	2301	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto	122:f9eeca106725	2302
Kojto	122:f9eeca106725	2303	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto	122:f9eeca106725	2304	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto	122:f9eeca106725	2305	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto	122:f9eeca106725	2306	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	122:f9eeca106725	2307	SysTick_CTRL_TICKINT_Msk \|
Kojto	122:f9eeca106725	2308	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	122:f9eeca106725	2309	return (0UL); /* Function successful */
Kojto	122:f9eeca106725	2310	}
Kojto	122:f9eeca106725	2311
Kojto	122:f9eeca106725	2312	#endif
Kojto	122:f9eeca106725	2313
Kojto	122:f9eeca106725	2314	/@} end of CMSIS_Core_SysTickFunctions /
Kojto	122:f9eeca106725	2315
Kojto	122:f9eeca106725	2316
Kojto	122:f9eeca106725	2317
Kojto	122:f9eeca106725	2318	/* ##################################### Debug In/Output function ########################################### */
Kojto	122:f9eeca106725	2319	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	122:f9eeca106725	2320	\defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto	122:f9eeca106725	2321	\brief Functions that access the ITM debug interface.
Kojto	122:f9eeca106725	2322	@{
Kojto	122:f9eeca106725	2323	*/
Kojto	122:f9eeca106725	2324
Kojto	122:f9eeca106725	2325	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Kojto	122:f9eeca106725	2326	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Kojto	122:f9eeca106725	2327
Kojto	122:f9eeca106725	2328
Kojto	122:f9eeca106725	2329	/** \brief ITM Send Character
Kojto	122:f9eeca106725	2330
Kojto	122:f9eeca106725	2331	The function transmits a character via the ITM channel 0, and
Kojto	122:f9eeca106725	2332	\li Just returns when no debugger is connected that has booked the output.
Kojto	122:f9eeca106725	2333	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto	122:f9eeca106725	2334
Kojto	122:f9eeca106725	2335	\param [in] ch Character to transmit.
Kojto	122:f9eeca106725	2336
Kojto	122:f9eeca106725	2337	\returns Character to transmit.
Kojto	122:f9eeca106725	2338	*/
Kojto	122:f9eeca106725	2339	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto	122:f9eeca106725	2340	{
Kojto	122:f9eeca106725	2341	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto	122:f9eeca106725	2342	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto	122:f9eeca106725	2343	{
Kojto	122:f9eeca106725	2344	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto	122:f9eeca106725	2345	ITM->PORT[0].u8 = (uint8_t)ch;
Kojto	122:f9eeca106725	2346	}
Kojto	122:f9eeca106725	2347	return (ch);
Kojto	122:f9eeca106725	2348	}
Kojto	122:f9eeca106725	2349
Kojto	122:f9eeca106725	2350
Kojto	122:f9eeca106725	2351	/** \brief ITM Receive Character
Kojto	122:f9eeca106725	2352
Kojto	122:f9eeca106725	2353	The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto	122:f9eeca106725	2354
Kojto	122:f9eeca106725	2355	\return Received character.
Kojto	122:f9eeca106725	2356	\return -1 No character pending.
Kojto	122:f9eeca106725	2357	*/
Kojto	122:f9eeca106725	2358	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto	122:f9eeca106725	2359	int32_t ch = -1; /* no character available */
Kojto	122:f9eeca106725	2360
Kojto	122:f9eeca106725	2361	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto	122:f9eeca106725	2362	ch = ITM_RxBuffer;
Kojto	122:f9eeca106725	2363	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto	122:f9eeca106725	2364	}
Kojto	122:f9eeca106725	2365
Kojto	122:f9eeca106725	2366	return (ch);
Kojto	122:f9eeca106725	2367	}
Kojto	122:f9eeca106725	2368
Kojto	122:f9eeca106725	2369
Kojto	122:f9eeca106725	2370	/** \brief ITM Check Character
Kojto	122:f9eeca106725	2371
Kojto	122:f9eeca106725	2372	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto	122:f9eeca106725	2373
Kojto	122:f9eeca106725	2374	\return 0 No character available.
Kojto	122:f9eeca106725	2375	\return 1 Character available.
Kojto	122:f9eeca106725	2376	*/
Kojto	122:f9eeca106725	2377	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto	122:f9eeca106725	2378
Kojto	122:f9eeca106725	2379	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto	122:f9eeca106725	2380	return (0); /* no character available */
Kojto	122:f9eeca106725	2381	} else {
Kojto	122:f9eeca106725	2382	return (1); /* character available */
Kojto	122:f9eeca106725	2383	}
Kojto	122:f9eeca106725	2384	}
Kojto	122:f9eeca106725	2385
Kojto	122:f9eeca106725	2386	/@} end of CMSIS_core_DebugFunctions /
Kojto	122:f9eeca106725	2387
Kojto	122:f9eeca106725	2388
Kojto	122:f9eeca106725	2389
Kojto	122:f9eeca106725	2390
Kojto	122:f9eeca106725	2391	#ifdef __cplusplus
Kojto	122:f9eeca106725	2392	}
Kojto	122:f9eeca106725	2393	#endif
Kojto	122:f9eeca106725	2394
Kojto	122:f9eeca106725	2395	#endif /* __CORE_CM7_H_DEPENDANT */
Kojto	122:f9eeca106725	2396
Kojto	122:f9eeca106725	2397	#endif /* __CMSIS_GENERIC */