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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_ARM_IOTSS_BEID/core_cm0plus.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Child:
128:9bcdf88f62b0
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**************************************************************************//**
Kojto 122:f9eeca106725 2 * @file core_cm0plus.h
Kojto 122:f9eeca106725 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 122:f9eeca106725 4 * @version V4.10
Kojto 122:f9eeca106725 5 * @date 18. March 2015
Kojto 122:f9eeca106725 6 *
Kojto 122:f9eeca106725 7 * @note
Kojto 122:f9eeca106725 8 *
Kojto 122:f9eeca106725 9 ******************************************************************************/
Kojto 122:f9eeca106725 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 122:f9eeca106725 11
Kojto 122:f9eeca106725 12 All rights reserved.
Kojto 122:f9eeca106725 13 Redistribution and use in source and binary forms, with or without
Kojto 122:f9eeca106725 14 modification, are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 15 - Redistributions of source code must retain the above copyright
Kojto 122:f9eeca106725 16 notice, this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 17 - Redistributions in binary form must reproduce the above copyright
Kojto 122:f9eeca106725 18 notice, this list of conditions and the following disclaimer in the
Kojto 122:f9eeca106725 19 documentation and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 122:f9eeca106725 21 to endorse or promote products derived from this software without
Kojto 122:f9eeca106725 22 specific prior written permission.
Kojto 122:f9eeca106725 23 *
Kojto 122:f9eeca106725 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 122:f9eeca106725 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 122:f9eeca106725 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 122:f9eeca106725 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 122:f9eeca106725 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 122:f9eeca106725 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 122:f9eeca106725 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 122:f9eeca106725 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 122:f9eeca106725 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 35 ---------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 36
Kojto 122:f9eeca106725 37
Kojto 122:f9eeca106725 38 #if defined ( __ICCARM__ )
Kojto 122:f9eeca106725 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 122:f9eeca106725 40 #endif
Kojto 122:f9eeca106725 41
Kojto 122:f9eeca106725 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 122:f9eeca106725 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 122:f9eeca106725 44
Kojto 122:f9eeca106725 45 #ifdef __cplusplus
Kojto 122:f9eeca106725 46 extern "C" {
Kojto 122:f9eeca106725 47 #endif
Kojto 122:f9eeca106725 48
Kojto 122:f9eeca106725 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 122:f9eeca106725 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 122:f9eeca106725 51
Kojto 122:f9eeca106725 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 122:f9eeca106725 53 Function definitions in header files are used to allow 'inlining'.
Kojto 122:f9eeca106725 54
Kojto 122:f9eeca106725 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 122:f9eeca106725 56 Unions are used for effective representation of core registers.
Kojto 122:f9eeca106725 57
Kojto 122:f9eeca106725 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 122:f9eeca106725 59 Function-like macros are used to allow more efficient code.
Kojto 122:f9eeca106725 60 */
Kojto 122:f9eeca106725 61
Kojto 122:f9eeca106725 62
Kojto 122:f9eeca106725 63 /*******************************************************************************
Kojto 122:f9eeca106725 64 * CMSIS definitions
Kojto 122:f9eeca106725 65 ******************************************************************************/
Kojto 122:f9eeca106725 66 /** \ingroup Cortex-M0+
Kojto 122:f9eeca106725 67 @{
Kojto 122:f9eeca106725 68 */
Kojto 122:f9eeca106725 69
Kojto 122:f9eeca106725 70 /* CMSIS CM0P definitions */
Kojto 122:f9eeca106725 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 122:f9eeca106725 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 122:f9eeca106725 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 122:f9eeca106725 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 122:f9eeca106725 77
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 #if defined ( __CC_ARM )
Kojto 122:f9eeca106725 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 122:f9eeca106725 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 122:f9eeca106725 82 #define __STATIC_INLINE static __inline
Kojto 122:f9eeca106725 83
Kojto 122:f9eeca106725 84 #elif defined ( __GNUC__ )
Kojto 122:f9eeca106725 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 122:f9eeca106725 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 122:f9eeca106725 87 #define __STATIC_INLINE static inline
Kojto 122:f9eeca106725 88
Kojto 122:f9eeca106725 89 #elif defined ( __ICCARM__ )
Kojto 122:f9eeca106725 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 122:f9eeca106725 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 122:f9eeca106725 92 #define __STATIC_INLINE static inline
Kojto 122:f9eeca106725 93
Kojto 122:f9eeca106725 94 #elif defined ( __TMS470__ )
Kojto 122:f9eeca106725 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 122:f9eeca106725 96 #define __STATIC_INLINE static inline
Kojto 122:f9eeca106725 97
Kojto 122:f9eeca106725 98 #elif defined ( __TASKING__ )
Kojto 122:f9eeca106725 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 122:f9eeca106725 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 122:f9eeca106725 101 #define __STATIC_INLINE static inline
Kojto 122:f9eeca106725 102
Kojto 122:f9eeca106725 103 #elif defined ( __CSMC__ )
Kojto 122:f9eeca106725 104 #define __packed
Kojto 122:f9eeca106725 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 122:f9eeca106725 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 122:f9eeca106725 107 #define __STATIC_INLINE static inline
Kojto 122:f9eeca106725 108
Kojto 122:f9eeca106725 109 #endif
Kojto 122:f9eeca106725 110
Kojto 122:f9eeca106725 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 122:f9eeca106725 112 This core does not support an FPU at all
Kojto 122:f9eeca106725 113 */
Kojto 122:f9eeca106725 114 #define __FPU_USED 0
Kojto 122:f9eeca106725 115
Kojto 122:f9eeca106725 116 #if defined ( __CC_ARM )
Kojto 122:f9eeca106725 117 #if defined __TARGET_FPU_VFP
Kojto 122:f9eeca106725 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 122:f9eeca106725 119 #endif
Kojto 122:f9eeca106725 120
Kojto 122:f9eeca106725 121 #elif defined ( __GNUC__ )
Kojto 122:f9eeca106725 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 122:f9eeca106725 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 122:f9eeca106725 124 #endif
Kojto 122:f9eeca106725 125
Kojto 122:f9eeca106725 126 #elif defined ( __ICCARM__ )
Kojto 122:f9eeca106725 127 #if defined __ARMVFP__
Kojto 122:f9eeca106725 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 122:f9eeca106725 129 #endif
Kojto 122:f9eeca106725 130
Kojto 122:f9eeca106725 131 #elif defined ( __TMS470__ )
Kojto 122:f9eeca106725 132 #if defined __TI__VFP_SUPPORT____
Kojto 122:f9eeca106725 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 122:f9eeca106725 134 #endif
Kojto 122:f9eeca106725 135
Kojto 122:f9eeca106725 136 #elif defined ( __TASKING__ )
Kojto 122:f9eeca106725 137 #if defined __FPU_VFP__
Kojto 122:f9eeca106725 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 122:f9eeca106725 139 #endif
Kojto 122:f9eeca106725 140
Kojto 122:f9eeca106725 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 122:f9eeca106725 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 122:f9eeca106725 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 122:f9eeca106725 144 #endif
Kojto 122:f9eeca106725 145 #endif
Kojto 122:f9eeca106725 146
Kojto 122:f9eeca106725 147 #include <stdint.h> /* standard types definitions */
Kojto 122:f9eeca106725 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 122:f9eeca106725 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 122:f9eeca106725 150
Kojto 122:f9eeca106725 151 #ifdef __cplusplus
Kojto 122:f9eeca106725 152 }
Kojto 122:f9eeca106725 153 #endif
Kojto 122:f9eeca106725 154
Kojto 122:f9eeca106725 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 122:f9eeca106725 156
Kojto 122:f9eeca106725 157 #ifndef __CMSIS_GENERIC
Kojto 122:f9eeca106725 158
Kojto 122:f9eeca106725 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 122:f9eeca106725 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 122:f9eeca106725 161
Kojto 122:f9eeca106725 162 #ifdef __cplusplus
Kojto 122:f9eeca106725 163 extern "C" {
Kojto 122:f9eeca106725 164 #endif
Kojto 122:f9eeca106725 165
Kojto 122:f9eeca106725 166 /* check device defines and use defaults */
Kojto 122:f9eeca106725 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 122:f9eeca106725 168 #ifndef __CM0PLUS_REV
Kojto 122:f9eeca106725 169 #define __CM0PLUS_REV 0x0000
Kojto 122:f9eeca106725 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 122:f9eeca106725 171 #endif
Kojto 122:f9eeca106725 172
Kojto 122:f9eeca106725 173 #ifndef __MPU_PRESENT
Kojto 122:f9eeca106725 174 #define __MPU_PRESENT 0
Kojto 122:f9eeca106725 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 122:f9eeca106725 176 #endif
Kojto 122:f9eeca106725 177
Kojto 122:f9eeca106725 178 #ifndef __VTOR_PRESENT
Kojto 122:f9eeca106725 179 #define __VTOR_PRESENT 0
Kojto 122:f9eeca106725 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 122:f9eeca106725 181 #endif
Kojto 122:f9eeca106725 182
Kojto 122:f9eeca106725 183 #ifndef __NVIC_PRIO_BITS
Kojto 122:f9eeca106725 184 #define __NVIC_PRIO_BITS 2
Kojto 122:f9eeca106725 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 122:f9eeca106725 186 #endif
Kojto 122:f9eeca106725 187
Kojto 122:f9eeca106725 188 #ifndef __Vendor_SysTickConfig
Kojto 122:f9eeca106725 189 #define __Vendor_SysTickConfig 0
Kojto 122:f9eeca106725 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 122:f9eeca106725 191 #endif
Kojto 122:f9eeca106725 192 #endif
Kojto 122:f9eeca106725 193
Kojto 122:f9eeca106725 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 122:f9eeca106725 195 /**
Kojto 122:f9eeca106725 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 122:f9eeca106725 197
Kojto 122:f9eeca106725 198 <strong>IO Type Qualifiers</strong> are used
Kojto 122:f9eeca106725 199 \li to specify the access to peripheral variables.
Kojto 122:f9eeca106725 200 \li for automatic generation of peripheral register debug information.
Kojto 122:f9eeca106725 201 */
Kojto 122:f9eeca106725 202 #ifdef __cplusplus
Kojto 122:f9eeca106725 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 122:f9eeca106725 204 #else
Kojto 122:f9eeca106725 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 122:f9eeca106725 206 #endif
Kojto 122:f9eeca106725 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 122:f9eeca106725 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 122:f9eeca106725 209
Kojto 122:f9eeca106725 210 /*@} end of group Cortex-M0+ */
Kojto 122:f9eeca106725 211
Kojto 122:f9eeca106725 212
Kojto 122:f9eeca106725 213
Kojto 122:f9eeca106725 214 /*******************************************************************************
Kojto 122:f9eeca106725 215 * Register Abstraction
Kojto 122:f9eeca106725 216 Core Register contain:
Kojto 122:f9eeca106725 217 - Core Register
Kojto 122:f9eeca106725 218 - Core NVIC Register
Kojto 122:f9eeca106725 219 - Core SCB Register
Kojto 122:f9eeca106725 220 - Core SysTick Register
Kojto 122:f9eeca106725 221 - Core MPU Register
Kojto 122:f9eeca106725 222 ******************************************************************************/
Kojto 122:f9eeca106725 223 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 122:f9eeca106725 224 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 122:f9eeca106725 225 */
Kojto 122:f9eeca106725 226
Kojto 122:f9eeca106725 227 /** \ingroup CMSIS_core_register
Kojto 122:f9eeca106725 228 \defgroup CMSIS_CORE Status and Control Registers
Kojto 122:f9eeca106725 229 \brief Core Register type definitions.
Kojto 122:f9eeca106725 230 @{
Kojto 122:f9eeca106725 231 */
Kojto 122:f9eeca106725 232
Kojto 122:f9eeca106725 233 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 122:f9eeca106725 234 */
Kojto 122:f9eeca106725 235 typedef union
Kojto 122:f9eeca106725 236 {
Kojto 122:f9eeca106725 237 struct
Kojto 122:f9eeca106725 238 {
Kojto 122:f9eeca106725 239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 122:f9eeca106725 240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 122:f9eeca106725 241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 122:f9eeca106725 242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 122:f9eeca106725 243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 122:f9eeca106725 244 } b; /*!< Structure used for bit access */
Kojto 122:f9eeca106725 245 uint32_t w; /*!< Type used for word access */
Kojto 122:f9eeca106725 246 } APSR_Type;
Kojto 122:f9eeca106725 247
Kojto 122:f9eeca106725 248 /* APSR Register Definitions */
Kojto 122:f9eeca106725 249 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 122:f9eeca106725 250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 122:f9eeca106725 251
Kojto 122:f9eeca106725 252 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 122:f9eeca106725 253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 122:f9eeca106725 254
Kojto 122:f9eeca106725 255 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 122:f9eeca106725 256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 122:f9eeca106725 257
Kojto 122:f9eeca106725 258 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 122:f9eeca106725 259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 122:f9eeca106725 260
Kojto 122:f9eeca106725 261
Kojto 122:f9eeca106725 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 122:f9eeca106725 263 */
Kojto 122:f9eeca106725 264 typedef union
Kojto 122:f9eeca106725 265 {
Kojto 122:f9eeca106725 266 struct
Kojto 122:f9eeca106725 267 {
Kojto 122:f9eeca106725 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 122:f9eeca106725 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 122:f9eeca106725 270 } b; /*!< Structure used for bit access */
Kojto 122:f9eeca106725 271 uint32_t w; /*!< Type used for word access */
Kojto 122:f9eeca106725 272 } IPSR_Type;
Kojto 122:f9eeca106725 273
Kojto 122:f9eeca106725 274 /* IPSR Register Definitions */
Kojto 122:f9eeca106725 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 122:f9eeca106725 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 122:f9eeca106725 277
Kojto 122:f9eeca106725 278
Kojto 122:f9eeca106725 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 122:f9eeca106725 280 */
Kojto 122:f9eeca106725 281 typedef union
Kojto 122:f9eeca106725 282 {
Kojto 122:f9eeca106725 283 struct
Kojto 122:f9eeca106725 284 {
Kojto 122:f9eeca106725 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 122:f9eeca106725 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 122:f9eeca106725 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 122:f9eeca106725 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 122:f9eeca106725 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 122:f9eeca106725 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 122:f9eeca106725 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 122:f9eeca106725 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 122:f9eeca106725 293 } b; /*!< Structure used for bit access */
Kojto 122:f9eeca106725 294 uint32_t w; /*!< Type used for word access */
Kojto 122:f9eeca106725 295 } xPSR_Type;
Kojto 122:f9eeca106725 296
Kojto 122:f9eeca106725 297 /* xPSR Register Definitions */
Kojto 122:f9eeca106725 298 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 122:f9eeca106725 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 122:f9eeca106725 300
Kojto 122:f9eeca106725 301 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 122:f9eeca106725 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 122:f9eeca106725 303
Kojto 122:f9eeca106725 304 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 122:f9eeca106725 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 122:f9eeca106725 306
Kojto 122:f9eeca106725 307 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 122:f9eeca106725 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 122:f9eeca106725 309
Kojto 122:f9eeca106725 310 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 122:f9eeca106725 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 122:f9eeca106725 312
Kojto 122:f9eeca106725 313 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 122:f9eeca106725 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 122:f9eeca106725 315
Kojto 122:f9eeca106725 316
Kojto 122:f9eeca106725 317 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 122:f9eeca106725 318 */
Kojto 122:f9eeca106725 319 typedef union
Kojto 122:f9eeca106725 320 {
Kojto 122:f9eeca106725 321 struct
Kojto 122:f9eeca106725 322 {
Kojto 122:f9eeca106725 323 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 122:f9eeca106725 324 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 122:f9eeca106725 325 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 122:f9eeca106725 326 } b; /*!< Structure used for bit access */
Kojto 122:f9eeca106725 327 uint32_t w; /*!< Type used for word access */
Kojto 122:f9eeca106725 328 } CONTROL_Type;
Kojto 122:f9eeca106725 329
Kojto 122:f9eeca106725 330 /* CONTROL Register Definitions */
Kojto 122:f9eeca106725 331 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 122:f9eeca106725 332 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 122:f9eeca106725 333
Kojto 122:f9eeca106725 334 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 122:f9eeca106725 335 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 122:f9eeca106725 336
Kojto 122:f9eeca106725 337 /*@} end of group CMSIS_CORE */
Kojto 122:f9eeca106725 338
Kojto 122:f9eeca106725 339
Kojto 122:f9eeca106725 340 /** \ingroup CMSIS_core_register
Kojto 122:f9eeca106725 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 122:f9eeca106725 342 \brief Type definitions for the NVIC Registers
Kojto 122:f9eeca106725 343 @{
Kojto 122:f9eeca106725 344 */
Kojto 122:f9eeca106725 345
Kojto 122:f9eeca106725 346 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 122:f9eeca106725 347 */
Kojto 122:f9eeca106725 348 typedef struct
Kojto 122:f9eeca106725 349 {
Kojto 122:f9eeca106725 350 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 122:f9eeca106725 351 uint32_t RESERVED0[31];
Kojto 122:f9eeca106725 352 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 122:f9eeca106725 353 uint32_t RSERVED1[31];
Kojto 122:f9eeca106725 354 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 122:f9eeca106725 355 uint32_t RESERVED2[31];
Kojto 122:f9eeca106725 356 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 122:f9eeca106725 357 uint32_t RESERVED3[31];
Kojto 122:f9eeca106725 358 uint32_t RESERVED4[64];
Kojto 122:f9eeca106725 359 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 122:f9eeca106725 360 } NVIC_Type;
Kojto 122:f9eeca106725 361
Kojto 122:f9eeca106725 362 /*@} end of group CMSIS_NVIC */
Kojto 122:f9eeca106725 363
Kojto 122:f9eeca106725 364
Kojto 122:f9eeca106725 365 /** \ingroup CMSIS_core_register
Kojto 122:f9eeca106725 366 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 122:f9eeca106725 367 \brief Type definitions for the System Control Block Registers
Kojto 122:f9eeca106725 368 @{
Kojto 122:f9eeca106725 369 */
Kojto 122:f9eeca106725 370
Kojto 122:f9eeca106725 371 /** \brief Structure type to access the System Control Block (SCB).
Kojto 122:f9eeca106725 372 */
Kojto 122:f9eeca106725 373 typedef struct
Kojto 122:f9eeca106725 374 {
Kojto 122:f9eeca106725 375 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 122:f9eeca106725 376 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 122:f9eeca106725 377 #if (__VTOR_PRESENT == 1)
Kojto 122:f9eeca106725 378 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 122:f9eeca106725 379 #else
Kojto 122:f9eeca106725 380 uint32_t RESERVED0;
Kojto 122:f9eeca106725 381 #endif
Kojto 122:f9eeca106725 382 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 122:f9eeca106725 383 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 122:f9eeca106725 384 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 122:f9eeca106725 385 uint32_t RESERVED1;
Kojto 122:f9eeca106725 386 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 122:f9eeca106725 387 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 122:f9eeca106725 388 } SCB_Type;
Kojto 122:f9eeca106725 389
Kojto 122:f9eeca106725 390 /* SCB CPUID Register Definitions */
Kojto 122:f9eeca106725 391 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 122:f9eeca106725 392 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 122:f9eeca106725 393
Kojto 122:f9eeca106725 394 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 122:f9eeca106725 395 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 122:f9eeca106725 396
Kojto 122:f9eeca106725 397 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 122:f9eeca106725 398 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 122:f9eeca106725 399
Kojto 122:f9eeca106725 400 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 122:f9eeca106725 401 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 122:f9eeca106725 402
Kojto 122:f9eeca106725 403 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 122:f9eeca106725 404 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 122:f9eeca106725 405
Kojto 122:f9eeca106725 406 /* SCB Interrupt Control State Register Definitions */
Kojto 122:f9eeca106725 407 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 122:f9eeca106725 408 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 122:f9eeca106725 409
Kojto 122:f9eeca106725 410 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 122:f9eeca106725 411 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 122:f9eeca106725 412
Kojto 122:f9eeca106725 413 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 122:f9eeca106725 414 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 122:f9eeca106725 415
Kojto 122:f9eeca106725 416 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 122:f9eeca106725 417 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 122:f9eeca106725 418
Kojto 122:f9eeca106725 419 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 122:f9eeca106725 420 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 122:f9eeca106725 421
Kojto 122:f9eeca106725 422 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 122:f9eeca106725 423 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 122:f9eeca106725 424
Kojto 122:f9eeca106725 425 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 122:f9eeca106725 426 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 122:f9eeca106725 427
Kojto 122:f9eeca106725 428 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 122:f9eeca106725 429 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 122:f9eeca106725 430
Kojto 122:f9eeca106725 431 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 122:f9eeca106725 432 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 122:f9eeca106725 433
Kojto 122:f9eeca106725 434 #if (__VTOR_PRESENT == 1)
Kojto 122:f9eeca106725 435 /* SCB Interrupt Control State Register Definitions */
Kojto 122:f9eeca106725 436 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 122:f9eeca106725 437 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 122:f9eeca106725 438 #endif
Kojto 122:f9eeca106725 439
Kojto 122:f9eeca106725 440 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 122:f9eeca106725 441 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 122:f9eeca106725 442 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 122:f9eeca106725 443
Kojto 122:f9eeca106725 444 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 122:f9eeca106725 445 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 122:f9eeca106725 446
Kojto 122:f9eeca106725 447 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 122:f9eeca106725 448 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 122:f9eeca106725 449
Kojto 122:f9eeca106725 450 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 122:f9eeca106725 451 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 122:f9eeca106725 452
Kojto 122:f9eeca106725 453 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 122:f9eeca106725 454 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 122:f9eeca106725 455
Kojto 122:f9eeca106725 456 /* SCB System Control Register Definitions */
Kojto 122:f9eeca106725 457 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 122:f9eeca106725 458 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 122:f9eeca106725 459
Kojto 122:f9eeca106725 460 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 122:f9eeca106725 461 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 122:f9eeca106725 462
Kojto 122:f9eeca106725 463 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 122:f9eeca106725 464 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 122:f9eeca106725 465
Kojto 122:f9eeca106725 466 /* SCB Configuration Control Register Definitions */
Kojto 122:f9eeca106725 467 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 122:f9eeca106725 468 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 122:f9eeca106725 469
Kojto 122:f9eeca106725 470 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 122:f9eeca106725 471 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 122:f9eeca106725 472
Kojto 122:f9eeca106725 473 /* SCB System Handler Control and State Register Definitions */
Kojto 122:f9eeca106725 474 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 122:f9eeca106725 475 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 122:f9eeca106725 476
Kojto 122:f9eeca106725 477 /*@} end of group CMSIS_SCB */
Kojto 122:f9eeca106725 478
Kojto 122:f9eeca106725 479
Kojto 122:f9eeca106725 480 /** \ingroup CMSIS_core_register
Kojto 122:f9eeca106725 481 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 122:f9eeca106725 482 \brief Type definitions for the System Timer Registers.
Kojto 122:f9eeca106725 483 @{
Kojto 122:f9eeca106725 484 */
Kojto 122:f9eeca106725 485
Kojto 122:f9eeca106725 486 /** \brief Structure type to access the System Timer (SysTick).
Kojto 122:f9eeca106725 487 */
Kojto 122:f9eeca106725 488 typedef struct
Kojto 122:f9eeca106725 489 {
Kojto 122:f9eeca106725 490 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 122:f9eeca106725 491 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 122:f9eeca106725 492 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 122:f9eeca106725 493 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 122:f9eeca106725 494 } SysTick_Type;
Kojto 122:f9eeca106725 495
Kojto 122:f9eeca106725 496 /* SysTick Control / Status Register Definitions */
Kojto 122:f9eeca106725 497 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 122:f9eeca106725 498 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 122:f9eeca106725 499
Kojto 122:f9eeca106725 500 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 122:f9eeca106725 501 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 122:f9eeca106725 502
Kojto 122:f9eeca106725 503 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 122:f9eeca106725 504 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 122:f9eeca106725 505
Kojto 122:f9eeca106725 506 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 122:f9eeca106725 507 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 122:f9eeca106725 508
Kojto 122:f9eeca106725 509 /* SysTick Reload Register Definitions */
Kojto 122:f9eeca106725 510 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 122:f9eeca106725 511 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 122:f9eeca106725 512
Kojto 122:f9eeca106725 513 /* SysTick Current Register Definitions */
Kojto 122:f9eeca106725 514 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 122:f9eeca106725 515 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 122:f9eeca106725 516
Kojto 122:f9eeca106725 517 /* SysTick Calibration Register Definitions */
Kojto 122:f9eeca106725 518 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 122:f9eeca106725 519 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 122:f9eeca106725 520
Kojto 122:f9eeca106725 521 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 122:f9eeca106725 522 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 122:f9eeca106725 523
Kojto 122:f9eeca106725 524 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 122:f9eeca106725 525 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 122:f9eeca106725 526
Kojto 122:f9eeca106725 527 /*@} end of group CMSIS_SysTick */
Kojto 122:f9eeca106725 528
Kojto 122:f9eeca106725 529 #if (__MPU_PRESENT == 1)
Kojto 122:f9eeca106725 530 /** \ingroup CMSIS_core_register
Kojto 122:f9eeca106725 531 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 122:f9eeca106725 532 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 122:f9eeca106725 533 @{
Kojto 122:f9eeca106725 534 */
Kojto 122:f9eeca106725 535
Kojto 122:f9eeca106725 536 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 122:f9eeca106725 537 */
Kojto 122:f9eeca106725 538 typedef struct
Kojto 122:f9eeca106725 539 {
Kojto 122:f9eeca106725 540 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 122:f9eeca106725 541 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 122:f9eeca106725 542 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 122:f9eeca106725 543 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 122:f9eeca106725 544 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 122:f9eeca106725 545 } MPU_Type;
Kojto 122:f9eeca106725 546
Kojto 122:f9eeca106725 547 /* MPU Type Register */
Kojto 122:f9eeca106725 548 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 122:f9eeca106725 549 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 122:f9eeca106725 550
Kojto 122:f9eeca106725 551 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 122:f9eeca106725 552 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 122:f9eeca106725 553
Kojto 122:f9eeca106725 554 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 122:f9eeca106725 555 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 122:f9eeca106725 556
Kojto 122:f9eeca106725 557 /* MPU Control Register */
Kojto 122:f9eeca106725 558 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 122:f9eeca106725 559 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 122:f9eeca106725 560
Kojto 122:f9eeca106725 561 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 122:f9eeca106725 562 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 122:f9eeca106725 563
Kojto 122:f9eeca106725 564 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 122:f9eeca106725 565 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 122:f9eeca106725 566
Kojto 122:f9eeca106725 567 /* MPU Region Number Register */
Kojto 122:f9eeca106725 568 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 122:f9eeca106725 569 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 122:f9eeca106725 570
Kojto 122:f9eeca106725 571 /* MPU Region Base Address Register */
Kojto 122:f9eeca106725 572 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 122:f9eeca106725 573 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 122:f9eeca106725 574
Kojto 122:f9eeca106725 575 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 122:f9eeca106725 576 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 122:f9eeca106725 577
Kojto 122:f9eeca106725 578 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 122:f9eeca106725 579 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 122:f9eeca106725 580
Kojto 122:f9eeca106725 581 /* MPU Region Attribute and Size Register */
Kojto 122:f9eeca106725 582 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 122:f9eeca106725 583 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 122:f9eeca106725 584
Kojto 122:f9eeca106725 585 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 122:f9eeca106725 586 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 122:f9eeca106725 587
Kojto 122:f9eeca106725 588 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 122:f9eeca106725 589 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 122:f9eeca106725 590
Kojto 122:f9eeca106725 591 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 122:f9eeca106725 592 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 122:f9eeca106725 593
Kojto 122:f9eeca106725 594 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 122:f9eeca106725 595 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 122:f9eeca106725 596
Kojto 122:f9eeca106725 597 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 122:f9eeca106725 598 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 122:f9eeca106725 599
Kojto 122:f9eeca106725 600 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 122:f9eeca106725 601 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 122:f9eeca106725 602
Kojto 122:f9eeca106725 603 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 122:f9eeca106725 604 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 122:f9eeca106725 605
Kojto 122:f9eeca106725 606 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 122:f9eeca106725 607 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 122:f9eeca106725 608
Kojto 122:f9eeca106725 609 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 122:f9eeca106725 610 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 122:f9eeca106725 611
Kojto 122:f9eeca106725 612 /*@} end of group CMSIS_MPU */
Kojto 122:f9eeca106725 613 #endif
Kojto 122:f9eeca106725 614
Kojto 122:f9eeca106725 615
Kojto 122:f9eeca106725 616 /** \ingroup CMSIS_core_register
Kojto 122:f9eeca106725 617 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 122:f9eeca106725 618 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 122:f9eeca106725 619 are only accessible over DAP and not via processor. Therefore
Kojto 122:f9eeca106725 620 they are not covered by the Cortex-M0 header file.
Kojto 122:f9eeca106725 621 @{
Kojto 122:f9eeca106725 622 */
Kojto 122:f9eeca106725 623 /*@} end of group CMSIS_CoreDebug */
Kojto 122:f9eeca106725 624
Kojto 122:f9eeca106725 625
Kojto 122:f9eeca106725 626 /** \ingroup CMSIS_core_register
Kojto 122:f9eeca106725 627 \defgroup CMSIS_core_base Core Definitions
Kojto 122:f9eeca106725 628 \brief Definitions for base addresses, unions, and structures.
Kojto 122:f9eeca106725 629 @{
Kojto 122:f9eeca106725 630 */
Kojto 122:f9eeca106725 631
Kojto 122:f9eeca106725 632 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 122:f9eeca106725 633 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 122:f9eeca106725 634 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 122:f9eeca106725 635 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 122:f9eeca106725 636 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 122:f9eeca106725 637
Kojto 122:f9eeca106725 638 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 122:f9eeca106725 639 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 122:f9eeca106725 640 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 122:f9eeca106725 641
Kojto 122:f9eeca106725 642 #if (__MPU_PRESENT == 1)
Kojto 122:f9eeca106725 643 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 122:f9eeca106725 644 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 122:f9eeca106725 645 #endif
Kojto 122:f9eeca106725 646
Kojto 122:f9eeca106725 647 /*@} */
Kojto 122:f9eeca106725 648
Kojto 122:f9eeca106725 649
Kojto 122:f9eeca106725 650
Kojto 122:f9eeca106725 651 /*******************************************************************************
Kojto 122:f9eeca106725 652 * Hardware Abstraction Layer
Kojto 122:f9eeca106725 653 Core Function Interface contains:
Kojto 122:f9eeca106725 654 - Core NVIC Functions
Kojto 122:f9eeca106725 655 - Core SysTick Functions
Kojto 122:f9eeca106725 656 - Core Register Access Functions
Kojto 122:f9eeca106725 657 ******************************************************************************/
Kojto 122:f9eeca106725 658 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 122:f9eeca106725 659 */
Kojto 122:f9eeca106725 660
Kojto 122:f9eeca106725 661
Kojto 122:f9eeca106725 662
Kojto 122:f9eeca106725 663 /* ########################## NVIC functions #################################### */
Kojto 122:f9eeca106725 664 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 122:f9eeca106725 665 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 122:f9eeca106725 666 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 122:f9eeca106725 667 @{
Kojto 122:f9eeca106725 668 */
Kojto 122:f9eeca106725 669
Kojto 122:f9eeca106725 670 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 122:f9eeca106725 671 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 122:f9eeca106725 672 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 122:f9eeca106725 673 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 122:f9eeca106725 674 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 122:f9eeca106725 675
Kojto 122:f9eeca106725 676
Kojto 122:f9eeca106725 677 /** \brief Enable External Interrupt
Kojto 122:f9eeca106725 678
Kojto 122:f9eeca106725 679 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 122:f9eeca106725 680
Kojto 122:f9eeca106725 681 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 122:f9eeca106725 682 */
Kojto 122:f9eeca106725 683 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 122:f9eeca106725 684 {
Kojto 122:f9eeca106725 685 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 122:f9eeca106725 686 }
Kojto 122:f9eeca106725 687
Kojto 122:f9eeca106725 688
Kojto 122:f9eeca106725 689 /** \brief Disable External Interrupt
Kojto 122:f9eeca106725 690
Kojto 122:f9eeca106725 691 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 122:f9eeca106725 692
Kojto 122:f9eeca106725 693 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 122:f9eeca106725 694 */
Kojto 122:f9eeca106725 695 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 122:f9eeca106725 696 {
Kojto 122:f9eeca106725 697 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 122:f9eeca106725 698 }
Kojto 122:f9eeca106725 699
Kojto 122:f9eeca106725 700
Kojto 122:f9eeca106725 701 /** \brief Get Pending Interrupt
Kojto 122:f9eeca106725 702
Kojto 122:f9eeca106725 703 The function reads the pending register in the NVIC and returns the pending bit
Kojto 122:f9eeca106725 704 for the specified interrupt.
Kojto 122:f9eeca106725 705
Kojto 122:f9eeca106725 706 \param [in] IRQn Interrupt number.
Kojto 122:f9eeca106725 707
Kojto 122:f9eeca106725 708 \return 0 Interrupt status is not pending.
Kojto 122:f9eeca106725 709 \return 1 Interrupt status is pending.
Kojto 122:f9eeca106725 710 */
Kojto 122:f9eeca106725 711 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 122:f9eeca106725 712 {
Kojto 122:f9eeca106725 713 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 122:f9eeca106725 714 }
Kojto 122:f9eeca106725 715
Kojto 122:f9eeca106725 716
Kojto 122:f9eeca106725 717 /** \brief Set Pending Interrupt
Kojto 122:f9eeca106725 718
Kojto 122:f9eeca106725 719 The function sets the pending bit of an external interrupt.
Kojto 122:f9eeca106725 720
Kojto 122:f9eeca106725 721 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 122:f9eeca106725 722 */
Kojto 122:f9eeca106725 723 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 122:f9eeca106725 724 {
Kojto 122:f9eeca106725 725 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 122:f9eeca106725 726 }
Kojto 122:f9eeca106725 727
Kojto 122:f9eeca106725 728
Kojto 122:f9eeca106725 729 /** \brief Clear Pending Interrupt
Kojto 122:f9eeca106725 730
Kojto 122:f9eeca106725 731 The function clears the pending bit of an external interrupt.
Kojto 122:f9eeca106725 732
Kojto 122:f9eeca106725 733 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 122:f9eeca106725 734 */
Kojto 122:f9eeca106725 735 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 122:f9eeca106725 736 {
Kojto 122:f9eeca106725 737 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 122:f9eeca106725 738 }
Kojto 122:f9eeca106725 739
Kojto 122:f9eeca106725 740
Kojto 122:f9eeca106725 741 /** \brief Set Interrupt Priority
Kojto 122:f9eeca106725 742
Kojto 122:f9eeca106725 743 The function sets the priority of an interrupt.
Kojto 122:f9eeca106725 744
Kojto 122:f9eeca106725 745 \note The priority cannot be set for every core interrupt.
Kojto 122:f9eeca106725 746
Kojto 122:f9eeca106725 747 \param [in] IRQn Interrupt number.
Kojto 122:f9eeca106725 748 \param [in] priority Priority to set.
Kojto 122:f9eeca106725 749 */
Kojto 122:f9eeca106725 750 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 122:f9eeca106725 751 {
Kojto 122:f9eeca106725 752 if((int32_t)(IRQn) < 0) {
Kojto 122:f9eeca106725 753 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 122:f9eeca106725 754 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 122:f9eeca106725 755 }
Kojto 122:f9eeca106725 756 else {
Kojto 122:f9eeca106725 757 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 122:f9eeca106725 758 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 122:f9eeca106725 759 }
Kojto 122:f9eeca106725 760 }
Kojto 122:f9eeca106725 761
Kojto 122:f9eeca106725 762
Kojto 122:f9eeca106725 763 /** \brief Get Interrupt Priority
Kojto 122:f9eeca106725 764
Kojto 122:f9eeca106725 765 The function reads the priority of an interrupt. The interrupt
Kojto 122:f9eeca106725 766 number can be positive to specify an external (device specific)
Kojto 122:f9eeca106725 767 interrupt, or negative to specify an internal (core) interrupt.
Kojto 122:f9eeca106725 768
Kojto 122:f9eeca106725 769
Kojto 122:f9eeca106725 770 \param [in] IRQn Interrupt number.
Kojto 122:f9eeca106725 771 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 122:f9eeca106725 772 priority bits of the microcontroller.
Kojto 122:f9eeca106725 773 */
Kojto 122:f9eeca106725 774 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 122:f9eeca106725 775 {
Kojto 122:f9eeca106725 776
Kojto 122:f9eeca106725 777 if((int32_t)(IRQn) < 0) {
Kojto 122:f9eeca106725 778 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 122:f9eeca106725 779 }
Kojto 122:f9eeca106725 780 else {
Kojto 122:f9eeca106725 781 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 122:f9eeca106725 782 }
Kojto 122:f9eeca106725 783 }
Kojto 122:f9eeca106725 784
Kojto 122:f9eeca106725 785
Kojto 122:f9eeca106725 786 /** \brief System Reset
Kojto 122:f9eeca106725 787
Kojto 122:f9eeca106725 788 The function initiates a system reset request to reset the MCU.
Kojto 122:f9eeca106725 789 */
Kojto 122:f9eeca106725 790 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 122:f9eeca106725 791 {
Kojto 122:f9eeca106725 792 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 122:f9eeca106725 793 buffered write are completed before reset */
Kojto 122:f9eeca106725 794 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 122:f9eeca106725 795 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 122:f9eeca106725 796 __DSB(); /* Ensure completion of memory access */
Kojto 122:f9eeca106725 797 while(1) { __NOP(); } /* wait until reset */
Kojto 122:f9eeca106725 798 }
Kojto 122:f9eeca106725 799
Kojto 122:f9eeca106725 800 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 122:f9eeca106725 801
Kojto 122:f9eeca106725 802
Kojto 122:f9eeca106725 803
Kojto 122:f9eeca106725 804 /* ################################## SysTick function ############################################ */
Kojto 122:f9eeca106725 805 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 122:f9eeca106725 806 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 122:f9eeca106725 807 \brief Functions that configure the System.
Kojto 122:f9eeca106725 808 @{
Kojto 122:f9eeca106725 809 */
Kojto 122:f9eeca106725 810
Kojto 122:f9eeca106725 811 #if (__Vendor_SysTickConfig == 0)
Kojto 122:f9eeca106725 812
Kojto 122:f9eeca106725 813 /** \brief System Tick Configuration
Kojto 122:f9eeca106725 814
Kojto 122:f9eeca106725 815 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 122:f9eeca106725 816 Counter is in free running mode to generate periodic interrupts.
Kojto 122:f9eeca106725 817
Kojto 122:f9eeca106725 818 \param [in] ticks Number of ticks between two interrupts.
Kojto 122:f9eeca106725 819
Kojto 122:f9eeca106725 820 \return 0 Function succeeded.
Kojto 122:f9eeca106725 821 \return 1 Function failed.
Kojto 122:f9eeca106725 822
Kojto 122:f9eeca106725 823 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 122:f9eeca106725 824 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 122:f9eeca106725 825 must contain a vendor-specific implementation of this function.
Kojto 122:f9eeca106725 826
Kojto 122:f9eeca106725 827 */
Kojto 122:f9eeca106725 828 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 122:f9eeca106725 829 {
Kojto 122:f9eeca106725 830 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 122:f9eeca106725 831
Kojto 122:f9eeca106725 832 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 122:f9eeca106725 833 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 122:f9eeca106725 834 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 122:f9eeca106725 835 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 122:f9eeca106725 836 SysTick_CTRL_TICKINT_Msk |
Kojto 122:f9eeca106725 837 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 122:f9eeca106725 838 return (0UL); /* Function successful */
Kojto 122:f9eeca106725 839 }
Kojto 122:f9eeca106725 840
Kojto 122:f9eeca106725 841 #endif
Kojto 122:f9eeca106725 842
Kojto 122:f9eeca106725 843 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 122:f9eeca106725 844
Kojto 122:f9eeca106725 845
Kojto 122:f9eeca106725 846
Kojto 122:f9eeca106725 847
Kojto 122:f9eeca106725 848 #ifdef __cplusplus
Kojto 122:f9eeca106725 849 }
Kojto 122:f9eeca106725 850 #endif
Kojto 122:f9eeca106725 851
Kojto 122:f9eeca106725 852 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 122:f9eeca106725 853
Kojto 122:f9eeca106725 854 #endif /* __CMSIS_GENERIC */