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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F031K6/core_cm7.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**************************************************************************//**
Kojto 109:9296ab0bfc11 2 * @file core_cm7.h
Kojto 109:9296ab0bfc11 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
Kojto 109:9296ab0bfc11 4 * @version V4.10
Kojto 109:9296ab0bfc11 5 * @date 18. March 2015
Kojto 109:9296ab0bfc11 6 *
Kojto 109:9296ab0bfc11 7 * @note
Kojto 109:9296ab0bfc11 8 *
Kojto 109:9296ab0bfc11 9 ******************************************************************************/
Kojto 109:9296ab0bfc11 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 109:9296ab0bfc11 11
Kojto 109:9296ab0bfc11 12 All rights reserved.
Kojto 109:9296ab0bfc11 13 Redistribution and use in source and binary forms, with or without
Kojto 109:9296ab0bfc11 14 modification, are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 - Redistributions of source code must retain the above copyright
Kojto 109:9296ab0bfc11 16 notice, this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 - Redistributions in binary form must reproduce the above copyright
Kojto 109:9296ab0bfc11 18 notice, this list of conditions and the following disclaimer in the
Kojto 109:9296ab0bfc11 19 documentation and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 109:9296ab0bfc11 21 to endorse or promote products derived from this software without
Kojto 109:9296ab0bfc11 22 specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 109:9296ab0bfc11 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 109:9296ab0bfc11 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 109:9296ab0bfc11 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 109:9296ab0bfc11 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 109:9296ab0bfc11 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 109:9296ab0bfc11 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 109:9296ab0bfc11 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 109:9296ab0bfc11 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 35 ---------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 36
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 #if defined ( __ICCARM__ )
Kojto 109:9296ab0bfc11 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 109:9296ab0bfc11 40 #endif
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 #ifndef __CORE_CM7_H_GENERIC
Kojto 109:9296ab0bfc11 43 #define __CORE_CM7_H_GENERIC
Kojto 109:9296ab0bfc11 44
Kojto 109:9296ab0bfc11 45 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 46 extern "C" {
Kojto 109:9296ab0bfc11 47 #endif
Kojto 109:9296ab0bfc11 48
Kojto 109:9296ab0bfc11 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 109:9296ab0bfc11 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 109:9296ab0bfc11 51
Kojto 109:9296ab0bfc11 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 109:9296ab0bfc11 53 Function definitions in header files are used to allow 'inlining'.
Kojto 109:9296ab0bfc11 54
Kojto 109:9296ab0bfc11 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 109:9296ab0bfc11 56 Unions are used for effective representation of core registers.
Kojto 109:9296ab0bfc11 57
Kojto 109:9296ab0bfc11 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 109:9296ab0bfc11 59 Function-like macros are used to allow more efficient code.
Kojto 109:9296ab0bfc11 60 */
Kojto 109:9296ab0bfc11 61
Kojto 109:9296ab0bfc11 62
Kojto 109:9296ab0bfc11 63 /*******************************************************************************
Kojto 109:9296ab0bfc11 64 * CMSIS definitions
Kojto 109:9296ab0bfc11 65 ******************************************************************************/
Kojto 109:9296ab0bfc11 66 /** \ingroup Cortex_M7
Kojto 109:9296ab0bfc11 67 @{
Kojto 109:9296ab0bfc11 68 */
Kojto 109:9296ab0bfc11 69
Kojto 109:9296ab0bfc11 70 /* CMSIS CM7 definitions */
Kojto 109:9296ab0bfc11 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 109:9296ab0bfc11 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 109:9296ab0bfc11 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
Kojto 109:9296ab0bfc11 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 109:9296ab0bfc11 75
Kojto 109:9296ab0bfc11 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
Kojto 109:9296ab0bfc11 77
Kojto 109:9296ab0bfc11 78
Kojto 109:9296ab0bfc11 79 #if defined ( __CC_ARM )
Kojto 109:9296ab0bfc11 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 109:9296ab0bfc11 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 109:9296ab0bfc11 82 #define __STATIC_INLINE static __inline
Kojto 109:9296ab0bfc11 83
Kojto 109:9296ab0bfc11 84 #elif defined ( __GNUC__ )
Kojto 109:9296ab0bfc11 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 109:9296ab0bfc11 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 109:9296ab0bfc11 87 #define __STATIC_INLINE static inline
Kojto 109:9296ab0bfc11 88
Kojto 109:9296ab0bfc11 89 #elif defined ( __ICCARM__ )
Kojto 109:9296ab0bfc11 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 109:9296ab0bfc11 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 109:9296ab0bfc11 92 #define __STATIC_INLINE static inline
Kojto 109:9296ab0bfc11 93
Kojto 109:9296ab0bfc11 94 #elif defined ( __TMS470__ )
Kojto 109:9296ab0bfc11 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 109:9296ab0bfc11 96 #define __STATIC_INLINE static inline
Kojto 109:9296ab0bfc11 97
Kojto 109:9296ab0bfc11 98 #elif defined ( __TASKING__ )
Kojto 109:9296ab0bfc11 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 109:9296ab0bfc11 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 109:9296ab0bfc11 101 #define __STATIC_INLINE static inline
Kojto 109:9296ab0bfc11 102
Kojto 109:9296ab0bfc11 103 #elif defined ( __CSMC__ )
Kojto 109:9296ab0bfc11 104 #define __packed
Kojto 109:9296ab0bfc11 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 109:9296ab0bfc11 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 109:9296ab0bfc11 107 #define __STATIC_INLINE static inline
Kojto 109:9296ab0bfc11 108
Kojto 109:9296ab0bfc11 109 #endif
Kojto 109:9296ab0bfc11 110
Kojto 109:9296ab0bfc11 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 109:9296ab0bfc11 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Kojto 109:9296ab0bfc11 113 */
Kojto 109:9296ab0bfc11 114 #if defined ( __CC_ARM )
Kojto 109:9296ab0bfc11 115 #if defined __TARGET_FPU_VFP
Kojto 109:9296ab0bfc11 116 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 117 #define __FPU_USED 1
Kojto 109:9296ab0bfc11 118 #else
Kojto 109:9296ab0bfc11 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 120 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 121 #endif
Kojto 109:9296ab0bfc11 122 #else
Kojto 109:9296ab0bfc11 123 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 124 #endif
Kojto 109:9296ab0bfc11 125
Kojto 109:9296ab0bfc11 126 #elif defined ( __GNUC__ )
Kojto 109:9296ab0bfc11 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 109:9296ab0bfc11 128 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 129 #define __FPU_USED 1
Kojto 109:9296ab0bfc11 130 #else
Kojto 109:9296ab0bfc11 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 132 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 133 #endif
Kojto 109:9296ab0bfc11 134 #else
Kojto 109:9296ab0bfc11 135 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 136 #endif
Kojto 109:9296ab0bfc11 137
Kojto 109:9296ab0bfc11 138 #elif defined ( __ICCARM__ )
Kojto 109:9296ab0bfc11 139 #if defined __ARMVFP__
Kojto 109:9296ab0bfc11 140 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 141 #define __FPU_USED 1
Kojto 109:9296ab0bfc11 142 #else
Kojto 109:9296ab0bfc11 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 144 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 145 #endif
Kojto 109:9296ab0bfc11 146 #else
Kojto 109:9296ab0bfc11 147 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 148 #endif
Kojto 109:9296ab0bfc11 149
Kojto 109:9296ab0bfc11 150 #elif defined ( __TMS470__ )
Kojto 109:9296ab0bfc11 151 #if defined __TI_VFP_SUPPORT__
Kojto 109:9296ab0bfc11 152 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 153 #define __FPU_USED 1
Kojto 109:9296ab0bfc11 154 #else
Kojto 109:9296ab0bfc11 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 156 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 157 #endif
Kojto 109:9296ab0bfc11 158 #else
Kojto 109:9296ab0bfc11 159 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 160 #endif
Kojto 109:9296ab0bfc11 161
Kojto 109:9296ab0bfc11 162 #elif defined ( __TASKING__ )
Kojto 109:9296ab0bfc11 163 #if defined __FPU_VFP__
Kojto 109:9296ab0bfc11 164 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 165 #define __FPU_USED 1
Kojto 109:9296ab0bfc11 166 #else
Kojto 109:9296ab0bfc11 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 168 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 169 #endif
Kojto 109:9296ab0bfc11 170 #else
Kojto 109:9296ab0bfc11 171 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 172 #endif
Kojto 109:9296ab0bfc11 173
Kojto 109:9296ab0bfc11 174 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 109:9296ab0bfc11 175 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 109:9296ab0bfc11 176 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 177 #define __FPU_USED 1
Kojto 109:9296ab0bfc11 178 #else
Kojto 109:9296ab0bfc11 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 109:9296ab0bfc11 180 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 181 #endif
Kojto 109:9296ab0bfc11 182 #else
Kojto 109:9296ab0bfc11 183 #define __FPU_USED 0
Kojto 109:9296ab0bfc11 184 #endif
Kojto 109:9296ab0bfc11 185 #endif
Kojto 109:9296ab0bfc11 186
Kojto 109:9296ab0bfc11 187 #include <stdint.h> /* standard types definitions */
Kojto 109:9296ab0bfc11 188 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 109:9296ab0bfc11 189 #include <core_cmFunc.h> /* Core Function Access */
Kojto 109:9296ab0bfc11 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Kojto 109:9296ab0bfc11 191
Kojto 109:9296ab0bfc11 192 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 193 }
Kojto 109:9296ab0bfc11 194 #endif
Kojto 109:9296ab0bfc11 195
Kojto 109:9296ab0bfc11 196 #endif /* __CORE_CM7_H_GENERIC */
Kojto 109:9296ab0bfc11 197
Kojto 109:9296ab0bfc11 198 #ifndef __CMSIS_GENERIC
Kojto 109:9296ab0bfc11 199
Kojto 109:9296ab0bfc11 200 #ifndef __CORE_CM7_H_DEPENDANT
Kojto 109:9296ab0bfc11 201 #define __CORE_CM7_H_DEPENDANT
Kojto 109:9296ab0bfc11 202
Kojto 109:9296ab0bfc11 203 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 204 extern "C" {
Kojto 109:9296ab0bfc11 205 #endif
Kojto 109:9296ab0bfc11 206
Kojto 109:9296ab0bfc11 207 /* check device defines and use defaults */
Kojto 109:9296ab0bfc11 208 #if defined __CHECK_DEVICE_DEFINES
Kojto 109:9296ab0bfc11 209 #ifndef __CM7_REV
Kojto 109:9296ab0bfc11 210 #define __CM7_REV 0x0000
Kojto 109:9296ab0bfc11 211 #warning "__CM7_REV not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 212 #endif
Kojto 109:9296ab0bfc11 213
Kojto 109:9296ab0bfc11 214 #ifndef __FPU_PRESENT
Kojto 109:9296ab0bfc11 215 #define __FPU_PRESENT 0
Kojto 109:9296ab0bfc11 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 217 #endif
Kojto 109:9296ab0bfc11 218
Kojto 109:9296ab0bfc11 219 #ifndef __MPU_PRESENT
Kojto 109:9296ab0bfc11 220 #define __MPU_PRESENT 0
Kojto 109:9296ab0bfc11 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 222 #endif
Kojto 109:9296ab0bfc11 223
Kojto 109:9296ab0bfc11 224 #ifndef __ICACHE_PRESENT
Kojto 109:9296ab0bfc11 225 #define __ICACHE_PRESENT 0
Kojto 109:9296ab0bfc11 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 227 #endif
Kojto 109:9296ab0bfc11 228
Kojto 109:9296ab0bfc11 229 #ifndef __DCACHE_PRESENT
Kojto 109:9296ab0bfc11 230 #define __DCACHE_PRESENT 0
Kojto 109:9296ab0bfc11 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 232 #endif
Kojto 109:9296ab0bfc11 233
Kojto 109:9296ab0bfc11 234 #ifndef __DTCM_PRESENT
Kojto 109:9296ab0bfc11 235 #define __DTCM_PRESENT 0
Kojto 109:9296ab0bfc11 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 237 #endif
Kojto 109:9296ab0bfc11 238
Kojto 109:9296ab0bfc11 239 #ifndef __NVIC_PRIO_BITS
Kojto 109:9296ab0bfc11 240 #define __NVIC_PRIO_BITS 3
Kojto 109:9296ab0bfc11 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 242 #endif
Kojto 109:9296ab0bfc11 243
Kojto 109:9296ab0bfc11 244 #ifndef __Vendor_SysTickConfig
Kojto 109:9296ab0bfc11 245 #define __Vendor_SysTickConfig 0
Kojto 109:9296ab0bfc11 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 109:9296ab0bfc11 247 #endif
Kojto 109:9296ab0bfc11 248 #endif
Kojto 109:9296ab0bfc11 249
Kojto 109:9296ab0bfc11 250 /* IO definitions (access restrictions to peripheral registers) */
Kojto 109:9296ab0bfc11 251 /**
Kojto 109:9296ab0bfc11 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 109:9296ab0bfc11 253
Kojto 109:9296ab0bfc11 254 <strong>IO Type Qualifiers</strong> are used
Kojto 109:9296ab0bfc11 255 \li to specify the access to peripheral variables.
Kojto 109:9296ab0bfc11 256 \li for automatic generation of peripheral register debug information.
Kojto 109:9296ab0bfc11 257 */
Kojto 109:9296ab0bfc11 258 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 259 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 109:9296ab0bfc11 260 #else
Kojto 109:9296ab0bfc11 261 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 109:9296ab0bfc11 262 #endif
Kojto 109:9296ab0bfc11 263 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 109:9296ab0bfc11 264 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 109:9296ab0bfc11 265
<> 128:9bcdf88f62b0 266 #ifdef __cplusplus
<> 128:9bcdf88f62b0 267 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 268 #else
<> 128:9bcdf88f62b0 269 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 270 #endif
<> 128:9bcdf88f62b0 271 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 272 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 273
Kojto 109:9296ab0bfc11 274 /*@} end of group Cortex_M7 */
Kojto 109:9296ab0bfc11 275
Kojto 109:9296ab0bfc11 276
Kojto 109:9296ab0bfc11 277
Kojto 109:9296ab0bfc11 278 /*******************************************************************************
Kojto 109:9296ab0bfc11 279 * Register Abstraction
Kojto 109:9296ab0bfc11 280 Core Register contain:
Kojto 109:9296ab0bfc11 281 - Core Register
Kojto 109:9296ab0bfc11 282 - Core NVIC Register
Kojto 109:9296ab0bfc11 283 - Core SCB Register
Kojto 109:9296ab0bfc11 284 - Core SysTick Register
Kojto 109:9296ab0bfc11 285 - Core Debug Register
Kojto 109:9296ab0bfc11 286 - Core MPU Register
Kojto 109:9296ab0bfc11 287 - Core FPU Register
Kojto 109:9296ab0bfc11 288 ******************************************************************************/
Kojto 109:9296ab0bfc11 289 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 109:9296ab0bfc11 290 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 109:9296ab0bfc11 291 */
Kojto 109:9296ab0bfc11 292
Kojto 109:9296ab0bfc11 293 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 294 \defgroup CMSIS_CORE Status and Control Registers
Kojto 109:9296ab0bfc11 295 \brief Core Register type definitions.
Kojto 109:9296ab0bfc11 296 @{
Kojto 109:9296ab0bfc11 297 */
Kojto 109:9296ab0bfc11 298
Kojto 109:9296ab0bfc11 299 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 109:9296ab0bfc11 300 */
Kojto 109:9296ab0bfc11 301 typedef union
Kojto 109:9296ab0bfc11 302 {
Kojto 109:9296ab0bfc11 303 struct
Kojto 109:9296ab0bfc11 304 {
Kojto 109:9296ab0bfc11 305 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 109:9296ab0bfc11 306 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 109:9296ab0bfc11 307 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 109:9296ab0bfc11 308 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 109:9296ab0bfc11 309 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 109:9296ab0bfc11 310 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 109:9296ab0bfc11 311 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 109:9296ab0bfc11 312 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 109:9296ab0bfc11 313 } b; /*!< Structure used for bit access */
Kojto 109:9296ab0bfc11 314 uint32_t w; /*!< Type used for word access */
Kojto 109:9296ab0bfc11 315 } APSR_Type;
Kojto 109:9296ab0bfc11 316
Kojto 109:9296ab0bfc11 317 /* APSR Register Definitions */
Kojto 109:9296ab0bfc11 318 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 109:9296ab0bfc11 319 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 109:9296ab0bfc11 320
Kojto 109:9296ab0bfc11 321 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 109:9296ab0bfc11 322 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 109:9296ab0bfc11 323
Kojto 109:9296ab0bfc11 324 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 109:9296ab0bfc11 325 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 109:9296ab0bfc11 326
Kojto 109:9296ab0bfc11 327 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 109:9296ab0bfc11 328 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 109:9296ab0bfc11 329
Kojto 109:9296ab0bfc11 330 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 109:9296ab0bfc11 331 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 109:9296ab0bfc11 332
Kojto 109:9296ab0bfc11 333 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
Kojto 109:9296ab0bfc11 334 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
Kojto 109:9296ab0bfc11 335
Kojto 109:9296ab0bfc11 336
Kojto 109:9296ab0bfc11 337 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 109:9296ab0bfc11 338 */
Kojto 109:9296ab0bfc11 339 typedef union
Kojto 109:9296ab0bfc11 340 {
Kojto 109:9296ab0bfc11 341 struct
Kojto 109:9296ab0bfc11 342 {
Kojto 109:9296ab0bfc11 343 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 109:9296ab0bfc11 344 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 109:9296ab0bfc11 345 } b; /*!< Structure used for bit access */
Kojto 109:9296ab0bfc11 346 uint32_t w; /*!< Type used for word access */
Kojto 109:9296ab0bfc11 347 } IPSR_Type;
Kojto 109:9296ab0bfc11 348
Kojto 109:9296ab0bfc11 349 /* IPSR Register Definitions */
Kojto 109:9296ab0bfc11 350 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 109:9296ab0bfc11 351 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 109:9296ab0bfc11 352
Kojto 109:9296ab0bfc11 353
Kojto 109:9296ab0bfc11 354 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 109:9296ab0bfc11 355 */
Kojto 109:9296ab0bfc11 356 typedef union
Kojto 109:9296ab0bfc11 357 {
Kojto 109:9296ab0bfc11 358 struct
Kojto 109:9296ab0bfc11 359 {
Kojto 109:9296ab0bfc11 360 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 109:9296ab0bfc11 361 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 109:9296ab0bfc11 362 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 109:9296ab0bfc11 363 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 109:9296ab0bfc11 364 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 109:9296ab0bfc11 365 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 109:9296ab0bfc11 366 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 109:9296ab0bfc11 367 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 109:9296ab0bfc11 368 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 109:9296ab0bfc11 369 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 109:9296ab0bfc11 370 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 109:9296ab0bfc11 371 } b; /*!< Structure used for bit access */
Kojto 109:9296ab0bfc11 372 uint32_t w; /*!< Type used for word access */
Kojto 109:9296ab0bfc11 373 } xPSR_Type;
Kojto 109:9296ab0bfc11 374
Kojto 109:9296ab0bfc11 375 /* xPSR Register Definitions */
Kojto 109:9296ab0bfc11 376 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 109:9296ab0bfc11 377 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 109:9296ab0bfc11 378
Kojto 109:9296ab0bfc11 379 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 109:9296ab0bfc11 380 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 109:9296ab0bfc11 381
Kojto 109:9296ab0bfc11 382 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 109:9296ab0bfc11 383 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 109:9296ab0bfc11 384
Kojto 109:9296ab0bfc11 385 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 109:9296ab0bfc11 386 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 109:9296ab0bfc11 387
Kojto 109:9296ab0bfc11 388 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 109:9296ab0bfc11 389 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 109:9296ab0bfc11 390
Kojto 109:9296ab0bfc11 391 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 109:9296ab0bfc11 392 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 109:9296ab0bfc11 393
Kojto 109:9296ab0bfc11 394 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 109:9296ab0bfc11 395 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 109:9296ab0bfc11 396
Kojto 109:9296ab0bfc11 397 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
Kojto 109:9296ab0bfc11 398 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
Kojto 109:9296ab0bfc11 399
Kojto 109:9296ab0bfc11 400 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 109:9296ab0bfc11 401 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 109:9296ab0bfc11 402
Kojto 109:9296ab0bfc11 403
Kojto 109:9296ab0bfc11 404 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 109:9296ab0bfc11 405 */
Kojto 109:9296ab0bfc11 406 typedef union
Kojto 109:9296ab0bfc11 407 {
Kojto 109:9296ab0bfc11 408 struct
Kojto 109:9296ab0bfc11 409 {
Kojto 109:9296ab0bfc11 410 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 109:9296ab0bfc11 411 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 109:9296ab0bfc11 412 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 109:9296ab0bfc11 413 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 109:9296ab0bfc11 414 } b; /*!< Structure used for bit access */
Kojto 109:9296ab0bfc11 415 uint32_t w; /*!< Type used for word access */
Kojto 109:9296ab0bfc11 416 } CONTROL_Type;
Kojto 109:9296ab0bfc11 417
Kojto 109:9296ab0bfc11 418 /* CONTROL Register Definitions */
Kojto 109:9296ab0bfc11 419 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
Kojto 109:9296ab0bfc11 420 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
Kojto 109:9296ab0bfc11 421
Kojto 109:9296ab0bfc11 422 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 109:9296ab0bfc11 423 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 109:9296ab0bfc11 424
Kojto 109:9296ab0bfc11 425 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 109:9296ab0bfc11 426 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 109:9296ab0bfc11 427
Kojto 109:9296ab0bfc11 428 /*@} end of group CMSIS_CORE */
Kojto 109:9296ab0bfc11 429
Kojto 109:9296ab0bfc11 430
Kojto 109:9296ab0bfc11 431 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 432 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 109:9296ab0bfc11 433 \brief Type definitions for the NVIC Registers
Kojto 109:9296ab0bfc11 434 @{
Kojto 109:9296ab0bfc11 435 */
Kojto 109:9296ab0bfc11 436
Kojto 109:9296ab0bfc11 437 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 109:9296ab0bfc11 438 */
Kojto 109:9296ab0bfc11 439 typedef struct
Kojto 109:9296ab0bfc11 440 {
Kojto 109:9296ab0bfc11 441 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 109:9296ab0bfc11 442 uint32_t RESERVED0[24];
Kojto 109:9296ab0bfc11 443 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 109:9296ab0bfc11 444 uint32_t RSERVED1[24];
Kojto 109:9296ab0bfc11 445 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 109:9296ab0bfc11 446 uint32_t RESERVED2[24];
Kojto 109:9296ab0bfc11 447 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 109:9296ab0bfc11 448 uint32_t RESERVED3[24];
Kojto 109:9296ab0bfc11 449 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 109:9296ab0bfc11 450 uint32_t RESERVED4[56];
Kojto 109:9296ab0bfc11 451 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 109:9296ab0bfc11 452 uint32_t RESERVED5[644];
Kojto 109:9296ab0bfc11 453 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 109:9296ab0bfc11 454 } NVIC_Type;
Kojto 109:9296ab0bfc11 455
Kojto 109:9296ab0bfc11 456 /* Software Triggered Interrupt Register Definitions */
Kojto 109:9296ab0bfc11 457 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 109:9296ab0bfc11 458 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
Kojto 109:9296ab0bfc11 459
Kojto 109:9296ab0bfc11 460 /*@} end of group CMSIS_NVIC */
Kojto 109:9296ab0bfc11 461
Kojto 109:9296ab0bfc11 462
Kojto 109:9296ab0bfc11 463 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 464 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 109:9296ab0bfc11 465 \brief Type definitions for the System Control Block Registers
Kojto 109:9296ab0bfc11 466 @{
Kojto 109:9296ab0bfc11 467 */
Kojto 109:9296ab0bfc11 468
Kojto 109:9296ab0bfc11 469 /** \brief Structure type to access the System Control Block (SCB).
Kojto 109:9296ab0bfc11 470 */
Kojto 109:9296ab0bfc11 471 typedef struct
Kojto 109:9296ab0bfc11 472 {
Kojto 109:9296ab0bfc11 473 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 109:9296ab0bfc11 474 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 109:9296ab0bfc11 475 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 109:9296ab0bfc11 476 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 109:9296ab0bfc11 477 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 109:9296ab0bfc11 478 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 109:9296ab0bfc11 479 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 109:9296ab0bfc11 480 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 109:9296ab0bfc11 481 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 109:9296ab0bfc11 482 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 109:9296ab0bfc11 483 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 109:9296ab0bfc11 484 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 109:9296ab0bfc11 485 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 109:9296ab0bfc11 486 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 109:9296ab0bfc11 487 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 109:9296ab0bfc11 488 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 109:9296ab0bfc11 489 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 109:9296ab0bfc11 490 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 109:9296ab0bfc11 491 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 109:9296ab0bfc11 492 uint32_t RESERVED0[1];
Kojto 109:9296ab0bfc11 493 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Kojto 109:9296ab0bfc11 494 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
Kojto 109:9296ab0bfc11 495 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
Kojto 109:9296ab0bfc11 496 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
Kojto 109:9296ab0bfc11 497 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 109:9296ab0bfc11 498 uint32_t RESERVED3[93];
Kojto 109:9296ab0bfc11 499 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
Kojto 109:9296ab0bfc11 500 uint32_t RESERVED4[15];
Kojto 109:9296ab0bfc11 501 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
Kojto 109:9296ab0bfc11 502 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
Kojto 109:9296ab0bfc11 503 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
Kojto 109:9296ab0bfc11 504 uint32_t RESERVED5[1];
Kojto 109:9296ab0bfc11 505 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
Kojto 109:9296ab0bfc11 506 uint32_t RESERVED6[1];
Kojto 109:9296ab0bfc11 507 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
Kojto 109:9296ab0bfc11 508 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
Kojto 109:9296ab0bfc11 509 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
Kojto 109:9296ab0bfc11 510 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
Kojto 109:9296ab0bfc11 511 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
Kojto 109:9296ab0bfc11 512 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
Kojto 109:9296ab0bfc11 513 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
Kojto 109:9296ab0bfc11 514 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
Kojto 109:9296ab0bfc11 515 uint32_t RESERVED7[6];
Kojto 109:9296ab0bfc11 516 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
Kojto 109:9296ab0bfc11 517 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
Kojto 109:9296ab0bfc11 518 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
Kojto 109:9296ab0bfc11 519 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
Kojto 109:9296ab0bfc11 520 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
Kojto 109:9296ab0bfc11 521 uint32_t RESERVED8[1];
Kojto 109:9296ab0bfc11 522 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
Kojto 109:9296ab0bfc11 523 } SCB_Type;
Kojto 109:9296ab0bfc11 524
Kojto 109:9296ab0bfc11 525 /* SCB CPUID Register Definitions */
Kojto 109:9296ab0bfc11 526 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 109:9296ab0bfc11 527 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 109:9296ab0bfc11 528
Kojto 109:9296ab0bfc11 529 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 109:9296ab0bfc11 530 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 109:9296ab0bfc11 531
Kojto 109:9296ab0bfc11 532 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 109:9296ab0bfc11 533 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 109:9296ab0bfc11 534
Kojto 109:9296ab0bfc11 535 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 109:9296ab0bfc11 536 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 109:9296ab0bfc11 537
Kojto 109:9296ab0bfc11 538 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 109:9296ab0bfc11 539 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 109:9296ab0bfc11 540
Kojto 109:9296ab0bfc11 541 /* SCB Interrupt Control State Register Definitions */
Kojto 109:9296ab0bfc11 542 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 109:9296ab0bfc11 543 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 109:9296ab0bfc11 544
Kojto 109:9296ab0bfc11 545 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 109:9296ab0bfc11 546 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 109:9296ab0bfc11 547
Kojto 109:9296ab0bfc11 548 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 109:9296ab0bfc11 549 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 109:9296ab0bfc11 550
Kojto 109:9296ab0bfc11 551 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 109:9296ab0bfc11 552 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 109:9296ab0bfc11 553
Kojto 109:9296ab0bfc11 554 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 109:9296ab0bfc11 555 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 109:9296ab0bfc11 556
Kojto 109:9296ab0bfc11 557 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 109:9296ab0bfc11 558 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 109:9296ab0bfc11 559
Kojto 109:9296ab0bfc11 560 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 109:9296ab0bfc11 561 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 109:9296ab0bfc11 562
Kojto 109:9296ab0bfc11 563 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 109:9296ab0bfc11 564 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 109:9296ab0bfc11 565
Kojto 109:9296ab0bfc11 566 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kojto 109:9296ab0bfc11 567 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 109:9296ab0bfc11 568
Kojto 109:9296ab0bfc11 569 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 109:9296ab0bfc11 570 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 109:9296ab0bfc11 571
Kojto 109:9296ab0bfc11 572 /* SCB Vector Table Offset Register Definitions */
Kojto 109:9296ab0bfc11 573 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 109:9296ab0bfc11 574 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 109:9296ab0bfc11 575
Kojto 109:9296ab0bfc11 576 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 109:9296ab0bfc11 577 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 109:9296ab0bfc11 578 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 109:9296ab0bfc11 579
Kojto 109:9296ab0bfc11 580 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 109:9296ab0bfc11 581 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 109:9296ab0bfc11 582
Kojto 109:9296ab0bfc11 583 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 109:9296ab0bfc11 584 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 109:9296ab0bfc11 585
Kojto 109:9296ab0bfc11 586 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kojto 109:9296ab0bfc11 587 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 109:9296ab0bfc11 588
Kojto 109:9296ab0bfc11 589 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 109:9296ab0bfc11 590 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 109:9296ab0bfc11 591
Kojto 109:9296ab0bfc11 592 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 109:9296ab0bfc11 593 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 109:9296ab0bfc11 594
Kojto 109:9296ab0bfc11 595 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 109:9296ab0bfc11 596 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 109:9296ab0bfc11 597
Kojto 109:9296ab0bfc11 598 /* SCB System Control Register Definitions */
Kojto 109:9296ab0bfc11 599 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 109:9296ab0bfc11 600 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 109:9296ab0bfc11 601
Kojto 109:9296ab0bfc11 602 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 109:9296ab0bfc11 603 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 109:9296ab0bfc11 604
Kojto 109:9296ab0bfc11 605 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 109:9296ab0bfc11 606 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 109:9296ab0bfc11 607
Kojto 109:9296ab0bfc11 608 /* SCB Configuration Control Register Definitions */
Kojto 109:9296ab0bfc11 609 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
Kojto 109:9296ab0bfc11 610 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
Kojto 109:9296ab0bfc11 611
Kojto 109:9296ab0bfc11 612 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
Kojto 109:9296ab0bfc11 613 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
Kojto 109:9296ab0bfc11 614
Kojto 109:9296ab0bfc11 615 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
Kojto 109:9296ab0bfc11 616 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
Kojto 109:9296ab0bfc11 617
Kojto 109:9296ab0bfc11 618 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 109:9296ab0bfc11 619 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 109:9296ab0bfc11 620
Kojto 109:9296ab0bfc11 621 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kojto 109:9296ab0bfc11 622 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 109:9296ab0bfc11 623
Kojto 109:9296ab0bfc11 624 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kojto 109:9296ab0bfc11 625 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 109:9296ab0bfc11 626
Kojto 109:9296ab0bfc11 627 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 109:9296ab0bfc11 628 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 109:9296ab0bfc11 629
Kojto 109:9296ab0bfc11 630 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kojto 109:9296ab0bfc11 631 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 109:9296ab0bfc11 632
Kojto 109:9296ab0bfc11 633 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 109:9296ab0bfc11 634 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 109:9296ab0bfc11 635
Kojto 109:9296ab0bfc11 636 /* SCB System Handler Control and State Register Definitions */
Kojto 109:9296ab0bfc11 637 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 109:9296ab0bfc11 638 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 109:9296ab0bfc11 639
Kojto 109:9296ab0bfc11 640 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 109:9296ab0bfc11 641 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 109:9296ab0bfc11 642
Kojto 109:9296ab0bfc11 643 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 109:9296ab0bfc11 644 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 109:9296ab0bfc11 645
Kojto 109:9296ab0bfc11 646 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 109:9296ab0bfc11 647 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 109:9296ab0bfc11 648
Kojto 109:9296ab0bfc11 649 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 109:9296ab0bfc11 650 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 109:9296ab0bfc11 651
Kojto 109:9296ab0bfc11 652 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 109:9296ab0bfc11 653 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 109:9296ab0bfc11 654
Kojto 109:9296ab0bfc11 655 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 109:9296ab0bfc11 656 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 109:9296ab0bfc11 657
Kojto 109:9296ab0bfc11 658 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 109:9296ab0bfc11 659 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 109:9296ab0bfc11 660
Kojto 109:9296ab0bfc11 661 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kojto 109:9296ab0bfc11 662 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 109:9296ab0bfc11 663
Kojto 109:9296ab0bfc11 664 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kojto 109:9296ab0bfc11 665 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 109:9296ab0bfc11 666
Kojto 109:9296ab0bfc11 667 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kojto 109:9296ab0bfc11 668 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 109:9296ab0bfc11 669
Kojto 109:9296ab0bfc11 670 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 109:9296ab0bfc11 671 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 109:9296ab0bfc11 672
Kojto 109:9296ab0bfc11 673 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 109:9296ab0bfc11 674 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 109:9296ab0bfc11 675
Kojto 109:9296ab0bfc11 676 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 109:9296ab0bfc11 677 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 109:9296ab0bfc11 678
Kojto 109:9296ab0bfc11 679 /* SCB Configurable Fault Status Registers Definitions */
Kojto 109:9296ab0bfc11 680 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 109:9296ab0bfc11 681 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 109:9296ab0bfc11 682
Kojto 109:9296ab0bfc11 683 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 109:9296ab0bfc11 684 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 109:9296ab0bfc11 685
Kojto 109:9296ab0bfc11 686 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 109:9296ab0bfc11 687 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 109:9296ab0bfc11 688
Kojto 109:9296ab0bfc11 689 /* SCB Hard Fault Status Registers Definitions */
Kojto 109:9296ab0bfc11 690 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kojto 109:9296ab0bfc11 691 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 109:9296ab0bfc11 692
Kojto 109:9296ab0bfc11 693 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kojto 109:9296ab0bfc11 694 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 109:9296ab0bfc11 695
Kojto 109:9296ab0bfc11 696 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kojto 109:9296ab0bfc11 697 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 109:9296ab0bfc11 698
Kojto 109:9296ab0bfc11 699 /* SCB Debug Fault Status Register Definitions */
Kojto 109:9296ab0bfc11 700 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kojto 109:9296ab0bfc11 701 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 109:9296ab0bfc11 702
Kojto 109:9296ab0bfc11 703 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kojto 109:9296ab0bfc11 704 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 109:9296ab0bfc11 705
Kojto 109:9296ab0bfc11 706 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kojto 109:9296ab0bfc11 707 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 109:9296ab0bfc11 708
Kojto 109:9296ab0bfc11 709 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kojto 109:9296ab0bfc11 710 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 109:9296ab0bfc11 711
Kojto 109:9296ab0bfc11 712 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 109:9296ab0bfc11 713 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
Kojto 109:9296ab0bfc11 714
Kojto 109:9296ab0bfc11 715 /* Cache Level ID register */
Kojto 109:9296ab0bfc11 716 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
Kojto 109:9296ab0bfc11 717 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
Kojto 109:9296ab0bfc11 718
Kojto 109:9296ab0bfc11 719 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
Kojto 109:9296ab0bfc11 720 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
Kojto 109:9296ab0bfc11 721
Kojto 109:9296ab0bfc11 722 /* Cache Type register */
Kojto 109:9296ab0bfc11 723 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
Kojto 109:9296ab0bfc11 724 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
Kojto 109:9296ab0bfc11 725
Kojto 109:9296ab0bfc11 726 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
Kojto 109:9296ab0bfc11 727 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
Kojto 109:9296ab0bfc11 728
Kojto 109:9296ab0bfc11 729 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
Kojto 109:9296ab0bfc11 730 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
Kojto 109:9296ab0bfc11 731
Kojto 109:9296ab0bfc11 732 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
Kojto 109:9296ab0bfc11 733 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
Kojto 109:9296ab0bfc11 734
Kojto 109:9296ab0bfc11 735 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
Kojto 109:9296ab0bfc11 736 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
Kojto 109:9296ab0bfc11 737
Kojto 109:9296ab0bfc11 738 /* Cache Size ID Register */
Kojto 109:9296ab0bfc11 739 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
Kojto 109:9296ab0bfc11 740 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
Kojto 109:9296ab0bfc11 741
Kojto 109:9296ab0bfc11 742 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
Kojto 109:9296ab0bfc11 743 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
Kojto 109:9296ab0bfc11 744
Kojto 109:9296ab0bfc11 745 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
Kojto 109:9296ab0bfc11 746 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
Kojto 109:9296ab0bfc11 747
Kojto 109:9296ab0bfc11 748 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
Kojto 109:9296ab0bfc11 749 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
Kojto 109:9296ab0bfc11 750
Kojto 109:9296ab0bfc11 751 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
Kojto 109:9296ab0bfc11 752 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
Kojto 109:9296ab0bfc11 753
Kojto 109:9296ab0bfc11 754 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
Kojto 109:9296ab0bfc11 755 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
Kojto 109:9296ab0bfc11 756
Kojto 109:9296ab0bfc11 757 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
Kojto 109:9296ab0bfc11 758 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
Kojto 109:9296ab0bfc11 759
Kojto 109:9296ab0bfc11 760 /* Cache Size Selection Register */
Kojto 109:9296ab0bfc11 761 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
Kojto 109:9296ab0bfc11 762 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
Kojto 109:9296ab0bfc11 763
Kojto 109:9296ab0bfc11 764 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
Kojto 109:9296ab0bfc11 765 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
Kojto 109:9296ab0bfc11 766
Kojto 109:9296ab0bfc11 767 /* SCB Software Triggered Interrupt Register */
Kojto 109:9296ab0bfc11 768 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
Kojto 109:9296ab0bfc11 769 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
Kojto 109:9296ab0bfc11 770
Kojto 109:9296ab0bfc11 771 /* Instruction Tightly-Coupled Memory Control Register*/
Kojto 109:9296ab0bfc11 772 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
Kojto 109:9296ab0bfc11 773 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
Kojto 109:9296ab0bfc11 774
Kojto 109:9296ab0bfc11 775 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
Kojto 109:9296ab0bfc11 776 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
Kojto 109:9296ab0bfc11 777
Kojto 109:9296ab0bfc11 778 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
Kojto 109:9296ab0bfc11 779 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
Kojto 109:9296ab0bfc11 780
Kojto 109:9296ab0bfc11 781 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
Kojto 109:9296ab0bfc11 782 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
Kojto 109:9296ab0bfc11 783
Kojto 109:9296ab0bfc11 784 /* Data Tightly-Coupled Memory Control Registers */
Kojto 109:9296ab0bfc11 785 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
Kojto 109:9296ab0bfc11 786 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
Kojto 109:9296ab0bfc11 787
Kojto 109:9296ab0bfc11 788 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
Kojto 109:9296ab0bfc11 789 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
Kojto 109:9296ab0bfc11 790
Kojto 109:9296ab0bfc11 791 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
Kojto 109:9296ab0bfc11 792 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
Kojto 109:9296ab0bfc11 793
Kojto 109:9296ab0bfc11 794 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
Kojto 109:9296ab0bfc11 795 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
Kojto 109:9296ab0bfc11 796
Kojto 109:9296ab0bfc11 797 /* AHBP Control Register */
Kojto 109:9296ab0bfc11 798 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
Kojto 109:9296ab0bfc11 799 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
Kojto 109:9296ab0bfc11 800
Kojto 109:9296ab0bfc11 801 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
Kojto 109:9296ab0bfc11 802 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
Kojto 109:9296ab0bfc11 803
Kojto 109:9296ab0bfc11 804 /* L1 Cache Control Register */
Kojto 109:9296ab0bfc11 805 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
Kojto 109:9296ab0bfc11 806 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
Kojto 109:9296ab0bfc11 807
Kojto 109:9296ab0bfc11 808 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
Kojto 109:9296ab0bfc11 809 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
Kojto 109:9296ab0bfc11 810
Kojto 109:9296ab0bfc11 811 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
Kojto 109:9296ab0bfc11 812 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
Kojto 109:9296ab0bfc11 813
Kojto 109:9296ab0bfc11 814 /* AHBS control register */
Kojto 109:9296ab0bfc11 815 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
Kojto 109:9296ab0bfc11 816 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
Kojto 109:9296ab0bfc11 817
Kojto 109:9296ab0bfc11 818 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
Kojto 109:9296ab0bfc11 819 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
Kojto 109:9296ab0bfc11 820
Kojto 109:9296ab0bfc11 821 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
Kojto 109:9296ab0bfc11 822 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
Kojto 109:9296ab0bfc11 823
Kojto 109:9296ab0bfc11 824 /* Auxiliary Bus Fault Status Register */
Kojto 109:9296ab0bfc11 825 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
Kojto 109:9296ab0bfc11 826 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
Kojto 109:9296ab0bfc11 827
Kojto 109:9296ab0bfc11 828 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
Kojto 109:9296ab0bfc11 829 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
Kojto 109:9296ab0bfc11 830
Kojto 109:9296ab0bfc11 831 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
Kojto 109:9296ab0bfc11 832 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
Kojto 109:9296ab0bfc11 833
Kojto 109:9296ab0bfc11 834 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
Kojto 109:9296ab0bfc11 835 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
Kojto 109:9296ab0bfc11 836
Kojto 109:9296ab0bfc11 837 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
Kojto 109:9296ab0bfc11 838 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
Kojto 109:9296ab0bfc11 839
Kojto 109:9296ab0bfc11 840 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
Kojto 109:9296ab0bfc11 841 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
Kojto 109:9296ab0bfc11 842
Kojto 109:9296ab0bfc11 843 /*@} end of group CMSIS_SCB */
Kojto 109:9296ab0bfc11 844
Kojto 109:9296ab0bfc11 845
Kojto 109:9296ab0bfc11 846 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 847 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 109:9296ab0bfc11 848 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 109:9296ab0bfc11 849 @{
Kojto 109:9296ab0bfc11 850 */
Kojto 109:9296ab0bfc11 851
Kojto 109:9296ab0bfc11 852 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 109:9296ab0bfc11 853 */
Kojto 109:9296ab0bfc11 854 typedef struct
Kojto 109:9296ab0bfc11 855 {
Kojto 109:9296ab0bfc11 856 uint32_t RESERVED0[1];
Kojto 109:9296ab0bfc11 857 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 109:9296ab0bfc11 858 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 109:9296ab0bfc11 859 } SCnSCB_Type;
Kojto 109:9296ab0bfc11 860
Kojto 109:9296ab0bfc11 861 /* Interrupt Controller Type Register Definitions */
Kojto 109:9296ab0bfc11 862 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 109:9296ab0bfc11 863 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
Kojto 109:9296ab0bfc11 864
Kojto 109:9296ab0bfc11 865 /* Auxiliary Control Register Definitions */
Kojto 109:9296ab0bfc11 866 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
Kojto 109:9296ab0bfc11 867 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
Kojto 109:9296ab0bfc11 868
Kojto 109:9296ab0bfc11 869 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
Kojto 109:9296ab0bfc11 870 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
Kojto 109:9296ab0bfc11 871
Kojto 109:9296ab0bfc11 872 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
Kojto 109:9296ab0bfc11 873 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
Kojto 109:9296ab0bfc11 874
Kojto 109:9296ab0bfc11 875 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Kojto 109:9296ab0bfc11 876 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Kojto 109:9296ab0bfc11 877
Kojto 109:9296ab0bfc11 878 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 109:9296ab0bfc11 879 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 109:9296ab0bfc11 880
Kojto 109:9296ab0bfc11 881 /*@} end of group CMSIS_SCnotSCB */
Kojto 109:9296ab0bfc11 882
Kojto 109:9296ab0bfc11 883
Kojto 109:9296ab0bfc11 884 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 885 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 109:9296ab0bfc11 886 \brief Type definitions for the System Timer Registers.
Kojto 109:9296ab0bfc11 887 @{
Kojto 109:9296ab0bfc11 888 */
Kojto 109:9296ab0bfc11 889
Kojto 109:9296ab0bfc11 890 /** \brief Structure type to access the System Timer (SysTick).
Kojto 109:9296ab0bfc11 891 */
Kojto 109:9296ab0bfc11 892 typedef struct
Kojto 109:9296ab0bfc11 893 {
Kojto 109:9296ab0bfc11 894 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 109:9296ab0bfc11 895 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 109:9296ab0bfc11 896 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 109:9296ab0bfc11 897 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 109:9296ab0bfc11 898 } SysTick_Type;
Kojto 109:9296ab0bfc11 899
Kojto 109:9296ab0bfc11 900 /* SysTick Control / Status Register Definitions */
Kojto 109:9296ab0bfc11 901 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 109:9296ab0bfc11 902 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 109:9296ab0bfc11 903
Kojto 109:9296ab0bfc11 904 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 109:9296ab0bfc11 905 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 109:9296ab0bfc11 906
Kojto 109:9296ab0bfc11 907 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 109:9296ab0bfc11 908 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 109:9296ab0bfc11 909
Kojto 109:9296ab0bfc11 910 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 109:9296ab0bfc11 911 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 109:9296ab0bfc11 912
Kojto 109:9296ab0bfc11 913 /* SysTick Reload Register Definitions */
Kojto 109:9296ab0bfc11 914 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 109:9296ab0bfc11 915 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 109:9296ab0bfc11 916
Kojto 109:9296ab0bfc11 917 /* SysTick Current Register Definitions */
Kojto 109:9296ab0bfc11 918 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 109:9296ab0bfc11 919 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 109:9296ab0bfc11 920
Kojto 109:9296ab0bfc11 921 /* SysTick Calibration Register Definitions */
Kojto 109:9296ab0bfc11 922 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 109:9296ab0bfc11 923 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 109:9296ab0bfc11 924
Kojto 109:9296ab0bfc11 925 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 109:9296ab0bfc11 926 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 109:9296ab0bfc11 927
Kojto 109:9296ab0bfc11 928 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 109:9296ab0bfc11 929 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 109:9296ab0bfc11 930
Kojto 109:9296ab0bfc11 931 /*@} end of group CMSIS_SysTick */
Kojto 109:9296ab0bfc11 932
Kojto 109:9296ab0bfc11 933
Kojto 109:9296ab0bfc11 934 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 935 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 109:9296ab0bfc11 936 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 109:9296ab0bfc11 937 @{
Kojto 109:9296ab0bfc11 938 */
Kojto 109:9296ab0bfc11 939
Kojto 109:9296ab0bfc11 940 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 109:9296ab0bfc11 941 */
Kojto 109:9296ab0bfc11 942 typedef struct
Kojto 109:9296ab0bfc11 943 {
Kojto 109:9296ab0bfc11 944 __O union
Kojto 109:9296ab0bfc11 945 {
Kojto 109:9296ab0bfc11 946 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 109:9296ab0bfc11 947 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 109:9296ab0bfc11 948 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 109:9296ab0bfc11 949 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 109:9296ab0bfc11 950 uint32_t RESERVED0[864];
Kojto 109:9296ab0bfc11 951 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 109:9296ab0bfc11 952 uint32_t RESERVED1[15];
Kojto 109:9296ab0bfc11 953 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 109:9296ab0bfc11 954 uint32_t RESERVED2[15];
Kojto 109:9296ab0bfc11 955 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 109:9296ab0bfc11 956 uint32_t RESERVED3[29];
Kojto 109:9296ab0bfc11 957 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 109:9296ab0bfc11 958 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 109:9296ab0bfc11 959 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 109:9296ab0bfc11 960 uint32_t RESERVED4[43];
Kojto 109:9296ab0bfc11 961 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 109:9296ab0bfc11 962 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 109:9296ab0bfc11 963 uint32_t RESERVED5[6];
Kojto 109:9296ab0bfc11 964 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 109:9296ab0bfc11 965 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 109:9296ab0bfc11 966 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 109:9296ab0bfc11 967 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 109:9296ab0bfc11 968 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 109:9296ab0bfc11 969 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 109:9296ab0bfc11 970 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 109:9296ab0bfc11 971 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 109:9296ab0bfc11 972 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 109:9296ab0bfc11 973 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 109:9296ab0bfc11 974 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 109:9296ab0bfc11 975 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 109:9296ab0bfc11 976 } ITM_Type;
Kojto 109:9296ab0bfc11 977
Kojto 109:9296ab0bfc11 978 /* ITM Trace Privilege Register Definitions */
Kojto 109:9296ab0bfc11 979 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 109:9296ab0bfc11 980 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
Kojto 109:9296ab0bfc11 981
Kojto 109:9296ab0bfc11 982 /* ITM Trace Control Register Definitions */
Kojto 109:9296ab0bfc11 983 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kojto 109:9296ab0bfc11 984 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 109:9296ab0bfc11 985
Kojto 109:9296ab0bfc11 986 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Kojto 109:9296ab0bfc11 987 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 109:9296ab0bfc11 988
Kojto 109:9296ab0bfc11 989 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Kojto 109:9296ab0bfc11 990 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 109:9296ab0bfc11 991
Kojto 109:9296ab0bfc11 992 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kojto 109:9296ab0bfc11 993 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 109:9296ab0bfc11 994
Kojto 109:9296ab0bfc11 995 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kojto 109:9296ab0bfc11 996 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 109:9296ab0bfc11 997
Kojto 109:9296ab0bfc11 998 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kojto 109:9296ab0bfc11 999 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 109:9296ab0bfc11 1000
Kojto 109:9296ab0bfc11 1001 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kojto 109:9296ab0bfc11 1002 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 109:9296ab0bfc11 1003
Kojto 109:9296ab0bfc11 1004 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kojto 109:9296ab0bfc11 1005 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 109:9296ab0bfc11 1006
Kojto 109:9296ab0bfc11 1007 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 109:9296ab0bfc11 1008 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 109:9296ab0bfc11 1009
Kojto 109:9296ab0bfc11 1010 /* ITM Integration Write Register Definitions */
Kojto 109:9296ab0bfc11 1011 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 109:9296ab0bfc11 1012 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
Kojto 109:9296ab0bfc11 1013
Kojto 109:9296ab0bfc11 1014 /* ITM Integration Read Register Definitions */
Kojto 109:9296ab0bfc11 1015 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 109:9296ab0bfc11 1016 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
Kojto 109:9296ab0bfc11 1017
Kojto 109:9296ab0bfc11 1018 /* ITM Integration Mode Control Register Definitions */
Kojto 109:9296ab0bfc11 1019 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 109:9296ab0bfc11 1020 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 109:9296ab0bfc11 1021
Kojto 109:9296ab0bfc11 1022 /* ITM Lock Status Register Definitions */
Kojto 109:9296ab0bfc11 1023 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kojto 109:9296ab0bfc11 1024 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 109:9296ab0bfc11 1025
Kojto 109:9296ab0bfc11 1026 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kojto 109:9296ab0bfc11 1027 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 109:9296ab0bfc11 1028
Kojto 109:9296ab0bfc11 1029 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 109:9296ab0bfc11 1030 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
Kojto 109:9296ab0bfc11 1031
Kojto 109:9296ab0bfc11 1032 /*@}*/ /* end of group CMSIS_ITM */
Kojto 109:9296ab0bfc11 1033
Kojto 109:9296ab0bfc11 1034
Kojto 109:9296ab0bfc11 1035 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 1036 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 109:9296ab0bfc11 1037 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 109:9296ab0bfc11 1038 @{
Kojto 109:9296ab0bfc11 1039 */
Kojto 109:9296ab0bfc11 1040
Kojto 109:9296ab0bfc11 1041 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 109:9296ab0bfc11 1042 */
Kojto 109:9296ab0bfc11 1043 typedef struct
Kojto 109:9296ab0bfc11 1044 {
Kojto 109:9296ab0bfc11 1045 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 109:9296ab0bfc11 1046 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 109:9296ab0bfc11 1047 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 109:9296ab0bfc11 1048 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 109:9296ab0bfc11 1049 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 109:9296ab0bfc11 1050 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 109:9296ab0bfc11 1051 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 109:9296ab0bfc11 1052 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 109:9296ab0bfc11 1053 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 109:9296ab0bfc11 1054 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 109:9296ab0bfc11 1055 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 109:9296ab0bfc11 1056 uint32_t RESERVED0[1];
Kojto 109:9296ab0bfc11 1057 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 109:9296ab0bfc11 1058 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 109:9296ab0bfc11 1059 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 109:9296ab0bfc11 1060 uint32_t RESERVED1[1];
Kojto 109:9296ab0bfc11 1061 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 109:9296ab0bfc11 1062 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 109:9296ab0bfc11 1063 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 109:9296ab0bfc11 1064 uint32_t RESERVED2[1];
Kojto 109:9296ab0bfc11 1065 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 109:9296ab0bfc11 1066 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 109:9296ab0bfc11 1067 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 109:9296ab0bfc11 1068 uint32_t RESERVED3[981];
Kojto 109:9296ab0bfc11 1069 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
Kojto 109:9296ab0bfc11 1070 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
Kojto 109:9296ab0bfc11 1071 } DWT_Type;
Kojto 109:9296ab0bfc11 1072
Kojto 109:9296ab0bfc11 1073 /* DWT Control Register Definitions */
Kojto 109:9296ab0bfc11 1074 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Kojto 109:9296ab0bfc11 1075 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 109:9296ab0bfc11 1076
Kojto 109:9296ab0bfc11 1077 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Kojto 109:9296ab0bfc11 1078 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 109:9296ab0bfc11 1079
Kojto 109:9296ab0bfc11 1080 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 109:9296ab0bfc11 1081 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 109:9296ab0bfc11 1082
Kojto 109:9296ab0bfc11 1083 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Kojto 109:9296ab0bfc11 1084 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 109:9296ab0bfc11 1085
Kojto 109:9296ab0bfc11 1086 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Kojto 109:9296ab0bfc11 1087 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 109:9296ab0bfc11 1088
Kojto 109:9296ab0bfc11 1089 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Kojto 109:9296ab0bfc11 1090 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 109:9296ab0bfc11 1091
Kojto 109:9296ab0bfc11 1092 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 109:9296ab0bfc11 1093 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 109:9296ab0bfc11 1094
Kojto 109:9296ab0bfc11 1095 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Kojto 109:9296ab0bfc11 1096 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 109:9296ab0bfc11 1097
Kojto 109:9296ab0bfc11 1098 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 109:9296ab0bfc11 1099 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 109:9296ab0bfc11 1100
Kojto 109:9296ab0bfc11 1101 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Kojto 109:9296ab0bfc11 1102 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 109:9296ab0bfc11 1103
Kojto 109:9296ab0bfc11 1104 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Kojto 109:9296ab0bfc11 1105 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 109:9296ab0bfc11 1106
Kojto 109:9296ab0bfc11 1107 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Kojto 109:9296ab0bfc11 1108 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 109:9296ab0bfc11 1109
Kojto 109:9296ab0bfc11 1110 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 109:9296ab0bfc11 1111 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 109:9296ab0bfc11 1112
Kojto 109:9296ab0bfc11 1113 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Kojto 109:9296ab0bfc11 1114 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 109:9296ab0bfc11 1115
Kojto 109:9296ab0bfc11 1116 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Kojto 109:9296ab0bfc11 1117 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 109:9296ab0bfc11 1118
Kojto 109:9296ab0bfc11 1119 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Kojto 109:9296ab0bfc11 1120 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 109:9296ab0bfc11 1121
Kojto 109:9296ab0bfc11 1122 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Kojto 109:9296ab0bfc11 1123 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 109:9296ab0bfc11 1124
Kojto 109:9296ab0bfc11 1125 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 109:9296ab0bfc11 1126 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 109:9296ab0bfc11 1127
Kojto 109:9296ab0bfc11 1128 /* DWT CPI Count Register Definitions */
Kojto 109:9296ab0bfc11 1129 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 109:9296ab0bfc11 1130 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
Kojto 109:9296ab0bfc11 1131
Kojto 109:9296ab0bfc11 1132 /* DWT Exception Overhead Count Register Definitions */
Kojto 109:9296ab0bfc11 1133 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 109:9296ab0bfc11 1134 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 109:9296ab0bfc11 1135
Kojto 109:9296ab0bfc11 1136 /* DWT Sleep Count Register Definitions */
Kojto 109:9296ab0bfc11 1137 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 109:9296ab0bfc11 1138 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 109:9296ab0bfc11 1139
Kojto 109:9296ab0bfc11 1140 /* DWT LSU Count Register Definitions */
Kojto 109:9296ab0bfc11 1141 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 109:9296ab0bfc11 1142 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 109:9296ab0bfc11 1143
Kojto 109:9296ab0bfc11 1144 /* DWT Folded-instruction Count Register Definitions */
Kojto 109:9296ab0bfc11 1145 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 109:9296ab0bfc11 1146 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 109:9296ab0bfc11 1147
Kojto 109:9296ab0bfc11 1148 /* DWT Comparator Mask Register Definitions */
Kojto 109:9296ab0bfc11 1149 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 109:9296ab0bfc11 1150 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
Kojto 109:9296ab0bfc11 1151
Kojto 109:9296ab0bfc11 1152 /* DWT Comparator Function Register Definitions */
Kojto 109:9296ab0bfc11 1153 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Kojto 109:9296ab0bfc11 1154 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 109:9296ab0bfc11 1155
Kojto 109:9296ab0bfc11 1156 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 109:9296ab0bfc11 1157 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 109:9296ab0bfc11 1158
Kojto 109:9296ab0bfc11 1159 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 109:9296ab0bfc11 1160 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 109:9296ab0bfc11 1161
Kojto 109:9296ab0bfc11 1162 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 109:9296ab0bfc11 1163 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 109:9296ab0bfc11 1164
Kojto 109:9296ab0bfc11 1165 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 109:9296ab0bfc11 1166 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 109:9296ab0bfc11 1167
Kojto 109:9296ab0bfc11 1168 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 109:9296ab0bfc11 1169 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 109:9296ab0bfc11 1170
Kojto 109:9296ab0bfc11 1171 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 109:9296ab0bfc11 1172 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 109:9296ab0bfc11 1173
Kojto 109:9296ab0bfc11 1174 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 109:9296ab0bfc11 1175 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 109:9296ab0bfc11 1176
Kojto 109:9296ab0bfc11 1177 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 109:9296ab0bfc11 1178 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 109:9296ab0bfc11 1179
Kojto 109:9296ab0bfc11 1180 /*@}*/ /* end of group CMSIS_DWT */
Kojto 109:9296ab0bfc11 1181
Kojto 109:9296ab0bfc11 1182
Kojto 109:9296ab0bfc11 1183 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 1184 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 109:9296ab0bfc11 1185 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 109:9296ab0bfc11 1186 @{
Kojto 109:9296ab0bfc11 1187 */
Kojto 109:9296ab0bfc11 1188
Kojto 109:9296ab0bfc11 1189 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 109:9296ab0bfc11 1190 */
Kojto 109:9296ab0bfc11 1191 typedef struct
Kojto 109:9296ab0bfc11 1192 {
Kojto 109:9296ab0bfc11 1193 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 109:9296ab0bfc11 1194 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 109:9296ab0bfc11 1195 uint32_t RESERVED0[2];
Kojto 109:9296ab0bfc11 1196 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 109:9296ab0bfc11 1197 uint32_t RESERVED1[55];
Kojto 109:9296ab0bfc11 1198 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 109:9296ab0bfc11 1199 uint32_t RESERVED2[131];
Kojto 109:9296ab0bfc11 1200 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 109:9296ab0bfc11 1201 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 109:9296ab0bfc11 1202 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 109:9296ab0bfc11 1203 uint32_t RESERVED3[759];
Kojto 109:9296ab0bfc11 1204 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 109:9296ab0bfc11 1205 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 109:9296ab0bfc11 1206 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 109:9296ab0bfc11 1207 uint32_t RESERVED4[1];
Kojto 109:9296ab0bfc11 1208 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 109:9296ab0bfc11 1209 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 109:9296ab0bfc11 1210 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 109:9296ab0bfc11 1211 uint32_t RESERVED5[39];
Kojto 109:9296ab0bfc11 1212 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 109:9296ab0bfc11 1213 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 109:9296ab0bfc11 1214 uint32_t RESERVED7[8];
Kojto 109:9296ab0bfc11 1215 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 109:9296ab0bfc11 1216 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 109:9296ab0bfc11 1217 } TPI_Type;
Kojto 109:9296ab0bfc11 1218
Kojto 109:9296ab0bfc11 1219 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 109:9296ab0bfc11 1220 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 109:9296ab0bfc11 1221 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
Kojto 109:9296ab0bfc11 1222
Kojto 109:9296ab0bfc11 1223 /* TPI Selected Pin Protocol Register Definitions */
Kojto 109:9296ab0bfc11 1224 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 109:9296ab0bfc11 1225 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
Kojto 109:9296ab0bfc11 1226
Kojto 109:9296ab0bfc11 1227 /* TPI Formatter and Flush Status Register Definitions */
Kojto 109:9296ab0bfc11 1228 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Kojto 109:9296ab0bfc11 1229 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 109:9296ab0bfc11 1230
Kojto 109:9296ab0bfc11 1231 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Kojto 109:9296ab0bfc11 1232 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 109:9296ab0bfc11 1233
Kojto 109:9296ab0bfc11 1234 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Kojto 109:9296ab0bfc11 1235 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 109:9296ab0bfc11 1236
Kojto 109:9296ab0bfc11 1237 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 109:9296ab0bfc11 1238 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
Kojto 109:9296ab0bfc11 1239
Kojto 109:9296ab0bfc11 1240 /* TPI Formatter and Flush Control Register Definitions */
Kojto 109:9296ab0bfc11 1241 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Kojto 109:9296ab0bfc11 1242 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 109:9296ab0bfc11 1243
Kojto 109:9296ab0bfc11 1244 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Kojto 109:9296ab0bfc11 1245 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 109:9296ab0bfc11 1246
Kojto 109:9296ab0bfc11 1247 /* TPI TRIGGER Register Definitions */
Kojto 109:9296ab0bfc11 1248 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 109:9296ab0bfc11 1249 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 109:9296ab0bfc11 1250
Kojto 109:9296ab0bfc11 1251 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 109:9296ab0bfc11 1252 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 109:9296ab0bfc11 1253 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 109:9296ab0bfc11 1254
Kojto 109:9296ab0bfc11 1255 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 109:9296ab0bfc11 1256 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 109:9296ab0bfc11 1257
Kojto 109:9296ab0bfc11 1258 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 109:9296ab0bfc11 1259 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 109:9296ab0bfc11 1260
Kojto 109:9296ab0bfc11 1261 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 109:9296ab0bfc11 1262 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 109:9296ab0bfc11 1263
Kojto 109:9296ab0bfc11 1264 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Kojto 109:9296ab0bfc11 1265 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 109:9296ab0bfc11 1266
Kojto 109:9296ab0bfc11 1267 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Kojto 109:9296ab0bfc11 1268 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 109:9296ab0bfc11 1269
Kojto 109:9296ab0bfc11 1270 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 109:9296ab0bfc11 1271 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
Kojto 109:9296ab0bfc11 1272
Kojto 109:9296ab0bfc11 1273 /* TPI ITATBCTR2 Register Definitions */
Kojto 109:9296ab0bfc11 1274 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 109:9296ab0bfc11 1275 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 109:9296ab0bfc11 1276
Kojto 109:9296ab0bfc11 1277 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 109:9296ab0bfc11 1278 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 109:9296ab0bfc11 1279 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 109:9296ab0bfc11 1280
Kojto 109:9296ab0bfc11 1281 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 109:9296ab0bfc11 1282 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 109:9296ab0bfc11 1283
Kojto 109:9296ab0bfc11 1284 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 109:9296ab0bfc11 1285 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 109:9296ab0bfc11 1286
Kojto 109:9296ab0bfc11 1287 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 109:9296ab0bfc11 1288 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 109:9296ab0bfc11 1289
Kojto 109:9296ab0bfc11 1290 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Kojto 109:9296ab0bfc11 1291 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 109:9296ab0bfc11 1292
Kojto 109:9296ab0bfc11 1293 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Kojto 109:9296ab0bfc11 1294 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 109:9296ab0bfc11 1295
Kojto 109:9296ab0bfc11 1296 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 109:9296ab0bfc11 1297 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
Kojto 109:9296ab0bfc11 1298
Kojto 109:9296ab0bfc11 1299 /* TPI ITATBCTR0 Register Definitions */
Kojto 109:9296ab0bfc11 1300 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 109:9296ab0bfc11 1301 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 109:9296ab0bfc11 1302
Kojto 109:9296ab0bfc11 1303 /* TPI Integration Mode Control Register Definitions */
Kojto 109:9296ab0bfc11 1304 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 109:9296ab0bfc11 1305 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
Kojto 109:9296ab0bfc11 1306
Kojto 109:9296ab0bfc11 1307 /* TPI DEVID Register Definitions */
Kojto 109:9296ab0bfc11 1308 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Kojto 109:9296ab0bfc11 1309 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 109:9296ab0bfc11 1310
Kojto 109:9296ab0bfc11 1311 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Kojto 109:9296ab0bfc11 1312 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 109:9296ab0bfc11 1313
Kojto 109:9296ab0bfc11 1314 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Kojto 109:9296ab0bfc11 1315 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 109:9296ab0bfc11 1316
Kojto 109:9296ab0bfc11 1317 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Kojto 109:9296ab0bfc11 1318 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 109:9296ab0bfc11 1319
Kojto 109:9296ab0bfc11 1320 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Kojto 109:9296ab0bfc11 1321 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 109:9296ab0bfc11 1322
Kojto 109:9296ab0bfc11 1323 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 109:9296ab0bfc11 1324 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 109:9296ab0bfc11 1325
Kojto 109:9296ab0bfc11 1326 /* TPI DEVTYPE Register Definitions */
Kojto 109:9296ab0bfc11 1327 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Kojto 109:9296ab0bfc11 1328 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 109:9296ab0bfc11 1329
Kojto 109:9296ab0bfc11 1330 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 109:9296ab0bfc11 1331 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 109:9296ab0bfc11 1332
Kojto 109:9296ab0bfc11 1333 /*@}*/ /* end of group CMSIS_TPI */
Kojto 109:9296ab0bfc11 1334
Kojto 109:9296ab0bfc11 1335
Kojto 109:9296ab0bfc11 1336 #if (__MPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 1337 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 1338 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 109:9296ab0bfc11 1339 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 109:9296ab0bfc11 1340 @{
Kojto 109:9296ab0bfc11 1341 */
Kojto 109:9296ab0bfc11 1342
Kojto 109:9296ab0bfc11 1343 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 109:9296ab0bfc11 1344 */
Kojto 109:9296ab0bfc11 1345 typedef struct
Kojto 109:9296ab0bfc11 1346 {
Kojto 109:9296ab0bfc11 1347 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 109:9296ab0bfc11 1348 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 109:9296ab0bfc11 1349 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 109:9296ab0bfc11 1350 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 109:9296ab0bfc11 1351 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 109:9296ab0bfc11 1352 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 109:9296ab0bfc11 1353 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 109:9296ab0bfc11 1354 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 109:9296ab0bfc11 1355 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 109:9296ab0bfc11 1356 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 109:9296ab0bfc11 1357 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 109:9296ab0bfc11 1358 } MPU_Type;
Kojto 109:9296ab0bfc11 1359
Kojto 109:9296ab0bfc11 1360 /* MPU Type Register */
Kojto 109:9296ab0bfc11 1361 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 109:9296ab0bfc11 1362 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 109:9296ab0bfc11 1363
Kojto 109:9296ab0bfc11 1364 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 109:9296ab0bfc11 1365 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 109:9296ab0bfc11 1366
Kojto 109:9296ab0bfc11 1367 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 109:9296ab0bfc11 1368 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 109:9296ab0bfc11 1369
Kojto 109:9296ab0bfc11 1370 /* MPU Control Register */
Kojto 109:9296ab0bfc11 1371 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 109:9296ab0bfc11 1372 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 109:9296ab0bfc11 1373
Kojto 109:9296ab0bfc11 1374 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 109:9296ab0bfc11 1375 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 109:9296ab0bfc11 1376
Kojto 109:9296ab0bfc11 1377 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 109:9296ab0bfc11 1378 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 109:9296ab0bfc11 1379
Kojto 109:9296ab0bfc11 1380 /* MPU Region Number Register */
Kojto 109:9296ab0bfc11 1381 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 109:9296ab0bfc11 1382 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 109:9296ab0bfc11 1383
Kojto 109:9296ab0bfc11 1384 /* MPU Region Base Address Register */
Kojto 109:9296ab0bfc11 1385 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kojto 109:9296ab0bfc11 1386 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 109:9296ab0bfc11 1387
Kojto 109:9296ab0bfc11 1388 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 109:9296ab0bfc11 1389 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 109:9296ab0bfc11 1390
Kojto 109:9296ab0bfc11 1391 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 109:9296ab0bfc11 1392 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 109:9296ab0bfc11 1393
Kojto 109:9296ab0bfc11 1394 /* MPU Region Attribute and Size Register */
Kojto 109:9296ab0bfc11 1395 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 109:9296ab0bfc11 1396 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 109:9296ab0bfc11 1397
Kojto 109:9296ab0bfc11 1398 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 109:9296ab0bfc11 1399 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 109:9296ab0bfc11 1400
Kojto 109:9296ab0bfc11 1401 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 109:9296ab0bfc11 1402 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 109:9296ab0bfc11 1403
Kojto 109:9296ab0bfc11 1404 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 109:9296ab0bfc11 1405 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 109:9296ab0bfc11 1406
Kojto 109:9296ab0bfc11 1407 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 109:9296ab0bfc11 1408 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 109:9296ab0bfc11 1409
Kojto 109:9296ab0bfc11 1410 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 109:9296ab0bfc11 1411 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 109:9296ab0bfc11 1412
Kojto 109:9296ab0bfc11 1413 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 109:9296ab0bfc11 1414 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 109:9296ab0bfc11 1415
Kojto 109:9296ab0bfc11 1416 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 109:9296ab0bfc11 1417 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 109:9296ab0bfc11 1418
Kojto 109:9296ab0bfc11 1419 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 109:9296ab0bfc11 1420 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 109:9296ab0bfc11 1421
Kojto 109:9296ab0bfc11 1422 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 109:9296ab0bfc11 1423 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 109:9296ab0bfc11 1424
Kojto 109:9296ab0bfc11 1425 /*@} end of group CMSIS_MPU */
Kojto 109:9296ab0bfc11 1426 #endif
Kojto 109:9296ab0bfc11 1427
Kojto 109:9296ab0bfc11 1428
Kojto 109:9296ab0bfc11 1429 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 1430 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 1431 \defgroup CMSIS_FPU Floating Point Unit (FPU)
Kojto 109:9296ab0bfc11 1432 \brief Type definitions for the Floating Point Unit (FPU)
Kojto 109:9296ab0bfc11 1433 @{
Kojto 109:9296ab0bfc11 1434 */
Kojto 109:9296ab0bfc11 1435
Kojto 109:9296ab0bfc11 1436 /** \brief Structure type to access the Floating Point Unit (FPU).
Kojto 109:9296ab0bfc11 1437 */
Kojto 109:9296ab0bfc11 1438 typedef struct
Kojto 109:9296ab0bfc11 1439 {
Kojto 109:9296ab0bfc11 1440 uint32_t RESERVED0[1];
Kojto 109:9296ab0bfc11 1441 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
Kojto 109:9296ab0bfc11 1442 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
Kojto 109:9296ab0bfc11 1443 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
Kojto 109:9296ab0bfc11 1444 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
Kojto 109:9296ab0bfc11 1445 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
Kojto 109:9296ab0bfc11 1446 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
Kojto 109:9296ab0bfc11 1447 } FPU_Type;
Kojto 109:9296ab0bfc11 1448
Kojto 109:9296ab0bfc11 1449 /* Floating-Point Context Control Register */
Kojto 109:9296ab0bfc11 1450 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
Kojto 109:9296ab0bfc11 1451 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
Kojto 109:9296ab0bfc11 1452
Kojto 109:9296ab0bfc11 1453 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
Kojto 109:9296ab0bfc11 1454 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
Kojto 109:9296ab0bfc11 1455
Kojto 109:9296ab0bfc11 1456 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
Kojto 109:9296ab0bfc11 1457 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
Kojto 109:9296ab0bfc11 1458
Kojto 109:9296ab0bfc11 1459 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
Kojto 109:9296ab0bfc11 1460 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
Kojto 109:9296ab0bfc11 1461
Kojto 109:9296ab0bfc11 1462 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
Kojto 109:9296ab0bfc11 1463 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
Kojto 109:9296ab0bfc11 1464
Kojto 109:9296ab0bfc11 1465 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
Kojto 109:9296ab0bfc11 1466 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
Kojto 109:9296ab0bfc11 1467
Kojto 109:9296ab0bfc11 1468 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
Kojto 109:9296ab0bfc11 1469 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
Kojto 109:9296ab0bfc11 1470
Kojto 109:9296ab0bfc11 1471 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
Kojto 109:9296ab0bfc11 1472 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
Kojto 109:9296ab0bfc11 1473
Kojto 109:9296ab0bfc11 1474 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
Kojto 109:9296ab0bfc11 1475 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
Kojto 109:9296ab0bfc11 1476
Kojto 109:9296ab0bfc11 1477 /* Floating-Point Context Address Register */
Kojto 109:9296ab0bfc11 1478 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
Kojto 109:9296ab0bfc11 1479 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
Kojto 109:9296ab0bfc11 1480
Kojto 109:9296ab0bfc11 1481 /* Floating-Point Default Status Control Register */
Kojto 109:9296ab0bfc11 1482 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
Kojto 109:9296ab0bfc11 1483 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
Kojto 109:9296ab0bfc11 1484
Kojto 109:9296ab0bfc11 1485 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
Kojto 109:9296ab0bfc11 1486 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
Kojto 109:9296ab0bfc11 1487
Kojto 109:9296ab0bfc11 1488 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
Kojto 109:9296ab0bfc11 1489 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
Kojto 109:9296ab0bfc11 1490
Kojto 109:9296ab0bfc11 1491 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
Kojto 109:9296ab0bfc11 1492 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
Kojto 109:9296ab0bfc11 1493
Kojto 109:9296ab0bfc11 1494 /* Media and FP Feature Register 0 */
Kojto 109:9296ab0bfc11 1495 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
Kojto 109:9296ab0bfc11 1496 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
Kojto 109:9296ab0bfc11 1497
Kojto 109:9296ab0bfc11 1498 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
Kojto 109:9296ab0bfc11 1499 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
Kojto 109:9296ab0bfc11 1500
Kojto 109:9296ab0bfc11 1501 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
Kojto 109:9296ab0bfc11 1502 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
Kojto 109:9296ab0bfc11 1503
Kojto 109:9296ab0bfc11 1504 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
Kojto 109:9296ab0bfc11 1505 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
Kojto 109:9296ab0bfc11 1506
Kojto 109:9296ab0bfc11 1507 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
Kojto 109:9296ab0bfc11 1508 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
Kojto 109:9296ab0bfc11 1509
Kojto 109:9296ab0bfc11 1510 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
Kojto 109:9296ab0bfc11 1511 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
Kojto 109:9296ab0bfc11 1512
Kojto 109:9296ab0bfc11 1513 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
Kojto 109:9296ab0bfc11 1514 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
Kojto 109:9296ab0bfc11 1515
Kojto 109:9296ab0bfc11 1516 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
Kojto 109:9296ab0bfc11 1517 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
Kojto 109:9296ab0bfc11 1518
Kojto 109:9296ab0bfc11 1519 /* Media and FP Feature Register 1 */
Kojto 109:9296ab0bfc11 1520 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
Kojto 109:9296ab0bfc11 1521 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
Kojto 109:9296ab0bfc11 1522
Kojto 109:9296ab0bfc11 1523 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
Kojto 109:9296ab0bfc11 1524 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
Kojto 109:9296ab0bfc11 1525
Kojto 109:9296ab0bfc11 1526 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
Kojto 109:9296ab0bfc11 1527 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
Kojto 109:9296ab0bfc11 1528
Kojto 109:9296ab0bfc11 1529 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
Kojto 109:9296ab0bfc11 1530 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
Kojto 109:9296ab0bfc11 1531
Kojto 109:9296ab0bfc11 1532 /* Media and FP Feature Register 2 */
Kojto 109:9296ab0bfc11 1533
Kojto 109:9296ab0bfc11 1534 /*@} end of group CMSIS_FPU */
Kojto 109:9296ab0bfc11 1535 #endif
Kojto 109:9296ab0bfc11 1536
Kojto 109:9296ab0bfc11 1537
Kojto 109:9296ab0bfc11 1538 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 1539 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 109:9296ab0bfc11 1540 \brief Type definitions for the Core Debug Registers
Kojto 109:9296ab0bfc11 1541 @{
Kojto 109:9296ab0bfc11 1542 */
Kojto 109:9296ab0bfc11 1543
Kojto 109:9296ab0bfc11 1544 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 109:9296ab0bfc11 1545 */
Kojto 109:9296ab0bfc11 1546 typedef struct
Kojto 109:9296ab0bfc11 1547 {
Kojto 109:9296ab0bfc11 1548 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 109:9296ab0bfc11 1549 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 109:9296ab0bfc11 1550 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 109:9296ab0bfc11 1551 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 109:9296ab0bfc11 1552 } CoreDebug_Type;
Kojto 109:9296ab0bfc11 1553
Kojto 109:9296ab0bfc11 1554 /* Debug Halting Control and Status Register */
Kojto 109:9296ab0bfc11 1555 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 109:9296ab0bfc11 1556 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 109:9296ab0bfc11 1557
Kojto 109:9296ab0bfc11 1558 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 109:9296ab0bfc11 1559 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 109:9296ab0bfc11 1560
Kojto 109:9296ab0bfc11 1561 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 109:9296ab0bfc11 1562 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 109:9296ab0bfc11 1563
Kojto 109:9296ab0bfc11 1564 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 109:9296ab0bfc11 1565 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 109:9296ab0bfc11 1566
Kojto 109:9296ab0bfc11 1567 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 109:9296ab0bfc11 1568 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 109:9296ab0bfc11 1569
Kojto 109:9296ab0bfc11 1570 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 109:9296ab0bfc11 1571 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 109:9296ab0bfc11 1572
Kojto 109:9296ab0bfc11 1573 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 109:9296ab0bfc11 1574 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 109:9296ab0bfc11 1575
Kojto 109:9296ab0bfc11 1576 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 109:9296ab0bfc11 1577 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 109:9296ab0bfc11 1578
Kojto 109:9296ab0bfc11 1579 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 109:9296ab0bfc11 1580 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 109:9296ab0bfc11 1581
Kojto 109:9296ab0bfc11 1582 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 109:9296ab0bfc11 1583 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 109:9296ab0bfc11 1584
Kojto 109:9296ab0bfc11 1585 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 109:9296ab0bfc11 1586 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 109:9296ab0bfc11 1587
Kojto 109:9296ab0bfc11 1588 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 109:9296ab0bfc11 1589 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 109:9296ab0bfc11 1590
Kojto 109:9296ab0bfc11 1591 /* Debug Core Register Selector Register */
Kojto 109:9296ab0bfc11 1592 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 109:9296ab0bfc11 1593 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 109:9296ab0bfc11 1594
Kojto 109:9296ab0bfc11 1595 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 109:9296ab0bfc11 1596 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 109:9296ab0bfc11 1597
Kojto 109:9296ab0bfc11 1598 /* Debug Exception and Monitor Control Register */
Kojto 109:9296ab0bfc11 1599 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 109:9296ab0bfc11 1600 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 109:9296ab0bfc11 1601
Kojto 109:9296ab0bfc11 1602 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 109:9296ab0bfc11 1603 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 109:9296ab0bfc11 1604
Kojto 109:9296ab0bfc11 1605 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 109:9296ab0bfc11 1606 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 109:9296ab0bfc11 1607
Kojto 109:9296ab0bfc11 1608 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 109:9296ab0bfc11 1609 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 109:9296ab0bfc11 1610
Kojto 109:9296ab0bfc11 1611 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 109:9296ab0bfc11 1612 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 109:9296ab0bfc11 1613
Kojto 109:9296ab0bfc11 1614 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 109:9296ab0bfc11 1615 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 109:9296ab0bfc11 1616
Kojto 109:9296ab0bfc11 1617 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 109:9296ab0bfc11 1618 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 109:9296ab0bfc11 1619
Kojto 109:9296ab0bfc11 1620 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 109:9296ab0bfc11 1621 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 109:9296ab0bfc11 1622
Kojto 109:9296ab0bfc11 1623 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 109:9296ab0bfc11 1624 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 109:9296ab0bfc11 1625
Kojto 109:9296ab0bfc11 1626 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 109:9296ab0bfc11 1627 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 109:9296ab0bfc11 1628
Kojto 109:9296ab0bfc11 1629 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 109:9296ab0bfc11 1630 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 109:9296ab0bfc11 1631
Kojto 109:9296ab0bfc11 1632 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 109:9296ab0bfc11 1633 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 109:9296ab0bfc11 1634
Kojto 109:9296ab0bfc11 1635 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 109:9296ab0bfc11 1636 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 109:9296ab0bfc11 1637
Kojto 109:9296ab0bfc11 1638 /*@} end of group CMSIS_CoreDebug */
Kojto 109:9296ab0bfc11 1639
Kojto 109:9296ab0bfc11 1640
Kojto 109:9296ab0bfc11 1641 /** \ingroup CMSIS_core_register
Kojto 109:9296ab0bfc11 1642 \defgroup CMSIS_core_base Core Definitions
Kojto 109:9296ab0bfc11 1643 \brief Definitions for base addresses, unions, and structures.
Kojto 109:9296ab0bfc11 1644 @{
Kojto 109:9296ab0bfc11 1645 */
Kojto 109:9296ab0bfc11 1646
Kojto 109:9296ab0bfc11 1647 /* Memory mapping of Cortex-M4 Hardware */
Kojto 109:9296ab0bfc11 1648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 109:9296ab0bfc11 1649 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 109:9296ab0bfc11 1650 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 109:9296ab0bfc11 1651 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 109:9296ab0bfc11 1652 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 109:9296ab0bfc11 1653 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 109:9296ab0bfc11 1654 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 109:9296ab0bfc11 1655 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 109:9296ab0bfc11 1656
Kojto 109:9296ab0bfc11 1657 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 109:9296ab0bfc11 1658 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 109:9296ab0bfc11 1659 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 109:9296ab0bfc11 1660 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 109:9296ab0bfc11 1661 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 109:9296ab0bfc11 1662 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 109:9296ab0bfc11 1663 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 109:9296ab0bfc11 1664 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 109:9296ab0bfc11 1665
Kojto 109:9296ab0bfc11 1666 #if (__MPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 1667 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 109:9296ab0bfc11 1668 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 109:9296ab0bfc11 1669 #endif
Kojto 109:9296ab0bfc11 1670
Kojto 109:9296ab0bfc11 1671 #if (__FPU_PRESENT == 1)
Kojto 109:9296ab0bfc11 1672 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
Kojto 109:9296ab0bfc11 1673 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
Kojto 109:9296ab0bfc11 1674 #endif
Kojto 109:9296ab0bfc11 1675
Kojto 109:9296ab0bfc11 1676 /*@} */
Kojto 109:9296ab0bfc11 1677
Kojto 109:9296ab0bfc11 1678
Kojto 109:9296ab0bfc11 1679
Kojto 109:9296ab0bfc11 1680 /*******************************************************************************
Kojto 109:9296ab0bfc11 1681 * Hardware Abstraction Layer
Kojto 109:9296ab0bfc11 1682 Core Function Interface contains:
Kojto 109:9296ab0bfc11 1683 - Core NVIC Functions
Kojto 109:9296ab0bfc11 1684 - Core SysTick Functions
Kojto 109:9296ab0bfc11 1685 - Core Debug Functions
Kojto 109:9296ab0bfc11 1686 - Core Register Access Functions
Kojto 109:9296ab0bfc11 1687 ******************************************************************************/
Kojto 109:9296ab0bfc11 1688 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 109:9296ab0bfc11 1689 */
Kojto 109:9296ab0bfc11 1690
Kojto 109:9296ab0bfc11 1691
Kojto 109:9296ab0bfc11 1692
Kojto 109:9296ab0bfc11 1693 /* ########################## NVIC functions #################################### */
Kojto 109:9296ab0bfc11 1694 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 1695 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 109:9296ab0bfc11 1696 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 109:9296ab0bfc11 1697 @{
Kojto 109:9296ab0bfc11 1698 */
Kojto 109:9296ab0bfc11 1699
Kojto 109:9296ab0bfc11 1700 /** \brief Set Priority Grouping
Kojto 109:9296ab0bfc11 1701
Kojto 109:9296ab0bfc11 1702 The function sets the priority grouping field using the required unlock sequence.
Kojto 109:9296ab0bfc11 1703 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 109:9296ab0bfc11 1704 Only values from 0..7 are used.
Kojto 109:9296ab0bfc11 1705 In case of a conflict between priority grouping and available
Kojto 109:9296ab0bfc11 1706 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 109:9296ab0bfc11 1707
Kojto 109:9296ab0bfc11 1708 \param [in] PriorityGroup Priority grouping field.
Kojto 109:9296ab0bfc11 1709 */
Kojto 109:9296ab0bfc11 1710 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 109:9296ab0bfc11 1711 {
Kojto 109:9296ab0bfc11 1712 uint32_t reg_value;
Kojto 109:9296ab0bfc11 1713 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 109:9296ab0bfc11 1714
Kojto 109:9296ab0bfc11 1715 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 109:9296ab0bfc11 1716 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 109:9296ab0bfc11 1717 reg_value = (reg_value |
Kojto 109:9296ab0bfc11 1718 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 109:9296ab0bfc11 1719 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
Kojto 109:9296ab0bfc11 1720 SCB->AIRCR = reg_value;
Kojto 109:9296ab0bfc11 1721 }
Kojto 109:9296ab0bfc11 1722
Kojto 109:9296ab0bfc11 1723
Kojto 109:9296ab0bfc11 1724 /** \brief Get Priority Grouping
Kojto 109:9296ab0bfc11 1725
Kojto 109:9296ab0bfc11 1726 The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 109:9296ab0bfc11 1727
Kojto 109:9296ab0bfc11 1728 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 109:9296ab0bfc11 1729 */
Kojto 109:9296ab0bfc11 1730 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto 109:9296ab0bfc11 1731 {
Kojto 109:9296ab0bfc11 1732 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
Kojto 109:9296ab0bfc11 1733 }
Kojto 109:9296ab0bfc11 1734
Kojto 109:9296ab0bfc11 1735
Kojto 109:9296ab0bfc11 1736 /** \brief Enable External Interrupt
Kojto 109:9296ab0bfc11 1737
Kojto 109:9296ab0bfc11 1738 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 109:9296ab0bfc11 1739
Kojto 109:9296ab0bfc11 1740 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 109:9296ab0bfc11 1741 */
Kojto 109:9296ab0bfc11 1742 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 1743 {
Kojto 109:9296ab0bfc11 1744 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 109:9296ab0bfc11 1745 }
Kojto 109:9296ab0bfc11 1746
Kojto 109:9296ab0bfc11 1747
Kojto 109:9296ab0bfc11 1748 /** \brief Disable External Interrupt
Kojto 109:9296ab0bfc11 1749
Kojto 109:9296ab0bfc11 1750 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 109:9296ab0bfc11 1751
Kojto 109:9296ab0bfc11 1752 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 109:9296ab0bfc11 1753 */
Kojto 109:9296ab0bfc11 1754 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 1755 {
Kojto 109:9296ab0bfc11 1756 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1757 __DSB();
<> 131:faff56e089b2 1758 __ISB();
Kojto 109:9296ab0bfc11 1759 }
Kojto 109:9296ab0bfc11 1760
Kojto 109:9296ab0bfc11 1761
Kojto 109:9296ab0bfc11 1762 /** \brief Get Pending Interrupt
Kojto 109:9296ab0bfc11 1763
Kojto 109:9296ab0bfc11 1764 The function reads the pending register in the NVIC and returns the pending bit
Kojto 109:9296ab0bfc11 1765 for the specified interrupt.
Kojto 109:9296ab0bfc11 1766
Kojto 109:9296ab0bfc11 1767 \param [in] IRQn Interrupt number.
Kojto 109:9296ab0bfc11 1768
Kojto 109:9296ab0bfc11 1769 \return 0 Interrupt status is not pending.
Kojto 109:9296ab0bfc11 1770 \return 1 Interrupt status is pending.
Kojto 109:9296ab0bfc11 1771 */
Kojto 109:9296ab0bfc11 1772 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 1773 {
Kojto 109:9296ab0bfc11 1774 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 109:9296ab0bfc11 1775 }
Kojto 109:9296ab0bfc11 1776
Kojto 109:9296ab0bfc11 1777
Kojto 109:9296ab0bfc11 1778 /** \brief Set Pending Interrupt
Kojto 109:9296ab0bfc11 1779
Kojto 109:9296ab0bfc11 1780 The function sets the pending bit of an external interrupt.
Kojto 109:9296ab0bfc11 1781
Kojto 109:9296ab0bfc11 1782 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 109:9296ab0bfc11 1783 */
Kojto 109:9296ab0bfc11 1784 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 1785 {
Kojto 109:9296ab0bfc11 1786 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 109:9296ab0bfc11 1787 }
Kojto 109:9296ab0bfc11 1788
Kojto 109:9296ab0bfc11 1789
Kojto 109:9296ab0bfc11 1790 /** \brief Clear Pending Interrupt
Kojto 109:9296ab0bfc11 1791
Kojto 109:9296ab0bfc11 1792 The function clears the pending bit of an external interrupt.
Kojto 109:9296ab0bfc11 1793
Kojto 109:9296ab0bfc11 1794 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 109:9296ab0bfc11 1795 */
Kojto 109:9296ab0bfc11 1796 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 1797 {
Kojto 109:9296ab0bfc11 1798 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 109:9296ab0bfc11 1799 }
Kojto 109:9296ab0bfc11 1800
Kojto 109:9296ab0bfc11 1801
Kojto 109:9296ab0bfc11 1802 /** \brief Get Active Interrupt
Kojto 109:9296ab0bfc11 1803
Kojto 109:9296ab0bfc11 1804 The function reads the active register in NVIC and returns the active bit.
Kojto 109:9296ab0bfc11 1805
Kojto 109:9296ab0bfc11 1806 \param [in] IRQn Interrupt number.
Kojto 109:9296ab0bfc11 1807
Kojto 109:9296ab0bfc11 1808 \return 0 Interrupt status is not active.
Kojto 109:9296ab0bfc11 1809 \return 1 Interrupt status is active.
Kojto 109:9296ab0bfc11 1810 */
Kojto 109:9296ab0bfc11 1811 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 1812 {
Kojto 109:9296ab0bfc11 1813 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 109:9296ab0bfc11 1814 }
Kojto 109:9296ab0bfc11 1815
Kojto 109:9296ab0bfc11 1816
Kojto 109:9296ab0bfc11 1817 /** \brief Set Interrupt Priority
Kojto 109:9296ab0bfc11 1818
Kojto 109:9296ab0bfc11 1819 The function sets the priority of an interrupt.
Kojto 109:9296ab0bfc11 1820
Kojto 109:9296ab0bfc11 1821 \note The priority cannot be set for every core interrupt.
Kojto 109:9296ab0bfc11 1822
Kojto 109:9296ab0bfc11 1823 \param [in] IRQn Interrupt number.
Kojto 109:9296ab0bfc11 1824 \param [in] priority Priority to set.
Kojto 109:9296ab0bfc11 1825 */
Kojto 109:9296ab0bfc11 1826 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 109:9296ab0bfc11 1827 {
Kojto 109:9296ab0bfc11 1828 if((int32_t)IRQn < 0) {
Kojto 109:9296ab0bfc11 1829 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 109:9296ab0bfc11 1830 }
Kojto 109:9296ab0bfc11 1831 else {
Kojto 109:9296ab0bfc11 1832 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 109:9296ab0bfc11 1833 }
Kojto 109:9296ab0bfc11 1834 }
Kojto 109:9296ab0bfc11 1835
Kojto 109:9296ab0bfc11 1836
Kojto 109:9296ab0bfc11 1837 /** \brief Get Interrupt Priority
Kojto 109:9296ab0bfc11 1838
Kojto 109:9296ab0bfc11 1839 The function reads the priority of an interrupt. The interrupt
Kojto 109:9296ab0bfc11 1840 number can be positive to specify an external (device specific)
Kojto 109:9296ab0bfc11 1841 interrupt, or negative to specify an internal (core) interrupt.
Kojto 109:9296ab0bfc11 1842
Kojto 109:9296ab0bfc11 1843
Kojto 109:9296ab0bfc11 1844 \param [in] IRQn Interrupt number.
Kojto 109:9296ab0bfc11 1845 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 109:9296ab0bfc11 1846 priority bits of the microcontroller.
Kojto 109:9296ab0bfc11 1847 */
Kojto 109:9296ab0bfc11 1848 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 109:9296ab0bfc11 1849 {
Kojto 109:9296ab0bfc11 1850
Kojto 109:9296ab0bfc11 1851 if((int32_t)IRQn < 0) {
Kojto 109:9296ab0bfc11 1852 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 109:9296ab0bfc11 1853 }
Kojto 109:9296ab0bfc11 1854 else {
Kojto 109:9296ab0bfc11 1855 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 109:9296ab0bfc11 1856 }
Kojto 109:9296ab0bfc11 1857 }
Kojto 109:9296ab0bfc11 1858
Kojto 109:9296ab0bfc11 1859
Kojto 109:9296ab0bfc11 1860 /** \brief Encode Priority
Kojto 109:9296ab0bfc11 1861
Kojto 109:9296ab0bfc11 1862 The function encodes the priority for an interrupt with the given priority group,
Kojto 109:9296ab0bfc11 1863 preemptive priority value, and subpriority value.
Kojto 109:9296ab0bfc11 1864 In case of a conflict between priority grouping and available
Kojto 109:9296ab0bfc11 1865 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 109:9296ab0bfc11 1866
Kojto 109:9296ab0bfc11 1867 \param [in] PriorityGroup Used priority group.
Kojto 109:9296ab0bfc11 1868 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 109:9296ab0bfc11 1869 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 109:9296ab0bfc11 1870 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 109:9296ab0bfc11 1871 */
Kojto 109:9296ab0bfc11 1872 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 109:9296ab0bfc11 1873 {
Kojto 109:9296ab0bfc11 1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 109:9296ab0bfc11 1875 uint32_t PreemptPriorityBits;
Kojto 109:9296ab0bfc11 1876 uint32_t SubPriorityBits;
Kojto 109:9296ab0bfc11 1877
Kojto 109:9296ab0bfc11 1878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 109:9296ab0bfc11 1879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 109:9296ab0bfc11 1880
Kojto 109:9296ab0bfc11 1881 return (
Kojto 109:9296ab0bfc11 1882 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 109:9296ab0bfc11 1883 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
Kojto 109:9296ab0bfc11 1884 );
Kojto 109:9296ab0bfc11 1885 }
Kojto 109:9296ab0bfc11 1886
Kojto 109:9296ab0bfc11 1887
Kojto 109:9296ab0bfc11 1888 /** \brief Decode Priority
Kojto 109:9296ab0bfc11 1889
Kojto 109:9296ab0bfc11 1890 The function decodes an interrupt priority value with a given priority group to
Kojto 109:9296ab0bfc11 1891 preemptive priority value and subpriority value.
Kojto 109:9296ab0bfc11 1892 In case of a conflict between priority grouping and available
Kojto 109:9296ab0bfc11 1893 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Kojto 109:9296ab0bfc11 1894
Kojto 109:9296ab0bfc11 1895 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 109:9296ab0bfc11 1896 \param [in] PriorityGroup Used priority group.
Kojto 109:9296ab0bfc11 1897 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 109:9296ab0bfc11 1898 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 109:9296ab0bfc11 1899 */
Kojto 109:9296ab0bfc11 1900 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto 109:9296ab0bfc11 1901 {
Kojto 109:9296ab0bfc11 1902 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
Kojto 109:9296ab0bfc11 1903 uint32_t PreemptPriorityBits;
Kojto 109:9296ab0bfc11 1904 uint32_t SubPriorityBits;
Kojto 109:9296ab0bfc11 1905
Kojto 109:9296ab0bfc11 1906 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 109:9296ab0bfc11 1907 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
Kojto 109:9296ab0bfc11 1908
Kojto 109:9296ab0bfc11 1909 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 109:9296ab0bfc11 1910 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
Kojto 109:9296ab0bfc11 1911 }
Kojto 109:9296ab0bfc11 1912
Kojto 109:9296ab0bfc11 1913
Kojto 109:9296ab0bfc11 1914 /** \brief System Reset
Kojto 109:9296ab0bfc11 1915
Kojto 109:9296ab0bfc11 1916 The function initiates a system reset request to reset the MCU.
Kojto 109:9296ab0bfc11 1917 */
Kojto 109:9296ab0bfc11 1918 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 109:9296ab0bfc11 1919 {
Kojto 109:9296ab0bfc11 1920 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 109:9296ab0bfc11 1921 buffered write are completed before reset */
Kojto 109:9296ab0bfc11 1922 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 109:9296ab0bfc11 1923 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 109:9296ab0bfc11 1924 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 109:9296ab0bfc11 1925 __DSB(); /* Ensure completion of memory access */
Kojto 109:9296ab0bfc11 1926 while(1) { __NOP(); } /* wait until reset */
Kojto 109:9296ab0bfc11 1927 }
Kojto 109:9296ab0bfc11 1928
Kojto 109:9296ab0bfc11 1929 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 109:9296ab0bfc11 1930
Kojto 109:9296ab0bfc11 1931
Kojto 109:9296ab0bfc11 1932 /* ########################## FPU functions #################################### */
Kojto 109:9296ab0bfc11 1933 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 1934 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Kojto 109:9296ab0bfc11 1935 \brief Function that provides FPU type.
Kojto 109:9296ab0bfc11 1936 @{
Kojto 109:9296ab0bfc11 1937 */
Kojto 109:9296ab0bfc11 1938
Kojto 109:9296ab0bfc11 1939 /**
Kojto 109:9296ab0bfc11 1940 \fn uint32_t SCB_GetFPUType(void)
Kojto 109:9296ab0bfc11 1941 \brief get FPU type
Kojto 109:9296ab0bfc11 1942 \returns
Kojto 109:9296ab0bfc11 1943 - \b 0: No FPU
Kojto 109:9296ab0bfc11 1944 - \b 1: Single precision FPU
Kojto 109:9296ab0bfc11 1945 - \b 2: Double + Single precision FPU
Kojto 109:9296ab0bfc11 1946 */
Kojto 109:9296ab0bfc11 1947 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Kojto 109:9296ab0bfc11 1948 {
Kojto 109:9296ab0bfc11 1949 uint32_t mvfr0;
Kojto 109:9296ab0bfc11 1950
Kojto 109:9296ab0bfc11 1951 mvfr0 = SCB->MVFR0;
Kojto 109:9296ab0bfc11 1952 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
Kojto 109:9296ab0bfc11 1953 return 2UL; // Double + Single precision FPU
Kojto 109:9296ab0bfc11 1954 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
Kojto 109:9296ab0bfc11 1955 return 1UL; // Single precision FPU
Kojto 109:9296ab0bfc11 1956 } else {
Kojto 109:9296ab0bfc11 1957 return 0UL; // No FPU
Kojto 109:9296ab0bfc11 1958 }
Kojto 109:9296ab0bfc11 1959 }
Kojto 109:9296ab0bfc11 1960
Kojto 109:9296ab0bfc11 1961
Kojto 109:9296ab0bfc11 1962 /*@} end of CMSIS_Core_FpuFunctions */
Kojto 109:9296ab0bfc11 1963
Kojto 109:9296ab0bfc11 1964
Kojto 109:9296ab0bfc11 1965
Kojto 109:9296ab0bfc11 1966 /* ########################## Cache functions #################################### */
Kojto 109:9296ab0bfc11 1967 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 1968 \defgroup CMSIS_Core_CacheFunctions Cache Functions
Kojto 109:9296ab0bfc11 1969 \brief Functions that configure Instruction and Data cache.
Kojto 109:9296ab0bfc11 1970 @{
Kojto 109:9296ab0bfc11 1971 */
Kojto 109:9296ab0bfc11 1972
Kojto 109:9296ab0bfc11 1973 /* Cache Size ID Register Macros */
Kojto 109:9296ab0bfc11 1974 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
Kojto 109:9296ab0bfc11 1975 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
Kojto 109:9296ab0bfc11 1976 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
Kojto 109:9296ab0bfc11 1977
Kojto 109:9296ab0bfc11 1978
Kojto 109:9296ab0bfc11 1979 /** \brief Enable I-Cache
Kojto 109:9296ab0bfc11 1980
Kojto 109:9296ab0bfc11 1981 The function turns on I-Cache
Kojto 109:9296ab0bfc11 1982 */
Kojto 109:9296ab0bfc11 1983 __STATIC_INLINE void SCB_EnableICache (void)
Kojto 109:9296ab0bfc11 1984 {
Kojto 109:9296ab0bfc11 1985 #if (__ICACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 1986 __DSB();
Kojto 109:9296ab0bfc11 1987 __ISB();
Kojto 109:9296ab0bfc11 1988 SCB->ICIALLU = 0UL; // invalidate I-Cache
Kojto 109:9296ab0bfc11 1989 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
Kojto 109:9296ab0bfc11 1990 __DSB();
Kojto 109:9296ab0bfc11 1991 __ISB();
Kojto 109:9296ab0bfc11 1992 #endif
Kojto 109:9296ab0bfc11 1993 }
Kojto 109:9296ab0bfc11 1994
Kojto 109:9296ab0bfc11 1995
Kojto 109:9296ab0bfc11 1996 /** \brief Disable I-Cache
Kojto 109:9296ab0bfc11 1997
Kojto 109:9296ab0bfc11 1998 The function turns off I-Cache
Kojto 109:9296ab0bfc11 1999 */
Kojto 109:9296ab0bfc11 2000 __STATIC_INLINE void SCB_DisableICache (void)
Kojto 109:9296ab0bfc11 2001 {
Kojto 109:9296ab0bfc11 2002 #if (__ICACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2003 __DSB();
Kojto 109:9296ab0bfc11 2004 __ISB();
Kojto 109:9296ab0bfc11 2005 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
Kojto 109:9296ab0bfc11 2006 SCB->ICIALLU = 0UL; // invalidate I-Cache
Kojto 109:9296ab0bfc11 2007 __DSB();
Kojto 109:9296ab0bfc11 2008 __ISB();
Kojto 109:9296ab0bfc11 2009 #endif
Kojto 109:9296ab0bfc11 2010 }
Kojto 109:9296ab0bfc11 2011
Kojto 109:9296ab0bfc11 2012
Kojto 109:9296ab0bfc11 2013 /** \brief Invalidate I-Cache
Kojto 109:9296ab0bfc11 2014
Kojto 109:9296ab0bfc11 2015 The function invalidates I-Cache
Kojto 109:9296ab0bfc11 2016 */
Kojto 109:9296ab0bfc11 2017 __STATIC_INLINE void SCB_InvalidateICache (void)
Kojto 109:9296ab0bfc11 2018 {
Kojto 109:9296ab0bfc11 2019 #if (__ICACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2020 __DSB();
Kojto 109:9296ab0bfc11 2021 __ISB();
Kojto 109:9296ab0bfc11 2022 SCB->ICIALLU = 0UL;
Kojto 109:9296ab0bfc11 2023 __DSB();
Kojto 109:9296ab0bfc11 2024 __ISB();
Kojto 109:9296ab0bfc11 2025 #endif
Kojto 109:9296ab0bfc11 2026 }
Kojto 109:9296ab0bfc11 2027
Kojto 109:9296ab0bfc11 2028
Kojto 109:9296ab0bfc11 2029 /** \brief Enable D-Cache
Kojto 109:9296ab0bfc11 2030
Kojto 109:9296ab0bfc11 2031 The function turns on D-Cache
Kojto 109:9296ab0bfc11 2032 */
Kojto 109:9296ab0bfc11 2033 __STATIC_INLINE void SCB_EnableDCache (void)
Kojto 109:9296ab0bfc11 2034 {
Kojto 109:9296ab0bfc11 2035 #if (__DCACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2036 uint32_t ccsidr, sshift, wshift, sw;
Kojto 109:9296ab0bfc11 2037 uint32_t sets, ways;
Kojto 109:9296ab0bfc11 2038
Kojto 109:9296ab0bfc11 2039 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 109:9296ab0bfc11 2040 ccsidr = SCB->CCSIDR;
Kojto 109:9296ab0bfc11 2041 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 109:9296ab0bfc11 2042 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 109:9296ab0bfc11 2043 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 109:9296ab0bfc11 2044 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 109:9296ab0bfc11 2045
Kojto 109:9296ab0bfc11 2046 __DSB();
Kojto 109:9296ab0bfc11 2047
Kojto 109:9296ab0bfc11 2048 do { // invalidate D-Cache
Kojto 109:9296ab0bfc11 2049 uint32_t tmpways = ways;
Kojto 109:9296ab0bfc11 2050 do {
Kojto 109:9296ab0bfc11 2051 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 109:9296ab0bfc11 2052 SCB->DCISW = sw;
Kojto 109:9296ab0bfc11 2053 } while(tmpways--);
Kojto 109:9296ab0bfc11 2054 } while(sets--);
Kojto 109:9296ab0bfc11 2055 __DSB();
Kojto 109:9296ab0bfc11 2056
Kojto 109:9296ab0bfc11 2057 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
Kojto 109:9296ab0bfc11 2058
Kojto 109:9296ab0bfc11 2059 __DSB();
Kojto 109:9296ab0bfc11 2060 __ISB();
Kojto 109:9296ab0bfc11 2061 #endif
Kojto 109:9296ab0bfc11 2062 }
Kojto 109:9296ab0bfc11 2063
Kojto 109:9296ab0bfc11 2064
Kojto 109:9296ab0bfc11 2065 /** \brief Disable D-Cache
Kojto 109:9296ab0bfc11 2066
Kojto 109:9296ab0bfc11 2067 The function turns off D-Cache
Kojto 109:9296ab0bfc11 2068 */
Kojto 109:9296ab0bfc11 2069 __STATIC_INLINE void SCB_DisableDCache (void)
Kojto 109:9296ab0bfc11 2070 {
Kojto 109:9296ab0bfc11 2071 #if (__DCACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2072 uint32_t ccsidr, sshift, wshift, sw;
Kojto 109:9296ab0bfc11 2073 uint32_t sets, ways;
Kojto 109:9296ab0bfc11 2074
Kojto 109:9296ab0bfc11 2075 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 109:9296ab0bfc11 2076 ccsidr = SCB->CCSIDR;
Kojto 109:9296ab0bfc11 2077 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 109:9296ab0bfc11 2078 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 109:9296ab0bfc11 2079 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 109:9296ab0bfc11 2080 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 109:9296ab0bfc11 2081
Kojto 109:9296ab0bfc11 2082 __DSB();
Kojto 109:9296ab0bfc11 2083
Kojto 109:9296ab0bfc11 2084 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
Kojto 109:9296ab0bfc11 2085
Kojto 109:9296ab0bfc11 2086 do { // clean & invalidate D-Cache
Kojto 109:9296ab0bfc11 2087 uint32_t tmpways = ways;
Kojto 109:9296ab0bfc11 2088 do {
Kojto 109:9296ab0bfc11 2089 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 109:9296ab0bfc11 2090 SCB->DCCISW = sw;
Kojto 109:9296ab0bfc11 2091 } while(tmpways--);
Kojto 109:9296ab0bfc11 2092 } while(sets--);
Kojto 109:9296ab0bfc11 2093
Kojto 109:9296ab0bfc11 2094
Kojto 109:9296ab0bfc11 2095 __DSB();
Kojto 109:9296ab0bfc11 2096 __ISB();
Kojto 109:9296ab0bfc11 2097 #endif
Kojto 109:9296ab0bfc11 2098 }
Kojto 109:9296ab0bfc11 2099
Kojto 109:9296ab0bfc11 2100
Kojto 109:9296ab0bfc11 2101 /** \brief Invalidate D-Cache
Kojto 109:9296ab0bfc11 2102
Kojto 109:9296ab0bfc11 2103 The function invalidates D-Cache
Kojto 109:9296ab0bfc11 2104 */
Kojto 109:9296ab0bfc11 2105 __STATIC_INLINE void SCB_InvalidateDCache (void)
Kojto 109:9296ab0bfc11 2106 {
Kojto 109:9296ab0bfc11 2107 #if (__DCACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2108 uint32_t ccsidr, sshift, wshift, sw;
Kojto 109:9296ab0bfc11 2109 uint32_t sets, ways;
Kojto 109:9296ab0bfc11 2110
Kojto 109:9296ab0bfc11 2111 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 109:9296ab0bfc11 2112 ccsidr = SCB->CCSIDR;
Kojto 109:9296ab0bfc11 2113 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 109:9296ab0bfc11 2114 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 109:9296ab0bfc11 2115 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 109:9296ab0bfc11 2116 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 109:9296ab0bfc11 2117
Kojto 109:9296ab0bfc11 2118 __DSB();
Kojto 109:9296ab0bfc11 2119
Kojto 109:9296ab0bfc11 2120 do { // invalidate D-Cache
Kojto 109:9296ab0bfc11 2121 uint32_t tmpways = ways;
Kojto 109:9296ab0bfc11 2122 do {
Kojto 109:9296ab0bfc11 2123 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 109:9296ab0bfc11 2124 SCB->DCISW = sw;
Kojto 109:9296ab0bfc11 2125 } while(tmpways--);
Kojto 109:9296ab0bfc11 2126 } while(sets--);
Kojto 109:9296ab0bfc11 2127
Kojto 109:9296ab0bfc11 2128 __DSB();
Kojto 109:9296ab0bfc11 2129 __ISB();
Kojto 109:9296ab0bfc11 2130 #endif
Kojto 109:9296ab0bfc11 2131 }
Kojto 109:9296ab0bfc11 2132
Kojto 109:9296ab0bfc11 2133
Kojto 109:9296ab0bfc11 2134 /** \brief Clean D-Cache
Kojto 109:9296ab0bfc11 2135
Kojto 109:9296ab0bfc11 2136 The function cleans D-Cache
Kojto 109:9296ab0bfc11 2137 */
Kojto 109:9296ab0bfc11 2138 __STATIC_INLINE void SCB_CleanDCache (void)
Kojto 109:9296ab0bfc11 2139 {
Kojto 109:9296ab0bfc11 2140 #if (__DCACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2141 uint32_t ccsidr, sshift, wshift, sw;
Kojto 109:9296ab0bfc11 2142 uint32_t sets, ways;
Kojto 109:9296ab0bfc11 2143
Kojto 109:9296ab0bfc11 2144 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 109:9296ab0bfc11 2145 ccsidr = SCB->CCSIDR;
Kojto 109:9296ab0bfc11 2146 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 109:9296ab0bfc11 2147 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 109:9296ab0bfc11 2148 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 109:9296ab0bfc11 2149 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 109:9296ab0bfc11 2150
Kojto 109:9296ab0bfc11 2151 __DSB();
Kojto 109:9296ab0bfc11 2152
Kojto 109:9296ab0bfc11 2153 do { // clean D-Cache
Kojto 109:9296ab0bfc11 2154 uint32_t tmpways = ways;
Kojto 109:9296ab0bfc11 2155 do {
Kojto 109:9296ab0bfc11 2156 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 109:9296ab0bfc11 2157 SCB->DCCSW = sw;
Kojto 109:9296ab0bfc11 2158 } while(tmpways--);
Kojto 109:9296ab0bfc11 2159 } while(sets--);
Kojto 109:9296ab0bfc11 2160
Kojto 109:9296ab0bfc11 2161 __DSB();
Kojto 109:9296ab0bfc11 2162 __ISB();
Kojto 109:9296ab0bfc11 2163 #endif
Kojto 109:9296ab0bfc11 2164 }
Kojto 109:9296ab0bfc11 2165
Kojto 109:9296ab0bfc11 2166
Kojto 109:9296ab0bfc11 2167 /** \brief Clean & Invalidate D-Cache
Kojto 109:9296ab0bfc11 2168
Kojto 109:9296ab0bfc11 2169 The function cleans and Invalidates D-Cache
Kojto 109:9296ab0bfc11 2170 */
Kojto 109:9296ab0bfc11 2171 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
Kojto 109:9296ab0bfc11 2172 {
Kojto 109:9296ab0bfc11 2173 #if (__DCACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2174 uint32_t ccsidr, sshift, wshift, sw;
Kojto 109:9296ab0bfc11 2175 uint32_t sets, ways;
Kojto 109:9296ab0bfc11 2176
Kojto 109:9296ab0bfc11 2177 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
Kojto 109:9296ab0bfc11 2178 ccsidr = SCB->CCSIDR;
Kojto 109:9296ab0bfc11 2179 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
Kojto 109:9296ab0bfc11 2180 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
Kojto 109:9296ab0bfc11 2181 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
Kojto 109:9296ab0bfc11 2182 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
Kojto 109:9296ab0bfc11 2183
Kojto 109:9296ab0bfc11 2184 __DSB();
Kojto 109:9296ab0bfc11 2185
Kojto 109:9296ab0bfc11 2186 do { // clean & invalidate D-Cache
Kojto 109:9296ab0bfc11 2187 uint32_t tmpways = ways;
Kojto 109:9296ab0bfc11 2188 do {
Kojto 109:9296ab0bfc11 2189 sw = ((tmpways << wshift) | (sets << sshift));
Kojto 109:9296ab0bfc11 2190 SCB->DCCISW = sw;
Kojto 109:9296ab0bfc11 2191 } while(tmpways--);
Kojto 109:9296ab0bfc11 2192 } while(sets--);
Kojto 109:9296ab0bfc11 2193
Kojto 109:9296ab0bfc11 2194 __DSB();
Kojto 109:9296ab0bfc11 2195 __ISB();
Kojto 109:9296ab0bfc11 2196 #endif
Kojto 109:9296ab0bfc11 2197 }
Kojto 109:9296ab0bfc11 2198
Kojto 109:9296ab0bfc11 2199
Kojto 109:9296ab0bfc11 2200 /**
Kojto 109:9296ab0bfc11 2201 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 109:9296ab0bfc11 2202 \brief D-Cache Invalidate by address
Kojto 109:9296ab0bfc11 2203 \param[in] addr address (aligned to 32-byte boundary)
Kojto 109:9296ab0bfc11 2204 \param[in] dsize size of memory block (in number of bytes)
Kojto 109:9296ab0bfc11 2205 */
Kojto 109:9296ab0bfc11 2206 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 109:9296ab0bfc11 2207 {
Kojto 109:9296ab0bfc11 2208 #if (__DCACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2209 int32_t op_size = dsize;
Kojto 109:9296ab0bfc11 2210 uint32_t op_addr = (uint32_t)addr;
Kojto 109:9296ab0bfc11 2211 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 109:9296ab0bfc11 2212
Kojto 109:9296ab0bfc11 2213 __DSB();
Kojto 109:9296ab0bfc11 2214
Kojto 109:9296ab0bfc11 2215 while (op_size > 0) {
Kojto 109:9296ab0bfc11 2216 SCB->DCIMVAC = op_addr;
Kojto 109:9296ab0bfc11 2217 op_addr += linesize;
Kojto 109:9296ab0bfc11 2218 op_size -= (int32_t)linesize;
Kojto 109:9296ab0bfc11 2219 }
Kojto 109:9296ab0bfc11 2220
Kojto 109:9296ab0bfc11 2221 __DSB();
Kojto 109:9296ab0bfc11 2222 __ISB();
Kojto 109:9296ab0bfc11 2223 #endif
Kojto 109:9296ab0bfc11 2224 }
Kojto 109:9296ab0bfc11 2225
Kojto 109:9296ab0bfc11 2226
Kojto 109:9296ab0bfc11 2227 /**
Kojto 109:9296ab0bfc11 2228 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 109:9296ab0bfc11 2229 \brief D-Cache Clean by address
Kojto 109:9296ab0bfc11 2230 \param[in] addr address (aligned to 32-byte boundary)
Kojto 109:9296ab0bfc11 2231 \param[in] dsize size of memory block (in number of bytes)
Kojto 109:9296ab0bfc11 2232 */
Kojto 109:9296ab0bfc11 2233 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 109:9296ab0bfc11 2234 {
Kojto 109:9296ab0bfc11 2235 #if (__DCACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2236 int32_t op_size = dsize;
Kojto 109:9296ab0bfc11 2237 uint32_t op_addr = (uint32_t) addr;
Kojto 109:9296ab0bfc11 2238 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 109:9296ab0bfc11 2239
Kojto 109:9296ab0bfc11 2240 __DSB();
Kojto 109:9296ab0bfc11 2241
Kojto 109:9296ab0bfc11 2242 while (op_size > 0) {
Kojto 109:9296ab0bfc11 2243 SCB->DCCMVAC = op_addr;
Kojto 109:9296ab0bfc11 2244 op_addr += linesize;
Kojto 109:9296ab0bfc11 2245 op_size -= (int32_t)linesize;
Kojto 109:9296ab0bfc11 2246 }
Kojto 109:9296ab0bfc11 2247
Kojto 109:9296ab0bfc11 2248 __DSB();
Kojto 109:9296ab0bfc11 2249 __ISB();
Kojto 109:9296ab0bfc11 2250 #endif
Kojto 109:9296ab0bfc11 2251 }
Kojto 109:9296ab0bfc11 2252
Kojto 109:9296ab0bfc11 2253
Kojto 109:9296ab0bfc11 2254 /**
Kojto 109:9296ab0bfc11 2255 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
Kojto 109:9296ab0bfc11 2256 \brief D-Cache Clean and Invalidate by address
Kojto 109:9296ab0bfc11 2257 \param[in] addr address (aligned to 32-byte boundary)
Kojto 109:9296ab0bfc11 2258 \param[in] dsize size of memory block (in number of bytes)
Kojto 109:9296ab0bfc11 2259 */
Kojto 109:9296ab0bfc11 2260 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
Kojto 109:9296ab0bfc11 2261 {
Kojto 109:9296ab0bfc11 2262 #if (__DCACHE_PRESENT == 1)
Kojto 109:9296ab0bfc11 2263 int32_t op_size = dsize;
Kojto 109:9296ab0bfc11 2264 uint32_t op_addr = (uint32_t) addr;
Kojto 109:9296ab0bfc11 2265 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
Kojto 109:9296ab0bfc11 2266
Kojto 109:9296ab0bfc11 2267 __DSB();
Kojto 109:9296ab0bfc11 2268
Kojto 109:9296ab0bfc11 2269 while (op_size > 0) {
Kojto 109:9296ab0bfc11 2270 SCB->DCCIMVAC = op_addr;
Kojto 109:9296ab0bfc11 2271 op_addr += linesize;
Kojto 109:9296ab0bfc11 2272 op_size -= (int32_t)linesize;
Kojto 109:9296ab0bfc11 2273 }
Kojto 109:9296ab0bfc11 2274
Kojto 109:9296ab0bfc11 2275 __DSB();
Kojto 109:9296ab0bfc11 2276 __ISB();
Kojto 109:9296ab0bfc11 2277 #endif
Kojto 109:9296ab0bfc11 2278 }
Kojto 109:9296ab0bfc11 2279
Kojto 109:9296ab0bfc11 2280
Kojto 109:9296ab0bfc11 2281 /*@} end of CMSIS_Core_CacheFunctions */
Kojto 109:9296ab0bfc11 2282
Kojto 109:9296ab0bfc11 2283
Kojto 109:9296ab0bfc11 2284
Kojto 109:9296ab0bfc11 2285 /* ################################## SysTick function ############################################ */
Kojto 109:9296ab0bfc11 2286 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 2287 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 109:9296ab0bfc11 2288 \brief Functions that configure the System.
Kojto 109:9296ab0bfc11 2289 @{
Kojto 109:9296ab0bfc11 2290 */
Kojto 109:9296ab0bfc11 2291
Kojto 109:9296ab0bfc11 2292 #if (__Vendor_SysTickConfig == 0)
Kojto 109:9296ab0bfc11 2293
Kojto 109:9296ab0bfc11 2294 /** \brief System Tick Configuration
Kojto 109:9296ab0bfc11 2295
Kojto 109:9296ab0bfc11 2296 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 109:9296ab0bfc11 2297 Counter is in free running mode to generate periodic interrupts.
Kojto 109:9296ab0bfc11 2298
Kojto 109:9296ab0bfc11 2299 \param [in] ticks Number of ticks between two interrupts.
Kojto 109:9296ab0bfc11 2300
Kojto 109:9296ab0bfc11 2301 \return 0 Function succeeded.
Kojto 109:9296ab0bfc11 2302 \return 1 Function failed.
Kojto 109:9296ab0bfc11 2303
Kojto 109:9296ab0bfc11 2304 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 109:9296ab0bfc11 2305 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 109:9296ab0bfc11 2306 must contain a vendor-specific implementation of this function.
Kojto 109:9296ab0bfc11 2307
Kojto 109:9296ab0bfc11 2308 */
Kojto 109:9296ab0bfc11 2309 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 109:9296ab0bfc11 2310 {
Kojto 109:9296ab0bfc11 2311 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
Kojto 109:9296ab0bfc11 2312
Kojto 109:9296ab0bfc11 2313 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 109:9296ab0bfc11 2314 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 109:9296ab0bfc11 2315 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 109:9296ab0bfc11 2316 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 109:9296ab0bfc11 2317 SysTick_CTRL_TICKINT_Msk |
Kojto 109:9296ab0bfc11 2318 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 109:9296ab0bfc11 2319 return (0UL); /* Function successful */
Kojto 109:9296ab0bfc11 2320 }
Kojto 109:9296ab0bfc11 2321
Kojto 109:9296ab0bfc11 2322 #endif
Kojto 109:9296ab0bfc11 2323
Kojto 109:9296ab0bfc11 2324 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 109:9296ab0bfc11 2325
Kojto 109:9296ab0bfc11 2326
Kojto 109:9296ab0bfc11 2327
Kojto 109:9296ab0bfc11 2328 /* ##################################### Debug In/Output function ########################################### */
Kojto 109:9296ab0bfc11 2329 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 109:9296ab0bfc11 2330 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 109:9296ab0bfc11 2331 \brief Functions that access the ITM debug interface.
Kojto 109:9296ab0bfc11 2332 @{
Kojto 109:9296ab0bfc11 2333 */
Kojto 109:9296ab0bfc11 2334
Kojto 109:9296ab0bfc11 2335 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 109:9296ab0bfc11 2336 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 109:9296ab0bfc11 2337
Kojto 109:9296ab0bfc11 2338
Kojto 109:9296ab0bfc11 2339 /** \brief ITM Send Character
Kojto 109:9296ab0bfc11 2340
Kojto 109:9296ab0bfc11 2341 The function transmits a character via the ITM channel 0, and
Kojto 109:9296ab0bfc11 2342 \li Just returns when no debugger is connected that has booked the output.
Kojto 109:9296ab0bfc11 2343 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 109:9296ab0bfc11 2344
Kojto 109:9296ab0bfc11 2345 \param [in] ch Character to transmit.
Kojto 109:9296ab0bfc11 2346
Kojto 109:9296ab0bfc11 2347 \returns Character to transmit.
Kojto 109:9296ab0bfc11 2348 */
Kojto 109:9296ab0bfc11 2349 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 109:9296ab0bfc11 2350 {
Kojto 109:9296ab0bfc11 2351 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 109:9296ab0bfc11 2352 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
Kojto 109:9296ab0bfc11 2353 {
Kojto 109:9296ab0bfc11 2354 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 109:9296ab0bfc11 2355 ITM->PORT[0].u8 = (uint8_t)ch;
Kojto 109:9296ab0bfc11 2356 }
Kojto 109:9296ab0bfc11 2357 return (ch);
Kojto 109:9296ab0bfc11 2358 }
Kojto 109:9296ab0bfc11 2359
Kojto 109:9296ab0bfc11 2360
Kojto 109:9296ab0bfc11 2361 /** \brief ITM Receive Character
Kojto 109:9296ab0bfc11 2362
Kojto 109:9296ab0bfc11 2363 The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 109:9296ab0bfc11 2364
Kojto 109:9296ab0bfc11 2365 \return Received character.
Kojto 109:9296ab0bfc11 2366 \return -1 No character pending.
Kojto 109:9296ab0bfc11 2367 */
Kojto 109:9296ab0bfc11 2368 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto 109:9296ab0bfc11 2369 int32_t ch = -1; /* no character available */
Kojto 109:9296ab0bfc11 2370
Kojto 109:9296ab0bfc11 2371 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto 109:9296ab0bfc11 2372 ch = ITM_RxBuffer;
Kojto 109:9296ab0bfc11 2373 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 109:9296ab0bfc11 2374 }
Kojto 109:9296ab0bfc11 2375
Kojto 109:9296ab0bfc11 2376 return (ch);
Kojto 109:9296ab0bfc11 2377 }
Kojto 109:9296ab0bfc11 2378
Kojto 109:9296ab0bfc11 2379
Kojto 109:9296ab0bfc11 2380 /** \brief ITM Check Character
Kojto 109:9296ab0bfc11 2381
Kojto 109:9296ab0bfc11 2382 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 109:9296ab0bfc11 2383
Kojto 109:9296ab0bfc11 2384 \return 0 No character available.
Kojto 109:9296ab0bfc11 2385 \return 1 Character available.
Kojto 109:9296ab0bfc11 2386 */
Kojto 109:9296ab0bfc11 2387 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto 109:9296ab0bfc11 2388
Kojto 109:9296ab0bfc11 2389 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto 109:9296ab0bfc11 2390 return (0); /* no character available */
Kojto 109:9296ab0bfc11 2391 } else {
Kojto 109:9296ab0bfc11 2392 return (1); /* character available */
Kojto 109:9296ab0bfc11 2393 }
Kojto 109:9296ab0bfc11 2394 }
Kojto 109:9296ab0bfc11 2395
Kojto 109:9296ab0bfc11 2396 /*@} end of CMSIS_core_DebugFunctions */
Kojto 109:9296ab0bfc11 2397
Kojto 109:9296ab0bfc11 2398
Kojto 109:9296ab0bfc11 2399
Kojto 109:9296ab0bfc11 2400
Kojto 109:9296ab0bfc11 2401 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 2402 }
Kojto 109:9296ab0bfc11 2403 #endif
Kojto 109:9296ab0bfc11 2404
Kojto 109:9296ab0bfc11 2405 #endif /* __CORE_CM7_H_DEPENDANT */
Kojto 109:9296ab0bfc11 2406
Kojto 109:9296ab0bfc11 2407 #endif /* __CMSIS_GENERIC */