The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 136 of the mbed library

Ports for Upcoming Targets


Fixes and Changes

3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432
3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181
3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626
3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628
3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629
3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632
3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642
3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664
3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655
3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657
3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658
3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685
3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692
3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621
3649: [STM32F7] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3649
3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695
3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 91:031413cf7a89 1 /**************************************************************************//**
Kojto 91:031413cf7a89 2 * @file core_cm0plus.h
Kojto 91:031413cf7a89 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
Kojto 91:031413cf7a89 6 *
Kojto 91:031413cf7a89 7 * @note
Kojto 91:031413cf7a89 8 *
Kojto 91:031413cf7a89 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
Kojto 91:031413cf7a89 11
Kojto 91:031413cf7a89 12 All rights reserved.
Kojto 91:031413cf7a89 13 Redistribution and use in source and binary forms, with or without
Kojto 91:031413cf7a89 14 modification, are permitted provided that the following conditions are met:
Kojto 91:031413cf7a89 15 - Redistributions of source code must retain the above copyright
Kojto 91:031413cf7a89 16 notice, this list of conditions and the following disclaimer.
Kojto 91:031413cf7a89 17 - Redistributions in binary form must reproduce the above copyright
Kojto 91:031413cf7a89 18 notice, this list of conditions and the following disclaimer in the
Kojto 91:031413cf7a89 19 documentation and/or other materials provided with the distribution.
Kojto 91:031413cf7a89 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 91:031413cf7a89 21 to endorse or promote products derived from this software without
Kojto 91:031413cf7a89 22 specific prior written permission.
Kojto 91:031413cf7a89 23 *
Kojto 91:031413cf7a89 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 91:031413cf7a89 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 91:031413cf7a89 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 91:031413cf7a89 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 91:031413cf7a89 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 91:031413cf7a89 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 91:031413cf7a89 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 91:031413cf7a89 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 91:031413cf7a89 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 91:031413cf7a89 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 91:031413cf7a89 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 91:031413cf7a89 35 ---------------------------------------------------------------------------*/
Kojto 91:031413cf7a89 36
Kojto 91:031413cf7a89 37
Kojto 91:031413cf7a89 38 #if defined ( __ICCARM__ )
Kojto 91:031413cf7a89 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 91:031413cf7a89 40 #endif
Kojto 91:031413cf7a89 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0PLUS_H_GENERIC
Kojto 110:165afa46840b 44
Kojto 91:031413cf7a89 45 #ifdef __cplusplus
Kojto 91:031413cf7a89 46 extern "C" {
Kojto 91:031413cf7a89 47 #endif
Kojto 91:031413cf7a89 48
Kojto 91:031413cf7a89 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 91:031413cf7a89 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 91:031413cf7a89 51
Kojto 91:031413cf7a89 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 91:031413cf7a89 53 Function definitions in header files are used to allow 'inlining'.
Kojto 91:031413cf7a89 54
Kojto 91:031413cf7a89 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 91:031413cf7a89 56 Unions are used for effective representation of core registers.
Kojto 91:031413cf7a89 57
Kojto 91:031413cf7a89 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 91:031413cf7a89 59 Function-like macros are used to allow more efficient code.
Kojto 91:031413cf7a89 60 */
Kojto 91:031413cf7a89 61
Kojto 91:031413cf7a89 62
Kojto 91:031413cf7a89 63 /*******************************************************************************
Kojto 91:031413cf7a89 64 * CMSIS definitions
Kojto 91:031413cf7a89 65 ******************************************************************************/
Kojto 91:031413cf7a89 66 /** \ingroup Cortex-M0+
Kojto 91:031413cf7a89 67 @{
Kojto 91:031413cf7a89 68 */
Kojto 91:031413cf7a89 69
Kojto 91:031413cf7a89 70 /* CMSIS CM0P definitions */
Kojto 110:165afa46840b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
Kojto 91:031413cf7a89 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 91:031413cf7a89 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 91:031413cf7a89 75
Kojto 91:031413cf7a89 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 91:031413cf7a89 77
Kojto 91:031413cf7a89 78
Kojto 91:031413cf7a89 79 #if defined ( __CC_ARM )
Kojto 91:031413cf7a89 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 91:031413cf7a89 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 91:031413cf7a89 82 #define __STATIC_INLINE static __inline
Kojto 91:031413cf7a89 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
Kojto 91:031413cf7a89 89 #elif defined ( __ICCARM__ )
Kojto 91:031413cf7a89 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 91:031413cf7a89 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 91:031413cf7a89 92 #define __STATIC_INLINE static inline
Kojto 91:031413cf7a89 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 91:031413cf7a89 96 #define __STATIC_INLINE static inline
Kojto 91:031413cf7a89 97
Kojto 91:031413cf7a89 98 #elif defined ( __TASKING__ )
Kojto 91:031413cf7a89 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 91:031413cf7a89 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 91:031413cf7a89 101 #define __STATIC_INLINE static inline
Kojto 91:031413cf7a89 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
Kojto 91:031413cf7a89 109 #endif
Kojto 91:031413cf7a89 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
Kojto 91:031413cf7a89 113 */
Kojto 91:031413cf7a89 114 #define __FPU_USED 0
Kojto 91:031413cf7a89 115
Kojto 91:031413cf7a89 116 #if defined ( __CC_ARM )
Kojto 91:031413cf7a89 117 #if defined __TARGET_FPU_VFP
Kojto 91:031413cf7a89 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 91:031413cf7a89 119 #endif
Kojto 91:031413cf7a89 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
Kojto 91:031413cf7a89 126 #elif defined ( __ICCARM__ )
Kojto 91:031413cf7a89 127 #if defined __ARMVFP__
Kojto 91:031413cf7a89 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 91:031413cf7a89 129 #endif
Kojto 91:031413cf7a89 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
Kojto 91:031413cf7a89 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 91:031413cf7a89 134 #endif
Kojto 91:031413cf7a89 135
Kojto 91:031413cf7a89 136 #elif defined ( __TASKING__ )
Kojto 91:031413cf7a89 137 #if defined __FPU_VFP__
Kojto 91:031413cf7a89 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 91:031413cf7a89 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
Kojto 91:031413cf7a89 145 #endif
Kojto 91:031413cf7a89 146
Kojto 91:031413cf7a89 147 #include <stdint.h> /* standard types definitions */
Kojto 91:031413cf7a89 148 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 91:031413cf7a89 149 #include <core_cmFunc.h> /* Core Function Access */
Kojto 91:031413cf7a89 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
Kojto 91:031413cf7a89 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 91:031413cf7a89 156
Kojto 91:031413cf7a89 157 #ifndef __CMSIS_GENERIC
Kojto 91:031413cf7a89 158
Kojto 91:031413cf7a89 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 91:031413cf7a89 160 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 91:031413cf7a89 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
Kojto 91:031413cf7a89 166 /* check device defines and use defaults */
Kojto 91:031413cf7a89 167 #if defined __CHECK_DEVICE_DEFINES
Kojto 91:031413cf7a89 168 #ifndef __CM0PLUS_REV
Kojto 91:031413cf7a89 169 #define __CM0PLUS_REV 0x0000
Kojto 91:031413cf7a89 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 91:031413cf7a89 171 #endif
Kojto 91:031413cf7a89 172
Kojto 91:031413cf7a89 173 #ifndef __MPU_PRESENT
Kojto 91:031413cf7a89 174 #define __MPU_PRESENT 0
Kojto 91:031413cf7a89 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 91:031413cf7a89 176 #endif
Kojto 91:031413cf7a89 177
Kojto 91:031413cf7a89 178 #ifndef __VTOR_PRESENT
Kojto 91:031413cf7a89 179 #define __VTOR_PRESENT 0
Kojto 91:031413cf7a89 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 91:031413cf7a89 181 #endif
Kojto 91:031413cf7a89 182
Kojto 91:031413cf7a89 183 #ifndef __NVIC_PRIO_BITS
Kojto 91:031413cf7a89 184 #define __NVIC_PRIO_BITS 2
Kojto 91:031413cf7a89 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 91:031413cf7a89 186 #endif
Kojto 91:031413cf7a89 187
Kojto 91:031413cf7a89 188 #ifndef __Vendor_SysTickConfig
Kojto 91:031413cf7a89 189 #define __Vendor_SysTickConfig 0
Kojto 91:031413cf7a89 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 91:031413cf7a89 191 #endif
Kojto 91:031413cf7a89 192 #endif
Kojto 91:031413cf7a89 193
Kojto 91:031413cf7a89 194 /* IO definitions (access restrictions to peripheral registers) */
Kojto 91:031413cf7a89 195 /**
Kojto 91:031413cf7a89 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 91:031413cf7a89 197
Kojto 91:031413cf7a89 198 <strong>IO Type Qualifiers</strong> are used
Kojto 91:031413cf7a89 199 \li to specify the access to peripheral variables.
Kojto 91:031413cf7a89 200 \li for automatic generation of peripheral register debug information.
Kojto 91:031413cf7a89 201 */
Kojto 91:031413cf7a89 202 #ifdef __cplusplus
Kojto 91:031413cf7a89 203 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 91:031413cf7a89 204 #else
Kojto 91:031413cf7a89 205 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 91:031413cf7a89 206 #endif
Kojto 91:031413cf7a89 207 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 91:031413cf7a89 208 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 91:031413cf7a89 209
<> 128:9bcdf88f62b0 210 #ifdef __cplusplus
<> 128:9bcdf88f62b0 211 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 212 #else
<> 128:9bcdf88f62b0 213 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 214 #endif
<> 128:9bcdf88f62b0 215 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 217
Kojto 91:031413cf7a89 218 /*@} end of group Cortex-M0+ */
Kojto 91:031413cf7a89 219
Kojto 91:031413cf7a89 220
Kojto 91:031413cf7a89 221
Kojto 91:031413cf7a89 222 /*******************************************************************************
Kojto 91:031413cf7a89 223 * Register Abstraction
Kojto 91:031413cf7a89 224 Core Register contain:
Kojto 91:031413cf7a89 225 - Core Register
Kojto 91:031413cf7a89 226 - Core NVIC Register
Kojto 91:031413cf7a89 227 - Core SCB Register
Kojto 91:031413cf7a89 228 - Core SysTick Register
Kojto 91:031413cf7a89 229 - Core MPU Register
Kojto 91:031413cf7a89 230 ******************************************************************************/
Kojto 91:031413cf7a89 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 91:031413cf7a89 232 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 91:031413cf7a89 233 */
Kojto 91:031413cf7a89 234
Kojto 91:031413cf7a89 235 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 236 \defgroup CMSIS_CORE Status and Control Registers
Kojto 91:031413cf7a89 237 \brief Core Register type definitions.
Kojto 91:031413cf7a89 238 @{
Kojto 91:031413cf7a89 239 */
Kojto 91:031413cf7a89 240
Kojto 91:031413cf7a89 241 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 91:031413cf7a89 242 */
Kojto 91:031413cf7a89 243 typedef union
Kojto 91:031413cf7a89 244 {
Kojto 91:031413cf7a89 245 struct
Kojto 91:031413cf7a89 246 {
Kojto 110:165afa46840b 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Kojto 91:031413cf7a89 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 91:031413cf7a89 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 91:031413cf7a89 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 91:031413cf7a89 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 91:031413cf7a89 252 } b; /*!< Structure used for bit access */
Kojto 91:031413cf7a89 253 uint32_t w; /*!< Type used for word access */
Kojto 91:031413cf7a89 254 } APSR_Type;
Kojto 91:031413cf7a89 255
Kojto 110:165afa46840b 256 /* APSR Register Definitions */
Kojto 110:165afa46840b 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 259
Kojto 110:165afa46840b 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 262
Kojto 110:165afa46840b 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 265
Kojto 110:165afa46840b 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 268
Kojto 91:031413cf7a89 269
Kojto 91:031413cf7a89 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 91:031413cf7a89 271 */
Kojto 91:031413cf7a89 272 typedef union
Kojto 91:031413cf7a89 273 {
Kojto 91:031413cf7a89 274 struct
Kojto 91:031413cf7a89 275 {
Kojto 91:031413cf7a89 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 91:031413cf7a89 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 91:031413cf7a89 278 } b; /*!< Structure used for bit access */
Kojto 91:031413cf7a89 279 uint32_t w; /*!< Type used for word access */
Kojto 91:031413cf7a89 280 } IPSR_Type;
Kojto 91:031413cf7a89 281
Kojto 110:165afa46840b 282 /* IPSR Register Definitions */
Kojto 110:165afa46840b 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 285
Kojto 91:031413cf7a89 286
Kojto 91:031413cf7a89 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 91:031413cf7a89 288 */
Kojto 91:031413cf7a89 289 typedef union
Kojto 91:031413cf7a89 290 {
Kojto 91:031413cf7a89 291 struct
Kojto 91:031413cf7a89 292 {
Kojto 91:031413cf7a89 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 91:031413cf7a89 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 91:031413cf7a89 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Kojto 91:031413cf7a89 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 91:031413cf7a89 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 91:031413cf7a89 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 91:031413cf7a89 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 91:031413cf7a89 301 } b; /*!< Structure used for bit access */
Kojto 91:031413cf7a89 302 uint32_t w; /*!< Type used for word access */
Kojto 91:031413cf7a89 303 } xPSR_Type;
Kojto 91:031413cf7a89 304
Kojto 110:165afa46840b 305 /* xPSR Register Definitions */
Kojto 110:165afa46840b 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 308
Kojto 110:165afa46840b 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 311
Kojto 110:165afa46840b 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 314
Kojto 110:165afa46840b 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 317
Kojto 110:165afa46840b 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 320
Kojto 110:165afa46840b 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 323
Kojto 91:031413cf7a89 324
Kojto 91:031413cf7a89 325 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 91:031413cf7a89 326 */
Kojto 91:031413cf7a89 327 typedef union
Kojto 91:031413cf7a89 328 {
Kojto 91:031413cf7a89 329 struct
Kojto 91:031413cf7a89 330 {
Kojto 91:031413cf7a89 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 91:031413cf7a89 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Kojto 91:031413cf7a89 334 } b; /*!< Structure used for bit access */
Kojto 91:031413cf7a89 335 uint32_t w; /*!< Type used for word access */
Kojto 91:031413cf7a89 336 } CONTROL_Type;
Kojto 91:031413cf7a89 337
Kojto 110:165afa46840b 338 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 341
Kojto 110:165afa46840b 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 344
Kojto 91:031413cf7a89 345 /*@} end of group CMSIS_CORE */
Kojto 91:031413cf7a89 346
Kojto 91:031413cf7a89 347
Kojto 91:031413cf7a89 348 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 91:031413cf7a89 350 \brief Type definitions for the NVIC Registers
Kojto 91:031413cf7a89 351 @{
Kojto 91:031413cf7a89 352 */
Kojto 91:031413cf7a89 353
Kojto 91:031413cf7a89 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 91:031413cf7a89 355 */
Kojto 91:031413cf7a89 356 typedef struct
Kojto 91:031413cf7a89 357 {
Kojto 91:031413cf7a89 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 91:031413cf7a89 359 uint32_t RESERVED0[31];
Kojto 91:031413cf7a89 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 91:031413cf7a89 361 uint32_t RSERVED1[31];
Kojto 91:031413cf7a89 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 91:031413cf7a89 363 uint32_t RESERVED2[31];
Kojto 91:031413cf7a89 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 91:031413cf7a89 365 uint32_t RESERVED3[31];
Kojto 91:031413cf7a89 366 uint32_t RESERVED4[64];
Kojto 91:031413cf7a89 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 91:031413cf7a89 368 } NVIC_Type;
Kojto 91:031413cf7a89 369
Kojto 91:031413cf7a89 370 /*@} end of group CMSIS_NVIC */
Kojto 91:031413cf7a89 371
Kojto 91:031413cf7a89 372
Kojto 91:031413cf7a89 373 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 374 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 91:031413cf7a89 375 \brief Type definitions for the System Control Block Registers
Kojto 91:031413cf7a89 376 @{
Kojto 91:031413cf7a89 377 */
Kojto 91:031413cf7a89 378
Kojto 91:031413cf7a89 379 /** \brief Structure type to access the System Control Block (SCB).
Kojto 91:031413cf7a89 380 */
Kojto 91:031413cf7a89 381 typedef struct
Kojto 91:031413cf7a89 382 {
Kojto 91:031413cf7a89 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 91:031413cf7a89 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 91:031413cf7a89 385 #if (__VTOR_PRESENT == 1)
Kojto 91:031413cf7a89 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 91:031413cf7a89 387 #else
Kojto 91:031413cf7a89 388 uint32_t RESERVED0;
Kojto 91:031413cf7a89 389 #endif
Kojto 91:031413cf7a89 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 91:031413cf7a89 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 91:031413cf7a89 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 91:031413cf7a89 393 uint32_t RESERVED1;
Kojto 91:031413cf7a89 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 91:031413cf7a89 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 91:031413cf7a89 396 } SCB_Type;
Kojto 91:031413cf7a89 397
Kojto 91:031413cf7a89 398 /* SCB CPUID Register Definitions */
Kojto 91:031413cf7a89 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 91:031413cf7a89 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 91:031413cf7a89 401
Kojto 91:031413cf7a89 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 91:031413cf7a89 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 91:031413cf7a89 404
Kojto 91:031413cf7a89 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 91:031413cf7a89 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 91:031413cf7a89 407
Kojto 91:031413cf7a89 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 91:031413cf7a89 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 91:031413cf7a89 410
Kojto 91:031413cf7a89 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 91:031413cf7a89 413
Kojto 91:031413cf7a89 414 /* SCB Interrupt Control State Register Definitions */
Kojto 91:031413cf7a89 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 91:031413cf7a89 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 91:031413cf7a89 417
Kojto 91:031413cf7a89 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 91:031413cf7a89 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 91:031413cf7a89 420
Kojto 91:031413cf7a89 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 91:031413cf7a89 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 91:031413cf7a89 423
Kojto 91:031413cf7a89 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 91:031413cf7a89 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 91:031413cf7a89 426
Kojto 91:031413cf7a89 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 91:031413cf7a89 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 91:031413cf7a89 429
Kojto 91:031413cf7a89 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 91:031413cf7a89 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 91:031413cf7a89 432
Kojto 91:031413cf7a89 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 91:031413cf7a89 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 91:031413cf7a89 435
Kojto 91:031413cf7a89 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 91:031413cf7a89 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 91:031413cf7a89 438
Kojto 91:031413cf7a89 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 91:031413cf7a89 441
Kojto 91:031413cf7a89 442 #if (__VTOR_PRESENT == 1)
Kojto 91:031413cf7a89 443 /* SCB Interrupt Control State Register Definitions */
Kojto 91:031413cf7a89 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 91:031413cf7a89 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 91:031413cf7a89 446 #endif
Kojto 91:031413cf7a89 447
Kojto 91:031413cf7a89 448 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 91:031413cf7a89 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 91:031413cf7a89 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 91:031413cf7a89 451
Kojto 91:031413cf7a89 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 91:031413cf7a89 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 91:031413cf7a89 454
Kojto 91:031413cf7a89 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 91:031413cf7a89 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 91:031413cf7a89 457
Kojto 91:031413cf7a89 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 91:031413cf7a89 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 91:031413cf7a89 460
Kojto 91:031413cf7a89 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 91:031413cf7a89 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 91:031413cf7a89 463
Kojto 91:031413cf7a89 464 /* SCB System Control Register Definitions */
Kojto 91:031413cf7a89 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 91:031413cf7a89 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 91:031413cf7a89 467
Kojto 91:031413cf7a89 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 91:031413cf7a89 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 91:031413cf7a89 470
Kojto 91:031413cf7a89 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 91:031413cf7a89 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 91:031413cf7a89 473
Kojto 91:031413cf7a89 474 /* SCB Configuration Control Register Definitions */
Kojto 91:031413cf7a89 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 91:031413cf7a89 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 91:031413cf7a89 477
Kojto 91:031413cf7a89 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 91:031413cf7a89 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 91:031413cf7a89 480
Kojto 91:031413cf7a89 481 /* SCB System Handler Control and State Register Definitions */
Kojto 91:031413cf7a89 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 91:031413cf7a89 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 91:031413cf7a89 484
Kojto 91:031413cf7a89 485 /*@} end of group CMSIS_SCB */
Kojto 91:031413cf7a89 486
Kojto 91:031413cf7a89 487
Kojto 91:031413cf7a89 488 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 91:031413cf7a89 490 \brief Type definitions for the System Timer Registers.
Kojto 91:031413cf7a89 491 @{
Kojto 91:031413cf7a89 492 */
Kojto 91:031413cf7a89 493
Kojto 91:031413cf7a89 494 /** \brief Structure type to access the System Timer (SysTick).
Kojto 91:031413cf7a89 495 */
Kojto 91:031413cf7a89 496 typedef struct
Kojto 91:031413cf7a89 497 {
Kojto 91:031413cf7a89 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 91:031413cf7a89 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 91:031413cf7a89 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 91:031413cf7a89 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 91:031413cf7a89 502 } SysTick_Type;
Kojto 91:031413cf7a89 503
Kojto 91:031413cf7a89 504 /* SysTick Control / Status Register Definitions */
Kojto 91:031413cf7a89 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 91:031413cf7a89 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 91:031413cf7a89 507
Kojto 91:031413cf7a89 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 91:031413cf7a89 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 91:031413cf7a89 510
Kojto 91:031413cf7a89 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 91:031413cf7a89 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 91:031413cf7a89 513
Kojto 91:031413cf7a89 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 91:031413cf7a89 516
Kojto 91:031413cf7a89 517 /* SysTick Reload Register Definitions */
Kojto 91:031413cf7a89 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 91:031413cf7a89 520
Kojto 91:031413cf7a89 521 /* SysTick Current Register Definitions */
Kojto 91:031413cf7a89 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 91:031413cf7a89 524
Kojto 91:031413cf7a89 525 /* SysTick Calibration Register Definitions */
Kojto 91:031413cf7a89 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 91:031413cf7a89 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 91:031413cf7a89 528
Kojto 91:031413cf7a89 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 91:031413cf7a89 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 91:031413cf7a89 531
Kojto 91:031413cf7a89 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 91:031413cf7a89 534
Kojto 91:031413cf7a89 535 /*@} end of group CMSIS_SysTick */
Kojto 91:031413cf7a89 536
Kojto 91:031413cf7a89 537 #if (__MPU_PRESENT == 1)
Kojto 91:031413cf7a89 538 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 91:031413cf7a89 540 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 91:031413cf7a89 541 @{
Kojto 91:031413cf7a89 542 */
Kojto 91:031413cf7a89 543
Kojto 91:031413cf7a89 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 91:031413cf7a89 545 */
Kojto 91:031413cf7a89 546 typedef struct
Kojto 91:031413cf7a89 547 {
Kojto 91:031413cf7a89 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 91:031413cf7a89 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 91:031413cf7a89 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 91:031413cf7a89 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 91:031413cf7a89 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 91:031413cf7a89 553 } MPU_Type;
Kojto 91:031413cf7a89 554
Kojto 91:031413cf7a89 555 /* MPU Type Register */
Kojto 91:031413cf7a89 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 91:031413cf7a89 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 91:031413cf7a89 558
Kojto 91:031413cf7a89 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 91:031413cf7a89 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 91:031413cf7a89 561
Kojto 91:031413cf7a89 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 91:031413cf7a89 564
Kojto 91:031413cf7a89 565 /* MPU Control Register */
Kojto 91:031413cf7a89 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 91:031413cf7a89 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 91:031413cf7a89 568
Kojto 91:031413cf7a89 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 91:031413cf7a89 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 91:031413cf7a89 571
Kojto 91:031413cf7a89 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 91:031413cf7a89 574
Kojto 91:031413cf7a89 575 /* MPU Region Number Register */
Kojto 91:031413cf7a89 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 91:031413cf7a89 578
Kojto 91:031413cf7a89 579 /* MPU Region Base Address Register */
Kojto 91:031413cf7a89 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 91:031413cf7a89 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 91:031413cf7a89 582
Kojto 91:031413cf7a89 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 91:031413cf7a89 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 91:031413cf7a89 585
Kojto 91:031413cf7a89 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 91:031413cf7a89 588
Kojto 91:031413cf7a89 589 /* MPU Region Attribute and Size Register */
Kojto 91:031413cf7a89 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 91:031413cf7a89 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 91:031413cf7a89 592
Kojto 91:031413cf7a89 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 91:031413cf7a89 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 91:031413cf7a89 595
Kojto 91:031413cf7a89 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 91:031413cf7a89 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 91:031413cf7a89 598
Kojto 91:031413cf7a89 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 91:031413cf7a89 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 91:031413cf7a89 601
Kojto 91:031413cf7a89 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 91:031413cf7a89 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 91:031413cf7a89 604
Kojto 91:031413cf7a89 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 91:031413cf7a89 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 91:031413cf7a89 607
Kojto 91:031413cf7a89 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 91:031413cf7a89 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 91:031413cf7a89 610
Kojto 91:031413cf7a89 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 91:031413cf7a89 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 91:031413cf7a89 613
Kojto 91:031413cf7a89 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 91:031413cf7a89 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 91:031413cf7a89 616
Kojto 91:031413cf7a89 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 91:031413cf7a89 619
Kojto 91:031413cf7a89 620 /*@} end of group CMSIS_MPU */
Kojto 91:031413cf7a89 621 #endif
Kojto 91:031413cf7a89 622
Kojto 91:031413cf7a89 623
Kojto 91:031413cf7a89 624 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 91:031413cf7a89 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 91:031413cf7a89 627 are only accessible over DAP and not via processor. Therefore
Kojto 91:031413cf7a89 628 they are not covered by the Cortex-M0 header file.
Kojto 91:031413cf7a89 629 @{
Kojto 91:031413cf7a89 630 */
Kojto 91:031413cf7a89 631 /*@} end of group CMSIS_CoreDebug */
Kojto 91:031413cf7a89 632
Kojto 91:031413cf7a89 633
Kojto 91:031413cf7a89 634 /** \ingroup CMSIS_core_register
Kojto 91:031413cf7a89 635 \defgroup CMSIS_core_base Core Definitions
Kojto 91:031413cf7a89 636 \brief Definitions for base addresses, unions, and structures.
Kojto 91:031413cf7a89 637 @{
Kojto 91:031413cf7a89 638 */
Kojto 91:031413cf7a89 639
Kojto 91:031413cf7a89 640 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 91:031413cf7a89 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 91:031413cf7a89 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 91:031413cf7a89 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 91:031413cf7a89 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 91:031413cf7a89 645
Kojto 91:031413cf7a89 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 91:031413cf7a89 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 91:031413cf7a89 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 91:031413cf7a89 649
Kojto 91:031413cf7a89 650 #if (__MPU_PRESENT == 1)
Kojto 91:031413cf7a89 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 91:031413cf7a89 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 91:031413cf7a89 653 #endif
Kojto 91:031413cf7a89 654
Kojto 91:031413cf7a89 655 /*@} */
Kojto 91:031413cf7a89 656
Kojto 91:031413cf7a89 657
Kojto 91:031413cf7a89 658
Kojto 91:031413cf7a89 659 /*******************************************************************************
Kojto 91:031413cf7a89 660 * Hardware Abstraction Layer
Kojto 91:031413cf7a89 661 Core Function Interface contains:
Kojto 91:031413cf7a89 662 - Core NVIC Functions
Kojto 91:031413cf7a89 663 - Core SysTick Functions
Kojto 91:031413cf7a89 664 - Core Register Access Functions
Kojto 91:031413cf7a89 665 ******************************************************************************/
Kojto 91:031413cf7a89 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 91:031413cf7a89 667 */
Kojto 91:031413cf7a89 668
Kojto 91:031413cf7a89 669
Kojto 91:031413cf7a89 670
Kojto 91:031413cf7a89 671 /* ########################## NVIC functions #################################### */
Kojto 91:031413cf7a89 672 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 91:031413cf7a89 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 91:031413cf7a89 674 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 91:031413cf7a89 675 @{
Kojto 91:031413cf7a89 676 */
Kojto 91:031413cf7a89 677
Kojto 91:031413cf7a89 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 91:031413cf7a89 679 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 91:031413cf7a89 683
Kojto 91:031413cf7a89 684
Kojto 91:031413cf7a89 685 /** \brief Enable External Interrupt
Kojto 91:031413cf7a89 686
Kojto 91:031413cf7a89 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 91:031413cf7a89 688
Kojto 91:031413cf7a89 689 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 91:031413cf7a89 690 */
Kojto 91:031413cf7a89 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 692 {
Kojto 110:165afa46840b 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 91:031413cf7a89 694 }
Kojto 91:031413cf7a89 695
Kojto 91:031413cf7a89 696
Kojto 91:031413cf7a89 697 /** \brief Disable External Interrupt
Kojto 91:031413cf7a89 698
Kojto 91:031413cf7a89 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 91:031413cf7a89 700
Kojto 91:031413cf7a89 701 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 91:031413cf7a89 702 */
Kojto 91:031413cf7a89 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 704 {
Kojto 110:165afa46840b 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 706 __DSB();
<> 131:faff56e089b2 707 __ISB();
Kojto 91:031413cf7a89 708 }
Kojto 91:031413cf7a89 709
Kojto 91:031413cf7a89 710
Kojto 91:031413cf7a89 711 /** \brief Get Pending Interrupt
Kojto 91:031413cf7a89 712
Kojto 91:031413cf7a89 713 The function reads the pending register in the NVIC and returns the pending bit
Kojto 91:031413cf7a89 714 for the specified interrupt.
Kojto 91:031413cf7a89 715
Kojto 91:031413cf7a89 716 \param [in] IRQn Interrupt number.
Kojto 91:031413cf7a89 717
Kojto 91:031413cf7a89 718 \return 0 Interrupt status is not pending.
Kojto 91:031413cf7a89 719 \return 1 Interrupt status is pending.
Kojto 91:031413cf7a89 720 */
Kojto 91:031413cf7a89 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 722 {
Kojto 110:165afa46840b 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Kojto 91:031413cf7a89 724 }
Kojto 91:031413cf7a89 725
Kojto 91:031413cf7a89 726
Kojto 91:031413cf7a89 727 /** \brief Set Pending Interrupt
Kojto 91:031413cf7a89 728
Kojto 91:031413cf7a89 729 The function sets the pending bit of an external interrupt.
Kojto 91:031413cf7a89 730
Kojto 91:031413cf7a89 731 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 91:031413cf7a89 732 */
Kojto 91:031413cf7a89 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 734 {
Kojto 110:165afa46840b 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 91:031413cf7a89 736 }
Kojto 91:031413cf7a89 737
Kojto 91:031413cf7a89 738
Kojto 91:031413cf7a89 739 /** \brief Clear Pending Interrupt
Kojto 91:031413cf7a89 740
Kojto 91:031413cf7a89 741 The function clears the pending bit of an external interrupt.
Kojto 91:031413cf7a89 742
Kojto 91:031413cf7a89 743 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 91:031413cf7a89 744 */
Kojto 91:031413cf7a89 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 91:031413cf7a89 746 {
Kojto 110:165afa46840b 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 91:031413cf7a89 748 }
Kojto 91:031413cf7a89 749
Kojto 91:031413cf7a89 750
Kojto 91:031413cf7a89 751 /** \brief Set Interrupt Priority
Kojto 91:031413cf7a89 752
Kojto 91:031413cf7a89 753 The function sets the priority of an interrupt.
Kojto 91:031413cf7a89 754
Kojto 91:031413cf7a89 755 \note The priority cannot be set for every core interrupt.
Kojto 91:031413cf7a89 756
Kojto 91:031413cf7a89 757 \param [in] IRQn Interrupt number.
Kojto 91:031413cf7a89 758 \param [in] priority Priority to set.
Kojto 91:031413cf7a89 759 */
Kojto 91:031413cf7a89 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 91:031413cf7a89 761 {
Kojto 110:165afa46840b 762 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 765 }
Kojto 91:031413cf7a89 766 else {
Kojto 110:165afa46840b 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 769 }
Kojto 91:031413cf7a89 770 }
Kojto 91:031413cf7a89 771
Kojto 91:031413cf7a89 772
Kojto 91:031413cf7a89 773 /** \brief Get Interrupt Priority
Kojto 91:031413cf7a89 774
Kojto 91:031413cf7a89 775 The function reads the priority of an interrupt. The interrupt
Kojto 91:031413cf7a89 776 number can be positive to specify an external (device specific)
Kojto 91:031413cf7a89 777 interrupt, or negative to specify an internal (core) interrupt.
Kojto 91:031413cf7a89 778
Kojto 91:031413cf7a89 779
Kojto 91:031413cf7a89 780 \param [in] IRQn Interrupt number.
Kojto 91:031413cf7a89 781 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 91:031413cf7a89 782 priority bits of the microcontroller.
Kojto 91:031413cf7a89 783 */
Kojto 91:031413cf7a89 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 91:031413cf7a89 785 {
Kojto 91:031413cf7a89 786
Kojto 110:165afa46840b 787 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 789 }
Kojto 91:031413cf7a89 790 else {
Kojto 110:165afa46840b 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 792 }
Kojto 91:031413cf7a89 793 }
Kojto 91:031413cf7a89 794
Kojto 91:031413cf7a89 795
Kojto 91:031413cf7a89 796 /** \brief System Reset
Kojto 91:031413cf7a89 797
Kojto 91:031413cf7a89 798 The function initiates a system reset request to reset the MCU.
Kojto 91:031413cf7a89 799 */
Kojto 91:031413cf7a89 800 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 91:031413cf7a89 801 {
Kojto 91:031413cf7a89 802 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 91:031413cf7a89 803 buffered write are completed before reset */
Kojto 110:165afa46840b 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 91:031413cf7a89 805 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 91:031413cf7a89 806 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 807 while(1) { __NOP(); } /* wait until reset */
Kojto 91:031413cf7a89 808 }
Kojto 91:031413cf7a89 809
Kojto 91:031413cf7a89 810 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 91:031413cf7a89 811
Kojto 91:031413cf7a89 812
Kojto 91:031413cf7a89 813
Kojto 91:031413cf7a89 814 /* ################################## SysTick function ############################################ */
Kojto 91:031413cf7a89 815 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 91:031413cf7a89 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 91:031413cf7a89 817 \brief Functions that configure the System.
Kojto 91:031413cf7a89 818 @{
Kojto 91:031413cf7a89 819 */
Kojto 91:031413cf7a89 820
Kojto 91:031413cf7a89 821 #if (__Vendor_SysTickConfig == 0)
Kojto 91:031413cf7a89 822
Kojto 91:031413cf7a89 823 /** \brief System Tick Configuration
Kojto 91:031413cf7a89 824
Kojto 91:031413cf7a89 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 91:031413cf7a89 826 Counter is in free running mode to generate periodic interrupts.
Kojto 91:031413cf7a89 827
Kojto 91:031413cf7a89 828 \param [in] ticks Number of ticks between two interrupts.
Kojto 91:031413cf7a89 829
Kojto 91:031413cf7a89 830 \return 0 Function succeeded.
Kojto 91:031413cf7a89 831 \return 1 Function failed.
Kojto 91:031413cf7a89 832
Kojto 91:031413cf7a89 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 91:031413cf7a89 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 91:031413cf7a89 835 must contain a vendor-specific implementation of this function.
Kojto 91:031413cf7a89 836
Kojto 91:031413cf7a89 837 */
Kojto 91:031413cf7a89 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 91:031413cf7a89 839 {
Kojto 110:165afa46840b 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
Kojto 91:031413cf7a89 841
Kojto 110:165afa46840b 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 91:031413cf7a89 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 91:031413cf7a89 846 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 848 return (0UL); /* Function successful */
Kojto 91:031413cf7a89 849 }
Kojto 91:031413cf7a89 850
Kojto 91:031413cf7a89 851 #endif
Kojto 91:031413cf7a89 852
Kojto 91:031413cf7a89 853 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 91:031413cf7a89 854
Kojto 91:031413cf7a89 855
Kojto 91:031413cf7a89 856
Kojto 91:031413cf7a89 857
Kojto 110:165afa46840b 858 #ifdef __cplusplus
Kojto 110:165afa46840b 859 }
Kojto 110:165afa46840b 860 #endif
Kojto 110:165afa46840b 861
Kojto 91:031413cf7a89 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 91:031413cf7a89 863
Kojto 91:031413cf7a89 864 #endif /* __CMSIS_GENERIC */