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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MTM_MTCONNECT04S/core_cm4.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**************************************************************************//**
AnnaBridge 126:abea610beb85 2 * @file core_cm4.h
AnnaBridge 126:abea610beb85 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
AnnaBridge 126:abea610beb85 4 * @version V4.10
AnnaBridge 126:abea610beb85 5 * @date 18. March 2015
AnnaBridge 126:abea610beb85 6 *
AnnaBridge 126:abea610beb85 7 * @note
AnnaBridge 126:abea610beb85 8 *
AnnaBridge 126:abea610beb85 9 ******************************************************************************/
AnnaBridge 126:abea610beb85 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
AnnaBridge 126:abea610beb85 11
AnnaBridge 126:abea610beb85 12 All rights reserved.
AnnaBridge 126:abea610beb85 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 126:abea610beb85 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 - Redistributions of source code must retain the above copyright
AnnaBridge 126:abea610beb85 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 126:abea610beb85 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 126:abea610beb85 19 documentation and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 126:abea610beb85 21 to endorse or promote products derived from this software without
AnnaBridge 126:abea610beb85 22 specific prior written permission.
AnnaBridge 126:abea610beb85 23 *
AnnaBridge 126:abea610beb85 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 126:abea610beb85 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 126:abea610beb85 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 126:abea610beb85 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 126:abea610beb85 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 126:abea610beb85 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 126:abea610beb85 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 126:abea610beb85 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 126:abea610beb85 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 35 ---------------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 36
AnnaBridge 126:abea610beb85 37
AnnaBridge 126:abea610beb85 38 #if defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 39 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 126:abea610beb85 40 #endif
AnnaBridge 126:abea610beb85 41
AnnaBridge 126:abea610beb85 42 #ifndef __CORE_CM4_H_GENERIC
AnnaBridge 126:abea610beb85 43 #define __CORE_CM4_H_GENERIC
AnnaBridge 126:abea610beb85 44
AnnaBridge 126:abea610beb85 45 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 46 extern "C" {
AnnaBridge 126:abea610beb85 47 #endif
AnnaBridge 126:abea610beb85 48
AnnaBridge 126:abea610beb85 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 126:abea610beb85 50 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 126:abea610beb85 51
AnnaBridge 126:abea610beb85 52 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 126:abea610beb85 53 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 126:abea610beb85 54
AnnaBridge 126:abea610beb85 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 126:abea610beb85 56 Unions are used for effective representation of core registers.
AnnaBridge 126:abea610beb85 57
AnnaBridge 126:abea610beb85 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 126:abea610beb85 59 Function-like macros are used to allow more efficient code.
AnnaBridge 126:abea610beb85 60 */
AnnaBridge 126:abea610beb85 61
AnnaBridge 126:abea610beb85 62
AnnaBridge 126:abea610beb85 63 /*******************************************************************************
AnnaBridge 126:abea610beb85 64 * CMSIS definitions
AnnaBridge 126:abea610beb85 65 ******************************************************************************/
AnnaBridge 126:abea610beb85 66 /** \ingroup Cortex_M4
AnnaBridge 126:abea610beb85 67 @{
AnnaBridge 126:abea610beb85 68 */
AnnaBridge 126:abea610beb85 69
AnnaBridge 126:abea610beb85 70 /* CMSIS CM4 definitions */
AnnaBridge 126:abea610beb85 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 126:abea610beb85 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 126:abea610beb85 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
AnnaBridge 126:abea610beb85 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 126:abea610beb85 75
AnnaBridge 126:abea610beb85 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
AnnaBridge 126:abea610beb85 77
AnnaBridge 126:abea610beb85 78
AnnaBridge 126:abea610beb85 79 #if defined ( __CC_ARM )
AnnaBridge 126:abea610beb85 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
AnnaBridge 126:abea610beb85 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
AnnaBridge 126:abea610beb85 82 #define __STATIC_INLINE static __inline
AnnaBridge 126:abea610beb85 83
AnnaBridge 126:abea610beb85 84 #elif defined ( __GNUC__ )
AnnaBridge 126:abea610beb85 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
AnnaBridge 126:abea610beb85 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
AnnaBridge 126:abea610beb85 87 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 88
AnnaBridge 126:abea610beb85 89 #elif defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
AnnaBridge 126:abea610beb85 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
AnnaBridge 126:abea610beb85 92 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 93
AnnaBridge 126:abea610beb85 94 #elif defined ( __TMS470__ )
AnnaBridge 126:abea610beb85 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
AnnaBridge 126:abea610beb85 96 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 97
AnnaBridge 126:abea610beb85 98 #elif defined ( __TASKING__ )
AnnaBridge 126:abea610beb85 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
AnnaBridge 126:abea610beb85 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
AnnaBridge 126:abea610beb85 101 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 102
AnnaBridge 126:abea610beb85 103 #elif defined ( __CSMC__ )
AnnaBridge 126:abea610beb85 104 #define __packed
AnnaBridge 126:abea610beb85 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
AnnaBridge 126:abea610beb85 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
AnnaBridge 126:abea610beb85 107 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 108
AnnaBridge 126:abea610beb85 109 #endif
AnnaBridge 126:abea610beb85 110
AnnaBridge 126:abea610beb85 111 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 126:abea610beb85 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge 126:abea610beb85 113 */
AnnaBridge 126:abea610beb85 114 #if defined ( __CC_ARM )
AnnaBridge 126:abea610beb85 115 #if defined __TARGET_FPU_VFP
AnnaBridge 126:abea610beb85 116 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 117 #define __FPU_USED 1
AnnaBridge 126:abea610beb85 118 #else
AnnaBridge 126:abea610beb85 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 120 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 121 #endif
AnnaBridge 126:abea610beb85 122 #else
AnnaBridge 126:abea610beb85 123 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 124 #endif
AnnaBridge 126:abea610beb85 125
AnnaBridge 126:abea610beb85 126 #elif defined ( __GNUC__ )
AnnaBridge 126:abea610beb85 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 126:abea610beb85 128 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 129 #define __FPU_USED 1
AnnaBridge 126:abea610beb85 130 #else
AnnaBridge 126:abea610beb85 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 132 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 133 #endif
AnnaBridge 126:abea610beb85 134 #else
AnnaBridge 126:abea610beb85 135 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 136 #endif
AnnaBridge 126:abea610beb85 137
AnnaBridge 126:abea610beb85 138 #elif defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 139 #if defined __ARMVFP__
AnnaBridge 126:abea610beb85 140 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 141 #define __FPU_USED 1
AnnaBridge 126:abea610beb85 142 #else
AnnaBridge 126:abea610beb85 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 144 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 145 #endif
AnnaBridge 126:abea610beb85 146 #else
AnnaBridge 126:abea610beb85 147 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 148 #endif
AnnaBridge 126:abea610beb85 149
AnnaBridge 126:abea610beb85 150 #elif defined ( __TMS470__ )
AnnaBridge 126:abea610beb85 151 #if defined __TI_VFP_SUPPORT__
AnnaBridge 126:abea610beb85 152 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 153 #define __FPU_USED 1
AnnaBridge 126:abea610beb85 154 #else
AnnaBridge 126:abea610beb85 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 156 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 157 #endif
AnnaBridge 126:abea610beb85 158 #else
AnnaBridge 126:abea610beb85 159 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 160 #endif
AnnaBridge 126:abea610beb85 161
AnnaBridge 126:abea610beb85 162 #elif defined ( __TASKING__ )
AnnaBridge 126:abea610beb85 163 #if defined __FPU_VFP__
AnnaBridge 126:abea610beb85 164 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 165 #define __FPU_USED 1
AnnaBridge 126:abea610beb85 166 #else
AnnaBridge 126:abea610beb85 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 168 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 169 #endif
AnnaBridge 126:abea610beb85 170 #else
AnnaBridge 126:abea610beb85 171 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 172 #endif
AnnaBridge 126:abea610beb85 173
AnnaBridge 126:abea610beb85 174 #elif defined ( __CSMC__ ) /* Cosmic */
AnnaBridge 126:abea610beb85 175 #if ( __CSMC__ & 0x400) // FPU present for parser
AnnaBridge 126:abea610beb85 176 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 177 #define __FPU_USED 1
AnnaBridge 126:abea610beb85 178 #else
AnnaBridge 126:abea610beb85 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 180 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 181 #endif
AnnaBridge 126:abea610beb85 182 #else
AnnaBridge 126:abea610beb85 183 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 184 #endif
AnnaBridge 126:abea610beb85 185 #endif
AnnaBridge 126:abea610beb85 186
AnnaBridge 126:abea610beb85 187 #include <stdint.h> /* standard types definitions */
AnnaBridge 126:abea610beb85 188 #include <core_cmInstr.h> /* Core Instruction Access */
AnnaBridge 126:abea610beb85 189 #include <core_cmFunc.h> /* Core Function Access */
AnnaBridge 126:abea610beb85 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
AnnaBridge 126:abea610beb85 191
AnnaBridge 126:abea610beb85 192 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 193 }
AnnaBridge 126:abea610beb85 194 #endif
AnnaBridge 126:abea610beb85 195
AnnaBridge 126:abea610beb85 196 #endif /* __CORE_CM4_H_GENERIC */
AnnaBridge 126:abea610beb85 197
AnnaBridge 126:abea610beb85 198 #ifndef __CMSIS_GENERIC
AnnaBridge 126:abea610beb85 199
AnnaBridge 126:abea610beb85 200 #ifndef __CORE_CM4_H_DEPENDANT
AnnaBridge 126:abea610beb85 201 #define __CORE_CM4_H_DEPENDANT
AnnaBridge 126:abea610beb85 202
AnnaBridge 126:abea610beb85 203 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 204 extern "C" {
AnnaBridge 126:abea610beb85 205 #endif
AnnaBridge 126:abea610beb85 206
AnnaBridge 126:abea610beb85 207 /* check device defines and use defaults */
AnnaBridge 126:abea610beb85 208 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 126:abea610beb85 209 #ifndef __CM4_REV
AnnaBridge 126:abea610beb85 210 #define __CM4_REV 0x0000
AnnaBridge 126:abea610beb85 211 #warning "__CM4_REV not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 212 #endif
AnnaBridge 126:abea610beb85 213
AnnaBridge 126:abea610beb85 214 #ifndef __FPU_PRESENT
AnnaBridge 126:abea610beb85 215 #define __FPU_PRESENT 0
AnnaBridge 126:abea610beb85 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 217 #endif
AnnaBridge 126:abea610beb85 218
AnnaBridge 126:abea610beb85 219 #ifndef __MPU_PRESENT
AnnaBridge 126:abea610beb85 220 #define __MPU_PRESENT 0
AnnaBridge 126:abea610beb85 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 222 #endif
AnnaBridge 126:abea610beb85 223
AnnaBridge 126:abea610beb85 224 #ifndef __NVIC_PRIO_BITS
AnnaBridge 126:abea610beb85 225 #define __NVIC_PRIO_BITS 4
AnnaBridge 126:abea610beb85 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 227 #endif
AnnaBridge 126:abea610beb85 228
AnnaBridge 126:abea610beb85 229 #ifndef __Vendor_SysTickConfig
AnnaBridge 126:abea610beb85 230 #define __Vendor_SysTickConfig 0
AnnaBridge 126:abea610beb85 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 232 #endif
AnnaBridge 126:abea610beb85 233 #endif
AnnaBridge 126:abea610beb85 234
AnnaBridge 126:abea610beb85 235 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 126:abea610beb85 236 /**
AnnaBridge 126:abea610beb85 237 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 126:abea610beb85 238
AnnaBridge 126:abea610beb85 239 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 126:abea610beb85 240 \li to specify the access to peripheral variables.
AnnaBridge 126:abea610beb85 241 \li for automatic generation of peripheral register debug information.
AnnaBridge 126:abea610beb85 242 */
AnnaBridge 126:abea610beb85 243 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 244 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 126:abea610beb85 245 #else
AnnaBridge 126:abea610beb85 246 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 126:abea610beb85 247 #endif
AnnaBridge 126:abea610beb85 248 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 126:abea610beb85 249 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 126:abea610beb85 250
<> 128:9bcdf88f62b0 251 #ifdef __cplusplus
<> 128:9bcdf88f62b0 252 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 253 #else
<> 128:9bcdf88f62b0 254 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 255 #endif
<> 128:9bcdf88f62b0 256 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 257 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 258
AnnaBridge 126:abea610beb85 259 /*@} end of group Cortex_M4 */
AnnaBridge 126:abea610beb85 260
AnnaBridge 126:abea610beb85 261
AnnaBridge 126:abea610beb85 262
AnnaBridge 126:abea610beb85 263 /*******************************************************************************
AnnaBridge 126:abea610beb85 264 * Register Abstraction
AnnaBridge 126:abea610beb85 265 Core Register contain:
AnnaBridge 126:abea610beb85 266 - Core Register
AnnaBridge 126:abea610beb85 267 - Core NVIC Register
AnnaBridge 126:abea610beb85 268 - Core SCB Register
AnnaBridge 126:abea610beb85 269 - Core SysTick Register
AnnaBridge 126:abea610beb85 270 - Core Debug Register
AnnaBridge 126:abea610beb85 271 - Core MPU Register
AnnaBridge 126:abea610beb85 272 - Core FPU Register
AnnaBridge 126:abea610beb85 273 ******************************************************************************/
AnnaBridge 126:abea610beb85 274 /** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 126:abea610beb85 275 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 126:abea610beb85 276 */
AnnaBridge 126:abea610beb85 277
AnnaBridge 126:abea610beb85 278 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 279 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 126:abea610beb85 280 \brief Core Register type definitions.
AnnaBridge 126:abea610beb85 281 @{
AnnaBridge 126:abea610beb85 282 */
AnnaBridge 126:abea610beb85 283
AnnaBridge 126:abea610beb85 284 /** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 126:abea610beb85 285 */
AnnaBridge 126:abea610beb85 286 typedef union
AnnaBridge 126:abea610beb85 287 {
AnnaBridge 126:abea610beb85 288 struct
AnnaBridge 126:abea610beb85 289 {
AnnaBridge 126:abea610beb85 290 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
AnnaBridge 126:abea610beb85 291 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 126:abea610beb85 292 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
AnnaBridge 126:abea610beb85 293 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 126:abea610beb85 294 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 126:abea610beb85 295 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 126:abea610beb85 296 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 126:abea610beb85 297 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 126:abea610beb85 298 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 299 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 300 } APSR_Type;
AnnaBridge 126:abea610beb85 301
AnnaBridge 126:abea610beb85 302 /* APSR Register Definitions */
AnnaBridge 126:abea610beb85 303 #define APSR_N_Pos 31 /*!< APSR: N Position */
AnnaBridge 126:abea610beb85 304 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 126:abea610beb85 305
AnnaBridge 126:abea610beb85 306 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
AnnaBridge 126:abea610beb85 307 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 126:abea610beb85 308
AnnaBridge 126:abea610beb85 309 #define APSR_C_Pos 29 /*!< APSR: C Position */
AnnaBridge 126:abea610beb85 310 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 126:abea610beb85 311
AnnaBridge 126:abea610beb85 312 #define APSR_V_Pos 28 /*!< APSR: V Position */
AnnaBridge 126:abea610beb85 313 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 126:abea610beb85 314
AnnaBridge 126:abea610beb85 315 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
AnnaBridge 126:abea610beb85 316 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
AnnaBridge 126:abea610beb85 317
AnnaBridge 126:abea610beb85 318 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
AnnaBridge 126:abea610beb85 319 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
AnnaBridge 126:abea610beb85 320
AnnaBridge 126:abea610beb85 321
AnnaBridge 126:abea610beb85 322 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 126:abea610beb85 323 */
AnnaBridge 126:abea610beb85 324 typedef union
AnnaBridge 126:abea610beb85 325 {
AnnaBridge 126:abea610beb85 326 struct
AnnaBridge 126:abea610beb85 327 {
AnnaBridge 126:abea610beb85 328 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 126:abea610beb85 329 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 126:abea610beb85 330 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 331 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 332 } IPSR_Type;
AnnaBridge 126:abea610beb85 333
AnnaBridge 126:abea610beb85 334 /* IPSR Register Definitions */
AnnaBridge 126:abea610beb85 335 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
AnnaBridge 126:abea610beb85 336 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 126:abea610beb85 337
AnnaBridge 126:abea610beb85 338
AnnaBridge 126:abea610beb85 339 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 126:abea610beb85 340 */
AnnaBridge 126:abea610beb85 341 typedef union
AnnaBridge 126:abea610beb85 342 {
AnnaBridge 126:abea610beb85 343 struct
AnnaBridge 126:abea610beb85 344 {
AnnaBridge 126:abea610beb85 345 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 126:abea610beb85 346 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
AnnaBridge 126:abea610beb85 347 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 126:abea610beb85 348 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
AnnaBridge 126:abea610beb85 349 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 126:abea610beb85 350 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
AnnaBridge 126:abea610beb85 351 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 126:abea610beb85 352 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 126:abea610beb85 353 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 126:abea610beb85 354 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 126:abea610beb85 355 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 126:abea610beb85 356 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 357 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 358 } xPSR_Type;
AnnaBridge 126:abea610beb85 359
AnnaBridge 126:abea610beb85 360 /* xPSR Register Definitions */
AnnaBridge 126:abea610beb85 361 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
AnnaBridge 126:abea610beb85 362 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 126:abea610beb85 363
AnnaBridge 126:abea610beb85 364 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
AnnaBridge 126:abea610beb85 365 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 126:abea610beb85 366
AnnaBridge 126:abea610beb85 367 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
AnnaBridge 126:abea610beb85 368 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 126:abea610beb85 369
AnnaBridge 126:abea610beb85 370 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
AnnaBridge 126:abea610beb85 371 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 126:abea610beb85 372
AnnaBridge 126:abea610beb85 373 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
AnnaBridge 126:abea610beb85 374 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
AnnaBridge 126:abea610beb85 375
AnnaBridge 126:abea610beb85 376 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
AnnaBridge 126:abea610beb85 377 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
AnnaBridge 126:abea610beb85 378
AnnaBridge 126:abea610beb85 379 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
AnnaBridge 126:abea610beb85 380 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 126:abea610beb85 381
AnnaBridge 126:abea610beb85 382 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
AnnaBridge 126:abea610beb85 383 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
AnnaBridge 126:abea610beb85 384
AnnaBridge 126:abea610beb85 385 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
AnnaBridge 126:abea610beb85 386 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 126:abea610beb85 387
AnnaBridge 126:abea610beb85 388
AnnaBridge 126:abea610beb85 389 /** \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 126:abea610beb85 390 */
AnnaBridge 126:abea610beb85 391 typedef union
AnnaBridge 126:abea610beb85 392 {
AnnaBridge 126:abea610beb85 393 struct
AnnaBridge 126:abea610beb85 394 {
AnnaBridge 126:abea610beb85 395 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 126:abea610beb85 396 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 126:abea610beb85 397 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
AnnaBridge 126:abea610beb85 398 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
AnnaBridge 126:abea610beb85 399 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 400 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 401 } CONTROL_Type;
AnnaBridge 126:abea610beb85 402
AnnaBridge 126:abea610beb85 403 /* CONTROL Register Definitions */
AnnaBridge 126:abea610beb85 404 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
AnnaBridge 126:abea610beb85 405 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
AnnaBridge 126:abea610beb85 406
AnnaBridge 126:abea610beb85 407 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
AnnaBridge 126:abea610beb85 408 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 126:abea610beb85 409
AnnaBridge 126:abea610beb85 410 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
AnnaBridge 126:abea610beb85 411 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 126:abea610beb85 412
AnnaBridge 126:abea610beb85 413 /*@} end of group CMSIS_CORE */
AnnaBridge 126:abea610beb85 414
AnnaBridge 126:abea610beb85 415
AnnaBridge 126:abea610beb85 416 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 417 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 126:abea610beb85 418 \brief Type definitions for the NVIC Registers
AnnaBridge 126:abea610beb85 419 @{
AnnaBridge 126:abea610beb85 420 */
AnnaBridge 126:abea610beb85 421
AnnaBridge 126:abea610beb85 422 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 126:abea610beb85 423 */
AnnaBridge 126:abea610beb85 424 typedef struct
AnnaBridge 126:abea610beb85 425 {
AnnaBridge 126:abea610beb85 426 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 126:abea610beb85 427 uint32_t RESERVED0[24];
AnnaBridge 126:abea610beb85 428 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 126:abea610beb85 429 uint32_t RSERVED1[24];
AnnaBridge 126:abea610beb85 430 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 126:abea610beb85 431 uint32_t RESERVED2[24];
AnnaBridge 126:abea610beb85 432 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 126:abea610beb85 433 uint32_t RESERVED3[24];
AnnaBridge 126:abea610beb85 434 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 126:abea610beb85 435 uint32_t RESERVED4[56];
AnnaBridge 126:abea610beb85 436 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 126:abea610beb85 437 uint32_t RESERVED5[644];
AnnaBridge 126:abea610beb85 438 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
AnnaBridge 126:abea610beb85 439 } NVIC_Type;
AnnaBridge 126:abea610beb85 440
AnnaBridge 126:abea610beb85 441 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 126:abea610beb85 442 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
AnnaBridge 126:abea610beb85 443 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
AnnaBridge 126:abea610beb85 444
AnnaBridge 126:abea610beb85 445 /*@} end of group CMSIS_NVIC */
AnnaBridge 126:abea610beb85 446
AnnaBridge 126:abea610beb85 447
AnnaBridge 126:abea610beb85 448 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 449 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 126:abea610beb85 450 \brief Type definitions for the System Control Block Registers
AnnaBridge 126:abea610beb85 451 @{
AnnaBridge 126:abea610beb85 452 */
AnnaBridge 126:abea610beb85 453
AnnaBridge 126:abea610beb85 454 /** \brief Structure type to access the System Control Block (SCB).
AnnaBridge 126:abea610beb85 455 */
AnnaBridge 126:abea610beb85 456 typedef struct
AnnaBridge 126:abea610beb85 457 {
AnnaBridge 126:abea610beb85 458 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 126:abea610beb85 459 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 126:abea610beb85 460 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 126:abea610beb85 461 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 126:abea610beb85 462 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 126:abea610beb85 463 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 126:abea610beb85 464 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 126:abea610beb85 465 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 126:abea610beb85 466 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 126:abea610beb85 467 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 126:abea610beb85 468 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 126:abea610beb85 469 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 126:abea610beb85 470 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 126:abea610beb85 471 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 126:abea610beb85 472 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 126:abea610beb85 473 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 126:abea610beb85 474 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 126:abea610beb85 475 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 126:abea610beb85 476 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 126:abea610beb85 477 uint32_t RESERVED0[5];
AnnaBridge 126:abea610beb85 478 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
AnnaBridge 126:abea610beb85 479 } SCB_Type;
AnnaBridge 126:abea610beb85 480
AnnaBridge 126:abea610beb85 481 /* SCB CPUID Register Definitions */
AnnaBridge 126:abea610beb85 482 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 126:abea610beb85 483 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 126:abea610beb85 484
AnnaBridge 126:abea610beb85 485 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
AnnaBridge 126:abea610beb85 486 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 126:abea610beb85 487
AnnaBridge 126:abea610beb85 488 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 126:abea610beb85 489 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 126:abea610beb85 490
AnnaBridge 126:abea610beb85 491 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
AnnaBridge 126:abea610beb85 492 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 126:abea610beb85 493
AnnaBridge 126:abea610beb85 494 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
AnnaBridge 126:abea610beb85 495 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 126:abea610beb85 496
AnnaBridge 126:abea610beb85 497 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 126:abea610beb85 498 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 126:abea610beb85 499 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 126:abea610beb85 500
AnnaBridge 126:abea610beb85 501 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 126:abea610beb85 502 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 126:abea610beb85 503
AnnaBridge 126:abea610beb85 504 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 126:abea610beb85 505 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 126:abea610beb85 506
AnnaBridge 126:abea610beb85 507 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 126:abea610beb85 508 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 126:abea610beb85 509
AnnaBridge 126:abea610beb85 510 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 126:abea610beb85 511 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 126:abea610beb85 512
AnnaBridge 126:abea610beb85 513 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 126:abea610beb85 514 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 126:abea610beb85 515
AnnaBridge 126:abea610beb85 516 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 126:abea610beb85 517 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 126:abea610beb85 518
AnnaBridge 126:abea610beb85 519 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 126:abea610beb85 520 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 126:abea610beb85 521
AnnaBridge 126:abea610beb85 522 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 126:abea610beb85 523 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 126:abea610beb85 524
AnnaBridge 126:abea610beb85 525 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 126:abea610beb85 526 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 126:abea610beb85 527
AnnaBridge 126:abea610beb85 528 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 126:abea610beb85 529 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 126:abea610beb85 530 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 126:abea610beb85 531
AnnaBridge 126:abea610beb85 532 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 126:abea610beb85 533 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 126:abea610beb85 534 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 126:abea610beb85 535
AnnaBridge 126:abea610beb85 536 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 126:abea610beb85 537 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 126:abea610beb85 538
AnnaBridge 126:abea610beb85 539 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 126:abea610beb85 540 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 126:abea610beb85 541
AnnaBridge 126:abea610beb85 542 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
AnnaBridge 126:abea610beb85 543 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
AnnaBridge 126:abea610beb85 544
AnnaBridge 126:abea610beb85 545 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 126:abea610beb85 546 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 126:abea610beb85 547
AnnaBridge 126:abea610beb85 548 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 126:abea610beb85 549 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 126:abea610beb85 550
AnnaBridge 126:abea610beb85 551 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
AnnaBridge 126:abea610beb85 552 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
AnnaBridge 126:abea610beb85 553
AnnaBridge 126:abea610beb85 554 /* SCB System Control Register Definitions */
AnnaBridge 126:abea610beb85 555 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 126:abea610beb85 556 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 126:abea610beb85 557
AnnaBridge 126:abea610beb85 558 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 126:abea610beb85 559 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 126:abea610beb85 560
AnnaBridge 126:abea610beb85 561 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 126:abea610beb85 562 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 126:abea610beb85 563
AnnaBridge 126:abea610beb85 564 /* SCB Configuration Control Register Definitions */
AnnaBridge 126:abea610beb85 565 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
AnnaBridge 126:abea610beb85 566 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 126:abea610beb85 567
AnnaBridge 126:abea610beb85 568 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 126:abea610beb85 569 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 126:abea610beb85 570
AnnaBridge 126:abea610beb85 571 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 126:abea610beb85 572 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 126:abea610beb85 573
AnnaBridge 126:abea610beb85 574 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 126:abea610beb85 575 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 126:abea610beb85 576
AnnaBridge 126:abea610beb85 577 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 126:abea610beb85 578 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 126:abea610beb85 579
AnnaBridge 126:abea610beb85 580 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
AnnaBridge 126:abea610beb85 581 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
AnnaBridge 126:abea610beb85 582
AnnaBridge 126:abea610beb85 583 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 126:abea610beb85 584 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
AnnaBridge 126:abea610beb85 585 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
AnnaBridge 126:abea610beb85 586
AnnaBridge 126:abea610beb85 587 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
AnnaBridge 126:abea610beb85 588 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
AnnaBridge 126:abea610beb85 589
AnnaBridge 126:abea610beb85 590 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
AnnaBridge 126:abea610beb85 591 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
AnnaBridge 126:abea610beb85 592
AnnaBridge 126:abea610beb85 593 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 126:abea610beb85 594 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 126:abea610beb85 595
AnnaBridge 126:abea610beb85 596 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
AnnaBridge 126:abea610beb85 597 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
AnnaBridge 126:abea610beb85 598
AnnaBridge 126:abea610beb85 599 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
AnnaBridge 126:abea610beb85 600 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
AnnaBridge 126:abea610beb85 601
AnnaBridge 126:abea610beb85 602 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
AnnaBridge 126:abea610beb85 603 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
AnnaBridge 126:abea610beb85 604
AnnaBridge 126:abea610beb85 605 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 126:abea610beb85 606 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 126:abea610beb85 607
AnnaBridge 126:abea610beb85 608 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 126:abea610beb85 609 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 126:abea610beb85 610
AnnaBridge 126:abea610beb85 611 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
AnnaBridge 126:abea610beb85 612 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
AnnaBridge 126:abea610beb85 613
AnnaBridge 126:abea610beb85 614 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 126:abea610beb85 615 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 126:abea610beb85 616
AnnaBridge 126:abea610beb85 617 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
AnnaBridge 126:abea610beb85 618 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
AnnaBridge 126:abea610beb85 619
AnnaBridge 126:abea610beb85 620 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
AnnaBridge 126:abea610beb85 621 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
AnnaBridge 126:abea610beb85 622
AnnaBridge 126:abea610beb85 623 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
AnnaBridge 126:abea610beb85 624 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
AnnaBridge 126:abea610beb85 625
AnnaBridge 126:abea610beb85 626 /* SCB Configurable Fault Status Registers Definitions */
AnnaBridge 126:abea610beb85 627 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
AnnaBridge 126:abea610beb85 628 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
AnnaBridge 126:abea610beb85 629
AnnaBridge 126:abea610beb85 630 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
AnnaBridge 126:abea610beb85 631 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
AnnaBridge 126:abea610beb85 632
AnnaBridge 126:abea610beb85 633 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
AnnaBridge 126:abea610beb85 634 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
AnnaBridge 126:abea610beb85 635
AnnaBridge 126:abea610beb85 636 /* SCB Hard Fault Status Registers Definitions */
AnnaBridge 126:abea610beb85 637 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
AnnaBridge 126:abea610beb85 638 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
AnnaBridge 126:abea610beb85 639
AnnaBridge 126:abea610beb85 640 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
AnnaBridge 126:abea610beb85 641 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
AnnaBridge 126:abea610beb85 642
AnnaBridge 126:abea610beb85 643 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
AnnaBridge 126:abea610beb85 644 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
AnnaBridge 126:abea610beb85 645
AnnaBridge 126:abea610beb85 646 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 126:abea610beb85 647 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
AnnaBridge 126:abea610beb85 648 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
AnnaBridge 126:abea610beb85 649
AnnaBridge 126:abea610beb85 650 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
AnnaBridge 126:abea610beb85 651 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
AnnaBridge 126:abea610beb85 652
AnnaBridge 126:abea610beb85 653 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
AnnaBridge 126:abea610beb85 654 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
AnnaBridge 126:abea610beb85 655
AnnaBridge 126:abea610beb85 656 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
AnnaBridge 126:abea610beb85 657 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
AnnaBridge 126:abea610beb85 658
AnnaBridge 126:abea610beb85 659 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
AnnaBridge 126:abea610beb85 660 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
AnnaBridge 126:abea610beb85 661
AnnaBridge 126:abea610beb85 662 /*@} end of group CMSIS_SCB */
AnnaBridge 126:abea610beb85 663
AnnaBridge 126:abea610beb85 664
AnnaBridge 126:abea610beb85 665 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 666 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 126:abea610beb85 667 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 126:abea610beb85 668 @{
AnnaBridge 126:abea610beb85 669 */
AnnaBridge 126:abea610beb85 670
AnnaBridge 126:abea610beb85 671 /** \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 126:abea610beb85 672 */
AnnaBridge 126:abea610beb85 673 typedef struct
AnnaBridge 126:abea610beb85 674 {
AnnaBridge 126:abea610beb85 675 uint32_t RESERVED0[1];
AnnaBridge 126:abea610beb85 676 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 126:abea610beb85 677 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
AnnaBridge 126:abea610beb85 678 } SCnSCB_Type;
AnnaBridge 126:abea610beb85 679
AnnaBridge 126:abea610beb85 680 /* Interrupt Controller Type Register Definitions */
AnnaBridge 126:abea610beb85 681 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
AnnaBridge 126:abea610beb85 682 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
AnnaBridge 126:abea610beb85 683
AnnaBridge 126:abea610beb85 684 /* Auxiliary Control Register Definitions */
AnnaBridge 126:abea610beb85 685 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
AnnaBridge 126:abea610beb85 686 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
AnnaBridge 126:abea610beb85 687
AnnaBridge 126:abea610beb85 688 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
AnnaBridge 126:abea610beb85 689 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
AnnaBridge 126:abea610beb85 690
AnnaBridge 126:abea610beb85 691 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
AnnaBridge 126:abea610beb85 692 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
AnnaBridge 126:abea610beb85 693
AnnaBridge 126:abea610beb85 694 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
AnnaBridge 126:abea610beb85 695 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
AnnaBridge 126:abea610beb85 696
AnnaBridge 126:abea610beb85 697 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
AnnaBridge 126:abea610beb85 698 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
AnnaBridge 126:abea610beb85 699
AnnaBridge 126:abea610beb85 700 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 126:abea610beb85 701
AnnaBridge 126:abea610beb85 702
AnnaBridge 126:abea610beb85 703 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 704 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 126:abea610beb85 705 \brief Type definitions for the System Timer Registers.
AnnaBridge 126:abea610beb85 706 @{
AnnaBridge 126:abea610beb85 707 */
AnnaBridge 126:abea610beb85 708
AnnaBridge 126:abea610beb85 709 /** \brief Structure type to access the System Timer (SysTick).
AnnaBridge 126:abea610beb85 710 */
AnnaBridge 126:abea610beb85 711 typedef struct
AnnaBridge 126:abea610beb85 712 {
AnnaBridge 126:abea610beb85 713 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 126:abea610beb85 714 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 126:abea610beb85 715 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 126:abea610beb85 716 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 126:abea610beb85 717 } SysTick_Type;
AnnaBridge 126:abea610beb85 718
AnnaBridge 126:abea610beb85 719 /* SysTick Control / Status Register Definitions */
AnnaBridge 126:abea610beb85 720 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 126:abea610beb85 721 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 126:abea610beb85 722
AnnaBridge 126:abea610beb85 723 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 126:abea610beb85 724 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 126:abea610beb85 725
AnnaBridge 126:abea610beb85 726 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 126:abea610beb85 727 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 126:abea610beb85 728
AnnaBridge 126:abea610beb85 729 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 126:abea610beb85 730 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 126:abea610beb85 731
AnnaBridge 126:abea610beb85 732 /* SysTick Reload Register Definitions */
AnnaBridge 126:abea610beb85 733 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 126:abea610beb85 734 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 126:abea610beb85 735
AnnaBridge 126:abea610beb85 736 /* SysTick Current Register Definitions */
AnnaBridge 126:abea610beb85 737 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
AnnaBridge 126:abea610beb85 738 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 126:abea610beb85 739
AnnaBridge 126:abea610beb85 740 /* SysTick Calibration Register Definitions */
AnnaBridge 126:abea610beb85 741 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
AnnaBridge 126:abea610beb85 742 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 126:abea610beb85 743
AnnaBridge 126:abea610beb85 744 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
AnnaBridge 126:abea610beb85 745 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 126:abea610beb85 746
AnnaBridge 126:abea610beb85 747 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
AnnaBridge 126:abea610beb85 748 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 126:abea610beb85 749
AnnaBridge 126:abea610beb85 750 /*@} end of group CMSIS_SysTick */
AnnaBridge 126:abea610beb85 751
AnnaBridge 126:abea610beb85 752
AnnaBridge 126:abea610beb85 753 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 754 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 126:abea610beb85 755 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge 126:abea610beb85 756 @{
AnnaBridge 126:abea610beb85 757 */
AnnaBridge 126:abea610beb85 758
AnnaBridge 126:abea610beb85 759 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge 126:abea610beb85 760 */
AnnaBridge 126:abea610beb85 761 typedef struct
AnnaBridge 126:abea610beb85 762 {
AnnaBridge 126:abea610beb85 763 __O union
AnnaBridge 126:abea610beb85 764 {
AnnaBridge 126:abea610beb85 765 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 126:abea610beb85 766 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 126:abea610beb85 767 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 126:abea610beb85 768 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 126:abea610beb85 769 uint32_t RESERVED0[864];
AnnaBridge 126:abea610beb85 770 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 126:abea610beb85 771 uint32_t RESERVED1[15];
AnnaBridge 126:abea610beb85 772 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 126:abea610beb85 773 uint32_t RESERVED2[15];
AnnaBridge 126:abea610beb85 774 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 126:abea610beb85 775 uint32_t RESERVED3[29];
AnnaBridge 126:abea610beb85 776 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 126:abea610beb85 777 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 126:abea610beb85 778 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 126:abea610beb85 779 uint32_t RESERVED4[43];
AnnaBridge 126:abea610beb85 780 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 126:abea610beb85 781 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 126:abea610beb85 782 uint32_t RESERVED5[6];
AnnaBridge 126:abea610beb85 783 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 126:abea610beb85 784 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 126:abea610beb85 785 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 126:abea610beb85 786 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 126:abea610beb85 787 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 126:abea610beb85 788 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 126:abea610beb85 789 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 126:abea610beb85 790 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 126:abea610beb85 791 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 126:abea610beb85 792 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 126:abea610beb85 793 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 126:abea610beb85 794 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
AnnaBridge 126:abea610beb85 795 } ITM_Type;
AnnaBridge 126:abea610beb85 796
AnnaBridge 126:abea610beb85 797 /* ITM Trace Privilege Register Definitions */
AnnaBridge 126:abea610beb85 798 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
AnnaBridge 126:abea610beb85 799 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
AnnaBridge 126:abea610beb85 800
AnnaBridge 126:abea610beb85 801 /* ITM Trace Control Register Definitions */
AnnaBridge 126:abea610beb85 802 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
AnnaBridge 126:abea610beb85 803 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
AnnaBridge 126:abea610beb85 804
AnnaBridge 126:abea610beb85 805 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
AnnaBridge 126:abea610beb85 806 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
AnnaBridge 126:abea610beb85 807
AnnaBridge 126:abea610beb85 808 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
AnnaBridge 126:abea610beb85 809 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
AnnaBridge 126:abea610beb85 810
AnnaBridge 126:abea610beb85 811 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
AnnaBridge 126:abea610beb85 812 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
AnnaBridge 126:abea610beb85 813
AnnaBridge 126:abea610beb85 814 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
AnnaBridge 126:abea610beb85 815 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
AnnaBridge 126:abea610beb85 816
AnnaBridge 126:abea610beb85 817 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
AnnaBridge 126:abea610beb85 818 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
AnnaBridge 126:abea610beb85 819
AnnaBridge 126:abea610beb85 820 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
AnnaBridge 126:abea610beb85 821 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
AnnaBridge 126:abea610beb85 822
AnnaBridge 126:abea610beb85 823 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
AnnaBridge 126:abea610beb85 824 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
AnnaBridge 126:abea610beb85 825
AnnaBridge 126:abea610beb85 826 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
AnnaBridge 126:abea610beb85 827 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
AnnaBridge 126:abea610beb85 828
AnnaBridge 126:abea610beb85 829 /* ITM Integration Write Register Definitions */
AnnaBridge 126:abea610beb85 830 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
AnnaBridge 126:abea610beb85 831 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
AnnaBridge 126:abea610beb85 832
AnnaBridge 126:abea610beb85 833 /* ITM Integration Read Register Definitions */
AnnaBridge 126:abea610beb85 834 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
AnnaBridge 126:abea610beb85 835 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
AnnaBridge 126:abea610beb85 836
AnnaBridge 126:abea610beb85 837 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 126:abea610beb85 838 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
AnnaBridge 126:abea610beb85 839 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
AnnaBridge 126:abea610beb85 840
AnnaBridge 126:abea610beb85 841 /* ITM Lock Status Register Definitions */
AnnaBridge 126:abea610beb85 842 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
AnnaBridge 126:abea610beb85 843 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
AnnaBridge 126:abea610beb85 844
AnnaBridge 126:abea610beb85 845 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
AnnaBridge 126:abea610beb85 846 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
AnnaBridge 126:abea610beb85 847
AnnaBridge 126:abea610beb85 848 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
AnnaBridge 126:abea610beb85 849 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
AnnaBridge 126:abea610beb85 850
AnnaBridge 126:abea610beb85 851 /*@}*/ /* end of group CMSIS_ITM */
AnnaBridge 126:abea610beb85 852
AnnaBridge 126:abea610beb85 853
AnnaBridge 126:abea610beb85 854 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 855 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 126:abea610beb85 856 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 126:abea610beb85 857 @{
AnnaBridge 126:abea610beb85 858 */
AnnaBridge 126:abea610beb85 859
AnnaBridge 126:abea610beb85 860 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 126:abea610beb85 861 */
AnnaBridge 126:abea610beb85 862 typedef struct
AnnaBridge 126:abea610beb85 863 {
AnnaBridge 126:abea610beb85 864 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 126:abea610beb85 865 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 126:abea610beb85 866 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 126:abea610beb85 867 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 126:abea610beb85 868 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 126:abea610beb85 869 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 126:abea610beb85 870 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 126:abea610beb85 871 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 126:abea610beb85 872 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 126:abea610beb85 873 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 126:abea610beb85 874 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 126:abea610beb85 875 uint32_t RESERVED0[1];
AnnaBridge 126:abea610beb85 876 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 126:abea610beb85 877 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 126:abea610beb85 878 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 126:abea610beb85 879 uint32_t RESERVED1[1];
AnnaBridge 126:abea610beb85 880 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 126:abea610beb85 881 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 126:abea610beb85 882 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 126:abea610beb85 883 uint32_t RESERVED2[1];
AnnaBridge 126:abea610beb85 884 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 126:abea610beb85 885 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 126:abea610beb85 886 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 126:abea610beb85 887 } DWT_Type;
AnnaBridge 126:abea610beb85 888
AnnaBridge 126:abea610beb85 889 /* DWT Control Register Definitions */
AnnaBridge 126:abea610beb85 890 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 126:abea610beb85 891 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 126:abea610beb85 892
AnnaBridge 126:abea610beb85 893 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 126:abea610beb85 894 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 126:abea610beb85 895
AnnaBridge 126:abea610beb85 896 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 126:abea610beb85 897 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 126:abea610beb85 898
AnnaBridge 126:abea610beb85 899 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 126:abea610beb85 900 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 126:abea610beb85 901
AnnaBridge 126:abea610beb85 902 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 126:abea610beb85 903 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 126:abea610beb85 904
AnnaBridge 126:abea610beb85 905 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
AnnaBridge 126:abea610beb85 906 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
AnnaBridge 126:abea610beb85 907
AnnaBridge 126:abea610beb85 908 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
AnnaBridge 126:abea610beb85 909 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
AnnaBridge 126:abea610beb85 910
AnnaBridge 126:abea610beb85 911 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
AnnaBridge 126:abea610beb85 912 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
AnnaBridge 126:abea610beb85 913
AnnaBridge 126:abea610beb85 914 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
AnnaBridge 126:abea610beb85 915 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
AnnaBridge 126:abea610beb85 916
AnnaBridge 126:abea610beb85 917 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
AnnaBridge 126:abea610beb85 918 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
AnnaBridge 126:abea610beb85 919
AnnaBridge 126:abea610beb85 920 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
AnnaBridge 126:abea610beb85 921 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
AnnaBridge 126:abea610beb85 922
AnnaBridge 126:abea610beb85 923 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
AnnaBridge 126:abea610beb85 924 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
AnnaBridge 126:abea610beb85 925
AnnaBridge 126:abea610beb85 926 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
AnnaBridge 126:abea610beb85 927 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
AnnaBridge 126:abea610beb85 928
AnnaBridge 126:abea610beb85 929 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
AnnaBridge 126:abea610beb85 930 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
AnnaBridge 126:abea610beb85 931
AnnaBridge 126:abea610beb85 932 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
AnnaBridge 126:abea610beb85 933 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
AnnaBridge 126:abea610beb85 934
AnnaBridge 126:abea610beb85 935 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
AnnaBridge 126:abea610beb85 936 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
AnnaBridge 126:abea610beb85 937
AnnaBridge 126:abea610beb85 938 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
AnnaBridge 126:abea610beb85 939 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
AnnaBridge 126:abea610beb85 940
AnnaBridge 126:abea610beb85 941 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
AnnaBridge 126:abea610beb85 942 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
AnnaBridge 126:abea610beb85 943
AnnaBridge 126:abea610beb85 944 /* DWT CPI Count Register Definitions */
AnnaBridge 126:abea610beb85 945 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
AnnaBridge 126:abea610beb85 946 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
AnnaBridge 126:abea610beb85 947
AnnaBridge 126:abea610beb85 948 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 126:abea610beb85 949 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
AnnaBridge 126:abea610beb85 950 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
AnnaBridge 126:abea610beb85 951
AnnaBridge 126:abea610beb85 952 /* DWT Sleep Count Register Definitions */
AnnaBridge 126:abea610beb85 953 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
AnnaBridge 126:abea610beb85 954 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
AnnaBridge 126:abea610beb85 955
AnnaBridge 126:abea610beb85 956 /* DWT LSU Count Register Definitions */
AnnaBridge 126:abea610beb85 957 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
AnnaBridge 126:abea610beb85 958 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
AnnaBridge 126:abea610beb85 959
AnnaBridge 126:abea610beb85 960 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 126:abea610beb85 961 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
AnnaBridge 126:abea610beb85 962 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
AnnaBridge 126:abea610beb85 963
AnnaBridge 126:abea610beb85 964 /* DWT Comparator Mask Register Definitions */
AnnaBridge 126:abea610beb85 965 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
AnnaBridge 126:abea610beb85 966 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
AnnaBridge 126:abea610beb85 967
AnnaBridge 126:abea610beb85 968 /* DWT Comparator Function Register Definitions */
AnnaBridge 126:abea610beb85 969 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 126:abea610beb85 970 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 126:abea610beb85 971
AnnaBridge 126:abea610beb85 972 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
AnnaBridge 126:abea610beb85 973 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
AnnaBridge 126:abea610beb85 974
AnnaBridge 126:abea610beb85 975 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
AnnaBridge 126:abea610beb85 976 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
AnnaBridge 126:abea610beb85 977
AnnaBridge 126:abea610beb85 978 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 126:abea610beb85 979 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 126:abea610beb85 980
AnnaBridge 126:abea610beb85 981 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
AnnaBridge 126:abea610beb85 982 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
AnnaBridge 126:abea610beb85 983
AnnaBridge 126:abea610beb85 984 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
AnnaBridge 126:abea610beb85 985 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
AnnaBridge 126:abea610beb85 986
AnnaBridge 126:abea610beb85 987 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
AnnaBridge 126:abea610beb85 988 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
AnnaBridge 126:abea610beb85 989
AnnaBridge 126:abea610beb85 990 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
AnnaBridge 126:abea610beb85 991 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
AnnaBridge 126:abea610beb85 992
AnnaBridge 126:abea610beb85 993 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
AnnaBridge 126:abea610beb85 994 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
AnnaBridge 126:abea610beb85 995
AnnaBridge 126:abea610beb85 996 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 126:abea610beb85 997
AnnaBridge 126:abea610beb85 998
AnnaBridge 126:abea610beb85 999 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 1000 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 126:abea610beb85 1001 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 126:abea610beb85 1002 @{
AnnaBridge 126:abea610beb85 1003 */
AnnaBridge 126:abea610beb85 1004
AnnaBridge 126:abea610beb85 1005 /** \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 126:abea610beb85 1006 */
AnnaBridge 126:abea610beb85 1007 typedef struct
AnnaBridge 126:abea610beb85 1008 {
AnnaBridge 126:abea610beb85 1009 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 126:abea610beb85 1010 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 126:abea610beb85 1011 uint32_t RESERVED0[2];
AnnaBridge 126:abea610beb85 1012 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 126:abea610beb85 1013 uint32_t RESERVED1[55];
AnnaBridge 126:abea610beb85 1014 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 126:abea610beb85 1015 uint32_t RESERVED2[131];
AnnaBridge 126:abea610beb85 1016 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 126:abea610beb85 1017 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 126:abea610beb85 1018 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 126:abea610beb85 1019 uint32_t RESERVED3[759];
AnnaBridge 126:abea610beb85 1020 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 126:abea610beb85 1021 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 126:abea610beb85 1022 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 126:abea610beb85 1023 uint32_t RESERVED4[1];
AnnaBridge 126:abea610beb85 1024 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 126:abea610beb85 1025 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 126:abea610beb85 1026 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 126:abea610beb85 1027 uint32_t RESERVED5[39];
AnnaBridge 126:abea610beb85 1028 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 126:abea610beb85 1029 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 126:abea610beb85 1030 uint32_t RESERVED7[8];
AnnaBridge 126:abea610beb85 1031 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 126:abea610beb85 1032 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 126:abea610beb85 1033 } TPI_Type;
AnnaBridge 126:abea610beb85 1034
AnnaBridge 126:abea610beb85 1035 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 126:abea610beb85 1036 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 126:abea610beb85 1037 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 126:abea610beb85 1038
AnnaBridge 126:abea610beb85 1039 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 126:abea610beb85 1040 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
AnnaBridge 126:abea610beb85 1041 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 126:abea610beb85 1042
AnnaBridge 126:abea610beb85 1043 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 126:abea610beb85 1044 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 126:abea610beb85 1045 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 126:abea610beb85 1046
AnnaBridge 126:abea610beb85 1047 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
AnnaBridge 126:abea610beb85 1048 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 126:abea610beb85 1049
AnnaBridge 126:abea610beb85 1050 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
AnnaBridge 126:abea610beb85 1051 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 126:abea610beb85 1052
AnnaBridge 126:abea610beb85 1053 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
AnnaBridge 126:abea610beb85 1054 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 126:abea610beb85 1055
AnnaBridge 126:abea610beb85 1056 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 126:abea610beb85 1057 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
AnnaBridge 126:abea610beb85 1058 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 126:abea610beb85 1059
AnnaBridge 126:abea610beb85 1060 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
AnnaBridge 126:abea610beb85 1061 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 126:abea610beb85 1062
AnnaBridge 126:abea610beb85 1063 /* TPI TRIGGER Register Definitions */
AnnaBridge 126:abea610beb85 1064 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 126:abea610beb85 1065 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 126:abea610beb85 1066
AnnaBridge 126:abea610beb85 1067 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 126:abea610beb85 1068 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 126:abea610beb85 1069 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 126:abea610beb85 1070
AnnaBridge 126:abea610beb85 1071 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 126:abea610beb85 1072 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 126:abea610beb85 1073
AnnaBridge 126:abea610beb85 1074 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 126:abea610beb85 1075 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 126:abea610beb85 1076
AnnaBridge 126:abea610beb85 1077 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 126:abea610beb85 1078 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 126:abea610beb85 1079
AnnaBridge 126:abea610beb85 1080 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 126:abea610beb85 1081 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 126:abea610beb85 1082
AnnaBridge 126:abea610beb85 1083 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 126:abea610beb85 1084 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 126:abea610beb85 1085
AnnaBridge 126:abea610beb85 1086 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 126:abea610beb85 1087 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 126:abea610beb85 1088
AnnaBridge 126:abea610beb85 1089 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 126:abea610beb85 1090 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 126:abea610beb85 1091 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 126:abea610beb85 1092
AnnaBridge 126:abea610beb85 1093 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 126:abea610beb85 1094 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 126:abea610beb85 1095 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 126:abea610beb85 1096
AnnaBridge 126:abea610beb85 1097 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 126:abea610beb85 1098 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 126:abea610beb85 1099
AnnaBridge 126:abea610beb85 1100 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 126:abea610beb85 1101 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 126:abea610beb85 1102
AnnaBridge 126:abea610beb85 1103 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 126:abea610beb85 1104 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 126:abea610beb85 1105
AnnaBridge 126:abea610beb85 1106 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 126:abea610beb85 1107 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 126:abea610beb85 1108
AnnaBridge 126:abea610beb85 1109 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 126:abea610beb85 1110 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 126:abea610beb85 1111
AnnaBridge 126:abea610beb85 1112 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 126:abea610beb85 1113 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 126:abea610beb85 1114
AnnaBridge 126:abea610beb85 1115 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 126:abea610beb85 1116 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 126:abea610beb85 1117 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 126:abea610beb85 1118
AnnaBridge 126:abea610beb85 1119 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 126:abea610beb85 1120 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
AnnaBridge 126:abea610beb85 1121 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 126:abea610beb85 1122
AnnaBridge 126:abea610beb85 1123 /* TPI DEVID Register Definitions */
AnnaBridge 126:abea610beb85 1124 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 126:abea610beb85 1125 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 126:abea610beb85 1126
AnnaBridge 126:abea610beb85 1127 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 126:abea610beb85 1128 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 126:abea610beb85 1129
AnnaBridge 126:abea610beb85 1130 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 126:abea610beb85 1131 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 126:abea610beb85 1132
AnnaBridge 126:abea610beb85 1133 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 126:abea610beb85 1134 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 126:abea610beb85 1135
AnnaBridge 126:abea610beb85 1136 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 126:abea610beb85 1137 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 126:abea610beb85 1138
AnnaBridge 126:abea610beb85 1139 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 126:abea610beb85 1140 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 126:abea610beb85 1141
AnnaBridge 126:abea610beb85 1142 /* TPI DEVTYPE Register Definitions */
AnnaBridge 126:abea610beb85 1143 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 126:abea610beb85 1144 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 126:abea610beb85 1145
AnnaBridge 126:abea610beb85 1146 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 126:abea610beb85 1147 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 126:abea610beb85 1148
AnnaBridge 126:abea610beb85 1149 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 126:abea610beb85 1150
AnnaBridge 126:abea610beb85 1151
AnnaBridge 126:abea610beb85 1152 #if (__MPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 1153 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 1154 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 126:abea610beb85 1155 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 126:abea610beb85 1156 @{
AnnaBridge 126:abea610beb85 1157 */
AnnaBridge 126:abea610beb85 1158
AnnaBridge 126:abea610beb85 1159 /** \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 126:abea610beb85 1160 */
AnnaBridge 126:abea610beb85 1161 typedef struct
AnnaBridge 126:abea610beb85 1162 {
AnnaBridge 126:abea610beb85 1163 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 126:abea610beb85 1164 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 126:abea610beb85 1165 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 126:abea610beb85 1166 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 126:abea610beb85 1167 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1168 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 126:abea610beb85 1169 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1170 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 126:abea610beb85 1171 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1172 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 126:abea610beb85 1173 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1174 } MPU_Type;
AnnaBridge 126:abea610beb85 1175
AnnaBridge 126:abea610beb85 1176 /* MPU Type Register */
AnnaBridge 126:abea610beb85 1177 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
AnnaBridge 126:abea610beb85 1178 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 126:abea610beb85 1179
AnnaBridge 126:abea610beb85 1180 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
AnnaBridge 126:abea610beb85 1181 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 126:abea610beb85 1182
AnnaBridge 126:abea610beb85 1183 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 126:abea610beb85 1184 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 126:abea610beb85 1185
AnnaBridge 126:abea610beb85 1186 /* MPU Control Register */
AnnaBridge 126:abea610beb85 1187 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 126:abea610beb85 1188 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 126:abea610beb85 1189
AnnaBridge 126:abea610beb85 1190 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 126:abea610beb85 1191 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 126:abea610beb85 1192
AnnaBridge 126:abea610beb85 1193 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
AnnaBridge 126:abea610beb85 1194 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 126:abea610beb85 1195
AnnaBridge 126:abea610beb85 1196 /* MPU Region Number Register */
AnnaBridge 126:abea610beb85 1197 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
AnnaBridge 126:abea610beb85 1198 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 126:abea610beb85 1199
AnnaBridge 126:abea610beb85 1200 /* MPU Region Base Address Register */
AnnaBridge 126:abea610beb85 1201 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
AnnaBridge 126:abea610beb85 1202 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 126:abea610beb85 1203
AnnaBridge 126:abea610beb85 1204 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
AnnaBridge 126:abea610beb85 1205 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 126:abea610beb85 1206
AnnaBridge 126:abea610beb85 1207 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
AnnaBridge 126:abea610beb85 1208 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 126:abea610beb85 1209
AnnaBridge 126:abea610beb85 1210 /* MPU Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1211 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 126:abea610beb85 1212 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 126:abea610beb85 1213
AnnaBridge 126:abea610beb85 1214 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 126:abea610beb85 1215 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 126:abea610beb85 1216
AnnaBridge 126:abea610beb85 1217 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 126:abea610beb85 1218 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 126:abea610beb85 1219
AnnaBridge 126:abea610beb85 1220 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 126:abea610beb85 1221 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 126:abea610beb85 1222
AnnaBridge 126:abea610beb85 1223 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 126:abea610beb85 1224 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 126:abea610beb85 1225
AnnaBridge 126:abea610beb85 1226 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 126:abea610beb85 1227 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 126:abea610beb85 1228
AnnaBridge 126:abea610beb85 1229 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 126:abea610beb85 1230 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 126:abea610beb85 1231
AnnaBridge 126:abea610beb85 1232 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 126:abea610beb85 1233 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 126:abea610beb85 1234
AnnaBridge 126:abea610beb85 1235 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
AnnaBridge 126:abea610beb85 1236 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 126:abea610beb85 1237
AnnaBridge 126:abea610beb85 1238 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
AnnaBridge 126:abea610beb85 1239 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 126:abea610beb85 1240
AnnaBridge 126:abea610beb85 1241 /*@} end of group CMSIS_MPU */
AnnaBridge 126:abea610beb85 1242 #endif
AnnaBridge 126:abea610beb85 1243
AnnaBridge 126:abea610beb85 1244
AnnaBridge 126:abea610beb85 1245 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 1246 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 1247 \defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge 126:abea610beb85 1248 \brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge 126:abea610beb85 1249 @{
AnnaBridge 126:abea610beb85 1250 */
AnnaBridge 126:abea610beb85 1251
AnnaBridge 126:abea610beb85 1252 /** \brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge 126:abea610beb85 1253 */
AnnaBridge 126:abea610beb85 1254 typedef struct
AnnaBridge 126:abea610beb85 1255 {
AnnaBridge 126:abea610beb85 1256 uint32_t RESERVED0[1];
AnnaBridge 126:abea610beb85 1257 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
AnnaBridge 126:abea610beb85 1258 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
AnnaBridge 126:abea610beb85 1259 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
AnnaBridge 126:abea610beb85 1260 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
AnnaBridge 126:abea610beb85 1261 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
AnnaBridge 126:abea610beb85 1262 } FPU_Type;
AnnaBridge 126:abea610beb85 1263
AnnaBridge 126:abea610beb85 1264 /* Floating-Point Context Control Register */
AnnaBridge 126:abea610beb85 1265 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
AnnaBridge 126:abea610beb85 1266 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
AnnaBridge 126:abea610beb85 1267
AnnaBridge 126:abea610beb85 1268 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
AnnaBridge 126:abea610beb85 1269 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
AnnaBridge 126:abea610beb85 1270
AnnaBridge 126:abea610beb85 1271 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
AnnaBridge 126:abea610beb85 1272 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
AnnaBridge 126:abea610beb85 1273
AnnaBridge 126:abea610beb85 1274 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
AnnaBridge 126:abea610beb85 1275 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
AnnaBridge 126:abea610beb85 1276
AnnaBridge 126:abea610beb85 1277 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
AnnaBridge 126:abea610beb85 1278 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
AnnaBridge 126:abea610beb85 1279
AnnaBridge 126:abea610beb85 1280 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
AnnaBridge 126:abea610beb85 1281 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
AnnaBridge 126:abea610beb85 1282
AnnaBridge 126:abea610beb85 1283 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
AnnaBridge 126:abea610beb85 1284 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
AnnaBridge 126:abea610beb85 1285
AnnaBridge 126:abea610beb85 1286 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
AnnaBridge 126:abea610beb85 1287 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
AnnaBridge 126:abea610beb85 1288
AnnaBridge 126:abea610beb85 1289 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
AnnaBridge 126:abea610beb85 1290 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
AnnaBridge 126:abea610beb85 1291
AnnaBridge 126:abea610beb85 1292 /* Floating-Point Context Address Register */
AnnaBridge 126:abea610beb85 1293 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
AnnaBridge 126:abea610beb85 1294 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
AnnaBridge 126:abea610beb85 1295
AnnaBridge 126:abea610beb85 1296 /* Floating-Point Default Status Control Register */
AnnaBridge 126:abea610beb85 1297 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
AnnaBridge 126:abea610beb85 1298 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
AnnaBridge 126:abea610beb85 1299
AnnaBridge 126:abea610beb85 1300 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
AnnaBridge 126:abea610beb85 1301 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
AnnaBridge 126:abea610beb85 1302
AnnaBridge 126:abea610beb85 1303 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
AnnaBridge 126:abea610beb85 1304 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
AnnaBridge 126:abea610beb85 1305
AnnaBridge 126:abea610beb85 1306 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
AnnaBridge 126:abea610beb85 1307 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
AnnaBridge 126:abea610beb85 1308
AnnaBridge 126:abea610beb85 1309 /* Media and FP Feature Register 0 */
AnnaBridge 126:abea610beb85 1310 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
AnnaBridge 126:abea610beb85 1311 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
AnnaBridge 126:abea610beb85 1312
AnnaBridge 126:abea610beb85 1313 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
AnnaBridge 126:abea610beb85 1314 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
AnnaBridge 126:abea610beb85 1315
AnnaBridge 126:abea610beb85 1316 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
AnnaBridge 126:abea610beb85 1317 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
AnnaBridge 126:abea610beb85 1318
AnnaBridge 126:abea610beb85 1319 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
AnnaBridge 126:abea610beb85 1320 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
AnnaBridge 126:abea610beb85 1321
AnnaBridge 126:abea610beb85 1322 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
AnnaBridge 126:abea610beb85 1323 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
AnnaBridge 126:abea610beb85 1324
AnnaBridge 126:abea610beb85 1325 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
AnnaBridge 126:abea610beb85 1326 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
AnnaBridge 126:abea610beb85 1327
AnnaBridge 126:abea610beb85 1328 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
AnnaBridge 126:abea610beb85 1329 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
AnnaBridge 126:abea610beb85 1330
AnnaBridge 126:abea610beb85 1331 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
AnnaBridge 126:abea610beb85 1332 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
AnnaBridge 126:abea610beb85 1333
AnnaBridge 126:abea610beb85 1334 /* Media and FP Feature Register 1 */
AnnaBridge 126:abea610beb85 1335 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
AnnaBridge 126:abea610beb85 1336 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
AnnaBridge 126:abea610beb85 1337
AnnaBridge 126:abea610beb85 1338 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
AnnaBridge 126:abea610beb85 1339 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
AnnaBridge 126:abea610beb85 1340
AnnaBridge 126:abea610beb85 1341 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
AnnaBridge 126:abea610beb85 1342 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
AnnaBridge 126:abea610beb85 1343
AnnaBridge 126:abea610beb85 1344 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
AnnaBridge 126:abea610beb85 1345 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
AnnaBridge 126:abea610beb85 1346
AnnaBridge 126:abea610beb85 1347 /*@} end of group CMSIS_FPU */
AnnaBridge 126:abea610beb85 1348 #endif
AnnaBridge 126:abea610beb85 1349
AnnaBridge 126:abea610beb85 1350
AnnaBridge 126:abea610beb85 1351 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 1352 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 126:abea610beb85 1353 \brief Type definitions for the Core Debug Registers
AnnaBridge 126:abea610beb85 1354 @{
AnnaBridge 126:abea610beb85 1355 */
AnnaBridge 126:abea610beb85 1356
AnnaBridge 126:abea610beb85 1357 /** \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 126:abea610beb85 1358 */
AnnaBridge 126:abea610beb85 1359 typedef struct
AnnaBridge 126:abea610beb85 1360 {
AnnaBridge 126:abea610beb85 1361 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 126:abea610beb85 1362 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 126:abea610beb85 1363 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 126:abea610beb85 1364 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 126:abea610beb85 1365 } CoreDebug_Type;
AnnaBridge 126:abea610beb85 1366
AnnaBridge 126:abea610beb85 1367 /* Debug Halting Control and Status Register */
AnnaBridge 126:abea610beb85 1368 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 126:abea610beb85 1369 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 126:abea610beb85 1370
AnnaBridge 126:abea610beb85 1371 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 126:abea610beb85 1372 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 126:abea610beb85 1373
AnnaBridge 126:abea610beb85 1374 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 126:abea610beb85 1375 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 126:abea610beb85 1376
AnnaBridge 126:abea610beb85 1377 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 126:abea610beb85 1378 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 126:abea610beb85 1379
AnnaBridge 126:abea610beb85 1380 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 126:abea610beb85 1381 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 126:abea610beb85 1382
AnnaBridge 126:abea610beb85 1383 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 126:abea610beb85 1384 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 126:abea610beb85 1385
AnnaBridge 126:abea610beb85 1386 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 126:abea610beb85 1387 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 126:abea610beb85 1388
AnnaBridge 126:abea610beb85 1389 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
AnnaBridge 126:abea610beb85 1390 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
AnnaBridge 126:abea610beb85 1391
AnnaBridge 126:abea610beb85 1392 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 126:abea610beb85 1393 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 126:abea610beb85 1394
AnnaBridge 126:abea610beb85 1395 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 126:abea610beb85 1396 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 126:abea610beb85 1397
AnnaBridge 126:abea610beb85 1398 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 126:abea610beb85 1399 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 126:abea610beb85 1400
AnnaBridge 126:abea610beb85 1401 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 126:abea610beb85 1402 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 126:abea610beb85 1403
AnnaBridge 126:abea610beb85 1404 /* Debug Core Register Selector Register */
AnnaBridge 126:abea610beb85 1405 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 126:abea610beb85 1406 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 126:abea610beb85 1407
AnnaBridge 126:abea610beb85 1408 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 126:abea610beb85 1409 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 126:abea610beb85 1410
AnnaBridge 126:abea610beb85 1411 /* Debug Exception and Monitor Control Register */
AnnaBridge 126:abea610beb85 1412 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
AnnaBridge 126:abea610beb85 1413 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
AnnaBridge 126:abea610beb85 1414
AnnaBridge 126:abea610beb85 1415 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
AnnaBridge 126:abea610beb85 1416 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
AnnaBridge 126:abea610beb85 1417
AnnaBridge 126:abea610beb85 1418 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
AnnaBridge 126:abea610beb85 1419 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
AnnaBridge 126:abea610beb85 1420
AnnaBridge 126:abea610beb85 1421 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
AnnaBridge 126:abea610beb85 1422 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
AnnaBridge 126:abea610beb85 1423
AnnaBridge 126:abea610beb85 1424 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
AnnaBridge 126:abea610beb85 1425 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
AnnaBridge 126:abea610beb85 1426
AnnaBridge 126:abea610beb85 1427 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 126:abea610beb85 1428 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 126:abea610beb85 1429
AnnaBridge 126:abea610beb85 1430 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
AnnaBridge 126:abea610beb85 1431 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
AnnaBridge 126:abea610beb85 1432
AnnaBridge 126:abea610beb85 1433 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
AnnaBridge 126:abea610beb85 1434 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
AnnaBridge 126:abea610beb85 1435
AnnaBridge 126:abea610beb85 1436 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
AnnaBridge 126:abea610beb85 1437 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
AnnaBridge 126:abea610beb85 1438
AnnaBridge 126:abea610beb85 1439 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
AnnaBridge 126:abea610beb85 1440 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
AnnaBridge 126:abea610beb85 1441
AnnaBridge 126:abea610beb85 1442 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
AnnaBridge 126:abea610beb85 1443 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
AnnaBridge 126:abea610beb85 1444
AnnaBridge 126:abea610beb85 1445 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
AnnaBridge 126:abea610beb85 1446 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
AnnaBridge 126:abea610beb85 1447
AnnaBridge 126:abea610beb85 1448 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 126:abea610beb85 1449 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 126:abea610beb85 1450
AnnaBridge 126:abea610beb85 1451 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 126:abea610beb85 1452
AnnaBridge 126:abea610beb85 1453
AnnaBridge 126:abea610beb85 1454 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 1455 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 126:abea610beb85 1456 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 126:abea610beb85 1457 @{
AnnaBridge 126:abea610beb85 1458 */
AnnaBridge 126:abea610beb85 1459
AnnaBridge 126:abea610beb85 1460 /* Memory mapping of Cortex-M4 Hardware */
AnnaBridge 126:abea610beb85 1461 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 126:abea610beb85 1462 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 126:abea610beb85 1463 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 126:abea610beb85 1464 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 126:abea610beb85 1465 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 126:abea610beb85 1466 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 126:abea610beb85 1467 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 126:abea610beb85 1468 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 126:abea610beb85 1469
AnnaBridge 126:abea610beb85 1470 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 126:abea610beb85 1471 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 126:abea610beb85 1472 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 126:abea610beb85 1473 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 126:abea610beb85 1474 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 126:abea610beb85 1475 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 126:abea610beb85 1476 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 126:abea610beb85 1477 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
AnnaBridge 126:abea610beb85 1478
AnnaBridge 126:abea610beb85 1479 #if (__MPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 1480 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 126:abea610beb85 1481 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 126:abea610beb85 1482 #endif
AnnaBridge 126:abea610beb85 1483
AnnaBridge 126:abea610beb85 1484 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 1485 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
AnnaBridge 126:abea610beb85 1486 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
AnnaBridge 126:abea610beb85 1487 #endif
AnnaBridge 126:abea610beb85 1488
AnnaBridge 126:abea610beb85 1489 /*@} */
AnnaBridge 126:abea610beb85 1490
AnnaBridge 126:abea610beb85 1491
AnnaBridge 126:abea610beb85 1492
AnnaBridge 126:abea610beb85 1493 /*******************************************************************************
AnnaBridge 126:abea610beb85 1494 * Hardware Abstraction Layer
AnnaBridge 126:abea610beb85 1495 Core Function Interface contains:
AnnaBridge 126:abea610beb85 1496 - Core NVIC Functions
AnnaBridge 126:abea610beb85 1497 - Core SysTick Functions
AnnaBridge 126:abea610beb85 1498 - Core Debug Functions
AnnaBridge 126:abea610beb85 1499 - Core Register Access Functions
AnnaBridge 126:abea610beb85 1500 ******************************************************************************/
AnnaBridge 126:abea610beb85 1501 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 126:abea610beb85 1502 */
AnnaBridge 126:abea610beb85 1503
AnnaBridge 126:abea610beb85 1504
AnnaBridge 126:abea610beb85 1505
AnnaBridge 126:abea610beb85 1506 /* ########################## NVIC functions #################################### */
AnnaBridge 126:abea610beb85 1507 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 1508 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 126:abea610beb85 1509 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 126:abea610beb85 1510 @{
AnnaBridge 126:abea610beb85 1511 */
AnnaBridge 126:abea610beb85 1512
AnnaBridge 126:abea610beb85 1513 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 126:abea610beb85 1514 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 126:abea610beb85 1515 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 126:abea610beb85 1516 #endif
AnnaBridge 126:abea610beb85 1517 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 126:abea610beb85 1518 #else
AnnaBridge 126:abea610beb85 1519 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge 126:abea610beb85 1520 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge 126:abea610beb85 1521 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 126:abea610beb85 1522 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 126:abea610beb85 1523 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 126:abea610beb85 1524 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 126:abea610beb85 1525 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 126:abea610beb85 1526 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 126:abea610beb85 1527 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 126:abea610beb85 1528 #define NVIC_GetPriority __NVIC_GetPriority
<> 128:9bcdf88f62b0 1529 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 126:abea610beb85 1530 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 126:abea610beb85 1531
AnnaBridge 126:abea610beb85 1532 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 126:abea610beb85 1533 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 126:abea610beb85 1534 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 126:abea610beb85 1535 #endif
AnnaBridge 126:abea610beb85 1536 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 126:abea610beb85 1537 #else
AnnaBridge 126:abea610beb85 1538 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 126:abea610beb85 1539 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 126:abea610beb85 1540 #endif /* CMSIS_VECTAB_VIRTUAL */
AnnaBridge 126:abea610beb85 1541
AnnaBridge 126:abea610beb85 1542
AnnaBridge 126:abea610beb85 1543 /** \brief Set Priority Grouping
AnnaBridge 126:abea610beb85 1544
AnnaBridge 126:abea610beb85 1545 The function sets the priority grouping field using the required unlock sequence.
AnnaBridge 126:abea610beb85 1546 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 126:abea610beb85 1547 Only values from 0..7 are used.
AnnaBridge 126:abea610beb85 1548 In case of a conflict between priority grouping and available
AnnaBridge 126:abea610beb85 1549 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 126:abea610beb85 1550
AnnaBridge 126:abea610beb85 1551 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 126:abea610beb85 1552 */
AnnaBridge 126:abea610beb85 1553 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge 126:abea610beb85 1554 {
AnnaBridge 126:abea610beb85 1555 uint32_t reg_value;
AnnaBridge 126:abea610beb85 1556 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 126:abea610beb85 1557
AnnaBridge 126:abea610beb85 1558 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 126:abea610beb85 1559 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 126:abea610beb85 1560 reg_value = (reg_value |
AnnaBridge 126:abea610beb85 1561 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 126:abea610beb85 1562 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
AnnaBridge 126:abea610beb85 1563 SCB->AIRCR = reg_value;
AnnaBridge 126:abea610beb85 1564 }
AnnaBridge 126:abea610beb85 1565
AnnaBridge 126:abea610beb85 1566
AnnaBridge 126:abea610beb85 1567 /** \brief Get Priority Grouping
AnnaBridge 126:abea610beb85 1568
AnnaBridge 126:abea610beb85 1569 The function reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 126:abea610beb85 1570
AnnaBridge 126:abea610beb85 1571 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 126:abea610beb85 1572 */
AnnaBridge 126:abea610beb85 1573 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge 126:abea610beb85 1574 {
AnnaBridge 126:abea610beb85 1575 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 126:abea610beb85 1576 }
AnnaBridge 126:abea610beb85 1577
AnnaBridge 126:abea610beb85 1578
AnnaBridge 126:abea610beb85 1579 /** \brief Enable External Interrupt
AnnaBridge 126:abea610beb85 1580
AnnaBridge 126:abea610beb85 1581 The function enables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 126:abea610beb85 1582
AnnaBridge 126:abea610beb85 1583 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 1584 */
AnnaBridge 126:abea610beb85 1585 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1586 {
AnnaBridge 126:abea610beb85 1587 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 1588 }
AnnaBridge 126:abea610beb85 1589
AnnaBridge 126:abea610beb85 1590
AnnaBridge 126:abea610beb85 1591 /** \brief Disable External Interrupt
AnnaBridge 126:abea610beb85 1592
AnnaBridge 126:abea610beb85 1593 The function disables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 126:abea610beb85 1594
AnnaBridge 126:abea610beb85 1595 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 1596 */
AnnaBridge 126:abea610beb85 1597 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1598 {
AnnaBridge 126:abea610beb85 1599 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1600 __DSB();
<> 131:faff56e089b2 1601 __ISB();
AnnaBridge 126:abea610beb85 1602 }
AnnaBridge 126:abea610beb85 1603
AnnaBridge 126:abea610beb85 1604
AnnaBridge 126:abea610beb85 1605 /** \brief Get Pending Interrupt
AnnaBridge 126:abea610beb85 1606
AnnaBridge 126:abea610beb85 1607 The function reads the pending register in the NVIC and returns the pending bit
AnnaBridge 126:abea610beb85 1608 for the specified interrupt.
AnnaBridge 126:abea610beb85 1609
AnnaBridge 126:abea610beb85 1610 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 1611
AnnaBridge 126:abea610beb85 1612 \return 0 Interrupt status is not pending.
AnnaBridge 126:abea610beb85 1613 \return 1 Interrupt status is pending.
AnnaBridge 126:abea610beb85 1614 */
AnnaBridge 126:abea610beb85 1615 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1616 {
AnnaBridge 126:abea610beb85 1617 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 126:abea610beb85 1618 }
AnnaBridge 126:abea610beb85 1619
AnnaBridge 126:abea610beb85 1620
AnnaBridge 126:abea610beb85 1621 /** \brief Set Pending Interrupt
AnnaBridge 126:abea610beb85 1622
AnnaBridge 126:abea610beb85 1623 The function sets the pending bit of an external interrupt.
AnnaBridge 126:abea610beb85 1624
AnnaBridge 126:abea610beb85 1625 \param [in] IRQn Interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 1626 */
AnnaBridge 126:abea610beb85 1627 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1628 {
AnnaBridge 126:abea610beb85 1629 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 1630 }
AnnaBridge 126:abea610beb85 1631
AnnaBridge 126:abea610beb85 1632
AnnaBridge 126:abea610beb85 1633 /** \brief Clear Pending Interrupt
AnnaBridge 126:abea610beb85 1634
AnnaBridge 126:abea610beb85 1635 The function clears the pending bit of an external interrupt.
AnnaBridge 126:abea610beb85 1636
AnnaBridge 126:abea610beb85 1637 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 1638 */
AnnaBridge 126:abea610beb85 1639 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1640 {
AnnaBridge 126:abea610beb85 1641 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 1642 }
AnnaBridge 126:abea610beb85 1643
AnnaBridge 126:abea610beb85 1644
AnnaBridge 126:abea610beb85 1645 /** \brief Get Active Interrupt
AnnaBridge 126:abea610beb85 1646
AnnaBridge 126:abea610beb85 1647 The function reads the active register in NVIC and returns the active bit.
AnnaBridge 126:abea610beb85 1648
AnnaBridge 126:abea610beb85 1649 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 1650
AnnaBridge 126:abea610beb85 1651 \return 0 Interrupt status is not active.
AnnaBridge 126:abea610beb85 1652 \return 1 Interrupt status is active.
AnnaBridge 126:abea610beb85 1653 */
AnnaBridge 126:abea610beb85 1654 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1655 {
AnnaBridge 126:abea610beb85 1656 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 126:abea610beb85 1657 }
AnnaBridge 126:abea610beb85 1658
AnnaBridge 126:abea610beb85 1659
AnnaBridge 126:abea610beb85 1660 /** \brief Set Interrupt Priority
AnnaBridge 126:abea610beb85 1661
AnnaBridge 126:abea610beb85 1662 The function sets the priority of an interrupt.
AnnaBridge 126:abea610beb85 1663
AnnaBridge 126:abea610beb85 1664 \note The priority cannot be set for every core interrupt.
AnnaBridge 126:abea610beb85 1665
AnnaBridge 126:abea610beb85 1666 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 1667 \param [in] priority Priority to set.
AnnaBridge 126:abea610beb85 1668 */
AnnaBridge 126:abea610beb85 1669 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 126:abea610beb85 1670 {
AnnaBridge 126:abea610beb85 1671 if((int32_t)IRQn < 0) {
AnnaBridge 126:abea610beb85 1672 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 126:abea610beb85 1673 }
AnnaBridge 126:abea610beb85 1674 else {
AnnaBridge 126:abea610beb85 1675 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 126:abea610beb85 1676 }
AnnaBridge 126:abea610beb85 1677 }
AnnaBridge 126:abea610beb85 1678
AnnaBridge 126:abea610beb85 1679
AnnaBridge 126:abea610beb85 1680 /** \brief Get Interrupt Priority
AnnaBridge 126:abea610beb85 1681
AnnaBridge 126:abea610beb85 1682 The function reads the priority of an interrupt. The interrupt
AnnaBridge 126:abea610beb85 1683 number can be positive to specify an external (device specific)
AnnaBridge 126:abea610beb85 1684 interrupt, or negative to specify an internal (core) interrupt.
AnnaBridge 126:abea610beb85 1685
AnnaBridge 126:abea610beb85 1686
AnnaBridge 126:abea610beb85 1687 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 1688 \return Interrupt Priority. Value is aligned automatically to the implemented
AnnaBridge 126:abea610beb85 1689 priority bits of the microcontroller.
AnnaBridge 126:abea610beb85 1690 */
AnnaBridge 126:abea610beb85 1691 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1692 {
AnnaBridge 126:abea610beb85 1693
AnnaBridge 126:abea610beb85 1694 if((int32_t)IRQn < 0) {
AnnaBridge 126:abea610beb85 1695 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 126:abea610beb85 1696 }
AnnaBridge 126:abea610beb85 1697 else {
AnnaBridge 126:abea610beb85 1698 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 126:abea610beb85 1699 }
AnnaBridge 126:abea610beb85 1700 }
AnnaBridge 126:abea610beb85 1701
AnnaBridge 126:abea610beb85 1702
AnnaBridge 126:abea610beb85 1703 /** \brief Encode Priority
AnnaBridge 126:abea610beb85 1704
AnnaBridge 126:abea610beb85 1705 The function encodes the priority for an interrupt with the given priority group,
AnnaBridge 126:abea610beb85 1706 preemptive priority value, and subpriority value.
AnnaBridge 126:abea610beb85 1707 In case of a conflict between priority grouping and available
AnnaBridge 126:abea610beb85 1708 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 126:abea610beb85 1709
AnnaBridge 126:abea610beb85 1710 \param [in] PriorityGroup Used priority group.
AnnaBridge 126:abea610beb85 1711 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 126:abea610beb85 1712 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 126:abea610beb85 1713 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 126:abea610beb85 1714 */
AnnaBridge 126:abea610beb85 1715 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 126:abea610beb85 1716 {
AnnaBridge 126:abea610beb85 1717 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 126:abea610beb85 1718 uint32_t PreemptPriorityBits;
AnnaBridge 126:abea610beb85 1719 uint32_t SubPriorityBits;
AnnaBridge 126:abea610beb85 1720
AnnaBridge 126:abea610beb85 1721 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 126:abea610beb85 1722 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 126:abea610beb85 1723
AnnaBridge 126:abea610beb85 1724 return (
AnnaBridge 126:abea610beb85 1725 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 126:abea610beb85 1726 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 126:abea610beb85 1727 );
AnnaBridge 126:abea610beb85 1728 }
AnnaBridge 126:abea610beb85 1729
AnnaBridge 126:abea610beb85 1730
AnnaBridge 126:abea610beb85 1731 /** \brief Decode Priority
AnnaBridge 126:abea610beb85 1732
AnnaBridge 126:abea610beb85 1733 The function decodes an interrupt priority value with a given priority group to
AnnaBridge 126:abea610beb85 1734 preemptive priority value and subpriority value.
AnnaBridge 126:abea610beb85 1735 In case of a conflict between priority grouping and available
AnnaBridge 126:abea610beb85 1736 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 126:abea610beb85 1737
AnnaBridge 126:abea610beb85 1738 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 126:abea610beb85 1739 \param [in] PriorityGroup Used priority group.
AnnaBridge 126:abea610beb85 1740 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 126:abea610beb85 1741 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 126:abea610beb85 1742 */
AnnaBridge 126:abea610beb85 1743 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
AnnaBridge 126:abea610beb85 1744 {
AnnaBridge 126:abea610beb85 1745 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 126:abea610beb85 1746 uint32_t PreemptPriorityBits;
AnnaBridge 126:abea610beb85 1747 uint32_t SubPriorityBits;
AnnaBridge 126:abea610beb85 1748
AnnaBridge 126:abea610beb85 1749 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 126:abea610beb85 1750 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 126:abea610beb85 1751
AnnaBridge 126:abea610beb85 1752 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 126:abea610beb85 1753 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 126:abea610beb85 1754 }
AnnaBridge 126:abea610beb85 1755
AnnaBridge 126:abea610beb85 1756
AnnaBridge 126:abea610beb85 1757 /** \brief System Reset
AnnaBridge 126:abea610beb85 1758
AnnaBridge 126:abea610beb85 1759 The function initiates a system reset request to reset the MCU.
AnnaBridge 126:abea610beb85 1760 */
<> 128:9bcdf88f62b0 1761 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 126:abea610beb85 1762 {
AnnaBridge 126:abea610beb85 1763 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 126:abea610beb85 1764 buffered write are completed before reset */
AnnaBridge 126:abea610beb85 1765 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 126:abea610beb85 1766 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
AnnaBridge 126:abea610beb85 1767 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge 126:abea610beb85 1768 __DSB(); /* Ensure completion of memory access */
AnnaBridge 126:abea610beb85 1769 while(1) { __NOP(); } /* wait until reset */
AnnaBridge 126:abea610beb85 1770 }
AnnaBridge 126:abea610beb85 1771
AnnaBridge 126:abea610beb85 1772 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 126:abea610beb85 1773
AnnaBridge 126:abea610beb85 1774
AnnaBridge 126:abea610beb85 1775
AnnaBridge 126:abea610beb85 1776 /* ################################## SysTick function ############################################ */
AnnaBridge 126:abea610beb85 1777 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 1778 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 126:abea610beb85 1779 \brief Functions that configure the System.
AnnaBridge 126:abea610beb85 1780 @{
AnnaBridge 126:abea610beb85 1781 */
AnnaBridge 126:abea610beb85 1782
AnnaBridge 126:abea610beb85 1783 #if (__Vendor_SysTickConfig == 0)
AnnaBridge 126:abea610beb85 1784
AnnaBridge 126:abea610beb85 1785 /** \brief System Tick Configuration
AnnaBridge 126:abea610beb85 1786
AnnaBridge 126:abea610beb85 1787 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 126:abea610beb85 1788 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 126:abea610beb85 1789
AnnaBridge 126:abea610beb85 1790 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 126:abea610beb85 1791
AnnaBridge 126:abea610beb85 1792 \return 0 Function succeeded.
AnnaBridge 126:abea610beb85 1793 \return 1 Function failed.
AnnaBridge 126:abea610beb85 1794
AnnaBridge 126:abea610beb85 1795 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 126:abea610beb85 1796 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 126:abea610beb85 1797 must contain a vendor-specific implementation of this function.
AnnaBridge 126:abea610beb85 1798
AnnaBridge 126:abea610beb85 1799 */
AnnaBridge 126:abea610beb85 1800 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 126:abea610beb85 1801 {
AnnaBridge 126:abea610beb85 1802 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
AnnaBridge 126:abea610beb85 1803
AnnaBridge 126:abea610beb85 1804 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 126:abea610beb85 1805 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 126:abea610beb85 1806 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 126:abea610beb85 1807 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 126:abea610beb85 1808 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 126:abea610beb85 1809 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 126:abea610beb85 1810 return (0UL); /* Function successful */
AnnaBridge 126:abea610beb85 1811 }
AnnaBridge 126:abea610beb85 1812
AnnaBridge 126:abea610beb85 1813 #endif
AnnaBridge 126:abea610beb85 1814
AnnaBridge 126:abea610beb85 1815 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 126:abea610beb85 1816
AnnaBridge 126:abea610beb85 1817
AnnaBridge 126:abea610beb85 1818
AnnaBridge 126:abea610beb85 1819 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 126:abea610beb85 1820 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 1821 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 126:abea610beb85 1822 \brief Functions that access the ITM debug interface.
AnnaBridge 126:abea610beb85 1823 @{
AnnaBridge 126:abea610beb85 1824 */
AnnaBridge 126:abea610beb85 1825
AnnaBridge 126:abea610beb85 1826 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 126:abea610beb85 1827 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
AnnaBridge 126:abea610beb85 1828
AnnaBridge 126:abea610beb85 1829
AnnaBridge 126:abea610beb85 1830 /** \brief ITM Send Character
AnnaBridge 126:abea610beb85 1831
AnnaBridge 126:abea610beb85 1832 The function transmits a character via the ITM channel 0, and
AnnaBridge 126:abea610beb85 1833 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 126:abea610beb85 1834 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 126:abea610beb85 1835
AnnaBridge 126:abea610beb85 1836 \param [in] ch Character to transmit.
AnnaBridge 126:abea610beb85 1837
AnnaBridge 126:abea610beb85 1838 \returns Character to transmit.
AnnaBridge 126:abea610beb85 1839 */
AnnaBridge 126:abea610beb85 1840 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge 126:abea610beb85 1841 {
AnnaBridge 126:abea610beb85 1842 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge 126:abea610beb85 1843 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge 126:abea610beb85 1844 {
AnnaBridge 126:abea610beb85 1845 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
AnnaBridge 126:abea610beb85 1846 ITM->PORT[0].u8 = (uint8_t)ch;
AnnaBridge 126:abea610beb85 1847 }
AnnaBridge 126:abea610beb85 1848 return (ch);
AnnaBridge 126:abea610beb85 1849 }
AnnaBridge 126:abea610beb85 1850
AnnaBridge 126:abea610beb85 1851
AnnaBridge 126:abea610beb85 1852 /** \brief ITM Receive Character
AnnaBridge 126:abea610beb85 1853
AnnaBridge 126:abea610beb85 1854 The function inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 126:abea610beb85 1855
AnnaBridge 126:abea610beb85 1856 \return Received character.
AnnaBridge 126:abea610beb85 1857 \return -1 No character pending.
AnnaBridge 126:abea610beb85 1858 */
AnnaBridge 126:abea610beb85 1859 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
AnnaBridge 126:abea610beb85 1860 int32_t ch = -1; /* no character available */
AnnaBridge 126:abea610beb85 1861
AnnaBridge 126:abea610beb85 1862 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
AnnaBridge 126:abea610beb85 1863 ch = ITM_RxBuffer;
AnnaBridge 126:abea610beb85 1864 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge 126:abea610beb85 1865 }
AnnaBridge 126:abea610beb85 1866
AnnaBridge 126:abea610beb85 1867 return (ch);
AnnaBridge 126:abea610beb85 1868 }
AnnaBridge 126:abea610beb85 1869
AnnaBridge 126:abea610beb85 1870
AnnaBridge 126:abea610beb85 1871 /** \brief ITM Check Character
AnnaBridge 126:abea610beb85 1872
AnnaBridge 126:abea610beb85 1873 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 126:abea610beb85 1874
AnnaBridge 126:abea610beb85 1875 \return 0 No character available.
AnnaBridge 126:abea610beb85 1876 \return 1 Character available.
AnnaBridge 126:abea610beb85 1877 */
AnnaBridge 126:abea610beb85 1878 __STATIC_INLINE int32_t ITM_CheckChar (void) {
AnnaBridge 126:abea610beb85 1879
AnnaBridge 126:abea610beb85 1880 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
AnnaBridge 126:abea610beb85 1881 return (0); /* no character available */
AnnaBridge 126:abea610beb85 1882 } else {
AnnaBridge 126:abea610beb85 1883 return (1); /* character available */
AnnaBridge 126:abea610beb85 1884 }
AnnaBridge 126:abea610beb85 1885 }
AnnaBridge 126:abea610beb85 1886
AnnaBridge 126:abea610beb85 1887 /*@} end of CMSIS_core_DebugFunctions */
AnnaBridge 126:abea610beb85 1888
AnnaBridge 126:abea610beb85 1889
AnnaBridge 126:abea610beb85 1890
AnnaBridge 126:abea610beb85 1891
AnnaBridge 126:abea610beb85 1892 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 1893 }
AnnaBridge 126:abea610beb85 1894 #endif
AnnaBridge 126:abea610beb85 1895
AnnaBridge 126:abea610beb85 1896 #endif /* __CORE_CM4_H_DEPENDANT */
AnnaBridge 126:abea610beb85 1897
AnnaBridge 126:abea610beb85 1898 #endif /* __CMSIS_GENERIC */