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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MTM_MTCONNECT04S/core_cm3.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**************************************************************************//**
AnnaBridge 126:abea610beb85 2 * @file core_cm3.h
AnnaBridge 126:abea610beb85 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
AnnaBridge 126:abea610beb85 4 * @version V4.10
AnnaBridge 126:abea610beb85 5 * @date 18. March 2015
AnnaBridge 126:abea610beb85 6 *
AnnaBridge 126:abea610beb85 7 * @note
AnnaBridge 126:abea610beb85 8 *
AnnaBridge 126:abea610beb85 9 ******************************************************************************/
AnnaBridge 126:abea610beb85 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
AnnaBridge 126:abea610beb85 11
AnnaBridge 126:abea610beb85 12 All rights reserved.
AnnaBridge 126:abea610beb85 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 126:abea610beb85 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 - Redistributions of source code must retain the above copyright
AnnaBridge 126:abea610beb85 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 126:abea610beb85 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 126:abea610beb85 19 documentation and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 126:abea610beb85 21 to endorse or promote products derived from this software without
AnnaBridge 126:abea610beb85 22 specific prior written permission.
AnnaBridge 126:abea610beb85 23 *
AnnaBridge 126:abea610beb85 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 126:abea610beb85 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 126:abea610beb85 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 126:abea610beb85 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 126:abea610beb85 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 126:abea610beb85 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 126:abea610beb85 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 126:abea610beb85 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 126:abea610beb85 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 35 ---------------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 36
AnnaBridge 126:abea610beb85 37
AnnaBridge 126:abea610beb85 38 #if defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 39 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 126:abea610beb85 40 #endif
AnnaBridge 126:abea610beb85 41
AnnaBridge 126:abea610beb85 42 #ifndef __CORE_CM3_H_GENERIC
AnnaBridge 126:abea610beb85 43 #define __CORE_CM3_H_GENERIC
AnnaBridge 126:abea610beb85 44
AnnaBridge 126:abea610beb85 45 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 46 extern "C" {
AnnaBridge 126:abea610beb85 47 #endif
AnnaBridge 126:abea610beb85 48
AnnaBridge 126:abea610beb85 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 126:abea610beb85 50 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 126:abea610beb85 51
AnnaBridge 126:abea610beb85 52 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 126:abea610beb85 53 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 126:abea610beb85 54
AnnaBridge 126:abea610beb85 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 126:abea610beb85 56 Unions are used for effective representation of core registers.
AnnaBridge 126:abea610beb85 57
AnnaBridge 126:abea610beb85 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 126:abea610beb85 59 Function-like macros are used to allow more efficient code.
AnnaBridge 126:abea610beb85 60 */
AnnaBridge 126:abea610beb85 61
AnnaBridge 126:abea610beb85 62
AnnaBridge 126:abea610beb85 63 /*******************************************************************************
AnnaBridge 126:abea610beb85 64 * CMSIS definitions
AnnaBridge 126:abea610beb85 65 ******************************************************************************/
AnnaBridge 126:abea610beb85 66 /** \ingroup Cortex_M3
AnnaBridge 126:abea610beb85 67 @{
AnnaBridge 126:abea610beb85 68 */
AnnaBridge 126:abea610beb85 69
AnnaBridge 126:abea610beb85 70 /* CMSIS CM3 definitions */
AnnaBridge 126:abea610beb85 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 126:abea610beb85 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 126:abea610beb85 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
AnnaBridge 126:abea610beb85 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
AnnaBridge 126:abea610beb85 75
AnnaBridge 126:abea610beb85 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
AnnaBridge 126:abea610beb85 77
AnnaBridge 126:abea610beb85 78
AnnaBridge 126:abea610beb85 79 #if defined ( __CC_ARM )
AnnaBridge 126:abea610beb85 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
AnnaBridge 126:abea610beb85 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
AnnaBridge 126:abea610beb85 82 #define __STATIC_INLINE static __inline
AnnaBridge 126:abea610beb85 83
AnnaBridge 126:abea610beb85 84 #elif defined ( __GNUC__ )
AnnaBridge 126:abea610beb85 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
AnnaBridge 126:abea610beb85 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
AnnaBridge 126:abea610beb85 87 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 88
AnnaBridge 126:abea610beb85 89 #elif defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
AnnaBridge 126:abea610beb85 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
AnnaBridge 126:abea610beb85 92 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 93
AnnaBridge 126:abea610beb85 94 #elif defined ( __TMS470__ )
AnnaBridge 126:abea610beb85 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
AnnaBridge 126:abea610beb85 96 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 97
AnnaBridge 126:abea610beb85 98 #elif defined ( __TASKING__ )
AnnaBridge 126:abea610beb85 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
AnnaBridge 126:abea610beb85 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
AnnaBridge 126:abea610beb85 101 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 102
AnnaBridge 126:abea610beb85 103 #elif defined ( __CSMC__ )
AnnaBridge 126:abea610beb85 104 #define __packed
AnnaBridge 126:abea610beb85 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
AnnaBridge 126:abea610beb85 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
AnnaBridge 126:abea610beb85 107 #define __STATIC_INLINE static inline
AnnaBridge 126:abea610beb85 108
AnnaBridge 126:abea610beb85 109 #endif
AnnaBridge 126:abea610beb85 110
AnnaBridge 126:abea610beb85 111 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 126:abea610beb85 112 This core does not support an FPU at all
AnnaBridge 126:abea610beb85 113 */
AnnaBridge 126:abea610beb85 114 #define __FPU_USED 0
AnnaBridge 126:abea610beb85 115
AnnaBridge 126:abea610beb85 116 #if defined ( __CC_ARM )
AnnaBridge 126:abea610beb85 117 #if defined __TARGET_FPU_VFP
AnnaBridge 126:abea610beb85 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 119 #endif
AnnaBridge 126:abea610beb85 120
AnnaBridge 126:abea610beb85 121 #elif defined ( __GNUC__ )
AnnaBridge 126:abea610beb85 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 126:abea610beb85 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 124 #endif
AnnaBridge 126:abea610beb85 125
AnnaBridge 126:abea610beb85 126 #elif defined ( __ICCARM__ )
AnnaBridge 126:abea610beb85 127 #if defined __ARMVFP__
AnnaBridge 126:abea610beb85 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 129 #endif
AnnaBridge 126:abea610beb85 130
AnnaBridge 126:abea610beb85 131 #elif defined ( __TMS470__ )
AnnaBridge 126:abea610beb85 132 #if defined __TI__VFP_SUPPORT____
AnnaBridge 126:abea610beb85 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 134 #endif
AnnaBridge 126:abea610beb85 135
AnnaBridge 126:abea610beb85 136 #elif defined ( __TASKING__ )
AnnaBridge 126:abea610beb85 137 #if defined __FPU_VFP__
AnnaBridge 126:abea610beb85 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 139 #endif
AnnaBridge 126:abea610beb85 140
AnnaBridge 126:abea610beb85 141 #elif defined ( __CSMC__ ) /* Cosmic */
AnnaBridge 126:abea610beb85 142 #if ( __CSMC__ & 0x400) // FPU present for parser
AnnaBridge 126:abea610beb85 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 126:abea610beb85 144 #endif
AnnaBridge 126:abea610beb85 145 #endif
AnnaBridge 126:abea610beb85 146
AnnaBridge 126:abea610beb85 147 #include <stdint.h> /* standard types definitions */
AnnaBridge 126:abea610beb85 148 #include <core_cmInstr.h> /* Core Instruction Access */
AnnaBridge 126:abea610beb85 149 #include <core_cmFunc.h> /* Core Function Access */
AnnaBridge 126:abea610beb85 150
AnnaBridge 126:abea610beb85 151 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 152 }
AnnaBridge 126:abea610beb85 153 #endif
AnnaBridge 126:abea610beb85 154
AnnaBridge 126:abea610beb85 155 #endif /* __CORE_CM3_H_GENERIC */
AnnaBridge 126:abea610beb85 156
AnnaBridge 126:abea610beb85 157 #ifndef __CMSIS_GENERIC
AnnaBridge 126:abea610beb85 158
AnnaBridge 126:abea610beb85 159 #ifndef __CORE_CM3_H_DEPENDANT
AnnaBridge 126:abea610beb85 160 #define __CORE_CM3_H_DEPENDANT
AnnaBridge 126:abea610beb85 161
AnnaBridge 126:abea610beb85 162 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 163 extern "C" {
AnnaBridge 126:abea610beb85 164 #endif
AnnaBridge 126:abea610beb85 165
AnnaBridge 126:abea610beb85 166 /* check device defines and use defaults */
AnnaBridge 126:abea610beb85 167 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 126:abea610beb85 168 #ifndef __CM3_REV
AnnaBridge 126:abea610beb85 169 #define __CM3_REV 0x0200
AnnaBridge 126:abea610beb85 170 #warning "__CM3_REV not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 171 #endif
AnnaBridge 126:abea610beb85 172
AnnaBridge 126:abea610beb85 173 #ifndef __MPU_PRESENT
AnnaBridge 126:abea610beb85 174 #define __MPU_PRESENT 0
AnnaBridge 126:abea610beb85 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 176 #endif
AnnaBridge 126:abea610beb85 177
AnnaBridge 126:abea610beb85 178 #ifndef __NVIC_PRIO_BITS
AnnaBridge 126:abea610beb85 179 #define __NVIC_PRIO_BITS 4
AnnaBridge 126:abea610beb85 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 181 #endif
AnnaBridge 126:abea610beb85 182
AnnaBridge 126:abea610beb85 183 #ifndef __Vendor_SysTickConfig
AnnaBridge 126:abea610beb85 184 #define __Vendor_SysTickConfig 0
AnnaBridge 126:abea610beb85 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 126:abea610beb85 186 #endif
AnnaBridge 126:abea610beb85 187 #endif
AnnaBridge 126:abea610beb85 188
AnnaBridge 126:abea610beb85 189 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 126:abea610beb85 190 /**
AnnaBridge 126:abea610beb85 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 126:abea610beb85 192
AnnaBridge 126:abea610beb85 193 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 126:abea610beb85 194 \li to specify the access to peripheral variables.
AnnaBridge 126:abea610beb85 195 \li for automatic generation of peripheral register debug information.
AnnaBridge 126:abea610beb85 196 */
AnnaBridge 126:abea610beb85 197 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 198 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 126:abea610beb85 199 #else
AnnaBridge 126:abea610beb85 200 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 126:abea610beb85 201 #endif
AnnaBridge 126:abea610beb85 202 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 126:abea610beb85 203 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 126:abea610beb85 204
<> 128:9bcdf88f62b0 205 #ifdef __cplusplus
<> 128:9bcdf88f62b0 206 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 207 #else
<> 128:9bcdf88f62b0 208 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 209 #endif
<> 128:9bcdf88f62b0 210 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 211 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 212
AnnaBridge 126:abea610beb85 213 /*@} end of group Cortex_M3 */
AnnaBridge 126:abea610beb85 214
AnnaBridge 126:abea610beb85 215
AnnaBridge 126:abea610beb85 216
AnnaBridge 126:abea610beb85 217 /*******************************************************************************
AnnaBridge 126:abea610beb85 218 * Register Abstraction
AnnaBridge 126:abea610beb85 219 Core Register contain:
AnnaBridge 126:abea610beb85 220 - Core Register
AnnaBridge 126:abea610beb85 221 - Core NVIC Register
AnnaBridge 126:abea610beb85 222 - Core SCB Register
AnnaBridge 126:abea610beb85 223 - Core SysTick Register
AnnaBridge 126:abea610beb85 224 - Core Debug Register
AnnaBridge 126:abea610beb85 225 - Core MPU Register
AnnaBridge 126:abea610beb85 226 ******************************************************************************/
AnnaBridge 126:abea610beb85 227 /** \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 126:abea610beb85 228 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 126:abea610beb85 229 */
AnnaBridge 126:abea610beb85 230
AnnaBridge 126:abea610beb85 231 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 232 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 126:abea610beb85 233 \brief Core Register type definitions.
AnnaBridge 126:abea610beb85 234 @{
AnnaBridge 126:abea610beb85 235 */
AnnaBridge 126:abea610beb85 236
AnnaBridge 126:abea610beb85 237 /** \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 126:abea610beb85 238 */
AnnaBridge 126:abea610beb85 239 typedef union
AnnaBridge 126:abea610beb85 240 {
AnnaBridge 126:abea610beb85 241 struct
AnnaBridge 126:abea610beb85 242 {
AnnaBridge 126:abea610beb85 243 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
AnnaBridge 126:abea610beb85 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 126:abea610beb85 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 126:abea610beb85 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 126:abea610beb85 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 126:abea610beb85 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 126:abea610beb85 249 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 250 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 251 } APSR_Type;
AnnaBridge 126:abea610beb85 252
AnnaBridge 126:abea610beb85 253 /* APSR Register Definitions */
AnnaBridge 126:abea610beb85 254 #define APSR_N_Pos 31 /*!< APSR: N Position */
AnnaBridge 126:abea610beb85 255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 126:abea610beb85 256
AnnaBridge 126:abea610beb85 257 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
AnnaBridge 126:abea610beb85 258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 126:abea610beb85 259
AnnaBridge 126:abea610beb85 260 #define APSR_C_Pos 29 /*!< APSR: C Position */
AnnaBridge 126:abea610beb85 261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 126:abea610beb85 262
AnnaBridge 126:abea610beb85 263 #define APSR_V_Pos 28 /*!< APSR: V Position */
AnnaBridge 126:abea610beb85 264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 126:abea610beb85 265
AnnaBridge 126:abea610beb85 266 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
AnnaBridge 126:abea610beb85 267 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
AnnaBridge 126:abea610beb85 268
AnnaBridge 126:abea610beb85 269
AnnaBridge 126:abea610beb85 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 126:abea610beb85 271 */
AnnaBridge 126:abea610beb85 272 typedef union
AnnaBridge 126:abea610beb85 273 {
AnnaBridge 126:abea610beb85 274 struct
AnnaBridge 126:abea610beb85 275 {
AnnaBridge 126:abea610beb85 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 126:abea610beb85 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 126:abea610beb85 278 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 279 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 280 } IPSR_Type;
AnnaBridge 126:abea610beb85 281
AnnaBridge 126:abea610beb85 282 /* IPSR Register Definitions */
AnnaBridge 126:abea610beb85 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
AnnaBridge 126:abea610beb85 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 126:abea610beb85 285
AnnaBridge 126:abea610beb85 286
AnnaBridge 126:abea610beb85 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 126:abea610beb85 288 */
AnnaBridge 126:abea610beb85 289 typedef union
AnnaBridge 126:abea610beb85 290 {
AnnaBridge 126:abea610beb85 291 struct
AnnaBridge 126:abea610beb85 292 {
AnnaBridge 126:abea610beb85 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 126:abea610beb85 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 126:abea610beb85 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 126:abea610beb85 296 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
AnnaBridge 126:abea610beb85 297 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 126:abea610beb85 298 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 126:abea610beb85 299 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 126:abea610beb85 300 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 126:abea610beb85 301 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 126:abea610beb85 302 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 303 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 304 } xPSR_Type;
AnnaBridge 126:abea610beb85 305
AnnaBridge 126:abea610beb85 306 /* xPSR Register Definitions */
AnnaBridge 126:abea610beb85 307 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
AnnaBridge 126:abea610beb85 308 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 126:abea610beb85 309
AnnaBridge 126:abea610beb85 310 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
AnnaBridge 126:abea610beb85 311 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 126:abea610beb85 312
AnnaBridge 126:abea610beb85 313 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
AnnaBridge 126:abea610beb85 314 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 126:abea610beb85 315
AnnaBridge 126:abea610beb85 316 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
AnnaBridge 126:abea610beb85 317 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 126:abea610beb85 318
AnnaBridge 126:abea610beb85 319 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
AnnaBridge 126:abea610beb85 320 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
AnnaBridge 126:abea610beb85 321
AnnaBridge 126:abea610beb85 322 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
AnnaBridge 126:abea610beb85 323 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
AnnaBridge 126:abea610beb85 324
AnnaBridge 126:abea610beb85 325 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
AnnaBridge 126:abea610beb85 326 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 126:abea610beb85 327
AnnaBridge 126:abea610beb85 328 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
AnnaBridge 126:abea610beb85 329 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 126:abea610beb85 330
AnnaBridge 126:abea610beb85 331
AnnaBridge 126:abea610beb85 332 /** \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 126:abea610beb85 333 */
AnnaBridge 126:abea610beb85 334 typedef union
AnnaBridge 126:abea610beb85 335 {
AnnaBridge 126:abea610beb85 336 struct
AnnaBridge 126:abea610beb85 337 {
AnnaBridge 126:abea610beb85 338 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 126:abea610beb85 339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 126:abea610beb85 340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 126:abea610beb85 341 } b; /*!< Structure used for bit access */
AnnaBridge 126:abea610beb85 342 uint32_t w; /*!< Type used for word access */
AnnaBridge 126:abea610beb85 343 } CONTROL_Type;
AnnaBridge 126:abea610beb85 344
AnnaBridge 126:abea610beb85 345 /* CONTROL Register Definitions */
AnnaBridge 126:abea610beb85 346 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
AnnaBridge 126:abea610beb85 347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 126:abea610beb85 348
AnnaBridge 126:abea610beb85 349 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
AnnaBridge 126:abea610beb85 350 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 126:abea610beb85 351
AnnaBridge 126:abea610beb85 352 /*@} end of group CMSIS_CORE */
AnnaBridge 126:abea610beb85 353
AnnaBridge 126:abea610beb85 354
AnnaBridge 126:abea610beb85 355 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 126:abea610beb85 357 \brief Type definitions for the NVIC Registers
AnnaBridge 126:abea610beb85 358 @{
AnnaBridge 126:abea610beb85 359 */
AnnaBridge 126:abea610beb85 360
AnnaBridge 126:abea610beb85 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 126:abea610beb85 362 */
AnnaBridge 126:abea610beb85 363 typedef struct
AnnaBridge 126:abea610beb85 364 {
AnnaBridge 126:abea610beb85 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 126:abea610beb85 366 uint32_t RESERVED0[24];
AnnaBridge 126:abea610beb85 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 126:abea610beb85 368 uint32_t RSERVED1[24];
AnnaBridge 126:abea610beb85 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 126:abea610beb85 370 uint32_t RESERVED2[24];
AnnaBridge 126:abea610beb85 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 126:abea610beb85 372 uint32_t RESERVED3[24];
AnnaBridge 126:abea610beb85 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 126:abea610beb85 374 uint32_t RESERVED4[56];
AnnaBridge 126:abea610beb85 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 126:abea610beb85 376 uint32_t RESERVED5[644];
AnnaBridge 126:abea610beb85 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
AnnaBridge 126:abea610beb85 378 } NVIC_Type;
AnnaBridge 126:abea610beb85 379
AnnaBridge 126:abea610beb85 380 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 126:abea610beb85 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
AnnaBridge 126:abea610beb85 382 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
AnnaBridge 126:abea610beb85 383
AnnaBridge 126:abea610beb85 384 /*@} end of group CMSIS_NVIC */
AnnaBridge 126:abea610beb85 385
AnnaBridge 126:abea610beb85 386
AnnaBridge 126:abea610beb85 387 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 388 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 126:abea610beb85 389 \brief Type definitions for the System Control Block Registers
AnnaBridge 126:abea610beb85 390 @{
AnnaBridge 126:abea610beb85 391 */
AnnaBridge 126:abea610beb85 392
AnnaBridge 126:abea610beb85 393 /** \brief Structure type to access the System Control Block (SCB).
AnnaBridge 126:abea610beb85 394 */
AnnaBridge 126:abea610beb85 395 typedef struct
AnnaBridge 126:abea610beb85 396 {
AnnaBridge 126:abea610beb85 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 126:abea610beb85 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 126:abea610beb85 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 126:abea610beb85 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 126:abea610beb85 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 126:abea610beb85 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 126:abea610beb85 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 126:abea610beb85 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 126:abea610beb85 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 126:abea610beb85 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 126:abea610beb85 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 126:abea610beb85 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 126:abea610beb85 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 126:abea610beb85 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 126:abea610beb85 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 126:abea610beb85 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 126:abea610beb85 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 126:abea610beb85 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 126:abea610beb85 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 126:abea610beb85 416 uint32_t RESERVED0[5];
AnnaBridge 126:abea610beb85 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
AnnaBridge 126:abea610beb85 418 } SCB_Type;
AnnaBridge 126:abea610beb85 419
AnnaBridge 126:abea610beb85 420 /* SCB CPUID Register Definitions */
AnnaBridge 126:abea610beb85 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 126:abea610beb85 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 126:abea610beb85 423
AnnaBridge 126:abea610beb85 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
AnnaBridge 126:abea610beb85 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 126:abea610beb85 426
AnnaBridge 126:abea610beb85 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 126:abea610beb85 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 126:abea610beb85 429
AnnaBridge 126:abea610beb85 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
AnnaBridge 126:abea610beb85 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 126:abea610beb85 432
AnnaBridge 126:abea610beb85 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
AnnaBridge 126:abea610beb85 434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 126:abea610beb85 435
AnnaBridge 126:abea610beb85 436 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 126:abea610beb85 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 126:abea610beb85 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 126:abea610beb85 439
AnnaBridge 126:abea610beb85 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 126:abea610beb85 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 126:abea610beb85 442
AnnaBridge 126:abea610beb85 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 126:abea610beb85 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 126:abea610beb85 445
AnnaBridge 126:abea610beb85 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 126:abea610beb85 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 126:abea610beb85 448
AnnaBridge 126:abea610beb85 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 126:abea610beb85 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 126:abea610beb85 451
AnnaBridge 126:abea610beb85 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 126:abea610beb85 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 126:abea610beb85 454
AnnaBridge 126:abea610beb85 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 126:abea610beb85 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 126:abea610beb85 457
AnnaBridge 126:abea610beb85 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 126:abea610beb85 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 126:abea610beb85 460
AnnaBridge 126:abea610beb85 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 126:abea610beb85 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 126:abea610beb85 463
AnnaBridge 126:abea610beb85 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 126:abea610beb85 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 126:abea610beb85 466
AnnaBridge 126:abea610beb85 467 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 126:abea610beb85 468 #if (__CM3_REV < 0x0201) /* core r2p1 */
AnnaBridge 126:abea610beb85 469 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
AnnaBridge 126:abea610beb85 470 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
AnnaBridge 126:abea610beb85 471
AnnaBridge 126:abea610beb85 472 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 126:abea610beb85 473 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 126:abea610beb85 474 #else
AnnaBridge 126:abea610beb85 475 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 126:abea610beb85 476 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 126:abea610beb85 477 #endif
AnnaBridge 126:abea610beb85 478
AnnaBridge 126:abea610beb85 479 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 126:abea610beb85 480 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 126:abea610beb85 481 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 126:abea610beb85 482
AnnaBridge 126:abea610beb85 483 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 126:abea610beb85 484 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 126:abea610beb85 485
AnnaBridge 126:abea610beb85 486 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 126:abea610beb85 487 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 126:abea610beb85 488
AnnaBridge 126:abea610beb85 489 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
AnnaBridge 126:abea610beb85 490 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
AnnaBridge 126:abea610beb85 491
AnnaBridge 126:abea610beb85 492 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 126:abea610beb85 493 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 126:abea610beb85 494
AnnaBridge 126:abea610beb85 495 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 126:abea610beb85 496 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 126:abea610beb85 497
AnnaBridge 126:abea610beb85 498 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
AnnaBridge 126:abea610beb85 499 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
AnnaBridge 126:abea610beb85 500
AnnaBridge 126:abea610beb85 501 /* SCB System Control Register Definitions */
AnnaBridge 126:abea610beb85 502 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 126:abea610beb85 503 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 126:abea610beb85 504
AnnaBridge 126:abea610beb85 505 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 126:abea610beb85 506 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 126:abea610beb85 507
AnnaBridge 126:abea610beb85 508 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 126:abea610beb85 509 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 126:abea610beb85 510
AnnaBridge 126:abea610beb85 511 /* SCB Configuration Control Register Definitions */
AnnaBridge 126:abea610beb85 512 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
AnnaBridge 126:abea610beb85 513 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 126:abea610beb85 514
AnnaBridge 126:abea610beb85 515 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 126:abea610beb85 516 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 126:abea610beb85 517
AnnaBridge 126:abea610beb85 518 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 126:abea610beb85 519 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 126:abea610beb85 520
AnnaBridge 126:abea610beb85 521 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 126:abea610beb85 522 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 126:abea610beb85 523
AnnaBridge 126:abea610beb85 524 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 126:abea610beb85 525 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 126:abea610beb85 526
AnnaBridge 126:abea610beb85 527 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
AnnaBridge 126:abea610beb85 528 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
AnnaBridge 126:abea610beb85 529
AnnaBridge 126:abea610beb85 530 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 126:abea610beb85 531 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
AnnaBridge 126:abea610beb85 532 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
AnnaBridge 126:abea610beb85 533
AnnaBridge 126:abea610beb85 534 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
AnnaBridge 126:abea610beb85 535 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
AnnaBridge 126:abea610beb85 536
AnnaBridge 126:abea610beb85 537 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
AnnaBridge 126:abea610beb85 538 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
AnnaBridge 126:abea610beb85 539
AnnaBridge 126:abea610beb85 540 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 126:abea610beb85 541 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 126:abea610beb85 542
AnnaBridge 126:abea610beb85 543 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
AnnaBridge 126:abea610beb85 544 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
AnnaBridge 126:abea610beb85 545
AnnaBridge 126:abea610beb85 546 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
AnnaBridge 126:abea610beb85 547 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
AnnaBridge 126:abea610beb85 548
AnnaBridge 126:abea610beb85 549 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
AnnaBridge 126:abea610beb85 550 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
AnnaBridge 126:abea610beb85 551
AnnaBridge 126:abea610beb85 552 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 126:abea610beb85 553 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 126:abea610beb85 554
AnnaBridge 126:abea610beb85 555 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 126:abea610beb85 556 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 126:abea610beb85 557
AnnaBridge 126:abea610beb85 558 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
AnnaBridge 126:abea610beb85 559 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
AnnaBridge 126:abea610beb85 560
AnnaBridge 126:abea610beb85 561 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 126:abea610beb85 562 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 126:abea610beb85 563
AnnaBridge 126:abea610beb85 564 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
AnnaBridge 126:abea610beb85 565 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
AnnaBridge 126:abea610beb85 566
AnnaBridge 126:abea610beb85 567 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
AnnaBridge 126:abea610beb85 568 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
AnnaBridge 126:abea610beb85 569
AnnaBridge 126:abea610beb85 570 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
AnnaBridge 126:abea610beb85 571 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
AnnaBridge 126:abea610beb85 572
AnnaBridge 126:abea610beb85 573 /* SCB Configurable Fault Status Registers Definitions */
AnnaBridge 126:abea610beb85 574 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
AnnaBridge 126:abea610beb85 575 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
AnnaBridge 126:abea610beb85 576
AnnaBridge 126:abea610beb85 577 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
AnnaBridge 126:abea610beb85 578 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
AnnaBridge 126:abea610beb85 579
AnnaBridge 126:abea610beb85 580 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
AnnaBridge 126:abea610beb85 581 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
AnnaBridge 126:abea610beb85 582
AnnaBridge 126:abea610beb85 583 /* SCB Hard Fault Status Registers Definitions */
AnnaBridge 126:abea610beb85 584 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
AnnaBridge 126:abea610beb85 585 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
AnnaBridge 126:abea610beb85 586
AnnaBridge 126:abea610beb85 587 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
AnnaBridge 126:abea610beb85 588 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
AnnaBridge 126:abea610beb85 589
AnnaBridge 126:abea610beb85 590 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
AnnaBridge 126:abea610beb85 591 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
AnnaBridge 126:abea610beb85 592
AnnaBridge 126:abea610beb85 593 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 126:abea610beb85 594 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
AnnaBridge 126:abea610beb85 595 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
AnnaBridge 126:abea610beb85 596
AnnaBridge 126:abea610beb85 597 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
AnnaBridge 126:abea610beb85 598 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
AnnaBridge 126:abea610beb85 599
AnnaBridge 126:abea610beb85 600 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
AnnaBridge 126:abea610beb85 601 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
AnnaBridge 126:abea610beb85 602
AnnaBridge 126:abea610beb85 603 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
AnnaBridge 126:abea610beb85 604 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
AnnaBridge 126:abea610beb85 605
AnnaBridge 126:abea610beb85 606 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
AnnaBridge 126:abea610beb85 607 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
AnnaBridge 126:abea610beb85 608
AnnaBridge 126:abea610beb85 609 /*@} end of group CMSIS_SCB */
AnnaBridge 126:abea610beb85 610
AnnaBridge 126:abea610beb85 611
AnnaBridge 126:abea610beb85 612 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 613 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 126:abea610beb85 614 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 126:abea610beb85 615 @{
AnnaBridge 126:abea610beb85 616 */
AnnaBridge 126:abea610beb85 617
AnnaBridge 126:abea610beb85 618 /** \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 126:abea610beb85 619 */
AnnaBridge 126:abea610beb85 620 typedef struct
AnnaBridge 126:abea610beb85 621 {
AnnaBridge 126:abea610beb85 622 uint32_t RESERVED0[1];
AnnaBridge 126:abea610beb85 623 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 126:abea610beb85 624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
AnnaBridge 126:abea610beb85 625 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
AnnaBridge 126:abea610beb85 626 #else
AnnaBridge 126:abea610beb85 627 uint32_t RESERVED1[1];
AnnaBridge 126:abea610beb85 628 #endif
AnnaBridge 126:abea610beb85 629 } SCnSCB_Type;
AnnaBridge 126:abea610beb85 630
AnnaBridge 126:abea610beb85 631 /* Interrupt Controller Type Register Definitions */
AnnaBridge 126:abea610beb85 632 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
AnnaBridge 126:abea610beb85 633 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
AnnaBridge 126:abea610beb85 634
AnnaBridge 126:abea610beb85 635 /* Auxiliary Control Register Definitions */
AnnaBridge 126:abea610beb85 636
AnnaBridge 126:abea610beb85 637 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
AnnaBridge 126:abea610beb85 638 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
AnnaBridge 126:abea610beb85 639
AnnaBridge 126:abea610beb85 640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
AnnaBridge 126:abea610beb85 641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
AnnaBridge 126:abea610beb85 642
AnnaBridge 126:abea610beb85 643 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
AnnaBridge 126:abea610beb85 644 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
AnnaBridge 126:abea610beb85 645
AnnaBridge 126:abea610beb85 646 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 126:abea610beb85 647
AnnaBridge 126:abea610beb85 648
AnnaBridge 126:abea610beb85 649 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 650 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 126:abea610beb85 651 \brief Type definitions for the System Timer Registers.
AnnaBridge 126:abea610beb85 652 @{
AnnaBridge 126:abea610beb85 653 */
AnnaBridge 126:abea610beb85 654
AnnaBridge 126:abea610beb85 655 /** \brief Structure type to access the System Timer (SysTick).
AnnaBridge 126:abea610beb85 656 */
AnnaBridge 126:abea610beb85 657 typedef struct
AnnaBridge 126:abea610beb85 658 {
AnnaBridge 126:abea610beb85 659 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 126:abea610beb85 660 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 126:abea610beb85 661 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 126:abea610beb85 662 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 126:abea610beb85 663 } SysTick_Type;
AnnaBridge 126:abea610beb85 664
AnnaBridge 126:abea610beb85 665 /* SysTick Control / Status Register Definitions */
AnnaBridge 126:abea610beb85 666 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 126:abea610beb85 667 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 126:abea610beb85 668
AnnaBridge 126:abea610beb85 669 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 126:abea610beb85 670 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 126:abea610beb85 671
AnnaBridge 126:abea610beb85 672 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 126:abea610beb85 673 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 126:abea610beb85 674
AnnaBridge 126:abea610beb85 675 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 126:abea610beb85 676 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 126:abea610beb85 677
AnnaBridge 126:abea610beb85 678 /* SysTick Reload Register Definitions */
AnnaBridge 126:abea610beb85 679 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 126:abea610beb85 680 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 126:abea610beb85 681
AnnaBridge 126:abea610beb85 682 /* SysTick Current Register Definitions */
AnnaBridge 126:abea610beb85 683 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
AnnaBridge 126:abea610beb85 684 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 126:abea610beb85 685
AnnaBridge 126:abea610beb85 686 /* SysTick Calibration Register Definitions */
AnnaBridge 126:abea610beb85 687 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
AnnaBridge 126:abea610beb85 688 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 126:abea610beb85 689
AnnaBridge 126:abea610beb85 690 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
AnnaBridge 126:abea610beb85 691 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 126:abea610beb85 692
AnnaBridge 126:abea610beb85 693 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
AnnaBridge 126:abea610beb85 694 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 126:abea610beb85 695
AnnaBridge 126:abea610beb85 696 /*@} end of group CMSIS_SysTick */
AnnaBridge 126:abea610beb85 697
AnnaBridge 126:abea610beb85 698
AnnaBridge 126:abea610beb85 699 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 700 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 126:abea610beb85 701 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge 126:abea610beb85 702 @{
AnnaBridge 126:abea610beb85 703 */
AnnaBridge 126:abea610beb85 704
AnnaBridge 126:abea610beb85 705 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge 126:abea610beb85 706 */
AnnaBridge 126:abea610beb85 707 typedef struct
AnnaBridge 126:abea610beb85 708 {
AnnaBridge 126:abea610beb85 709 __O union
AnnaBridge 126:abea610beb85 710 {
AnnaBridge 126:abea610beb85 711 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 126:abea610beb85 712 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 126:abea610beb85 713 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 126:abea610beb85 714 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 126:abea610beb85 715 uint32_t RESERVED0[864];
AnnaBridge 126:abea610beb85 716 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 126:abea610beb85 717 uint32_t RESERVED1[15];
AnnaBridge 126:abea610beb85 718 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 126:abea610beb85 719 uint32_t RESERVED2[15];
AnnaBridge 126:abea610beb85 720 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 126:abea610beb85 721 uint32_t RESERVED3[29];
AnnaBridge 126:abea610beb85 722 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 126:abea610beb85 723 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 126:abea610beb85 724 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 126:abea610beb85 725 uint32_t RESERVED4[43];
AnnaBridge 126:abea610beb85 726 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 126:abea610beb85 727 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 126:abea610beb85 728 uint32_t RESERVED5[6];
AnnaBridge 126:abea610beb85 729 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 126:abea610beb85 730 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 126:abea610beb85 731 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 126:abea610beb85 732 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 126:abea610beb85 733 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 126:abea610beb85 734 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 126:abea610beb85 735 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 126:abea610beb85 736 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 126:abea610beb85 737 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 126:abea610beb85 738 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 126:abea610beb85 739 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 126:abea610beb85 740 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
AnnaBridge 126:abea610beb85 741 } ITM_Type;
AnnaBridge 126:abea610beb85 742
AnnaBridge 126:abea610beb85 743 /* ITM Trace Privilege Register Definitions */
AnnaBridge 126:abea610beb85 744 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
AnnaBridge 126:abea610beb85 745 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
AnnaBridge 126:abea610beb85 746
AnnaBridge 126:abea610beb85 747 /* ITM Trace Control Register Definitions */
AnnaBridge 126:abea610beb85 748 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
AnnaBridge 126:abea610beb85 749 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
AnnaBridge 126:abea610beb85 750
AnnaBridge 126:abea610beb85 751 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
AnnaBridge 126:abea610beb85 752 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
AnnaBridge 126:abea610beb85 753
AnnaBridge 126:abea610beb85 754 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
AnnaBridge 126:abea610beb85 755 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
AnnaBridge 126:abea610beb85 756
AnnaBridge 126:abea610beb85 757 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
AnnaBridge 126:abea610beb85 758 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
AnnaBridge 126:abea610beb85 759
AnnaBridge 126:abea610beb85 760 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
AnnaBridge 126:abea610beb85 761 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
AnnaBridge 126:abea610beb85 762
AnnaBridge 126:abea610beb85 763 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
AnnaBridge 126:abea610beb85 764 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
AnnaBridge 126:abea610beb85 765
AnnaBridge 126:abea610beb85 766 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
AnnaBridge 126:abea610beb85 767 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
AnnaBridge 126:abea610beb85 768
AnnaBridge 126:abea610beb85 769 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
AnnaBridge 126:abea610beb85 770 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
AnnaBridge 126:abea610beb85 771
AnnaBridge 126:abea610beb85 772 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
AnnaBridge 126:abea610beb85 773 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
AnnaBridge 126:abea610beb85 774
AnnaBridge 126:abea610beb85 775 /* ITM Integration Write Register Definitions */
AnnaBridge 126:abea610beb85 776 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
AnnaBridge 126:abea610beb85 777 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
AnnaBridge 126:abea610beb85 778
AnnaBridge 126:abea610beb85 779 /* ITM Integration Read Register Definitions */
AnnaBridge 126:abea610beb85 780 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
AnnaBridge 126:abea610beb85 781 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
AnnaBridge 126:abea610beb85 782
AnnaBridge 126:abea610beb85 783 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 126:abea610beb85 784 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
AnnaBridge 126:abea610beb85 785 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
AnnaBridge 126:abea610beb85 786
AnnaBridge 126:abea610beb85 787 /* ITM Lock Status Register Definitions */
AnnaBridge 126:abea610beb85 788 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
AnnaBridge 126:abea610beb85 789 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
AnnaBridge 126:abea610beb85 790
AnnaBridge 126:abea610beb85 791 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
AnnaBridge 126:abea610beb85 792 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
AnnaBridge 126:abea610beb85 793
AnnaBridge 126:abea610beb85 794 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
AnnaBridge 126:abea610beb85 795 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
AnnaBridge 126:abea610beb85 796
AnnaBridge 126:abea610beb85 797 /*@}*/ /* end of group CMSIS_ITM */
AnnaBridge 126:abea610beb85 798
AnnaBridge 126:abea610beb85 799
AnnaBridge 126:abea610beb85 800 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 801 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 126:abea610beb85 802 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 126:abea610beb85 803 @{
AnnaBridge 126:abea610beb85 804 */
AnnaBridge 126:abea610beb85 805
AnnaBridge 126:abea610beb85 806 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 126:abea610beb85 807 */
AnnaBridge 126:abea610beb85 808 typedef struct
AnnaBridge 126:abea610beb85 809 {
AnnaBridge 126:abea610beb85 810 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 126:abea610beb85 811 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 126:abea610beb85 812 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 126:abea610beb85 813 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 126:abea610beb85 814 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 126:abea610beb85 815 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 126:abea610beb85 816 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 126:abea610beb85 817 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 126:abea610beb85 818 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 126:abea610beb85 819 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 126:abea610beb85 820 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 126:abea610beb85 821 uint32_t RESERVED0[1];
AnnaBridge 126:abea610beb85 822 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 126:abea610beb85 823 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 126:abea610beb85 824 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 126:abea610beb85 825 uint32_t RESERVED1[1];
AnnaBridge 126:abea610beb85 826 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 126:abea610beb85 827 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 126:abea610beb85 828 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 126:abea610beb85 829 uint32_t RESERVED2[1];
AnnaBridge 126:abea610beb85 830 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 126:abea610beb85 831 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 126:abea610beb85 832 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 126:abea610beb85 833 } DWT_Type;
AnnaBridge 126:abea610beb85 834
AnnaBridge 126:abea610beb85 835 /* DWT Control Register Definitions */
AnnaBridge 126:abea610beb85 836 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 126:abea610beb85 837 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 126:abea610beb85 838
AnnaBridge 126:abea610beb85 839 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 126:abea610beb85 840 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 126:abea610beb85 841
AnnaBridge 126:abea610beb85 842 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 126:abea610beb85 843 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 126:abea610beb85 844
AnnaBridge 126:abea610beb85 845 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 126:abea610beb85 846 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 126:abea610beb85 847
AnnaBridge 126:abea610beb85 848 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 126:abea610beb85 849 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 126:abea610beb85 850
AnnaBridge 126:abea610beb85 851 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
AnnaBridge 126:abea610beb85 852 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
AnnaBridge 126:abea610beb85 853
AnnaBridge 126:abea610beb85 854 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
AnnaBridge 126:abea610beb85 855 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
AnnaBridge 126:abea610beb85 856
AnnaBridge 126:abea610beb85 857 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
AnnaBridge 126:abea610beb85 858 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
AnnaBridge 126:abea610beb85 859
AnnaBridge 126:abea610beb85 860 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
AnnaBridge 126:abea610beb85 861 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
AnnaBridge 126:abea610beb85 862
AnnaBridge 126:abea610beb85 863 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
AnnaBridge 126:abea610beb85 864 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
AnnaBridge 126:abea610beb85 865
AnnaBridge 126:abea610beb85 866 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
AnnaBridge 126:abea610beb85 867 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
AnnaBridge 126:abea610beb85 868
AnnaBridge 126:abea610beb85 869 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
AnnaBridge 126:abea610beb85 870 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
AnnaBridge 126:abea610beb85 871
AnnaBridge 126:abea610beb85 872 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
AnnaBridge 126:abea610beb85 873 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
AnnaBridge 126:abea610beb85 874
AnnaBridge 126:abea610beb85 875 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
AnnaBridge 126:abea610beb85 876 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
AnnaBridge 126:abea610beb85 877
AnnaBridge 126:abea610beb85 878 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
AnnaBridge 126:abea610beb85 879 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
AnnaBridge 126:abea610beb85 880
AnnaBridge 126:abea610beb85 881 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
AnnaBridge 126:abea610beb85 882 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
AnnaBridge 126:abea610beb85 883
AnnaBridge 126:abea610beb85 884 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
AnnaBridge 126:abea610beb85 885 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
AnnaBridge 126:abea610beb85 886
AnnaBridge 126:abea610beb85 887 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
AnnaBridge 126:abea610beb85 888 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
AnnaBridge 126:abea610beb85 889
AnnaBridge 126:abea610beb85 890 /* DWT CPI Count Register Definitions */
AnnaBridge 126:abea610beb85 891 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
AnnaBridge 126:abea610beb85 892 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
AnnaBridge 126:abea610beb85 893
AnnaBridge 126:abea610beb85 894 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 126:abea610beb85 895 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
AnnaBridge 126:abea610beb85 896 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
AnnaBridge 126:abea610beb85 897
AnnaBridge 126:abea610beb85 898 /* DWT Sleep Count Register Definitions */
AnnaBridge 126:abea610beb85 899 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
AnnaBridge 126:abea610beb85 900 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
AnnaBridge 126:abea610beb85 901
AnnaBridge 126:abea610beb85 902 /* DWT LSU Count Register Definitions */
AnnaBridge 126:abea610beb85 903 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
AnnaBridge 126:abea610beb85 904 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
AnnaBridge 126:abea610beb85 905
AnnaBridge 126:abea610beb85 906 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 126:abea610beb85 907 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
AnnaBridge 126:abea610beb85 908 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
AnnaBridge 126:abea610beb85 909
AnnaBridge 126:abea610beb85 910 /* DWT Comparator Mask Register Definitions */
AnnaBridge 126:abea610beb85 911 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
AnnaBridge 126:abea610beb85 912 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
AnnaBridge 126:abea610beb85 913
AnnaBridge 126:abea610beb85 914 /* DWT Comparator Function Register Definitions */
AnnaBridge 126:abea610beb85 915 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 126:abea610beb85 916 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 126:abea610beb85 917
AnnaBridge 126:abea610beb85 918 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
AnnaBridge 126:abea610beb85 919 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
AnnaBridge 126:abea610beb85 920
AnnaBridge 126:abea610beb85 921 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
AnnaBridge 126:abea610beb85 922 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
AnnaBridge 126:abea610beb85 923
AnnaBridge 126:abea610beb85 924 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 126:abea610beb85 925 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 126:abea610beb85 926
AnnaBridge 126:abea610beb85 927 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
AnnaBridge 126:abea610beb85 928 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
AnnaBridge 126:abea610beb85 929
AnnaBridge 126:abea610beb85 930 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
AnnaBridge 126:abea610beb85 931 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
AnnaBridge 126:abea610beb85 932
AnnaBridge 126:abea610beb85 933 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
AnnaBridge 126:abea610beb85 934 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
AnnaBridge 126:abea610beb85 935
AnnaBridge 126:abea610beb85 936 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
AnnaBridge 126:abea610beb85 937 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
AnnaBridge 126:abea610beb85 938
AnnaBridge 126:abea610beb85 939 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
AnnaBridge 126:abea610beb85 940 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
AnnaBridge 126:abea610beb85 941
AnnaBridge 126:abea610beb85 942 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 126:abea610beb85 943
AnnaBridge 126:abea610beb85 944
AnnaBridge 126:abea610beb85 945 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 946 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 126:abea610beb85 947 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 126:abea610beb85 948 @{
AnnaBridge 126:abea610beb85 949 */
AnnaBridge 126:abea610beb85 950
AnnaBridge 126:abea610beb85 951 /** \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 126:abea610beb85 952 */
AnnaBridge 126:abea610beb85 953 typedef struct
AnnaBridge 126:abea610beb85 954 {
AnnaBridge 126:abea610beb85 955 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 126:abea610beb85 956 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 126:abea610beb85 957 uint32_t RESERVED0[2];
AnnaBridge 126:abea610beb85 958 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 126:abea610beb85 959 uint32_t RESERVED1[55];
AnnaBridge 126:abea610beb85 960 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 126:abea610beb85 961 uint32_t RESERVED2[131];
AnnaBridge 126:abea610beb85 962 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 126:abea610beb85 963 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 126:abea610beb85 964 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 126:abea610beb85 965 uint32_t RESERVED3[759];
AnnaBridge 126:abea610beb85 966 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
AnnaBridge 126:abea610beb85 967 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 126:abea610beb85 968 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 126:abea610beb85 969 uint32_t RESERVED4[1];
AnnaBridge 126:abea610beb85 970 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 126:abea610beb85 971 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 126:abea610beb85 972 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 126:abea610beb85 973 uint32_t RESERVED5[39];
AnnaBridge 126:abea610beb85 974 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 126:abea610beb85 975 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 126:abea610beb85 976 uint32_t RESERVED7[8];
AnnaBridge 126:abea610beb85 977 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 126:abea610beb85 978 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 126:abea610beb85 979 } TPI_Type;
AnnaBridge 126:abea610beb85 980
AnnaBridge 126:abea610beb85 981 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 126:abea610beb85 982 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 126:abea610beb85 983 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 126:abea610beb85 984
AnnaBridge 126:abea610beb85 985 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 126:abea610beb85 986 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
AnnaBridge 126:abea610beb85 987 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 126:abea610beb85 988
AnnaBridge 126:abea610beb85 989 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 126:abea610beb85 990 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 126:abea610beb85 991 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 126:abea610beb85 992
AnnaBridge 126:abea610beb85 993 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
AnnaBridge 126:abea610beb85 994 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 126:abea610beb85 995
AnnaBridge 126:abea610beb85 996 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
AnnaBridge 126:abea610beb85 997 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 126:abea610beb85 998
AnnaBridge 126:abea610beb85 999 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
AnnaBridge 126:abea610beb85 1000 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 126:abea610beb85 1001
AnnaBridge 126:abea610beb85 1002 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 126:abea610beb85 1003 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
AnnaBridge 126:abea610beb85 1004 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 126:abea610beb85 1005
AnnaBridge 126:abea610beb85 1006 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
AnnaBridge 126:abea610beb85 1007 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 126:abea610beb85 1008
AnnaBridge 126:abea610beb85 1009 /* TPI TRIGGER Register Definitions */
AnnaBridge 126:abea610beb85 1010 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 126:abea610beb85 1011 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 126:abea610beb85 1012
AnnaBridge 126:abea610beb85 1013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 126:abea610beb85 1014 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 126:abea610beb85 1015 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 126:abea610beb85 1016
AnnaBridge 126:abea610beb85 1017 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 126:abea610beb85 1018 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 126:abea610beb85 1019
AnnaBridge 126:abea610beb85 1020 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 126:abea610beb85 1021 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 126:abea610beb85 1022
AnnaBridge 126:abea610beb85 1023 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 126:abea610beb85 1024 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 126:abea610beb85 1025
AnnaBridge 126:abea610beb85 1026 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 126:abea610beb85 1027 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 126:abea610beb85 1028
AnnaBridge 126:abea610beb85 1029 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 126:abea610beb85 1030 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 126:abea610beb85 1031
AnnaBridge 126:abea610beb85 1032 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 126:abea610beb85 1033 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 126:abea610beb85 1034
AnnaBridge 126:abea610beb85 1035 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 126:abea610beb85 1036 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
AnnaBridge 126:abea610beb85 1037 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
AnnaBridge 126:abea610beb85 1038
AnnaBridge 126:abea610beb85 1039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 126:abea610beb85 1040 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 126:abea610beb85 1041 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 126:abea610beb85 1042
AnnaBridge 126:abea610beb85 1043 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 126:abea610beb85 1044 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 126:abea610beb85 1045
AnnaBridge 126:abea610beb85 1046 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 126:abea610beb85 1047 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 126:abea610beb85 1048
AnnaBridge 126:abea610beb85 1049 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 126:abea610beb85 1050 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 126:abea610beb85 1051
AnnaBridge 126:abea610beb85 1052 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 126:abea610beb85 1053 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 126:abea610beb85 1054
AnnaBridge 126:abea610beb85 1055 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 126:abea610beb85 1056 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 126:abea610beb85 1057
AnnaBridge 126:abea610beb85 1058 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 126:abea610beb85 1059 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 126:abea610beb85 1060
AnnaBridge 126:abea610beb85 1061 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 126:abea610beb85 1062 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
AnnaBridge 126:abea610beb85 1063 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
AnnaBridge 126:abea610beb85 1064
AnnaBridge 126:abea610beb85 1065 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 126:abea610beb85 1066 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
AnnaBridge 126:abea610beb85 1067 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 126:abea610beb85 1068
AnnaBridge 126:abea610beb85 1069 /* TPI DEVID Register Definitions */
AnnaBridge 126:abea610beb85 1070 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 126:abea610beb85 1071 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 126:abea610beb85 1072
AnnaBridge 126:abea610beb85 1073 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 126:abea610beb85 1074 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 126:abea610beb85 1075
AnnaBridge 126:abea610beb85 1076 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 126:abea610beb85 1077 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 126:abea610beb85 1078
AnnaBridge 126:abea610beb85 1079 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 126:abea610beb85 1080 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 126:abea610beb85 1081
AnnaBridge 126:abea610beb85 1082 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 126:abea610beb85 1083 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 126:abea610beb85 1084
AnnaBridge 126:abea610beb85 1085 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 126:abea610beb85 1086 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 126:abea610beb85 1087
AnnaBridge 126:abea610beb85 1088 /* TPI DEVTYPE Register Definitions */
AnnaBridge 126:abea610beb85 1089 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 126:abea610beb85 1090 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 126:abea610beb85 1091
AnnaBridge 126:abea610beb85 1092 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 126:abea610beb85 1093 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 126:abea610beb85 1094
AnnaBridge 126:abea610beb85 1095 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 126:abea610beb85 1096
AnnaBridge 126:abea610beb85 1097
AnnaBridge 126:abea610beb85 1098 #if (__MPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 1099 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 1100 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 126:abea610beb85 1101 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 126:abea610beb85 1102 @{
AnnaBridge 126:abea610beb85 1103 */
AnnaBridge 126:abea610beb85 1104
AnnaBridge 126:abea610beb85 1105 /** \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 126:abea610beb85 1106 */
AnnaBridge 126:abea610beb85 1107 typedef struct
AnnaBridge 126:abea610beb85 1108 {
AnnaBridge 126:abea610beb85 1109 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 126:abea610beb85 1110 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 126:abea610beb85 1111 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 126:abea610beb85 1112 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 126:abea610beb85 1113 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1114 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 126:abea610beb85 1115 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1116 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 126:abea610beb85 1117 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1118 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 126:abea610beb85 1119 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1120 } MPU_Type;
AnnaBridge 126:abea610beb85 1121
AnnaBridge 126:abea610beb85 1122 /* MPU Type Register */
AnnaBridge 126:abea610beb85 1123 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
AnnaBridge 126:abea610beb85 1124 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 126:abea610beb85 1125
AnnaBridge 126:abea610beb85 1126 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
AnnaBridge 126:abea610beb85 1127 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 126:abea610beb85 1128
AnnaBridge 126:abea610beb85 1129 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 126:abea610beb85 1130 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 126:abea610beb85 1131
AnnaBridge 126:abea610beb85 1132 /* MPU Control Register */
AnnaBridge 126:abea610beb85 1133 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 126:abea610beb85 1134 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 126:abea610beb85 1135
AnnaBridge 126:abea610beb85 1136 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 126:abea610beb85 1137 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 126:abea610beb85 1138
AnnaBridge 126:abea610beb85 1139 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
AnnaBridge 126:abea610beb85 1140 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 126:abea610beb85 1141
AnnaBridge 126:abea610beb85 1142 /* MPU Region Number Register */
AnnaBridge 126:abea610beb85 1143 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
AnnaBridge 126:abea610beb85 1144 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 126:abea610beb85 1145
AnnaBridge 126:abea610beb85 1146 /* MPU Region Base Address Register */
AnnaBridge 126:abea610beb85 1147 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
AnnaBridge 126:abea610beb85 1148 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 126:abea610beb85 1149
AnnaBridge 126:abea610beb85 1150 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
AnnaBridge 126:abea610beb85 1151 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 126:abea610beb85 1152
AnnaBridge 126:abea610beb85 1153 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
AnnaBridge 126:abea610beb85 1154 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 126:abea610beb85 1155
AnnaBridge 126:abea610beb85 1156 /* MPU Region Attribute and Size Register */
AnnaBridge 126:abea610beb85 1157 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 126:abea610beb85 1158 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 126:abea610beb85 1159
AnnaBridge 126:abea610beb85 1160 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 126:abea610beb85 1161 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 126:abea610beb85 1162
AnnaBridge 126:abea610beb85 1163 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 126:abea610beb85 1164 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 126:abea610beb85 1165
AnnaBridge 126:abea610beb85 1166 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 126:abea610beb85 1167 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 126:abea610beb85 1168
AnnaBridge 126:abea610beb85 1169 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 126:abea610beb85 1170 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 126:abea610beb85 1171
AnnaBridge 126:abea610beb85 1172 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 126:abea610beb85 1173 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 126:abea610beb85 1174
AnnaBridge 126:abea610beb85 1175 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 126:abea610beb85 1176 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 126:abea610beb85 1177
AnnaBridge 126:abea610beb85 1178 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 126:abea610beb85 1179 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 126:abea610beb85 1180
AnnaBridge 126:abea610beb85 1181 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
AnnaBridge 126:abea610beb85 1182 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 126:abea610beb85 1183
AnnaBridge 126:abea610beb85 1184 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
AnnaBridge 126:abea610beb85 1185 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 126:abea610beb85 1186
AnnaBridge 126:abea610beb85 1187 /*@} end of group CMSIS_MPU */
AnnaBridge 126:abea610beb85 1188 #endif
AnnaBridge 126:abea610beb85 1189
AnnaBridge 126:abea610beb85 1190
AnnaBridge 126:abea610beb85 1191 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 1192 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 126:abea610beb85 1193 \brief Type definitions for the Core Debug Registers
AnnaBridge 126:abea610beb85 1194 @{
AnnaBridge 126:abea610beb85 1195 */
AnnaBridge 126:abea610beb85 1196
AnnaBridge 126:abea610beb85 1197 /** \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 126:abea610beb85 1198 */
AnnaBridge 126:abea610beb85 1199 typedef struct
AnnaBridge 126:abea610beb85 1200 {
AnnaBridge 126:abea610beb85 1201 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 126:abea610beb85 1202 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 126:abea610beb85 1203 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 126:abea610beb85 1204 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 126:abea610beb85 1205 } CoreDebug_Type;
AnnaBridge 126:abea610beb85 1206
AnnaBridge 126:abea610beb85 1207 /* Debug Halting Control and Status Register */
AnnaBridge 126:abea610beb85 1208 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 126:abea610beb85 1209 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 126:abea610beb85 1210
AnnaBridge 126:abea610beb85 1211 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 126:abea610beb85 1212 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 126:abea610beb85 1213
AnnaBridge 126:abea610beb85 1214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 126:abea610beb85 1215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 126:abea610beb85 1216
AnnaBridge 126:abea610beb85 1217 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 126:abea610beb85 1218 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 126:abea610beb85 1219
AnnaBridge 126:abea610beb85 1220 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 126:abea610beb85 1221 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 126:abea610beb85 1222
AnnaBridge 126:abea610beb85 1223 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 126:abea610beb85 1224 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 126:abea610beb85 1225
AnnaBridge 126:abea610beb85 1226 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 126:abea610beb85 1227 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 126:abea610beb85 1228
AnnaBridge 126:abea610beb85 1229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
AnnaBridge 126:abea610beb85 1230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
AnnaBridge 126:abea610beb85 1231
AnnaBridge 126:abea610beb85 1232 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 126:abea610beb85 1233 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 126:abea610beb85 1234
AnnaBridge 126:abea610beb85 1235 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 126:abea610beb85 1236 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 126:abea610beb85 1237
AnnaBridge 126:abea610beb85 1238 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 126:abea610beb85 1239 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 126:abea610beb85 1240
AnnaBridge 126:abea610beb85 1241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 126:abea610beb85 1242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 126:abea610beb85 1243
AnnaBridge 126:abea610beb85 1244 /* Debug Core Register Selector Register */
AnnaBridge 126:abea610beb85 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 126:abea610beb85 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 126:abea610beb85 1247
AnnaBridge 126:abea610beb85 1248 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 126:abea610beb85 1249 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 126:abea610beb85 1250
AnnaBridge 126:abea610beb85 1251 /* Debug Exception and Monitor Control Register */
AnnaBridge 126:abea610beb85 1252 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
AnnaBridge 126:abea610beb85 1253 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
AnnaBridge 126:abea610beb85 1254
AnnaBridge 126:abea610beb85 1255 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
AnnaBridge 126:abea610beb85 1256 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
AnnaBridge 126:abea610beb85 1257
AnnaBridge 126:abea610beb85 1258 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
AnnaBridge 126:abea610beb85 1259 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
AnnaBridge 126:abea610beb85 1260
AnnaBridge 126:abea610beb85 1261 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
AnnaBridge 126:abea610beb85 1262 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
AnnaBridge 126:abea610beb85 1263
AnnaBridge 126:abea610beb85 1264 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
AnnaBridge 126:abea610beb85 1265 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
AnnaBridge 126:abea610beb85 1266
AnnaBridge 126:abea610beb85 1267 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 126:abea610beb85 1268 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 126:abea610beb85 1269
AnnaBridge 126:abea610beb85 1270 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
AnnaBridge 126:abea610beb85 1271 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
AnnaBridge 126:abea610beb85 1272
AnnaBridge 126:abea610beb85 1273 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
AnnaBridge 126:abea610beb85 1274 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
AnnaBridge 126:abea610beb85 1275
AnnaBridge 126:abea610beb85 1276 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
AnnaBridge 126:abea610beb85 1277 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
AnnaBridge 126:abea610beb85 1278
AnnaBridge 126:abea610beb85 1279 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
AnnaBridge 126:abea610beb85 1280 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
AnnaBridge 126:abea610beb85 1281
AnnaBridge 126:abea610beb85 1282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
AnnaBridge 126:abea610beb85 1283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
AnnaBridge 126:abea610beb85 1284
AnnaBridge 126:abea610beb85 1285 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
AnnaBridge 126:abea610beb85 1286 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
AnnaBridge 126:abea610beb85 1287
AnnaBridge 126:abea610beb85 1288 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 126:abea610beb85 1289 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 126:abea610beb85 1290
AnnaBridge 126:abea610beb85 1291 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 126:abea610beb85 1292
AnnaBridge 126:abea610beb85 1293
AnnaBridge 126:abea610beb85 1294 /** \ingroup CMSIS_core_register
AnnaBridge 126:abea610beb85 1295 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 126:abea610beb85 1296 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 126:abea610beb85 1297 @{
AnnaBridge 126:abea610beb85 1298 */
AnnaBridge 126:abea610beb85 1299
AnnaBridge 126:abea610beb85 1300 /* Memory mapping of Cortex-M3 Hardware */
AnnaBridge 126:abea610beb85 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 126:abea610beb85 1302 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 126:abea610beb85 1303 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 126:abea610beb85 1304 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 126:abea610beb85 1305 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 126:abea610beb85 1306 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 126:abea610beb85 1307 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 126:abea610beb85 1308 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 126:abea610beb85 1309
AnnaBridge 126:abea610beb85 1310 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 126:abea610beb85 1311 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 126:abea610beb85 1312 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 126:abea610beb85 1313 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 126:abea610beb85 1314 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 126:abea610beb85 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 126:abea610beb85 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 126:abea610beb85 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
AnnaBridge 126:abea610beb85 1318
AnnaBridge 126:abea610beb85 1319 #if (__MPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 1320 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 126:abea610beb85 1321 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 126:abea610beb85 1322 #endif
AnnaBridge 126:abea610beb85 1323
AnnaBridge 126:abea610beb85 1324 /*@} */
AnnaBridge 126:abea610beb85 1325
AnnaBridge 126:abea610beb85 1326
AnnaBridge 126:abea610beb85 1327
AnnaBridge 126:abea610beb85 1328 /*******************************************************************************
AnnaBridge 126:abea610beb85 1329 * Hardware Abstraction Layer
AnnaBridge 126:abea610beb85 1330 Core Function Interface contains:
AnnaBridge 126:abea610beb85 1331 - Core NVIC Functions
AnnaBridge 126:abea610beb85 1332 - Core SysTick Functions
AnnaBridge 126:abea610beb85 1333 - Core Debug Functions
AnnaBridge 126:abea610beb85 1334 - Core Register Access Functions
AnnaBridge 126:abea610beb85 1335 ******************************************************************************/
AnnaBridge 126:abea610beb85 1336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 126:abea610beb85 1337 */
AnnaBridge 126:abea610beb85 1338
AnnaBridge 126:abea610beb85 1339
AnnaBridge 126:abea610beb85 1340
AnnaBridge 126:abea610beb85 1341 /* ########################## NVIC functions #################################### */
AnnaBridge 126:abea610beb85 1342 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 1343 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 126:abea610beb85 1344 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 126:abea610beb85 1345 @{
AnnaBridge 126:abea610beb85 1346 */
AnnaBridge 126:abea610beb85 1347
<> 127:25aea2a3f4e3 1348 #ifdef CMSIS_NVIC_VIRTUAL
<> 127:25aea2a3f4e3 1349 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1350 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
<> 127:25aea2a3f4e3 1351 #endif
<> 127:25aea2a3f4e3 1352 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1353 #else
<> 127:25aea2a3f4e3 1354 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
<> 127:25aea2a3f4e3 1355 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
<> 127:25aea2a3f4e3 1356 #define NVIC_EnableIRQ __NVIC_EnableIRQ
<> 127:25aea2a3f4e3 1357 #define NVIC_DisableIRQ __NVIC_DisableIRQ
<> 127:25aea2a3f4e3 1358 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
<> 127:25aea2a3f4e3 1359 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
<> 127:25aea2a3f4e3 1360 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
<> 127:25aea2a3f4e3 1361 #define NVIC_GetActive __NVIC_GetActive
<> 127:25aea2a3f4e3 1362 #define NVIC_SetPriority __NVIC_SetPriority
<> 127:25aea2a3f4e3 1363 #define NVIC_GetPriority __NVIC_GetPriority
<> 128:9bcdf88f62b0 1364 #define NVIC_SystemReset __NVIC_SystemReset
<> 127:25aea2a3f4e3 1365 #endif /* CMSIS_NVIC_VIRTUAL */
<> 127:25aea2a3f4e3 1366
<> 127:25aea2a3f4e3 1367 #ifdef CMSIS_VECTAB_VIRTUAL
<> 127:25aea2a3f4e3 1368 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1369 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
<> 127:25aea2a3f4e3 1370 #endif
<> 127:25aea2a3f4e3 1371 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
<> 127:25aea2a3f4e3 1372 #else
<> 127:25aea2a3f4e3 1373 #define NVIC_SetVector __NVIC_SetVector
<> 127:25aea2a3f4e3 1374 #define NVIC_GetVector __NVIC_GetVector
<> 127:25aea2a3f4e3 1375 #endif /* CMSIS_VECTAB_VIRTUAL */
<> 127:25aea2a3f4e3 1376
AnnaBridge 126:abea610beb85 1377 /** \brief Set Priority Grouping
AnnaBridge 126:abea610beb85 1378
AnnaBridge 126:abea610beb85 1379 The function sets the priority grouping field using the required unlock sequence.
AnnaBridge 126:abea610beb85 1380 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 126:abea610beb85 1381 Only values from 0..7 are used.
AnnaBridge 126:abea610beb85 1382 In case of a conflict between priority grouping and available
AnnaBridge 126:abea610beb85 1383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 126:abea610beb85 1384
AnnaBridge 126:abea610beb85 1385 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 126:abea610beb85 1386 */
<> 127:25aea2a3f4e3 1387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge 126:abea610beb85 1388 {
AnnaBridge 126:abea610beb85 1389 uint32_t reg_value;
AnnaBridge 126:abea610beb85 1390 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 126:abea610beb85 1391
AnnaBridge 126:abea610beb85 1392 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 126:abea610beb85 1393 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 126:abea610beb85 1394 reg_value = (reg_value |
AnnaBridge 126:abea610beb85 1395 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 126:abea610beb85 1396 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
AnnaBridge 126:abea610beb85 1397 SCB->AIRCR = reg_value;
AnnaBridge 126:abea610beb85 1398 }
AnnaBridge 126:abea610beb85 1399
AnnaBridge 126:abea610beb85 1400
AnnaBridge 126:abea610beb85 1401 /** \brief Get Priority Grouping
AnnaBridge 126:abea610beb85 1402
AnnaBridge 126:abea610beb85 1403 The function reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 126:abea610beb85 1404
AnnaBridge 126:abea610beb85 1405 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 126:abea610beb85 1406 */
<> 127:25aea2a3f4e3 1407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge 126:abea610beb85 1408 {
AnnaBridge 126:abea610beb85 1409 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 126:abea610beb85 1410 }
AnnaBridge 126:abea610beb85 1411
AnnaBridge 126:abea610beb85 1412
AnnaBridge 126:abea610beb85 1413 /** \brief Enable External Interrupt
AnnaBridge 126:abea610beb85 1414
AnnaBridge 126:abea610beb85 1415 The function enables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 126:abea610beb85 1416
AnnaBridge 126:abea610beb85 1417 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 1418 */
<> 127:25aea2a3f4e3 1419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1420 {
AnnaBridge 126:abea610beb85 1421 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 1422 }
AnnaBridge 126:abea610beb85 1423
AnnaBridge 126:abea610beb85 1424
AnnaBridge 126:abea610beb85 1425 /** \brief Disable External Interrupt
AnnaBridge 126:abea610beb85 1426
AnnaBridge 126:abea610beb85 1427 The function disables a device-specific interrupt in the NVIC interrupt controller.
AnnaBridge 126:abea610beb85 1428
AnnaBridge 126:abea610beb85 1429 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 1430 */
<> 127:25aea2a3f4e3 1431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1432 {
AnnaBridge 126:abea610beb85 1433 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 1434 __DSB();
<> 131:faff56e089b2 1435 __ISB();
AnnaBridge 126:abea610beb85 1436 }
AnnaBridge 126:abea610beb85 1437
AnnaBridge 126:abea610beb85 1438
AnnaBridge 126:abea610beb85 1439 /** \brief Get Pending Interrupt
AnnaBridge 126:abea610beb85 1440
AnnaBridge 126:abea610beb85 1441 The function reads the pending register in the NVIC and returns the pending bit
AnnaBridge 126:abea610beb85 1442 for the specified interrupt.
AnnaBridge 126:abea610beb85 1443
AnnaBridge 126:abea610beb85 1444 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 1445
AnnaBridge 126:abea610beb85 1446 \return 0 Interrupt status is not pending.
AnnaBridge 126:abea610beb85 1447 \return 1 Interrupt status is pending.
AnnaBridge 126:abea610beb85 1448 */
<> 127:25aea2a3f4e3 1449 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1450 {
AnnaBridge 126:abea610beb85 1451 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 126:abea610beb85 1452 }
AnnaBridge 126:abea610beb85 1453
AnnaBridge 126:abea610beb85 1454
AnnaBridge 126:abea610beb85 1455 /** \brief Set Pending Interrupt
AnnaBridge 126:abea610beb85 1456
AnnaBridge 126:abea610beb85 1457 The function sets the pending bit of an external interrupt.
AnnaBridge 126:abea610beb85 1458
AnnaBridge 126:abea610beb85 1459 \param [in] IRQn Interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 1460 */
<> 127:25aea2a3f4e3 1461 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1462 {
AnnaBridge 126:abea610beb85 1463 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 1464 }
AnnaBridge 126:abea610beb85 1465
AnnaBridge 126:abea610beb85 1466
AnnaBridge 126:abea610beb85 1467 /** \brief Clear Pending Interrupt
AnnaBridge 126:abea610beb85 1468
AnnaBridge 126:abea610beb85 1469 The function clears the pending bit of an external interrupt.
AnnaBridge 126:abea610beb85 1470
AnnaBridge 126:abea610beb85 1471 \param [in] IRQn External interrupt number. Value cannot be negative.
AnnaBridge 126:abea610beb85 1472 */
<> 127:25aea2a3f4e3 1473 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1474 {
AnnaBridge 126:abea610beb85 1475 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 126:abea610beb85 1476 }
AnnaBridge 126:abea610beb85 1477
AnnaBridge 126:abea610beb85 1478
AnnaBridge 126:abea610beb85 1479 /** \brief Get Active Interrupt
AnnaBridge 126:abea610beb85 1480
AnnaBridge 126:abea610beb85 1481 The function reads the active register in NVIC and returns the active bit.
AnnaBridge 126:abea610beb85 1482
AnnaBridge 126:abea610beb85 1483 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 1484
AnnaBridge 126:abea610beb85 1485 \return 0 Interrupt status is not active.
AnnaBridge 126:abea610beb85 1486 \return 1 Interrupt status is active.
AnnaBridge 126:abea610beb85 1487 */
<> 127:25aea2a3f4e3 1488 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1489 {
AnnaBridge 126:abea610beb85 1490 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 126:abea610beb85 1491 }
AnnaBridge 126:abea610beb85 1492
AnnaBridge 126:abea610beb85 1493
AnnaBridge 126:abea610beb85 1494 /** \brief Set Interrupt Priority
AnnaBridge 126:abea610beb85 1495
AnnaBridge 126:abea610beb85 1496 The function sets the priority of an interrupt.
AnnaBridge 126:abea610beb85 1497
AnnaBridge 126:abea610beb85 1498 \note The priority cannot be set for every core interrupt.
AnnaBridge 126:abea610beb85 1499
AnnaBridge 126:abea610beb85 1500 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 1501 \param [in] priority Priority to set.
AnnaBridge 126:abea610beb85 1502 */
<> 127:25aea2a3f4e3 1503 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 126:abea610beb85 1504 {
AnnaBridge 126:abea610beb85 1505 if((int32_t)IRQn < 0) {
AnnaBridge 126:abea610beb85 1506 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 126:abea610beb85 1507 }
AnnaBridge 126:abea610beb85 1508 else {
AnnaBridge 126:abea610beb85 1509 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 126:abea610beb85 1510 }
AnnaBridge 126:abea610beb85 1511 }
AnnaBridge 126:abea610beb85 1512
AnnaBridge 126:abea610beb85 1513
AnnaBridge 126:abea610beb85 1514 /** \brief Get Interrupt Priority
AnnaBridge 126:abea610beb85 1515
AnnaBridge 126:abea610beb85 1516 The function reads the priority of an interrupt. The interrupt
AnnaBridge 126:abea610beb85 1517 number can be positive to specify an external (device specific)
AnnaBridge 126:abea610beb85 1518 interrupt, or negative to specify an internal (core) interrupt.
AnnaBridge 126:abea610beb85 1519
AnnaBridge 126:abea610beb85 1520
AnnaBridge 126:abea610beb85 1521 \param [in] IRQn Interrupt number.
AnnaBridge 126:abea610beb85 1522 \return Interrupt Priority. Value is aligned automatically to the implemented
AnnaBridge 126:abea610beb85 1523 priority bits of the microcontroller.
AnnaBridge 126:abea610beb85 1524 */
<> 127:25aea2a3f4e3 1525 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 126:abea610beb85 1526 {
AnnaBridge 126:abea610beb85 1527
AnnaBridge 126:abea610beb85 1528 if((int32_t)IRQn < 0) {
AnnaBridge 126:abea610beb85 1529 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 126:abea610beb85 1530 }
AnnaBridge 126:abea610beb85 1531 else {
AnnaBridge 126:abea610beb85 1532 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
AnnaBridge 126:abea610beb85 1533 }
AnnaBridge 126:abea610beb85 1534 }
AnnaBridge 126:abea610beb85 1535
AnnaBridge 126:abea610beb85 1536
AnnaBridge 126:abea610beb85 1537 /** \brief Encode Priority
AnnaBridge 126:abea610beb85 1538
AnnaBridge 126:abea610beb85 1539 The function encodes the priority for an interrupt with the given priority group,
AnnaBridge 126:abea610beb85 1540 preemptive priority value, and subpriority value.
AnnaBridge 126:abea610beb85 1541 In case of a conflict between priority grouping and available
AnnaBridge 126:abea610beb85 1542 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 126:abea610beb85 1543
AnnaBridge 126:abea610beb85 1544 \param [in] PriorityGroup Used priority group.
AnnaBridge 126:abea610beb85 1545 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 126:abea610beb85 1546 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 126:abea610beb85 1547 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 126:abea610beb85 1548 */
AnnaBridge 126:abea610beb85 1549 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 126:abea610beb85 1550 {
AnnaBridge 126:abea610beb85 1551 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 126:abea610beb85 1552 uint32_t PreemptPriorityBits;
AnnaBridge 126:abea610beb85 1553 uint32_t SubPriorityBits;
AnnaBridge 126:abea610beb85 1554
AnnaBridge 126:abea610beb85 1555 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 126:abea610beb85 1556 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 126:abea610beb85 1557
AnnaBridge 126:abea610beb85 1558 return (
AnnaBridge 126:abea610beb85 1559 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 126:abea610beb85 1560 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 126:abea610beb85 1561 );
AnnaBridge 126:abea610beb85 1562 }
AnnaBridge 126:abea610beb85 1563
AnnaBridge 126:abea610beb85 1564
AnnaBridge 126:abea610beb85 1565 /** \brief Decode Priority
AnnaBridge 126:abea610beb85 1566
AnnaBridge 126:abea610beb85 1567 The function decodes an interrupt priority value with a given priority group to
AnnaBridge 126:abea610beb85 1568 preemptive priority value and subpriority value.
AnnaBridge 126:abea610beb85 1569 In case of a conflict between priority grouping and available
AnnaBridge 126:abea610beb85 1570 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 126:abea610beb85 1571
AnnaBridge 126:abea610beb85 1572 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 126:abea610beb85 1573 \param [in] PriorityGroup Used priority group.
AnnaBridge 126:abea610beb85 1574 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 126:abea610beb85 1575 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 126:abea610beb85 1576 */
AnnaBridge 126:abea610beb85 1577 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
AnnaBridge 126:abea610beb85 1578 {
AnnaBridge 126:abea610beb85 1579 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 126:abea610beb85 1580 uint32_t PreemptPriorityBits;
AnnaBridge 126:abea610beb85 1581 uint32_t SubPriorityBits;
AnnaBridge 126:abea610beb85 1582
AnnaBridge 126:abea610beb85 1583 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 126:abea610beb85 1584 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 126:abea610beb85 1585
AnnaBridge 126:abea610beb85 1586 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 126:abea610beb85 1587 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 126:abea610beb85 1588 }
AnnaBridge 126:abea610beb85 1589
AnnaBridge 126:abea610beb85 1590
AnnaBridge 126:abea610beb85 1591 /** \brief System Reset
AnnaBridge 126:abea610beb85 1592
AnnaBridge 126:abea610beb85 1593 The function initiates a system reset request to reset the MCU.
AnnaBridge 126:abea610beb85 1594 */
<> 128:9bcdf88f62b0 1595 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 126:abea610beb85 1596 {
AnnaBridge 126:abea610beb85 1597 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 126:abea610beb85 1598 buffered write are completed before reset */
AnnaBridge 126:abea610beb85 1599 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 126:abea610beb85 1600 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
AnnaBridge 126:abea610beb85 1601 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge 126:abea610beb85 1602 __DSB(); /* Ensure completion of memory access */
AnnaBridge 126:abea610beb85 1603 while(1) { __NOP(); } /* wait until reset */
AnnaBridge 126:abea610beb85 1604 }
AnnaBridge 126:abea610beb85 1605
AnnaBridge 126:abea610beb85 1606 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 126:abea610beb85 1607
AnnaBridge 126:abea610beb85 1608
AnnaBridge 126:abea610beb85 1609
AnnaBridge 126:abea610beb85 1610 /* ################################## SysTick function ############################################ */
AnnaBridge 126:abea610beb85 1611 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 1612 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 126:abea610beb85 1613 \brief Functions that configure the System.
AnnaBridge 126:abea610beb85 1614 @{
AnnaBridge 126:abea610beb85 1615 */
AnnaBridge 126:abea610beb85 1616
AnnaBridge 126:abea610beb85 1617 #if (__Vendor_SysTickConfig == 0)
AnnaBridge 126:abea610beb85 1618
AnnaBridge 126:abea610beb85 1619 /** \brief System Tick Configuration
AnnaBridge 126:abea610beb85 1620
AnnaBridge 126:abea610beb85 1621 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 126:abea610beb85 1622 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 126:abea610beb85 1623
AnnaBridge 126:abea610beb85 1624 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 126:abea610beb85 1625
AnnaBridge 126:abea610beb85 1626 \return 0 Function succeeded.
AnnaBridge 126:abea610beb85 1627 \return 1 Function failed.
AnnaBridge 126:abea610beb85 1628
AnnaBridge 126:abea610beb85 1629 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 126:abea610beb85 1630 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 126:abea610beb85 1631 must contain a vendor-specific implementation of this function.
AnnaBridge 126:abea610beb85 1632
AnnaBridge 126:abea610beb85 1633 */
AnnaBridge 126:abea610beb85 1634 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 126:abea610beb85 1635 {
AnnaBridge 126:abea610beb85 1636 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
AnnaBridge 126:abea610beb85 1637
AnnaBridge 126:abea610beb85 1638 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 126:abea610beb85 1639 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 126:abea610beb85 1640 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 126:abea610beb85 1641 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 126:abea610beb85 1642 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 126:abea610beb85 1643 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 126:abea610beb85 1644 return (0UL); /* Function successful */
AnnaBridge 126:abea610beb85 1645 }
AnnaBridge 126:abea610beb85 1646
AnnaBridge 126:abea610beb85 1647 #endif
AnnaBridge 126:abea610beb85 1648
AnnaBridge 126:abea610beb85 1649 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 126:abea610beb85 1650
AnnaBridge 126:abea610beb85 1651
AnnaBridge 126:abea610beb85 1652
AnnaBridge 126:abea610beb85 1653 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 126:abea610beb85 1654 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 1655 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 126:abea610beb85 1656 \brief Functions that access the ITM debug interface.
AnnaBridge 126:abea610beb85 1657 @{
AnnaBridge 126:abea610beb85 1658 */
AnnaBridge 126:abea610beb85 1659
AnnaBridge 126:abea610beb85 1660 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 126:abea610beb85 1661 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
AnnaBridge 126:abea610beb85 1662
AnnaBridge 126:abea610beb85 1663
AnnaBridge 126:abea610beb85 1664 /** \brief ITM Send Character
AnnaBridge 126:abea610beb85 1665
AnnaBridge 126:abea610beb85 1666 The function transmits a character via the ITM channel 0, and
AnnaBridge 126:abea610beb85 1667 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 126:abea610beb85 1668 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 126:abea610beb85 1669
AnnaBridge 126:abea610beb85 1670 \param [in] ch Character to transmit.
AnnaBridge 126:abea610beb85 1671
AnnaBridge 126:abea610beb85 1672 \returns Character to transmit.
AnnaBridge 126:abea610beb85 1673 */
AnnaBridge 126:abea610beb85 1674 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge 126:abea610beb85 1675 {
AnnaBridge 126:abea610beb85 1676 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge 126:abea610beb85 1677 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge 126:abea610beb85 1678 {
AnnaBridge 126:abea610beb85 1679 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
AnnaBridge 126:abea610beb85 1680 ITM->PORT[0].u8 = (uint8_t)ch;
AnnaBridge 126:abea610beb85 1681 }
AnnaBridge 126:abea610beb85 1682 return (ch);
AnnaBridge 126:abea610beb85 1683 }
AnnaBridge 126:abea610beb85 1684
AnnaBridge 126:abea610beb85 1685
AnnaBridge 126:abea610beb85 1686 /** \brief ITM Receive Character
AnnaBridge 126:abea610beb85 1687
AnnaBridge 126:abea610beb85 1688 The function inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 126:abea610beb85 1689
AnnaBridge 126:abea610beb85 1690 \return Received character.
AnnaBridge 126:abea610beb85 1691 \return -1 No character pending.
AnnaBridge 126:abea610beb85 1692 */
AnnaBridge 126:abea610beb85 1693 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
AnnaBridge 126:abea610beb85 1694 int32_t ch = -1; /* no character available */
AnnaBridge 126:abea610beb85 1695
AnnaBridge 126:abea610beb85 1696 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
AnnaBridge 126:abea610beb85 1697 ch = ITM_RxBuffer;
AnnaBridge 126:abea610beb85 1698 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge 126:abea610beb85 1699 }
AnnaBridge 126:abea610beb85 1700
AnnaBridge 126:abea610beb85 1701 return (ch);
AnnaBridge 126:abea610beb85 1702 }
AnnaBridge 126:abea610beb85 1703
AnnaBridge 126:abea610beb85 1704
AnnaBridge 126:abea610beb85 1705 /** \brief ITM Check Character
AnnaBridge 126:abea610beb85 1706
AnnaBridge 126:abea610beb85 1707 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 126:abea610beb85 1708
AnnaBridge 126:abea610beb85 1709 \return 0 No character available.
AnnaBridge 126:abea610beb85 1710 \return 1 Character available.
AnnaBridge 126:abea610beb85 1711 */
AnnaBridge 126:abea610beb85 1712 __STATIC_INLINE int32_t ITM_CheckChar (void) {
AnnaBridge 126:abea610beb85 1713
AnnaBridge 126:abea610beb85 1714 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
AnnaBridge 126:abea610beb85 1715 return (0); /* no character available */
AnnaBridge 126:abea610beb85 1716 } else {
AnnaBridge 126:abea610beb85 1717 return (1); /* character available */
AnnaBridge 126:abea610beb85 1718 }
AnnaBridge 126:abea610beb85 1719 }
AnnaBridge 126:abea610beb85 1720
AnnaBridge 126:abea610beb85 1721 /*@} end of CMSIS_core_DebugFunctions */
AnnaBridge 126:abea610beb85 1722
AnnaBridge 126:abea610beb85 1723
AnnaBridge 126:abea610beb85 1724
AnnaBridge 126:abea610beb85 1725
AnnaBridge 126:abea610beb85 1726 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 1727 }
AnnaBridge 126:abea610beb85 1728 #endif
AnnaBridge 126:abea610beb85 1729
AnnaBridge 126:abea610beb85 1730 #endif /* __CORE_CM3_H_DEPENDANT */
AnnaBridge 126:abea610beb85 1731
AnnaBridge 126:abea610beb85 1732 #endif /* __CMSIS_GENERIC */