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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MTM_MTCONNECT04S/core_ca_mmu.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
126:abea610beb85 
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 ;/**************************************************************************//**
AnnaBridge 126:abea610beb85 2 ; * @file core_ca_mmu.h
AnnaBridge 126:abea610beb85 3 ; * @brief MMU Startup File for A9_MP Device Series
AnnaBridge 126:abea610beb85 4 ; * @version V1.01
AnnaBridge 126:abea610beb85 5 ; * @date 10 Sept 2014
AnnaBridge 126:abea610beb85 6 ; *
AnnaBridge 126:abea610beb85 7 ; * @note
AnnaBridge 126:abea610beb85 8 ; *
AnnaBridge 126:abea610beb85 9 ; ******************************************************************************/
AnnaBridge 126:abea610beb85 10 ;/* Copyright (c) 2012-2014 ARM LIMITED
AnnaBridge 126:abea610beb85 11 ;
AnnaBridge 126:abea610beb85 12 ; All rights reserved.
AnnaBridge 126:abea610beb85 13 ; Redistribution and use in source and binary forms, with or without
AnnaBridge 126:abea610beb85 14 ; modification, are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 ; - Redistributions of source code must retain the above copyright
AnnaBridge 126:abea610beb85 16 ; notice, this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 ; - Redistributions in binary form must reproduce the above copyright
AnnaBridge 126:abea610beb85 18 ; notice, this list of conditions and the following disclaimer in the
AnnaBridge 126:abea610beb85 19 ; documentation and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 ; - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 126:abea610beb85 21 ; to endorse or promote products derived from this software without
AnnaBridge 126:abea610beb85 22 ; specific prior written permission.
AnnaBridge 126:abea610beb85 23 ; *
AnnaBridge 126:abea610beb85 24 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 ; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 ; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 126:abea610beb85 27 ; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 126:abea610beb85 28 ; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 126:abea610beb85 29 ; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 126:abea610beb85 30 ; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 126:abea610beb85 31 ; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 126:abea610beb85 32 ; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 126:abea610beb85 33 ; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 126:abea610beb85 34 ; POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 35 ; ---------------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 36
AnnaBridge 126:abea610beb85 37 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 38 extern "C" {
AnnaBridge 126:abea610beb85 39 #endif
AnnaBridge 126:abea610beb85 40
AnnaBridge 126:abea610beb85 41 #ifndef _MMU_FUNC_H
AnnaBridge 126:abea610beb85 42 #define _MMU_FUNC_H
AnnaBridge 126:abea610beb85 43
AnnaBridge 126:abea610beb85 44 #define SECTION_DESCRIPTOR (0x2)
AnnaBridge 126:abea610beb85 45 #define SECTION_MASK (0xFFFFFFFC)
AnnaBridge 126:abea610beb85 46
AnnaBridge 126:abea610beb85 47 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 126:abea610beb85 48 #define SECTION_B_SHIFT (2)
AnnaBridge 126:abea610beb85 49 #define SECTION_C_SHIFT (3)
AnnaBridge 126:abea610beb85 50 #define SECTION_TEX0_SHIFT (12)
AnnaBridge 126:abea610beb85 51 #define SECTION_TEX1_SHIFT (13)
AnnaBridge 126:abea610beb85 52 #define SECTION_TEX2_SHIFT (14)
AnnaBridge 126:abea610beb85 53
AnnaBridge 126:abea610beb85 54 #define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge 126:abea610beb85 55 #define SECTION_XN_SHIFT (4)
AnnaBridge 126:abea610beb85 56
AnnaBridge 126:abea610beb85 57 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 126:abea610beb85 58 #define SECTION_DOMAIN_SHIFT (5)
AnnaBridge 126:abea610beb85 59
AnnaBridge 126:abea610beb85 60 #define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge 126:abea610beb85 61 #define SECTION_P_SHIFT (9)
AnnaBridge 126:abea610beb85 62
AnnaBridge 126:abea610beb85 63 #define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge 126:abea610beb85 64 #define SECTION_AP_SHIFT (10)
AnnaBridge 126:abea610beb85 65 #define SECTION_AP2_SHIFT (15)
AnnaBridge 126:abea610beb85 66
AnnaBridge 126:abea610beb85 67 #define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge 126:abea610beb85 68 #define SECTION_S_SHIFT (16)
AnnaBridge 126:abea610beb85 69
AnnaBridge 126:abea610beb85 70 #define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge 126:abea610beb85 71 #define SECTION_NG_SHIFT (17)
AnnaBridge 126:abea610beb85 72
AnnaBridge 126:abea610beb85 73 #define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge 126:abea610beb85 74 #define SECTION_NS_SHIFT (19)
AnnaBridge 126:abea610beb85 75
AnnaBridge 126:abea610beb85 76
AnnaBridge 126:abea610beb85 77 #define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge 126:abea610beb85 78 #define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge 126:abea610beb85 79
AnnaBridge 126:abea610beb85 80 #define PAGE_L2_4K_DESC (0x2)
AnnaBridge 126:abea610beb85 81 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge 126:abea610beb85 82
AnnaBridge 126:abea610beb85 83 #define PAGE_L2_64K_DESC (0x1)
AnnaBridge 126:abea610beb85 84 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge 126:abea610beb85 85
AnnaBridge 126:abea610beb85 86 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge 126:abea610beb85 87 #define PAGE_4K_B_SHIFT (2)
AnnaBridge 126:abea610beb85 88 #define PAGE_4K_C_SHIFT (3)
AnnaBridge 126:abea610beb85 89 #define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge 126:abea610beb85 90 #define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge 126:abea610beb85 91 #define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge 126:abea610beb85 92
AnnaBridge 126:abea610beb85 93 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 126:abea610beb85 94 #define PAGE_64K_B_SHIFT (2)
AnnaBridge 126:abea610beb85 95 #define PAGE_64K_C_SHIFT (3)
AnnaBridge 126:abea610beb85 96 #define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge 126:abea610beb85 97 #define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge 126:abea610beb85 98 #define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge 126:abea610beb85 99
AnnaBridge 126:abea610beb85 100 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge 126:abea610beb85 101 #define PAGE_B_SHIFT (2)
AnnaBridge 126:abea610beb85 102 #define PAGE_C_SHIFT (3)
AnnaBridge 126:abea610beb85 103 #define PAGE_TEX_SHIFT (12)
AnnaBridge 126:abea610beb85 104
AnnaBridge 126:abea610beb85 105 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge 126:abea610beb85 106 #define PAGE_XN_4K_SHIFT (0)
AnnaBridge 126:abea610beb85 107 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge 126:abea610beb85 108 #define PAGE_XN_64K_SHIFT (15)
AnnaBridge 126:abea610beb85 109
AnnaBridge 126:abea610beb85 110
AnnaBridge 126:abea610beb85 111 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge 126:abea610beb85 112 #define PAGE_DOMAIN_SHIFT (5)
AnnaBridge 126:abea610beb85 113
AnnaBridge 126:abea610beb85 114 #define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge 126:abea610beb85 115 #define PAGE_P_SHIFT (9)
AnnaBridge 126:abea610beb85 116
AnnaBridge 126:abea610beb85 117 #define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge 126:abea610beb85 118 #define PAGE_AP_SHIFT (4)
AnnaBridge 126:abea610beb85 119 #define PAGE_AP2_SHIFT (9)
AnnaBridge 126:abea610beb85 120
AnnaBridge 126:abea610beb85 121 #define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge 126:abea610beb85 122 #define PAGE_S_SHIFT (10)
AnnaBridge 126:abea610beb85 123
AnnaBridge 126:abea610beb85 124 #define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge 126:abea610beb85 125 #define PAGE_NG_SHIFT (11)
AnnaBridge 126:abea610beb85 126
AnnaBridge 126:abea610beb85 127 #define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge 126:abea610beb85 128 #define PAGE_NS_SHIFT (3)
AnnaBridge 126:abea610beb85 129
AnnaBridge 126:abea610beb85 130 #define OFFSET_1M (0x00100000)
AnnaBridge 126:abea610beb85 131 #define OFFSET_64K (0x00010000)
AnnaBridge 126:abea610beb85 132 #define OFFSET_4K (0x00001000)
AnnaBridge 126:abea610beb85 133
AnnaBridge 126:abea610beb85 134 #define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge 126:abea610beb85 135
AnnaBridge 126:abea610beb85 136 /* ########################### MMU Function Access ########################### */
AnnaBridge 126:abea610beb85 137 /** \ingroup MMU_FunctionInterface
AnnaBridge 126:abea610beb85 138 \defgroup MMU_Functions MMU Functions Interface
AnnaBridge 126:abea610beb85 139 @{
AnnaBridge 126:abea610beb85 140 */
AnnaBridge 126:abea610beb85 141
AnnaBridge 126:abea610beb85 142 /* Attributes enumerations */
AnnaBridge 126:abea610beb85 143
AnnaBridge 126:abea610beb85 144 /* Region size attributes */
AnnaBridge 126:abea610beb85 145 typedef enum
AnnaBridge 126:abea610beb85 146 {
AnnaBridge 126:abea610beb85 147 SECTION,
AnnaBridge 126:abea610beb85 148 PAGE_4k,
AnnaBridge 126:abea610beb85 149 PAGE_64k,
AnnaBridge 126:abea610beb85 150 } mmu_region_size_Type;
AnnaBridge 126:abea610beb85 151
AnnaBridge 126:abea610beb85 152 /* Region type attributes */
AnnaBridge 126:abea610beb85 153 typedef enum
AnnaBridge 126:abea610beb85 154 {
AnnaBridge 126:abea610beb85 155 NORMAL,
AnnaBridge 126:abea610beb85 156 DEVICE,
AnnaBridge 126:abea610beb85 157 SHARED_DEVICE,
AnnaBridge 126:abea610beb85 158 NON_SHARED_DEVICE,
AnnaBridge 126:abea610beb85 159 STRONGLY_ORDERED
AnnaBridge 126:abea610beb85 160 } mmu_memory_Type;
AnnaBridge 126:abea610beb85 161
AnnaBridge 126:abea610beb85 162 /* Region cacheability attributes */
AnnaBridge 126:abea610beb85 163 typedef enum
AnnaBridge 126:abea610beb85 164 {
AnnaBridge 126:abea610beb85 165 NON_CACHEABLE,
AnnaBridge 126:abea610beb85 166 WB_WA,
AnnaBridge 126:abea610beb85 167 WT,
AnnaBridge 126:abea610beb85 168 WB_NO_WA,
AnnaBridge 126:abea610beb85 169 } mmu_cacheability_Type;
AnnaBridge 126:abea610beb85 170
AnnaBridge 126:abea610beb85 171 /* Region parity check attributes */
AnnaBridge 126:abea610beb85 172 typedef enum
AnnaBridge 126:abea610beb85 173 {
AnnaBridge 126:abea610beb85 174 ECC_DISABLED,
AnnaBridge 126:abea610beb85 175 ECC_ENABLED,
AnnaBridge 126:abea610beb85 176 } mmu_ecc_check_Type;
AnnaBridge 126:abea610beb85 177
AnnaBridge 126:abea610beb85 178 /* Region execution attributes */
AnnaBridge 126:abea610beb85 179 typedef enum
AnnaBridge 126:abea610beb85 180 {
AnnaBridge 126:abea610beb85 181 EXECUTE,
AnnaBridge 126:abea610beb85 182 NON_EXECUTE,
AnnaBridge 126:abea610beb85 183 } mmu_execute_Type;
AnnaBridge 126:abea610beb85 184
AnnaBridge 126:abea610beb85 185 /* Region global attributes */
AnnaBridge 126:abea610beb85 186 typedef enum
AnnaBridge 126:abea610beb85 187 {
AnnaBridge 126:abea610beb85 188 GLOBAL,
AnnaBridge 126:abea610beb85 189 NON_GLOBAL,
AnnaBridge 126:abea610beb85 190 } mmu_global_Type;
AnnaBridge 126:abea610beb85 191
AnnaBridge 126:abea610beb85 192 /* Region shareability attributes */
AnnaBridge 126:abea610beb85 193 typedef enum
AnnaBridge 126:abea610beb85 194 {
AnnaBridge 126:abea610beb85 195 NON_SHARED,
AnnaBridge 126:abea610beb85 196 SHARED,
AnnaBridge 126:abea610beb85 197 } mmu_shared_Type;
AnnaBridge 126:abea610beb85 198
AnnaBridge 126:abea610beb85 199 /* Region security attributes */
AnnaBridge 126:abea610beb85 200 typedef enum
AnnaBridge 126:abea610beb85 201 {
AnnaBridge 126:abea610beb85 202 SECURE,
AnnaBridge 126:abea610beb85 203 NON_SECURE,
AnnaBridge 126:abea610beb85 204 } mmu_secure_Type;
AnnaBridge 126:abea610beb85 205
AnnaBridge 126:abea610beb85 206 /* Region access attributes */
AnnaBridge 126:abea610beb85 207 typedef enum
AnnaBridge 126:abea610beb85 208 {
AnnaBridge 126:abea610beb85 209 NO_ACCESS,
AnnaBridge 126:abea610beb85 210 RW,
AnnaBridge 126:abea610beb85 211 READ,
AnnaBridge 126:abea610beb85 212 } mmu_access_Type;
AnnaBridge 126:abea610beb85 213
AnnaBridge 126:abea610beb85 214 /* Memory Region definition */
AnnaBridge 126:abea610beb85 215 typedef struct RegionStruct {
AnnaBridge 126:abea610beb85 216 mmu_region_size_Type rg_t;
AnnaBridge 126:abea610beb85 217 mmu_memory_Type mem_t;
AnnaBridge 126:abea610beb85 218 uint8_t domain;
AnnaBridge 126:abea610beb85 219 mmu_cacheability_Type inner_norm_t;
AnnaBridge 126:abea610beb85 220 mmu_cacheability_Type outer_norm_t;
AnnaBridge 126:abea610beb85 221 mmu_ecc_check_Type e_t;
AnnaBridge 126:abea610beb85 222 mmu_execute_Type xn_t;
AnnaBridge 126:abea610beb85 223 mmu_global_Type g_t;
AnnaBridge 126:abea610beb85 224 mmu_secure_Type sec_t;
AnnaBridge 126:abea610beb85 225 mmu_access_Type priv_t;
AnnaBridge 126:abea610beb85 226 mmu_access_Type user_t;
AnnaBridge 126:abea610beb85 227 mmu_shared_Type sh_t;
AnnaBridge 126:abea610beb85 228
AnnaBridge 126:abea610beb85 229 } mmu_region_attributes_Type;
AnnaBridge 126:abea610beb85 230
AnnaBridge 126:abea610beb85 231 /** \brief Set section execution-never attribute
AnnaBridge 126:abea610beb85 232
AnnaBridge 126:abea610beb85 233 The function sets section execution-never attribute
AnnaBridge 126:abea610beb85 234
AnnaBridge 126:abea610beb85 235 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 236 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 126:abea610beb85 237
AnnaBridge 126:abea610beb85 238 \return 0
AnnaBridge 126:abea610beb85 239 */
AnnaBridge 126:abea610beb85 240 __STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge 126:abea610beb85 241 {
AnnaBridge 126:abea610beb85 242 *descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge 126:abea610beb85 243 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge 126:abea610beb85 244 return 0;
AnnaBridge 126:abea610beb85 245 }
AnnaBridge 126:abea610beb85 246
AnnaBridge 126:abea610beb85 247 /** \brief Set section domain
AnnaBridge 126:abea610beb85 248
AnnaBridge 126:abea610beb85 249 The function sets section domain
AnnaBridge 126:abea610beb85 250
AnnaBridge 126:abea610beb85 251 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 252 \param [in] domain Section domain
AnnaBridge 126:abea610beb85 253
AnnaBridge 126:abea610beb85 254 \return 0
AnnaBridge 126:abea610beb85 255 */
AnnaBridge 126:abea610beb85 256 __STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 126:abea610beb85 257 {
AnnaBridge 126:abea610beb85 258 *descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge 126:abea610beb85 259 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge 126:abea610beb85 260 return 0;
AnnaBridge 126:abea610beb85 261 }
AnnaBridge 126:abea610beb85 262
AnnaBridge 126:abea610beb85 263 /** \brief Set section parity check
AnnaBridge 126:abea610beb85 264
AnnaBridge 126:abea610beb85 265 The function sets section parity check
AnnaBridge 126:abea610beb85 266
AnnaBridge 126:abea610beb85 267 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 268 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 126:abea610beb85 269
AnnaBridge 126:abea610beb85 270 \return 0
AnnaBridge 126:abea610beb85 271 */
AnnaBridge 126:abea610beb85 272 __STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 126:abea610beb85 273 {
AnnaBridge 126:abea610beb85 274 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 126:abea610beb85 275 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 126:abea610beb85 276 return 0;
AnnaBridge 126:abea610beb85 277 }
AnnaBridge 126:abea610beb85 278
AnnaBridge 126:abea610beb85 279 /** \brief Set section access privileges
AnnaBridge 126:abea610beb85 280
AnnaBridge 126:abea610beb85 281 The function sets section access privileges
AnnaBridge 126:abea610beb85 282
AnnaBridge 126:abea610beb85 283 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 284 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 126:abea610beb85 285 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 126:abea610beb85 286 \param [in] afe Access flag enable
AnnaBridge 126:abea610beb85 287
AnnaBridge 126:abea610beb85 288 \return 0
AnnaBridge 126:abea610beb85 289 */
AnnaBridge 126:abea610beb85 290 __STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 126:abea610beb85 291 {
AnnaBridge 126:abea610beb85 292 uint32_t ap = 0;
AnnaBridge 126:abea610beb85 293
AnnaBridge 126:abea610beb85 294 if (afe == 0) { //full access
AnnaBridge 126:abea610beb85 295 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 126:abea610beb85 296 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 126:abea610beb85 297 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 126:abea610beb85 298 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 126:abea610beb85 299 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 126:abea610beb85 300 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 126:abea610beb85 301 }
AnnaBridge 126:abea610beb85 302
AnnaBridge 126:abea610beb85 303 else { //Simplified access
AnnaBridge 126:abea610beb85 304 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 126:abea610beb85 305 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 126:abea610beb85 306 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 126:abea610beb85 307 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 126:abea610beb85 308 }
AnnaBridge 126:abea610beb85 309
AnnaBridge 126:abea610beb85 310 *descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge 126:abea610beb85 311 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge 126:abea610beb85 312 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge 126:abea610beb85 313
AnnaBridge 126:abea610beb85 314 return 0;
AnnaBridge 126:abea610beb85 315 }
AnnaBridge 126:abea610beb85 316
AnnaBridge 126:abea610beb85 317 /** \brief Set section shareability
AnnaBridge 126:abea610beb85 318
AnnaBridge 126:abea610beb85 319 The function sets section shareability
AnnaBridge 126:abea610beb85 320
AnnaBridge 126:abea610beb85 321 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 322 \param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge 126:abea610beb85 323
AnnaBridge 126:abea610beb85 324 \return 0
AnnaBridge 126:abea610beb85 325 */
AnnaBridge 126:abea610beb85 326 __STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge 126:abea610beb85 327 {
AnnaBridge 126:abea610beb85 328 *descriptor_l1 &= SECTION_S_MASK;
AnnaBridge 126:abea610beb85 329 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge 126:abea610beb85 330 return 0;
AnnaBridge 126:abea610beb85 331 }
AnnaBridge 126:abea610beb85 332
AnnaBridge 126:abea610beb85 333 /** \brief Set section Global attribute
AnnaBridge 126:abea610beb85 334
AnnaBridge 126:abea610beb85 335 The function sets section Global attribute
AnnaBridge 126:abea610beb85 336
AnnaBridge 126:abea610beb85 337 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 338 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge 126:abea610beb85 339
AnnaBridge 126:abea610beb85 340 \return 0
AnnaBridge 126:abea610beb85 341 */
AnnaBridge 126:abea610beb85 342 __STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge 126:abea610beb85 343 {
AnnaBridge 126:abea610beb85 344 *descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge 126:abea610beb85 345 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge 126:abea610beb85 346 return 0;
AnnaBridge 126:abea610beb85 347 }
AnnaBridge 126:abea610beb85 348
AnnaBridge 126:abea610beb85 349 /** \brief Set section Security attribute
AnnaBridge 126:abea610beb85 350
AnnaBridge 126:abea610beb85 351 The function sets section Global attribute
AnnaBridge 126:abea610beb85 352
AnnaBridge 126:abea610beb85 353 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 354 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge 126:abea610beb85 355
AnnaBridge 126:abea610beb85 356 \return 0
AnnaBridge 126:abea610beb85 357 */
AnnaBridge 126:abea610beb85 358 __STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 126:abea610beb85 359 {
AnnaBridge 126:abea610beb85 360 *descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge 126:abea610beb85 361 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge 126:abea610beb85 362 return 0;
AnnaBridge 126:abea610beb85 363 }
AnnaBridge 126:abea610beb85 364
AnnaBridge 126:abea610beb85 365 /* Page 4k or 64k */
AnnaBridge 126:abea610beb85 366 /** \brief Set 4k/64k page execution-never attribute
AnnaBridge 126:abea610beb85 367
AnnaBridge 126:abea610beb85 368 The function sets 4k/64k page execution-never attribute
AnnaBridge 126:abea610beb85 369
AnnaBridge 126:abea610beb85 370 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 126:abea610beb85 371 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge 126:abea610beb85 372 \param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge 126:abea610beb85 373
AnnaBridge 126:abea610beb85 374 \return 0
AnnaBridge 126:abea610beb85 375 */
AnnaBridge 126:abea610beb85 376 __STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge 126:abea610beb85 377 {
AnnaBridge 126:abea610beb85 378 if (page == PAGE_4k)
AnnaBridge 126:abea610beb85 379 {
AnnaBridge 126:abea610beb85 380 *descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge 126:abea610beb85 381 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge 126:abea610beb85 382 }
AnnaBridge 126:abea610beb85 383 else
AnnaBridge 126:abea610beb85 384 {
AnnaBridge 126:abea610beb85 385 *descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge 126:abea610beb85 386 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge 126:abea610beb85 387 }
AnnaBridge 126:abea610beb85 388 return 0;
AnnaBridge 126:abea610beb85 389 }
AnnaBridge 126:abea610beb85 390
AnnaBridge 126:abea610beb85 391 /** \brief Set 4k/64k page domain
AnnaBridge 126:abea610beb85 392
AnnaBridge 126:abea610beb85 393 The function sets 4k/64k page domain
AnnaBridge 126:abea610beb85 394
AnnaBridge 126:abea610beb85 395 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 396 \param [in] domain Page domain
AnnaBridge 126:abea610beb85 397
AnnaBridge 126:abea610beb85 398 \return 0
AnnaBridge 126:abea610beb85 399 */
AnnaBridge 126:abea610beb85 400 __STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge 126:abea610beb85 401 {
AnnaBridge 126:abea610beb85 402 *descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge 126:abea610beb85 403 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge 126:abea610beb85 404 return 0;
AnnaBridge 126:abea610beb85 405 }
AnnaBridge 126:abea610beb85 406
AnnaBridge 126:abea610beb85 407 /** \brief Set 4k/64k page parity check
AnnaBridge 126:abea610beb85 408
AnnaBridge 126:abea610beb85 409 The function sets 4k/64k page parity check
AnnaBridge 126:abea610beb85 410
AnnaBridge 126:abea610beb85 411 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 412 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge 126:abea610beb85 413
AnnaBridge 126:abea610beb85 414 \return 0
AnnaBridge 126:abea610beb85 415 */
AnnaBridge 126:abea610beb85 416 __STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge 126:abea610beb85 417 {
AnnaBridge 126:abea610beb85 418 *descriptor_l1 &= SECTION_P_MASK;
AnnaBridge 126:abea610beb85 419 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge 126:abea610beb85 420 return 0;
AnnaBridge 126:abea610beb85 421 }
AnnaBridge 126:abea610beb85 422
AnnaBridge 126:abea610beb85 423 /** \brief Set 4k/64k page access privileges
AnnaBridge 126:abea610beb85 424
AnnaBridge 126:abea610beb85 425 The function sets 4k/64k page access privileges
AnnaBridge 126:abea610beb85 426
AnnaBridge 126:abea610beb85 427 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 126:abea610beb85 428 \param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge 126:abea610beb85 429 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge 126:abea610beb85 430 \param [in] afe Access flag enable
AnnaBridge 126:abea610beb85 431
AnnaBridge 126:abea610beb85 432 \return 0
AnnaBridge 126:abea610beb85 433 */
AnnaBridge 126:abea610beb85 434 __STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge 126:abea610beb85 435 {
AnnaBridge 126:abea610beb85 436 uint32_t ap = 0;
AnnaBridge 126:abea610beb85 437
AnnaBridge 126:abea610beb85 438 if (afe == 0) { //full access
AnnaBridge 126:abea610beb85 439 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge 126:abea610beb85 440 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 126:abea610beb85 441 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge 126:abea610beb85 442 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 126:abea610beb85 443 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 126:abea610beb85 444 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge 126:abea610beb85 445 }
AnnaBridge 126:abea610beb85 446
AnnaBridge 126:abea610beb85 447 else { //Simplified access
AnnaBridge 126:abea610beb85 448 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge 126:abea610beb85 449 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge 126:abea610beb85 450 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge 126:abea610beb85 451 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge 126:abea610beb85 452 }
AnnaBridge 126:abea610beb85 453
AnnaBridge 126:abea610beb85 454 *descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge 126:abea610beb85 455 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge 126:abea610beb85 456 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge 126:abea610beb85 457
AnnaBridge 126:abea610beb85 458 return 0;
AnnaBridge 126:abea610beb85 459 }
AnnaBridge 126:abea610beb85 460
AnnaBridge 126:abea610beb85 461 /** \brief Set 4k/64k page shareability
AnnaBridge 126:abea610beb85 462
AnnaBridge 126:abea610beb85 463 The function sets 4k/64k page shareability
AnnaBridge 126:abea610beb85 464
AnnaBridge 126:abea610beb85 465 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 126:abea610beb85 466 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge 126:abea610beb85 467
AnnaBridge 126:abea610beb85 468 \return 0
AnnaBridge 126:abea610beb85 469 */
AnnaBridge 126:abea610beb85 470 __STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge 126:abea610beb85 471 {
AnnaBridge 126:abea610beb85 472 *descriptor_l2 &= PAGE_S_MASK;
AnnaBridge 126:abea610beb85 473 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge 126:abea610beb85 474 return 0;
AnnaBridge 126:abea610beb85 475 }
AnnaBridge 126:abea610beb85 476
AnnaBridge 126:abea610beb85 477 /** \brief Set 4k/64k page Global attribute
AnnaBridge 126:abea610beb85 478
AnnaBridge 126:abea610beb85 479 The function sets 4k/64k page Global attribute
AnnaBridge 126:abea610beb85 480
AnnaBridge 126:abea610beb85 481 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 126:abea610beb85 482 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge 126:abea610beb85 483
AnnaBridge 126:abea610beb85 484 \return 0
AnnaBridge 126:abea610beb85 485 */
AnnaBridge 126:abea610beb85 486 __STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge 126:abea610beb85 487 {
AnnaBridge 126:abea610beb85 488 *descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge 126:abea610beb85 489 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge 126:abea610beb85 490 return 0;
AnnaBridge 126:abea610beb85 491 }
AnnaBridge 126:abea610beb85 492
AnnaBridge 126:abea610beb85 493 /** \brief Set 4k/64k page Security attribute
AnnaBridge 126:abea610beb85 494
AnnaBridge 126:abea610beb85 495 The function sets 4k/64k page Global attribute
AnnaBridge 126:abea610beb85 496
AnnaBridge 126:abea610beb85 497 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 498 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge 126:abea610beb85 499
AnnaBridge 126:abea610beb85 500 \return 0
AnnaBridge 126:abea610beb85 501 */
AnnaBridge 126:abea610beb85 502 __STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge 126:abea610beb85 503 {
AnnaBridge 126:abea610beb85 504 *descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge 126:abea610beb85 505 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge 126:abea610beb85 506 return 0;
AnnaBridge 126:abea610beb85 507 }
AnnaBridge 126:abea610beb85 508
AnnaBridge 126:abea610beb85 509
AnnaBridge 126:abea610beb85 510 /** \brief Set Section memory attributes
AnnaBridge 126:abea610beb85 511
AnnaBridge 126:abea610beb85 512 The function sets section memory attributes
AnnaBridge 126:abea610beb85 513
AnnaBridge 126:abea610beb85 514 \param [out] descriptor_l1 L1 descriptor.
AnnaBridge 126:abea610beb85 515 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 126:abea610beb85 516 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 126:abea610beb85 517 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 126:abea610beb85 518
AnnaBridge 126:abea610beb85 519 \return 0
AnnaBridge 126:abea610beb85 520 */
AnnaBridge 126:abea610beb85 521 __STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge 126:abea610beb85 522 {
AnnaBridge 126:abea610beb85 523 *descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge 126:abea610beb85 524
AnnaBridge 126:abea610beb85 525 if (STRONGLY_ORDERED == mem)
AnnaBridge 126:abea610beb85 526 {
AnnaBridge 126:abea610beb85 527 return 0;
AnnaBridge 126:abea610beb85 528 }
AnnaBridge 126:abea610beb85 529 else if (SHARED_DEVICE == mem)
AnnaBridge 126:abea610beb85 530 {
AnnaBridge 126:abea610beb85 531 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 126:abea610beb85 532 }
AnnaBridge 126:abea610beb85 533 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 126:abea610beb85 534 {
AnnaBridge 126:abea610beb85 535 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
AnnaBridge 126:abea610beb85 536 }
AnnaBridge 126:abea610beb85 537 else if (NORMAL == mem)
AnnaBridge 126:abea610beb85 538 {
AnnaBridge 126:abea610beb85 539 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
AnnaBridge 126:abea610beb85 540 switch(inner)
AnnaBridge 126:abea610beb85 541 {
AnnaBridge 126:abea610beb85 542 case NON_CACHEABLE:
AnnaBridge 126:abea610beb85 543 break;
AnnaBridge 126:abea610beb85 544 case WB_WA:
AnnaBridge 126:abea610beb85 545 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
AnnaBridge 126:abea610beb85 546 break;
AnnaBridge 126:abea610beb85 547 case WT:
AnnaBridge 126:abea610beb85 548 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
AnnaBridge 126:abea610beb85 549 break;
AnnaBridge 126:abea610beb85 550 case WB_NO_WA:
AnnaBridge 126:abea610beb85 551 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
AnnaBridge 126:abea610beb85 552 break;
AnnaBridge 126:abea610beb85 553 }
AnnaBridge 126:abea610beb85 554 switch(outer)
AnnaBridge 126:abea610beb85 555 {
AnnaBridge 126:abea610beb85 556 case NON_CACHEABLE:
AnnaBridge 126:abea610beb85 557 break;
AnnaBridge 126:abea610beb85 558 case WB_WA:
AnnaBridge 126:abea610beb85 559 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
AnnaBridge 126:abea610beb85 560 break;
AnnaBridge 126:abea610beb85 561 case WT:
AnnaBridge 126:abea610beb85 562 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
AnnaBridge 126:abea610beb85 563 break;
AnnaBridge 126:abea610beb85 564 case WB_NO_WA:
AnnaBridge 126:abea610beb85 565 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
AnnaBridge 126:abea610beb85 566 break;
AnnaBridge 126:abea610beb85 567 }
AnnaBridge 126:abea610beb85 568 }
AnnaBridge 126:abea610beb85 569
AnnaBridge 126:abea610beb85 570 return 0;
AnnaBridge 126:abea610beb85 571 }
AnnaBridge 126:abea610beb85 572
AnnaBridge 126:abea610beb85 573 /** \brief Set 4k/64k page memory attributes
AnnaBridge 126:abea610beb85 574
AnnaBridge 126:abea610beb85 575 The function sets 4k/64k page memory attributes
AnnaBridge 126:abea610beb85 576
AnnaBridge 126:abea610beb85 577 \param [out] descriptor_l2 L2 descriptor.
AnnaBridge 126:abea610beb85 578 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge 126:abea610beb85 579 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 126:abea610beb85 580 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge 126:abea610beb85 581
AnnaBridge 126:abea610beb85 582 \return 0
AnnaBridge 126:abea610beb85 583 */
AnnaBridge 126:abea610beb85 584 __STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge 126:abea610beb85 585 {
AnnaBridge 126:abea610beb85 586 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge 126:abea610beb85 587
AnnaBridge 126:abea610beb85 588 if (page == PAGE_64k)
AnnaBridge 126:abea610beb85 589 {
AnnaBridge 126:abea610beb85 590 //same as section
AnnaBridge 126:abea610beb85 591 __memory_section(descriptor_l2, mem, outer, inner);
AnnaBridge 126:abea610beb85 592 }
AnnaBridge 126:abea610beb85 593 else
AnnaBridge 126:abea610beb85 594 {
AnnaBridge 126:abea610beb85 595 if (STRONGLY_ORDERED == mem)
AnnaBridge 126:abea610beb85 596 {
AnnaBridge 126:abea610beb85 597 return 0;
AnnaBridge 126:abea610beb85 598 }
AnnaBridge 126:abea610beb85 599 else if (SHARED_DEVICE == mem)
AnnaBridge 126:abea610beb85 600 {
AnnaBridge 126:abea610beb85 601 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 126:abea610beb85 602 }
AnnaBridge 126:abea610beb85 603 else if (NON_SHARED_DEVICE == mem)
AnnaBridge 126:abea610beb85 604 {
AnnaBridge 126:abea610beb85 605 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge 126:abea610beb85 606 }
AnnaBridge 126:abea610beb85 607 else if (NORMAL == mem)
AnnaBridge 126:abea610beb85 608 {
AnnaBridge 126:abea610beb85 609 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge 126:abea610beb85 610 switch(inner)
AnnaBridge 126:abea610beb85 611 {
AnnaBridge 126:abea610beb85 612 case NON_CACHEABLE:
AnnaBridge 126:abea610beb85 613 break;
AnnaBridge 126:abea610beb85 614 case WB_WA:
AnnaBridge 126:abea610beb85 615 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
AnnaBridge 126:abea610beb85 616 break;
AnnaBridge 126:abea610beb85 617 case WT:
AnnaBridge 126:abea610beb85 618 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
AnnaBridge 126:abea610beb85 619 break;
AnnaBridge 126:abea610beb85 620 case WB_NO_WA:
AnnaBridge 126:abea610beb85 621 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
AnnaBridge 126:abea610beb85 622 break;
AnnaBridge 126:abea610beb85 623 }
AnnaBridge 126:abea610beb85 624 switch(outer)
AnnaBridge 126:abea610beb85 625 {
AnnaBridge 126:abea610beb85 626 case NON_CACHEABLE:
AnnaBridge 126:abea610beb85 627 break;
AnnaBridge 126:abea610beb85 628 case WB_WA:
AnnaBridge 126:abea610beb85 629 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 126:abea610beb85 630 break;
AnnaBridge 126:abea610beb85 631 case WT:
AnnaBridge 126:abea610beb85 632 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge 126:abea610beb85 633 break;
AnnaBridge 126:abea610beb85 634 case WB_NO_WA:
AnnaBridge 126:abea610beb85 635 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge 126:abea610beb85 636 break;
AnnaBridge 126:abea610beb85 637 }
AnnaBridge 126:abea610beb85 638 }
AnnaBridge 126:abea610beb85 639 }
AnnaBridge 126:abea610beb85 640
AnnaBridge 126:abea610beb85 641 return 0;
AnnaBridge 126:abea610beb85 642 }
AnnaBridge 126:abea610beb85 643
AnnaBridge 126:abea610beb85 644 /** \brief Create a L1 section descriptor
AnnaBridge 126:abea610beb85 645
AnnaBridge 126:abea610beb85 646 The function creates a section descriptor.
AnnaBridge 126:abea610beb85 647
AnnaBridge 126:abea610beb85 648 Assumptions:
AnnaBridge 126:abea610beb85 649 - 16MB super sections not supported
AnnaBridge 126:abea610beb85 650 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
AnnaBridge 126:abea610beb85 651 - Functions always return 0
AnnaBridge 126:abea610beb85 652
AnnaBridge 126:abea610beb85 653 \param [out] descriptor L1 descriptor
AnnaBridge 126:abea610beb85 654 \param [out] descriptor2 L2 descriptor
AnnaBridge 126:abea610beb85 655 \param [in] reg Section attributes
AnnaBridge 126:abea610beb85 656
AnnaBridge 126:abea610beb85 657 \return 0
AnnaBridge 126:abea610beb85 658 */
AnnaBridge 126:abea610beb85 659 __STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge 126:abea610beb85 660 {
AnnaBridge 126:abea610beb85 661 *descriptor = 0;
AnnaBridge 126:abea610beb85 662
AnnaBridge 126:abea610beb85 663 __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge 126:abea610beb85 664 __xn_section(descriptor,reg.xn_t);
AnnaBridge 126:abea610beb85 665 __domain_section(descriptor, reg.domain);
AnnaBridge 126:abea610beb85 666 __p_section(descriptor, reg.e_t);
AnnaBridge 126:abea610beb85 667 __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge 126:abea610beb85 668 __shared_section(descriptor,reg.sh_t);
AnnaBridge 126:abea610beb85 669 __global_section(descriptor,reg.g_t);
AnnaBridge 126:abea610beb85 670 __secure_section(descriptor,reg.sec_t);
AnnaBridge 126:abea610beb85 671 *descriptor &= SECTION_MASK;
AnnaBridge 126:abea610beb85 672 *descriptor |= SECTION_DESCRIPTOR;
AnnaBridge 126:abea610beb85 673
AnnaBridge 126:abea610beb85 674 return 0;
AnnaBridge 126:abea610beb85 675
AnnaBridge 126:abea610beb85 676 }
AnnaBridge 126:abea610beb85 677
AnnaBridge 126:abea610beb85 678
AnnaBridge 126:abea610beb85 679 /** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge 126:abea610beb85 680
AnnaBridge 126:abea610beb85 681 The function creates a 4k/64k page descriptor.
AnnaBridge 126:abea610beb85 682 Assumptions:
AnnaBridge 126:abea610beb85 683 - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
AnnaBridge 126:abea610beb85 684 - Functions always return 0
AnnaBridge 126:abea610beb85 685
AnnaBridge 126:abea610beb85 686 \param [out] descriptor L1 descriptor
AnnaBridge 126:abea610beb85 687 \param [out] descriptor2 L2 descriptor
AnnaBridge 126:abea610beb85 688 \param [in] reg 4k/64k page attributes
AnnaBridge 126:abea610beb85 689
AnnaBridge 126:abea610beb85 690 \return 0
AnnaBridge 126:abea610beb85 691 */
AnnaBridge 126:abea610beb85 692 __STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
AnnaBridge 126:abea610beb85 693 {
AnnaBridge 126:abea610beb85 694 *descriptor = 0;
AnnaBridge 126:abea610beb85 695 *descriptor2 = 0;
AnnaBridge 126:abea610beb85 696
AnnaBridge 126:abea610beb85 697 switch (reg.rg_t)
AnnaBridge 126:abea610beb85 698 {
AnnaBridge 126:abea610beb85 699 case PAGE_4k:
AnnaBridge 126:abea610beb85 700 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge 126:abea610beb85 701 __xn_page(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge 126:abea610beb85 702 __domain_page(descriptor, reg.domain);
AnnaBridge 126:abea610beb85 703 __p_page(descriptor, reg.e_t);
AnnaBridge 126:abea610beb85 704 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 126:abea610beb85 705 __shared_page(descriptor2,reg.sh_t);
AnnaBridge 126:abea610beb85 706 __global_page(descriptor2,reg.g_t);
AnnaBridge 126:abea610beb85 707 __secure_page(descriptor,reg.sec_t);
AnnaBridge 126:abea610beb85 708 *descriptor &= PAGE_L1_MASK;
AnnaBridge 126:abea610beb85 709 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 126:abea610beb85 710 *descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge 126:abea610beb85 711 *descriptor2 |= PAGE_L2_4K_DESC;
AnnaBridge 126:abea610beb85 712 break;
AnnaBridge 126:abea610beb85 713
AnnaBridge 126:abea610beb85 714 case PAGE_64k:
AnnaBridge 126:abea610beb85 715 __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge 126:abea610beb85 716 __xn_page(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge 126:abea610beb85 717 __domain_page(descriptor, reg.domain);
AnnaBridge 126:abea610beb85 718 __p_page(descriptor, reg.e_t);
AnnaBridge 126:abea610beb85 719 __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge 126:abea610beb85 720 __shared_page(descriptor2,reg.sh_t);
AnnaBridge 126:abea610beb85 721 __global_page(descriptor2,reg.g_t);
AnnaBridge 126:abea610beb85 722 __secure_page(descriptor,reg.sec_t);
AnnaBridge 126:abea610beb85 723 *descriptor &= PAGE_L1_MASK;
AnnaBridge 126:abea610beb85 724 *descriptor |= PAGE_L1_DESCRIPTOR;
AnnaBridge 126:abea610beb85 725 *descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge 126:abea610beb85 726 *descriptor2 |= PAGE_L2_64K_DESC;
AnnaBridge 126:abea610beb85 727 break;
AnnaBridge 126:abea610beb85 728
AnnaBridge 126:abea610beb85 729 case SECTION:
AnnaBridge 126:abea610beb85 730 //error
AnnaBridge 126:abea610beb85 731 break;
AnnaBridge 126:abea610beb85 732
AnnaBridge 126:abea610beb85 733 }
AnnaBridge 126:abea610beb85 734
AnnaBridge 126:abea610beb85 735 return 0;
AnnaBridge 126:abea610beb85 736
AnnaBridge 126:abea610beb85 737 }
AnnaBridge 126:abea610beb85 738
AnnaBridge 126:abea610beb85 739 /** \brief Create a 1MB Section
AnnaBridge 126:abea610beb85 740
AnnaBridge 126:abea610beb85 741 \param [in] ttb Translation table base address
AnnaBridge 126:abea610beb85 742 \param [in] base_address Section base address
AnnaBridge 126:abea610beb85 743 \param [in] count Number of sections to create
AnnaBridge 126:abea610beb85 744 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 126:abea610beb85 745
AnnaBridge 126:abea610beb85 746 */
AnnaBridge 126:abea610beb85 747 __STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge 126:abea610beb85 748 {
AnnaBridge 126:abea610beb85 749 uint32_t offset;
AnnaBridge 126:abea610beb85 750 uint32_t entry;
AnnaBridge 126:abea610beb85 751 uint32_t i;
AnnaBridge 126:abea610beb85 752
AnnaBridge 126:abea610beb85 753 offset = base_address >> 20;
AnnaBridge 126:abea610beb85 754 entry = (base_address & 0xFFF00000) | descriptor_l1;
AnnaBridge 126:abea610beb85 755
AnnaBridge 126:abea610beb85 756 //4 bytes aligned
AnnaBridge 126:abea610beb85 757 ttb = ttb + offset;
AnnaBridge 126:abea610beb85 758
AnnaBridge 126:abea610beb85 759 for (i = 0; i < count; i++ )
AnnaBridge 126:abea610beb85 760 {
AnnaBridge 126:abea610beb85 761 //4 bytes aligned
AnnaBridge 126:abea610beb85 762 *ttb++ = entry;
AnnaBridge 126:abea610beb85 763 entry += OFFSET_1M;
AnnaBridge 126:abea610beb85 764 }
AnnaBridge 126:abea610beb85 765 }
AnnaBridge 126:abea610beb85 766
AnnaBridge 126:abea610beb85 767 /** \brief Create a 4k page entry
AnnaBridge 126:abea610beb85 768
AnnaBridge 126:abea610beb85 769 \param [in] ttb L1 table base address
AnnaBridge 126:abea610beb85 770 \param [in] base_address 4k base address
AnnaBridge 126:abea610beb85 771 \param [in] count Number of 4k pages to create
AnnaBridge 126:abea610beb85 772 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 126:abea610beb85 773 \param [in] ttb_l2 L2 table base address
AnnaBridge 126:abea610beb85 774 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 126:abea610beb85 775
AnnaBridge 126:abea610beb85 776 */
AnnaBridge 126:abea610beb85 777 __STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 126:abea610beb85 778 {
AnnaBridge 126:abea610beb85 779
AnnaBridge 126:abea610beb85 780 uint32_t offset, offset2;
AnnaBridge 126:abea610beb85 781 uint32_t entry, entry2;
AnnaBridge 126:abea610beb85 782 uint32_t i;
AnnaBridge 126:abea610beb85 783
AnnaBridge 126:abea610beb85 784
AnnaBridge 126:abea610beb85 785 offset = base_address >> 20;
AnnaBridge 126:abea610beb85 786 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 126:abea610beb85 787
AnnaBridge 126:abea610beb85 788 //4 bytes aligned
AnnaBridge 126:abea610beb85 789 ttb += offset;
AnnaBridge 126:abea610beb85 790 //create l1_entry
AnnaBridge 126:abea610beb85 791 *ttb = entry;
AnnaBridge 126:abea610beb85 792
AnnaBridge 126:abea610beb85 793 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 126:abea610beb85 794 ttb_l2 += offset2;
AnnaBridge 126:abea610beb85 795 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
AnnaBridge 126:abea610beb85 796 for (i = 0; i < count; i++ )
AnnaBridge 126:abea610beb85 797 {
AnnaBridge 126:abea610beb85 798 //4 bytes aligned
AnnaBridge 126:abea610beb85 799 *ttb_l2++ = entry2;
AnnaBridge 126:abea610beb85 800 entry2 += OFFSET_4K;
AnnaBridge 126:abea610beb85 801 }
AnnaBridge 126:abea610beb85 802 }
AnnaBridge 126:abea610beb85 803
AnnaBridge 126:abea610beb85 804 /** \brief Create a 64k page entry
AnnaBridge 126:abea610beb85 805
AnnaBridge 126:abea610beb85 806 \param [in] ttb L1 table base address
AnnaBridge 126:abea610beb85 807 \param [in] base_address 64k base address
AnnaBridge 126:abea610beb85 808 \param [in] count Number of 64k pages to create
AnnaBridge 126:abea610beb85 809 \param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge 126:abea610beb85 810 \param [in] ttb_l2 L2 table base address
AnnaBridge 126:abea610beb85 811 \param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge 126:abea610beb85 812
AnnaBridge 126:abea610beb85 813 */
AnnaBridge 126:abea610beb85 814 __STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
AnnaBridge 126:abea610beb85 815 {
AnnaBridge 126:abea610beb85 816 uint32_t offset, offset2;
AnnaBridge 126:abea610beb85 817 uint32_t entry, entry2;
AnnaBridge 126:abea610beb85 818 uint32_t i,j;
AnnaBridge 126:abea610beb85 819
AnnaBridge 126:abea610beb85 820
AnnaBridge 126:abea610beb85 821 offset = base_address >> 20;
AnnaBridge 126:abea610beb85 822 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
AnnaBridge 126:abea610beb85 823
AnnaBridge 126:abea610beb85 824 //4 bytes aligned
AnnaBridge 126:abea610beb85 825 ttb += offset;
AnnaBridge 126:abea610beb85 826 //create l1_entry
AnnaBridge 126:abea610beb85 827 *ttb = entry;
AnnaBridge 126:abea610beb85 828
AnnaBridge 126:abea610beb85 829 offset2 = (base_address & 0xff000) >> 12;
AnnaBridge 126:abea610beb85 830 ttb_l2 += offset2;
AnnaBridge 126:abea610beb85 831 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
AnnaBridge 126:abea610beb85 832 for (i = 0; i < count; i++ )
AnnaBridge 126:abea610beb85 833 {
AnnaBridge 126:abea610beb85 834 //create 16 entries
AnnaBridge 126:abea610beb85 835 for (j = 0; j < 16; j++)
AnnaBridge 126:abea610beb85 836 //4 bytes aligned
AnnaBridge 126:abea610beb85 837 *ttb_l2++ = entry2;
AnnaBridge 126:abea610beb85 838 entry2 += OFFSET_64K;
AnnaBridge 126:abea610beb85 839 }
AnnaBridge 126:abea610beb85 840 }
AnnaBridge 126:abea610beb85 841
AnnaBridge 126:abea610beb85 842 /*@} end of MMU_Functions */
AnnaBridge 126:abea610beb85 843 #endif
AnnaBridge 126:abea610beb85 844
AnnaBridge 126:abea610beb85 845 #ifdef __cplusplus
AnnaBridge 126:abea610beb85 846 }
AnnaBridge 126:abea610beb85 847 #endif