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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MTM_MTCONNECT04S/core_caFunc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
130:d75b3fe1f5cb 
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 126:abea610beb85 1 /**************************************************************************//**
AnnaBridge 126:abea610beb85 2 * @file core_caFunc.h
AnnaBridge 126:abea610beb85 3 * @brief CMSIS Cortex-A Core Function Access Header File
AnnaBridge 126:abea610beb85 4 * @version V3.10
AnnaBridge 126:abea610beb85 5 * @date 30 Oct 2013
AnnaBridge 126:abea610beb85 6 *
AnnaBridge 126:abea610beb85 7 * @note
AnnaBridge 126:abea610beb85 8 *
AnnaBridge 126:abea610beb85 9 ******************************************************************************/
AnnaBridge 126:abea610beb85 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
AnnaBridge 126:abea610beb85 11
AnnaBridge 126:abea610beb85 12 All rights reserved.
AnnaBridge 126:abea610beb85 13 Redistribution and use in source and binary forms, with or without
AnnaBridge 126:abea610beb85 14 modification, are permitted provided that the following conditions are met:
AnnaBridge 126:abea610beb85 15 - Redistributions of source code must retain the above copyright
AnnaBridge 126:abea610beb85 16 notice, this list of conditions and the following disclaimer.
AnnaBridge 126:abea610beb85 17 - Redistributions in binary form must reproduce the above copyright
AnnaBridge 126:abea610beb85 18 notice, this list of conditions and the following disclaimer in the
AnnaBridge 126:abea610beb85 19 documentation and/or other materials provided with the distribution.
AnnaBridge 126:abea610beb85 20 - Neither the name of ARM nor the names of its contributors may be used
AnnaBridge 126:abea610beb85 21 to endorse or promote products derived from this software without
AnnaBridge 126:abea610beb85 22 specific prior written permission.
AnnaBridge 126:abea610beb85 23 *
AnnaBridge 126:abea610beb85 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 126:abea610beb85 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 126:abea610beb85 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 126:abea610beb85 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
AnnaBridge 126:abea610beb85 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 126:abea610beb85 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 126:abea610beb85 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 126:abea610beb85 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 126:abea610beb85 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 126:abea610beb85 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 126:abea610beb85 34 POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 126:abea610beb85 35 ---------------------------------------------------------------------------*/
AnnaBridge 126:abea610beb85 36
AnnaBridge 126:abea610beb85 37
AnnaBridge 126:abea610beb85 38 #ifndef __CORE_CAFUNC_H__
AnnaBridge 126:abea610beb85 39 #define __CORE_CAFUNC_H__
AnnaBridge 126:abea610beb85 40
AnnaBridge 126:abea610beb85 41
AnnaBridge 126:abea610beb85 42 /* ########################### Core Function Access ########################### */
AnnaBridge 126:abea610beb85 43 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 126:abea610beb85 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 126:abea610beb85 45 @{
AnnaBridge 126:abea610beb85 46 */
AnnaBridge 126:abea610beb85 47
AnnaBridge 126:abea610beb85 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
AnnaBridge 126:abea610beb85 49 /* ARM armcc specific functions */
AnnaBridge 126:abea610beb85 50
AnnaBridge 126:abea610beb85 51 #if (__ARMCC_VERSION < 400677)
AnnaBridge 126:abea610beb85 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
AnnaBridge 126:abea610beb85 53 #endif
AnnaBridge 126:abea610beb85 54
AnnaBridge 126:abea610beb85 55 #define MODE_USR 0x10
AnnaBridge 126:abea610beb85 56 #define MODE_FIQ 0x11
AnnaBridge 126:abea610beb85 57 #define MODE_IRQ 0x12
AnnaBridge 126:abea610beb85 58 #define MODE_SVC 0x13
AnnaBridge 126:abea610beb85 59 #define MODE_MON 0x16
AnnaBridge 126:abea610beb85 60 #define MODE_ABT 0x17
AnnaBridge 126:abea610beb85 61 #define MODE_HYP 0x1A
AnnaBridge 126:abea610beb85 62 #define MODE_UND 0x1B
AnnaBridge 126:abea610beb85 63 #define MODE_SYS 0x1F
AnnaBridge 126:abea610beb85 64
AnnaBridge 126:abea610beb85 65 /** \brief Get APSR Register
AnnaBridge 126:abea610beb85 66
AnnaBridge 126:abea610beb85 67 This function returns the content of the APSR Register.
AnnaBridge 126:abea610beb85 68
AnnaBridge 126:abea610beb85 69 \return APSR Register value
AnnaBridge 126:abea610beb85 70 */
AnnaBridge 126:abea610beb85 71 __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 126:abea610beb85 72 {
AnnaBridge 126:abea610beb85 73 register uint32_t __regAPSR __ASM("apsr");
AnnaBridge 126:abea610beb85 74 return(__regAPSR);
AnnaBridge 126:abea610beb85 75 }
AnnaBridge 126:abea610beb85 76
AnnaBridge 126:abea610beb85 77
AnnaBridge 126:abea610beb85 78 /** \brief Get CPSR Register
AnnaBridge 126:abea610beb85 79
AnnaBridge 126:abea610beb85 80 This function returns the content of the CPSR Register.
AnnaBridge 126:abea610beb85 81
AnnaBridge 126:abea610beb85 82 \return CPSR Register value
AnnaBridge 126:abea610beb85 83 */
AnnaBridge 126:abea610beb85 84 __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 126:abea610beb85 85 {
AnnaBridge 126:abea610beb85 86 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 126:abea610beb85 87 return(__regCPSR);
AnnaBridge 126:abea610beb85 88 }
AnnaBridge 126:abea610beb85 89
AnnaBridge 126:abea610beb85 90 /** \brief Set Stack Pointer
AnnaBridge 126:abea610beb85 91
AnnaBridge 126:abea610beb85 92 This function assigns the given value to the current stack pointer.
AnnaBridge 126:abea610beb85 93
AnnaBridge 126:abea610beb85 94 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 126:abea610beb85 95 */
AnnaBridge 126:abea610beb85 96 register uint32_t __regSP __ASM("sp");
AnnaBridge 126:abea610beb85 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
AnnaBridge 126:abea610beb85 98 {
AnnaBridge 126:abea610beb85 99 __regSP = topOfStack;
AnnaBridge 126:abea610beb85 100 }
AnnaBridge 126:abea610beb85 101
AnnaBridge 126:abea610beb85 102
AnnaBridge 126:abea610beb85 103 /** \brief Get link register
AnnaBridge 126:abea610beb85 104
AnnaBridge 126:abea610beb85 105 This function returns the value of the link register
AnnaBridge 126:abea610beb85 106
AnnaBridge 126:abea610beb85 107 \return Value of link register
AnnaBridge 126:abea610beb85 108 */
AnnaBridge 126:abea610beb85 109 register uint32_t __reglr __ASM("lr");
AnnaBridge 126:abea610beb85 110 __STATIC_INLINE uint32_t __get_LR(void)
AnnaBridge 126:abea610beb85 111 {
AnnaBridge 126:abea610beb85 112 return(__reglr);
AnnaBridge 126:abea610beb85 113 }
AnnaBridge 126:abea610beb85 114
AnnaBridge 126:abea610beb85 115 /** \brief Set link register
AnnaBridge 126:abea610beb85 116
AnnaBridge 126:abea610beb85 117 This function sets the value of the link register
AnnaBridge 126:abea610beb85 118
AnnaBridge 126:abea610beb85 119 \param [in] lr LR value to set
AnnaBridge 126:abea610beb85 120 */
AnnaBridge 126:abea610beb85 121 __STATIC_INLINE void __set_LR(uint32_t lr)
AnnaBridge 126:abea610beb85 122 {
AnnaBridge 126:abea610beb85 123 __reglr = lr;
AnnaBridge 126:abea610beb85 124 }
AnnaBridge 126:abea610beb85 125
AnnaBridge 126:abea610beb85 126 /** \brief Set Process Stack Pointer
AnnaBridge 126:abea610beb85 127
AnnaBridge 126:abea610beb85 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 126:abea610beb85 129
AnnaBridge 126:abea610beb85 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 126:abea610beb85 131 */
AnnaBridge 126:abea610beb85 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 126:abea610beb85 133 {
AnnaBridge 126:abea610beb85 134 ARM
AnnaBridge 126:abea610beb85 135 PRESERVE8
AnnaBridge 126:abea610beb85 136
AnnaBridge 126:abea610beb85 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
AnnaBridge 126:abea610beb85 138 MRS R1, CPSR
AnnaBridge 126:abea610beb85 139 CPS #MODE_SYS ;no effect in USR mode
AnnaBridge 126:abea610beb85 140 MOV SP, R0
AnnaBridge 126:abea610beb85 141 MSR CPSR_c, R1 ;no effect in USR mode
AnnaBridge 126:abea610beb85 142 ISB
AnnaBridge 126:abea610beb85 143 BX LR
AnnaBridge 126:abea610beb85 144
AnnaBridge 126:abea610beb85 145 }
AnnaBridge 126:abea610beb85 146
AnnaBridge 126:abea610beb85 147 /** \brief Set User Mode
AnnaBridge 126:abea610beb85 148
AnnaBridge 126:abea610beb85 149 This function changes the processor state to User Mode
AnnaBridge 126:abea610beb85 150 */
AnnaBridge 126:abea610beb85 151 __STATIC_ASM void __set_CPS_USR(void)
AnnaBridge 126:abea610beb85 152 {
AnnaBridge 126:abea610beb85 153 ARM
AnnaBridge 126:abea610beb85 154
AnnaBridge 126:abea610beb85 155 CPS #MODE_USR
AnnaBridge 126:abea610beb85 156 BX LR
AnnaBridge 126:abea610beb85 157 }
AnnaBridge 126:abea610beb85 158
AnnaBridge 126:abea610beb85 159
AnnaBridge 126:abea610beb85 160 /** \brief Enable FIQ
AnnaBridge 126:abea610beb85 161
AnnaBridge 126:abea610beb85 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 126:abea610beb85 163 Can only be executed in Privileged modes.
AnnaBridge 126:abea610beb85 164 */
AnnaBridge 126:abea610beb85 165 #define __enable_fault_irq __enable_fiq
AnnaBridge 126:abea610beb85 166
AnnaBridge 126:abea610beb85 167
AnnaBridge 126:abea610beb85 168 /** \brief Disable FIQ
AnnaBridge 126:abea610beb85 169
AnnaBridge 126:abea610beb85 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 126:abea610beb85 171 Can only be executed in Privileged modes.
AnnaBridge 126:abea610beb85 172 */
AnnaBridge 126:abea610beb85 173 #define __disable_fault_irq __disable_fiq
AnnaBridge 126:abea610beb85 174
AnnaBridge 126:abea610beb85 175
AnnaBridge 126:abea610beb85 176 /** \brief Get FPSCR
AnnaBridge 126:abea610beb85 177
AnnaBridge 126:abea610beb85 178 This function returns the current value of the Floating Point Status/Control register.
AnnaBridge 126:abea610beb85 179
AnnaBridge 126:abea610beb85 180 \return Floating Point Status/Control register value
AnnaBridge 126:abea610beb85 181 */
AnnaBridge 126:abea610beb85 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 126:abea610beb85 183 {
AnnaBridge 126:abea610beb85 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 126:abea610beb85 185 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 126:abea610beb85 186 return(__regfpscr);
AnnaBridge 126:abea610beb85 187 #else
AnnaBridge 126:abea610beb85 188 return(0);
AnnaBridge 126:abea610beb85 189 #endif
AnnaBridge 126:abea610beb85 190 }
AnnaBridge 126:abea610beb85 191
AnnaBridge 126:abea610beb85 192
AnnaBridge 126:abea610beb85 193 /** \brief Set FPSCR
AnnaBridge 126:abea610beb85 194
AnnaBridge 126:abea610beb85 195 This function assigns the given value to the Floating Point Status/Control register.
AnnaBridge 126:abea610beb85 196
AnnaBridge 126:abea610beb85 197 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 126:abea610beb85 198 */
AnnaBridge 126:abea610beb85 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 126:abea610beb85 200 {
AnnaBridge 126:abea610beb85 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 126:abea610beb85 202 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 126:abea610beb85 203 __regfpscr = (fpscr);
AnnaBridge 126:abea610beb85 204 #endif
AnnaBridge 126:abea610beb85 205 }
AnnaBridge 126:abea610beb85 206
AnnaBridge 126:abea610beb85 207 /** \brief Get FPEXC
AnnaBridge 126:abea610beb85 208
AnnaBridge 126:abea610beb85 209 This function returns the current value of the Floating Point Exception Control register.
AnnaBridge 126:abea610beb85 210
AnnaBridge 126:abea610beb85 211 \return Floating Point Exception Control register value
AnnaBridge 126:abea610beb85 212 */
AnnaBridge 126:abea610beb85 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 126:abea610beb85 214 {
AnnaBridge 126:abea610beb85 215 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 216 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 126:abea610beb85 217 return(__regfpexc);
AnnaBridge 126:abea610beb85 218 #else
AnnaBridge 126:abea610beb85 219 return(0);
AnnaBridge 126:abea610beb85 220 #endif
AnnaBridge 126:abea610beb85 221 }
AnnaBridge 126:abea610beb85 222
AnnaBridge 126:abea610beb85 223
AnnaBridge 126:abea610beb85 224 /** \brief Set FPEXC
AnnaBridge 126:abea610beb85 225
AnnaBridge 126:abea610beb85 226 This function assigns the given value to the Floating Point Exception Control register.
AnnaBridge 126:abea610beb85 227
AnnaBridge 126:abea610beb85 228 \param [in] fpscr Floating Point Exception Control value to set
AnnaBridge 126:abea610beb85 229 */
AnnaBridge 126:abea610beb85 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 126:abea610beb85 231 {
AnnaBridge 126:abea610beb85 232 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 233 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 126:abea610beb85 234 __regfpexc = (fpexc);
AnnaBridge 126:abea610beb85 235 #endif
AnnaBridge 126:abea610beb85 236 }
AnnaBridge 126:abea610beb85 237
AnnaBridge 126:abea610beb85 238 /** \brief Get CPACR
AnnaBridge 126:abea610beb85 239
AnnaBridge 126:abea610beb85 240 This function returns the current value of the Coprocessor Access Control register.
AnnaBridge 126:abea610beb85 241
AnnaBridge 126:abea610beb85 242 \return Coprocessor Access Control register value
AnnaBridge 126:abea610beb85 243 */
AnnaBridge 126:abea610beb85 244 __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 126:abea610beb85 245 {
AnnaBridge 126:abea610beb85 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 126:abea610beb85 247 return __regCPACR;
AnnaBridge 126:abea610beb85 248 }
AnnaBridge 126:abea610beb85 249
AnnaBridge 126:abea610beb85 250 /** \brief Set CPACR
AnnaBridge 126:abea610beb85 251
AnnaBridge 126:abea610beb85 252 This function assigns the given value to the Coprocessor Access Control register.
AnnaBridge 126:abea610beb85 253
AnnaBridge 126:abea610beb85 254 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 126:abea610beb85 255 */
AnnaBridge 126:abea610beb85 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 126:abea610beb85 257 {
AnnaBridge 126:abea610beb85 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 126:abea610beb85 259 __regCPACR = cpacr;
AnnaBridge 126:abea610beb85 260 __ISB();
AnnaBridge 126:abea610beb85 261 }
AnnaBridge 126:abea610beb85 262
AnnaBridge 126:abea610beb85 263 /** \brief Get CBAR
AnnaBridge 126:abea610beb85 264
AnnaBridge 126:abea610beb85 265 This function returns the value of the Configuration Base Address register.
AnnaBridge 126:abea610beb85 266
AnnaBridge 126:abea610beb85 267 \return Configuration Base Address register value
AnnaBridge 126:abea610beb85 268 */
AnnaBridge 126:abea610beb85 269 __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 126:abea610beb85 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 126:abea610beb85 271 return(__regCBAR);
AnnaBridge 126:abea610beb85 272 }
AnnaBridge 126:abea610beb85 273
AnnaBridge 126:abea610beb85 274 /** \brief Get TTBR0
AnnaBridge 126:abea610beb85 275
AnnaBridge 126:abea610beb85 276 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 126:abea610beb85 277
AnnaBridge 126:abea610beb85 278 \return Translation Table Base Register 0 value
AnnaBridge 126:abea610beb85 279 */
AnnaBridge 126:abea610beb85 280 __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 126:abea610beb85 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 126:abea610beb85 282 return(__regTTBR0);
AnnaBridge 126:abea610beb85 283 }
AnnaBridge 126:abea610beb85 284
AnnaBridge 126:abea610beb85 285 /** \brief Set TTBR0
AnnaBridge 126:abea610beb85 286
AnnaBridge 126:abea610beb85 287 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 126:abea610beb85 288
AnnaBridge 126:abea610beb85 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 126:abea610beb85 290 */
AnnaBridge 126:abea610beb85 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 126:abea610beb85 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 126:abea610beb85 293 __regTTBR0 = ttbr0;
AnnaBridge 126:abea610beb85 294 __ISB();
AnnaBridge 126:abea610beb85 295 }
AnnaBridge 126:abea610beb85 296
AnnaBridge 126:abea610beb85 297 /** \brief Get DACR
AnnaBridge 126:abea610beb85 298
AnnaBridge 126:abea610beb85 299 This function returns the value of the Domain Access Control Register.
AnnaBridge 126:abea610beb85 300
AnnaBridge 126:abea610beb85 301 \return Domain Access Control Register value
AnnaBridge 126:abea610beb85 302 */
AnnaBridge 126:abea610beb85 303 __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 126:abea610beb85 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 126:abea610beb85 305 return(__regDACR);
AnnaBridge 126:abea610beb85 306 }
AnnaBridge 126:abea610beb85 307
AnnaBridge 126:abea610beb85 308 /** \brief Set DACR
AnnaBridge 126:abea610beb85 309
AnnaBridge 126:abea610beb85 310 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 126:abea610beb85 311
AnnaBridge 126:abea610beb85 312 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 126:abea610beb85 313 */
AnnaBridge 126:abea610beb85 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 126:abea610beb85 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 126:abea610beb85 316 __regDACR = dacr;
AnnaBridge 126:abea610beb85 317 __ISB();
AnnaBridge 126:abea610beb85 318 }
AnnaBridge 126:abea610beb85 319
AnnaBridge 126:abea610beb85 320 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 126:abea610beb85 321
AnnaBridge 126:abea610beb85 322 /** \brief Set SCTLR
AnnaBridge 126:abea610beb85 323
AnnaBridge 126:abea610beb85 324 This function assigns the given value to the System Control Register.
AnnaBridge 126:abea610beb85 325
AnnaBridge 126:abea610beb85 326 \param [in] sctlr System Control Register value to set
AnnaBridge 126:abea610beb85 327 */
AnnaBridge 126:abea610beb85 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 126:abea610beb85 329 {
AnnaBridge 126:abea610beb85 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 126:abea610beb85 331 __regSCTLR = sctlr;
AnnaBridge 126:abea610beb85 332 }
AnnaBridge 126:abea610beb85 333
AnnaBridge 126:abea610beb85 334 /** \brief Get SCTLR
AnnaBridge 126:abea610beb85 335
AnnaBridge 126:abea610beb85 336 This function returns the value of the System Control Register.
AnnaBridge 126:abea610beb85 337
AnnaBridge 126:abea610beb85 338 \return System Control Register value
AnnaBridge 126:abea610beb85 339 */
AnnaBridge 126:abea610beb85 340 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 126:abea610beb85 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 126:abea610beb85 342 return(__regSCTLR);
AnnaBridge 126:abea610beb85 343 }
AnnaBridge 126:abea610beb85 344
AnnaBridge 126:abea610beb85 345 /** \brief Enable Caches
AnnaBridge 126:abea610beb85 346
AnnaBridge 126:abea610beb85 347 Enable Caches
AnnaBridge 126:abea610beb85 348 */
AnnaBridge 126:abea610beb85 349 __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 126:abea610beb85 350 // Set I bit 12 to enable I Cache
AnnaBridge 126:abea610beb85 351 // Set C bit 2 to enable D Cache
AnnaBridge 126:abea610beb85 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 126:abea610beb85 353 }
AnnaBridge 126:abea610beb85 354
AnnaBridge 126:abea610beb85 355 /** \brief Disable Caches
AnnaBridge 126:abea610beb85 356
AnnaBridge 126:abea610beb85 357 Disable Caches
AnnaBridge 126:abea610beb85 358 */
AnnaBridge 126:abea610beb85 359 __STATIC_INLINE void __disable_caches(void) {
AnnaBridge 126:abea610beb85 360 // Clear I bit 12 to disable I Cache
AnnaBridge 126:abea610beb85 361 // Clear C bit 2 to disable D Cache
AnnaBridge 126:abea610beb85 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 126:abea610beb85 363 __ISB();
AnnaBridge 126:abea610beb85 364 }
AnnaBridge 126:abea610beb85 365
AnnaBridge 126:abea610beb85 366 /** \brief Enable BTAC
AnnaBridge 126:abea610beb85 367
AnnaBridge 126:abea610beb85 368 Enable BTAC
AnnaBridge 126:abea610beb85 369 */
AnnaBridge 126:abea610beb85 370 __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 126:abea610beb85 371 // Set Z bit 11 to enable branch prediction
AnnaBridge 126:abea610beb85 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 126:abea610beb85 373 __ISB();
AnnaBridge 126:abea610beb85 374 }
AnnaBridge 126:abea610beb85 375
AnnaBridge 126:abea610beb85 376 /** \brief Disable BTAC
AnnaBridge 126:abea610beb85 377
AnnaBridge 126:abea610beb85 378 Disable BTAC
AnnaBridge 126:abea610beb85 379 */
AnnaBridge 126:abea610beb85 380 __STATIC_INLINE void __disable_btac(void) {
AnnaBridge 126:abea610beb85 381 // Clear Z bit 11 to disable branch prediction
AnnaBridge 126:abea610beb85 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 126:abea610beb85 383 }
AnnaBridge 126:abea610beb85 384
AnnaBridge 126:abea610beb85 385
AnnaBridge 126:abea610beb85 386 /** \brief Enable MMU
AnnaBridge 126:abea610beb85 387
AnnaBridge 126:abea610beb85 388 Enable MMU
AnnaBridge 126:abea610beb85 389 */
AnnaBridge 126:abea610beb85 390 __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 126:abea610beb85 391 // Set M bit 0 to enable the MMU
AnnaBridge 126:abea610beb85 392 // Set AFE bit to enable simplified access permissions model
AnnaBridge 126:abea610beb85 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 126:abea610beb85 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 126:abea610beb85 395 __ISB();
AnnaBridge 126:abea610beb85 396 }
AnnaBridge 126:abea610beb85 397
AnnaBridge 126:abea610beb85 398 /** \brief Disable MMU
AnnaBridge 126:abea610beb85 399
AnnaBridge 126:abea610beb85 400 Disable MMU
AnnaBridge 126:abea610beb85 401 */
AnnaBridge 126:abea610beb85 402 __STATIC_INLINE void __disable_mmu(void) {
AnnaBridge 126:abea610beb85 403 // Clear M bit 0 to disable the MMU
AnnaBridge 126:abea610beb85 404 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 126:abea610beb85 405 __ISB();
AnnaBridge 126:abea610beb85 406 }
AnnaBridge 126:abea610beb85 407
AnnaBridge 126:abea610beb85 408 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 126:abea610beb85 409 /** \brief Invalidate the whole tlb
AnnaBridge 126:abea610beb85 410
AnnaBridge 126:abea610beb85 411 TLBIALL. Invalidate the whole tlb
AnnaBridge 126:abea610beb85 412 */
AnnaBridge 126:abea610beb85 413
AnnaBridge 126:abea610beb85 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 126:abea610beb85 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 126:abea610beb85 416 __TLBIALL = 0;
AnnaBridge 126:abea610beb85 417 __DSB();
AnnaBridge 126:abea610beb85 418 __ISB();
AnnaBridge 126:abea610beb85 419 }
AnnaBridge 126:abea610beb85 420
AnnaBridge 126:abea610beb85 421 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 126:abea610beb85 422 /** \brief Invalidate entire branch predictor array
AnnaBridge 126:abea610beb85 423
AnnaBridge 126:abea610beb85 424 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 126:abea610beb85 425 */
AnnaBridge 126:abea610beb85 426
AnnaBridge 126:abea610beb85 427 __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 126:abea610beb85 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 126:abea610beb85 429 __BPIALL = 0;
AnnaBridge 126:abea610beb85 430 __DSB(); //ensure completion of the invalidation
AnnaBridge 126:abea610beb85 431 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 126:abea610beb85 432 }
AnnaBridge 126:abea610beb85 433
AnnaBridge 126:abea610beb85 434
AnnaBridge 126:abea610beb85 435 /******************************** L1 cache operations ******************************************************/
AnnaBridge 126:abea610beb85 436
AnnaBridge 126:abea610beb85 437 /** \brief Invalidate the whole I$
AnnaBridge 126:abea610beb85 438
AnnaBridge 126:abea610beb85 439 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 126:abea610beb85 440 */
AnnaBridge 126:abea610beb85 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 126:abea610beb85 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 126:abea610beb85 443 __ICIALLU = 0;
AnnaBridge 126:abea610beb85 444 __DSB(); //ensure completion of the invalidation
AnnaBridge 126:abea610beb85 445 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 126:abea610beb85 446 }
AnnaBridge 126:abea610beb85 447
AnnaBridge 126:abea610beb85 448 /** \brief Clean D$ by MVA
AnnaBridge 126:abea610beb85 449
AnnaBridge 126:abea610beb85 450 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 126:abea610beb85 451 */
AnnaBridge 126:abea610beb85 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
AnnaBridge 126:abea610beb85 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 126:abea610beb85 454 __DCCMVAC = (uint32_t)va;
AnnaBridge 126:abea610beb85 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 126:abea610beb85 456 }
AnnaBridge 126:abea610beb85 457
AnnaBridge 126:abea610beb85 458 /** \brief Invalidate D$ by MVA
AnnaBridge 126:abea610beb85 459
AnnaBridge 126:abea610beb85 460 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 126:abea610beb85 461 */
AnnaBridge 126:abea610beb85 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
AnnaBridge 126:abea610beb85 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 126:abea610beb85 464 __DCIMVAC = (uint32_t)va;
AnnaBridge 126:abea610beb85 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 126:abea610beb85 466 }
AnnaBridge 126:abea610beb85 467
AnnaBridge 126:abea610beb85 468 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 126:abea610beb85 469
AnnaBridge 126:abea610beb85 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 126:abea610beb85 471 */
AnnaBridge 126:abea610beb85 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 126:abea610beb85 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 126:abea610beb85 474 __DCCIMVAC = (uint32_t)va;
AnnaBridge 126:abea610beb85 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 126:abea610beb85 476 }
AnnaBridge 126:abea610beb85 477
AnnaBridge 126:abea610beb85 478 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 126:abea610beb85 479
AnnaBridge 126:abea610beb85 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 126:abea610beb85 481 */
AnnaBridge 126:abea610beb85 482 #pragma push
AnnaBridge 126:abea610beb85 483 #pragma arm
AnnaBridge 126:abea610beb85 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
AnnaBridge 126:abea610beb85 485 ARM
AnnaBridge 126:abea610beb85 486
AnnaBridge 126:abea610beb85 487 PUSH {R4-R11}
AnnaBridge 126:abea610beb85 488
AnnaBridge 126:abea610beb85 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
AnnaBridge 126:abea610beb85 490 ANDS R3, R6, #0x07000000 // Extract coherency level
AnnaBridge 126:abea610beb85 491 MOV R3, R3, LSR #23 // Total cache levels << 1
AnnaBridge 126:abea610beb85 492 BEQ Finished // If 0, no need to clean
AnnaBridge 126:abea610beb85 493
AnnaBridge 126:abea610beb85 494 MOV R10, #0 // R10 holds current cache level << 1
AnnaBridge 126:abea610beb85 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
AnnaBridge 126:abea610beb85 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
AnnaBridge 126:abea610beb85 497 AND R1, R1, #7 // Isolate those lower 3 bits
AnnaBridge 126:abea610beb85 498 CMP R1, #2
AnnaBridge 126:abea610beb85 499 BLT Skip // No cache or only instruction cache at this level
AnnaBridge 126:abea610beb85 500
AnnaBridge 126:abea610beb85 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
AnnaBridge 126:abea610beb85 502 ISB // ISB to sync the change to the CacheSizeID reg
AnnaBridge 126:abea610beb85 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
AnnaBridge 126:abea610beb85 504 AND R2, R1, #7 // Extract the line length field
AnnaBridge 126:abea610beb85 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 126:abea610beb85 506 LDR R4, =0x3FF
AnnaBridge 126:abea610beb85 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
AnnaBridge 126:abea610beb85 508 CLZ R5, R4 // R5 is the bit position of the way size increment
AnnaBridge 126:abea610beb85 509 LDR R7, =0x7FFF
AnnaBridge 126:abea610beb85 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
AnnaBridge 126:abea610beb85 511
AnnaBridge 126:abea610beb85 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
AnnaBridge 126:abea610beb85 513
AnnaBridge 126:abea610beb85 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
AnnaBridge 126:abea610beb85 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
AnnaBridge 126:abea610beb85 516 CMP R0, #0
AnnaBridge 126:abea610beb85 517 BNE Dccsw
AnnaBridge 126:abea610beb85 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
AnnaBridge 126:abea610beb85 519 B cont
AnnaBridge 126:abea610beb85 520 Dccsw CMP R0, #1
AnnaBridge 126:abea610beb85 521 BNE Dccisw
AnnaBridge 126:abea610beb85 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
AnnaBridge 126:abea610beb85 523 B cont
AnnaBridge 126:abea610beb85 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 126:abea610beb85 525 cont SUBS R9, R9, #1 // Decrement the Way number
AnnaBridge 126:abea610beb85 526 BGE Loop3
AnnaBridge 126:abea610beb85 527 SUBS R7, R7, #1 // Decrement the Set number
AnnaBridge 126:abea610beb85 528 BGE Loop2
AnnaBridge 126:abea610beb85 529 Skip ADD R10, R10, #2 // Increment the cache number
AnnaBridge 126:abea610beb85 530 CMP R3, R10
AnnaBridge 126:abea610beb85 531 BGT Loop1
AnnaBridge 126:abea610beb85 532
AnnaBridge 126:abea610beb85 533 Finished
AnnaBridge 126:abea610beb85 534 DSB
AnnaBridge 126:abea610beb85 535 POP {R4-R11}
AnnaBridge 126:abea610beb85 536 BX lr
AnnaBridge 126:abea610beb85 537
AnnaBridge 126:abea610beb85 538 }
AnnaBridge 126:abea610beb85 539 #pragma pop
AnnaBridge 126:abea610beb85 540
AnnaBridge 126:abea610beb85 541
AnnaBridge 126:abea610beb85 542 /** \brief Invalidate the whole D$
AnnaBridge 126:abea610beb85 543
AnnaBridge 126:abea610beb85 544 DCISW. Invalidate by Set/Way
AnnaBridge 126:abea610beb85 545 */
AnnaBridge 126:abea610beb85 546
AnnaBridge 126:abea610beb85 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 126:abea610beb85 548 __v7_all_cache(0);
AnnaBridge 126:abea610beb85 549 }
AnnaBridge 126:abea610beb85 550
AnnaBridge 126:abea610beb85 551 /** \brief Clean the whole D$
AnnaBridge 126:abea610beb85 552
AnnaBridge 126:abea610beb85 553 DCCSW. Clean by Set/Way
AnnaBridge 126:abea610beb85 554 */
AnnaBridge 126:abea610beb85 555
AnnaBridge 126:abea610beb85 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 126:abea610beb85 557 __v7_all_cache(1);
AnnaBridge 126:abea610beb85 558 }
AnnaBridge 126:abea610beb85 559
AnnaBridge 126:abea610beb85 560 /** \brief Clean and invalidate the whole D$
AnnaBridge 126:abea610beb85 561
AnnaBridge 126:abea610beb85 562 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 126:abea610beb85 563 */
AnnaBridge 126:abea610beb85 564
AnnaBridge 126:abea610beb85 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 126:abea610beb85 566 __v7_all_cache(2);
AnnaBridge 126:abea610beb85 567 }
AnnaBridge 126:abea610beb85 568
AnnaBridge 126:abea610beb85 569 #include "core_ca_mmu.h"
AnnaBridge 126:abea610beb85 570
AnnaBridge 126:abea610beb85 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
AnnaBridge 126:abea610beb85 572
AnnaBridge 126:abea610beb85 573 #define __inline inline
AnnaBridge 126:abea610beb85 574
AnnaBridge 126:abea610beb85 575 inline static uint32_t __disable_irq_iar() {
AnnaBridge 126:abea610beb85 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
AnnaBridge 126:abea610beb85 577 __disable_irq();
AnnaBridge 126:abea610beb85 578 return irq_dis;
AnnaBridge 126:abea610beb85 579 }
AnnaBridge 126:abea610beb85 580
AnnaBridge 126:abea610beb85 581 #define MODE_USR 0x10
AnnaBridge 126:abea610beb85 582 #define MODE_FIQ 0x11
AnnaBridge 126:abea610beb85 583 #define MODE_IRQ 0x12
AnnaBridge 126:abea610beb85 584 #define MODE_SVC 0x13
AnnaBridge 126:abea610beb85 585 #define MODE_MON 0x16
AnnaBridge 126:abea610beb85 586 #define MODE_ABT 0x17
AnnaBridge 126:abea610beb85 587 #define MODE_HYP 0x1A
AnnaBridge 126:abea610beb85 588 #define MODE_UND 0x1B
AnnaBridge 126:abea610beb85 589 #define MODE_SYS 0x1F
AnnaBridge 126:abea610beb85 590
AnnaBridge 126:abea610beb85 591 /** \brief Set Process Stack Pointer
AnnaBridge 126:abea610beb85 592
AnnaBridge 126:abea610beb85 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 126:abea610beb85 594
AnnaBridge 126:abea610beb85 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 126:abea610beb85 596 */
AnnaBridge 126:abea610beb85 597 // from rt_CMSIS.c
AnnaBridge 126:abea610beb85 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
AnnaBridge 126:abea610beb85 599 __asm(
AnnaBridge 126:abea610beb85 600 " ARM\n"
AnnaBridge 126:abea610beb85 601 // " PRESERVE8\n"
AnnaBridge 126:abea610beb85 602
AnnaBridge 126:abea610beb85 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
AnnaBridge 126:abea610beb85 604 " MRS R1, CPSR \n"
AnnaBridge 126:abea610beb85 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
AnnaBridge 126:abea610beb85 606 " MOV SP, R0 \n"
AnnaBridge 126:abea610beb85 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
AnnaBridge 126:abea610beb85 608 " ISB \n"
AnnaBridge 126:abea610beb85 609 " BX LR \n");
AnnaBridge 126:abea610beb85 610 }
AnnaBridge 126:abea610beb85 611
AnnaBridge 126:abea610beb85 612 /** \brief Set User Mode
AnnaBridge 126:abea610beb85 613
AnnaBridge 126:abea610beb85 614 This function changes the processor state to User Mode
AnnaBridge 126:abea610beb85 615 */
AnnaBridge 126:abea610beb85 616 // from rt_CMSIS.c
AnnaBridge 126:abea610beb85 617 __arm static inline void __set_CPS_USR(void) {
AnnaBridge 126:abea610beb85 618 __asm(
AnnaBridge 126:abea610beb85 619 " ARM \n"
AnnaBridge 126:abea610beb85 620
AnnaBridge 126:abea610beb85 621 " CPS #0x10 \n" // MODE_USR
AnnaBridge 126:abea610beb85 622 " BX LR\n");
AnnaBridge 126:abea610beb85 623 }
AnnaBridge 126:abea610beb85 624
AnnaBridge 126:abea610beb85 625 /** \brief Set TTBR0
AnnaBridge 126:abea610beb85 626
AnnaBridge 126:abea610beb85 627 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 126:abea610beb85 628
AnnaBridge 126:abea610beb85 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 126:abea610beb85 630 */
AnnaBridge 126:abea610beb85 631 // from mmu_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 126:abea610beb85 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
AnnaBridge 126:abea610beb85 634 __ISB();
AnnaBridge 126:abea610beb85 635 }
AnnaBridge 126:abea610beb85 636
AnnaBridge 126:abea610beb85 637 /** \brief Set DACR
AnnaBridge 126:abea610beb85 638
AnnaBridge 126:abea610beb85 639 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 126:abea610beb85 640
AnnaBridge 126:abea610beb85 641 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 126:abea610beb85 642 */
AnnaBridge 126:abea610beb85 643 // from mmu_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 126:abea610beb85 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
AnnaBridge 126:abea610beb85 646 __ISB();
AnnaBridge 126:abea610beb85 647 }
AnnaBridge 126:abea610beb85 648
AnnaBridge 126:abea610beb85 649
AnnaBridge 126:abea610beb85 650 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 126:abea610beb85 651 /** \brief Set SCTLR
AnnaBridge 126:abea610beb85 652
AnnaBridge 126:abea610beb85 653 This function assigns the given value to the System Control Register.
AnnaBridge 126:abea610beb85 654
AnnaBridge 126:abea610beb85 655 \param [in] sctlr System Control Register value to set
AnnaBridge 126:abea610beb85 656 */
AnnaBridge 126:abea610beb85 657 // from __enable_mmu()
AnnaBridge 126:abea610beb85 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
AnnaBridge 126:abea610beb85 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
AnnaBridge 126:abea610beb85 660 }
AnnaBridge 126:abea610beb85 661
AnnaBridge 126:abea610beb85 662 /** \brief Get SCTLR
AnnaBridge 126:abea610beb85 663
AnnaBridge 126:abea610beb85 664 This function returns the value of the System Control Register.
AnnaBridge 126:abea610beb85 665
AnnaBridge 126:abea610beb85 666 \return System Control Register value
AnnaBridge 126:abea610beb85 667 */
AnnaBridge 126:abea610beb85 668 // from __enable_mmu()
AnnaBridge 126:abea610beb85 669 __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 126:abea610beb85 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
AnnaBridge 126:abea610beb85 671 return __regSCTLR;
AnnaBridge 126:abea610beb85 672 }
AnnaBridge 126:abea610beb85 673
AnnaBridge 126:abea610beb85 674 /** \brief Enable Caches
AnnaBridge 126:abea610beb85 675
AnnaBridge 126:abea610beb85 676 Enable Caches
AnnaBridge 126:abea610beb85 677 */
AnnaBridge 126:abea610beb85 678 // from system_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 679 __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 126:abea610beb85 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 126:abea610beb85 681 }
AnnaBridge 126:abea610beb85 682
AnnaBridge 126:abea610beb85 683 /** \brief Enable BTAC
AnnaBridge 126:abea610beb85 684
AnnaBridge 126:abea610beb85 685 Enable BTAC
AnnaBridge 126:abea610beb85 686 */
AnnaBridge 126:abea610beb85 687 // from system_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 688 __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 126:abea610beb85 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 126:abea610beb85 690 __ISB();
AnnaBridge 126:abea610beb85 691 }
AnnaBridge 126:abea610beb85 692
AnnaBridge 126:abea610beb85 693 /** \brief Enable MMU
AnnaBridge 126:abea610beb85 694
AnnaBridge 126:abea610beb85 695 Enable MMU
AnnaBridge 126:abea610beb85 696 */
AnnaBridge 126:abea610beb85 697 // from system_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 698 __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 126:abea610beb85 699 // Set M bit 0 to enable the MMU
AnnaBridge 126:abea610beb85 700 // Set AFE bit to enable simplified access permissions model
AnnaBridge 126:abea610beb85 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 126:abea610beb85 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 126:abea610beb85 703 __ISB();
AnnaBridge 126:abea610beb85 704 }
AnnaBridge 126:abea610beb85 705
AnnaBridge 126:abea610beb85 706 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 126:abea610beb85 707 /** \brief Invalidate the whole tlb
AnnaBridge 126:abea610beb85 708
AnnaBridge 126:abea610beb85 709 TLBIALL. Invalidate the whole tlb
AnnaBridge 126:abea610beb85 710 */
AnnaBridge 126:abea610beb85 711 // from system_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 126:abea610beb85 713 uint32_t val = 0;
AnnaBridge 126:abea610beb85 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
AnnaBridge 126:abea610beb85 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
AnnaBridge 126:abea610beb85 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
AnnaBridge 126:abea610beb85 717 __DSB();
AnnaBridge 126:abea610beb85 718 __ISB();
AnnaBridge 126:abea610beb85 719 }
AnnaBridge 126:abea610beb85 720
AnnaBridge 126:abea610beb85 721 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 126:abea610beb85 722 /** \brief Invalidate entire branch predictor array
AnnaBridge 126:abea610beb85 723
AnnaBridge 126:abea610beb85 724 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 126:abea610beb85 725 */
AnnaBridge 126:abea610beb85 726 // from system_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 727 __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 126:abea610beb85 728 uint32_t val = 0;
AnnaBridge 126:abea610beb85 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
AnnaBridge 126:abea610beb85 730 __DSB(); //ensure completion of the invalidation
AnnaBridge 126:abea610beb85 731 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 126:abea610beb85 732 }
AnnaBridge 126:abea610beb85 733
AnnaBridge 126:abea610beb85 734
AnnaBridge 126:abea610beb85 735 /******************************** L1 cache operations ******************************************************/
AnnaBridge 126:abea610beb85 736
AnnaBridge 126:abea610beb85 737 /** \brief Invalidate the whole I$
AnnaBridge 126:abea610beb85 738
AnnaBridge 126:abea610beb85 739 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 126:abea610beb85 740 */
AnnaBridge 126:abea610beb85 741 // from system_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 126:abea610beb85 743 uint32_t val = 0;
AnnaBridge 126:abea610beb85 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
AnnaBridge 126:abea610beb85 745 __DSB(); //ensure completion of the invalidation
AnnaBridge 126:abea610beb85 746 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 126:abea610beb85 747 }
AnnaBridge 126:abea610beb85 748
AnnaBridge 126:abea610beb85 749 // from __v7_inv_dcache_all()
AnnaBridge 126:abea610beb85 750 __arm static inline void __v7_all_cache(uint32_t op) {
AnnaBridge 126:abea610beb85 751 __asm(
AnnaBridge 126:abea610beb85 752 " ARM \n"
AnnaBridge 126:abea610beb85 753
AnnaBridge 126:abea610beb85 754 " PUSH {R4-R11} \n"
AnnaBridge 126:abea610beb85 755
AnnaBridge 126:abea610beb85 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
AnnaBridge 126:abea610beb85 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
AnnaBridge 126:abea610beb85 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
AnnaBridge 126:abea610beb85 759 " BEQ Finished\n" // If 0, no need to clean
AnnaBridge 126:abea610beb85 760
AnnaBridge 126:abea610beb85 761 " MOV R10, #0\n" // R10 holds current cache level << 1
AnnaBridge 126:abea610beb85 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
AnnaBridge 126:abea610beb85 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
AnnaBridge 126:abea610beb85 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
AnnaBridge 126:abea610beb85 765 " CMP R1, #2 \n"
AnnaBridge 126:abea610beb85 766 " BLT Skip \n" // No cache or only instruction cache at this level
AnnaBridge 126:abea610beb85 767
AnnaBridge 126:abea610beb85 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
AnnaBridge 126:abea610beb85 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
AnnaBridge 126:abea610beb85 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
AnnaBridge 126:abea610beb85 771 " AND R2, R1, #7 \n" // Extract the line length field
AnnaBridge 126:abea610beb85 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
AnnaBridge 126:abea610beb85 773 " movw R4, #0x3FF \n"
AnnaBridge 126:abea610beb85 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
AnnaBridge 126:abea610beb85 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
AnnaBridge 126:abea610beb85 776 " movw R7, #0x7FFF \n"
AnnaBridge 126:abea610beb85 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
AnnaBridge 126:abea610beb85 778
AnnaBridge 126:abea610beb85 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
AnnaBridge 126:abea610beb85 780
AnnaBridge 126:abea610beb85 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
AnnaBridge 126:abea610beb85 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
AnnaBridge 126:abea610beb85 783 " CMP R0, #0 \n"
AnnaBridge 126:abea610beb85 784 " BNE Dccsw \n"
AnnaBridge 126:abea610beb85 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
AnnaBridge 126:abea610beb85 786 " B cont \n"
AnnaBridge 126:abea610beb85 787 "Dccsw: CMP R0, #1 \n"
AnnaBridge 126:abea610beb85 788 " BNE Dccisw \n"
AnnaBridge 126:abea610beb85 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
AnnaBridge 126:abea610beb85 790 " B cont \n"
AnnaBridge 126:abea610beb85 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
AnnaBridge 126:abea610beb85 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
AnnaBridge 126:abea610beb85 793 " BGE Loop3 \n"
AnnaBridge 126:abea610beb85 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
AnnaBridge 126:abea610beb85 795 " BGE Loop2 \n"
AnnaBridge 126:abea610beb85 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
AnnaBridge 126:abea610beb85 797 " CMP R3, R10 \n"
AnnaBridge 126:abea610beb85 798 " BGT Loop1 \n"
AnnaBridge 126:abea610beb85 799
AnnaBridge 126:abea610beb85 800 "Finished: \n"
AnnaBridge 126:abea610beb85 801 " DSB \n"
AnnaBridge 126:abea610beb85 802 " POP {R4-R11} \n"
AnnaBridge 126:abea610beb85 803 " BX lr \n" );
AnnaBridge 126:abea610beb85 804 }
AnnaBridge 126:abea610beb85 805
AnnaBridge 126:abea610beb85 806 /** \brief Invalidate the whole D$
AnnaBridge 126:abea610beb85 807
AnnaBridge 126:abea610beb85 808 DCISW. Invalidate by Set/Way
AnnaBridge 126:abea610beb85 809 */
AnnaBridge 126:abea610beb85 810 // from system_Renesas_RZ_A1.c
AnnaBridge 126:abea610beb85 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 126:abea610beb85 812 __v7_all_cache(0);
AnnaBridge 126:abea610beb85 813 }
<> 130:d75b3fe1f5cb 814 /** \brief Clean the whole D$
<> 130:d75b3fe1f5cb 815
<> 130:d75b3fe1f5cb 816 DCCSW. Clean by Set/Way
<> 130:d75b3fe1f5cb 817 */
<> 130:d75b3fe1f5cb 818
<> 130:d75b3fe1f5cb 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
<> 130:d75b3fe1f5cb 820 __v7_all_cache(1);
<> 130:d75b3fe1f5cb 821 }
<> 130:d75b3fe1f5cb 822
<> 130:d75b3fe1f5cb 823 /** \brief Clean and invalidate the whole D$
<> 130:d75b3fe1f5cb 824
<> 130:d75b3fe1f5cb 825 DCCISW. Clean and Invalidate by Set/Way
<> 130:d75b3fe1f5cb 826 */
<> 130:d75b3fe1f5cb 827
<> 130:d75b3fe1f5cb 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
<> 130:d75b3fe1f5cb 829 __v7_all_cache(2);
<> 130:d75b3fe1f5cb 830 }
AnnaBridge 126:abea610beb85 831 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 126:abea610beb85 832
AnnaBridge 126:abea610beb85 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 126:abea610beb85 834 */
AnnaBridge 126:abea610beb85 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 126:abea610beb85 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
AnnaBridge 126:abea610beb85 837 __DMB();
AnnaBridge 126:abea610beb85 838 }
AnnaBridge 126:abea610beb85 839
AnnaBridge 126:abea610beb85 840 #include "core_ca_mmu.h"
AnnaBridge 126:abea610beb85 841
AnnaBridge 126:abea610beb85 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
AnnaBridge 126:abea610beb85 843 /* GNU gcc specific functions */
AnnaBridge 126:abea610beb85 844
AnnaBridge 126:abea610beb85 845 #define MODE_USR 0x10
AnnaBridge 126:abea610beb85 846 #define MODE_FIQ 0x11
AnnaBridge 126:abea610beb85 847 #define MODE_IRQ 0x12
AnnaBridge 126:abea610beb85 848 #define MODE_SVC 0x13
AnnaBridge 126:abea610beb85 849 #define MODE_MON 0x16
AnnaBridge 126:abea610beb85 850 #define MODE_ABT 0x17
AnnaBridge 126:abea610beb85 851 #define MODE_HYP 0x1A
AnnaBridge 126:abea610beb85 852 #define MODE_UND 0x1B
AnnaBridge 126:abea610beb85 853 #define MODE_SYS 0x1F
AnnaBridge 126:abea610beb85 854
AnnaBridge 126:abea610beb85 855
AnnaBridge 126:abea610beb85 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
AnnaBridge 126:abea610beb85 857 {
AnnaBridge 126:abea610beb85 858 __ASM volatile ("cpsie i");
AnnaBridge 126:abea610beb85 859 }
AnnaBridge 126:abea610beb85 860
AnnaBridge 126:abea610beb85 861 /** \brief Disable IRQ Interrupts
AnnaBridge 126:abea610beb85 862
AnnaBridge 126:abea610beb85 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 126:abea610beb85 864 Can only be executed in Privileged modes.
AnnaBridge 126:abea610beb85 865 */
AnnaBridge 126:abea610beb85 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
AnnaBridge 126:abea610beb85 867 {
AnnaBridge 126:abea610beb85 868 uint32_t result;
AnnaBridge 126:abea610beb85 869
AnnaBridge 126:abea610beb85 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
AnnaBridge 126:abea610beb85 871 __ASM volatile ("cpsid i");
AnnaBridge 126:abea610beb85 872 return(result & 0x80);
AnnaBridge 126:abea610beb85 873 }
AnnaBridge 126:abea610beb85 874
AnnaBridge 126:abea610beb85 875
AnnaBridge 126:abea610beb85 876 /** \brief Get APSR Register
AnnaBridge 126:abea610beb85 877
AnnaBridge 126:abea610beb85 878 This function returns the content of the APSR Register.
AnnaBridge 126:abea610beb85 879
AnnaBridge 126:abea610beb85 880 \return APSR Register value
AnnaBridge 126:abea610beb85 881 */
AnnaBridge 126:abea610beb85 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 126:abea610beb85 883 {
AnnaBridge 126:abea610beb85 884 #if 1
AnnaBridge 126:abea610beb85 885 register uint32_t __regAPSR;
AnnaBridge 126:abea610beb85 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
AnnaBridge 126:abea610beb85 887 #else
AnnaBridge 126:abea610beb85 888 register uint32_t __regAPSR __ASM("apsr");
AnnaBridge 126:abea610beb85 889 #endif
AnnaBridge 126:abea610beb85 890 return(__regAPSR);
AnnaBridge 126:abea610beb85 891 }
AnnaBridge 126:abea610beb85 892
AnnaBridge 126:abea610beb85 893
AnnaBridge 126:abea610beb85 894 /** \brief Get CPSR Register
AnnaBridge 126:abea610beb85 895
AnnaBridge 126:abea610beb85 896 This function returns the content of the CPSR Register.
AnnaBridge 126:abea610beb85 897
AnnaBridge 126:abea610beb85 898 \return CPSR Register value
AnnaBridge 126:abea610beb85 899 */
AnnaBridge 126:abea610beb85 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
AnnaBridge 126:abea610beb85 901 {
AnnaBridge 126:abea610beb85 902 #if 1
AnnaBridge 126:abea610beb85 903 register uint32_t __regCPSR;
AnnaBridge 126:abea610beb85 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
AnnaBridge 126:abea610beb85 905 #else
AnnaBridge 126:abea610beb85 906 register uint32_t __regCPSR __ASM("cpsr");
AnnaBridge 126:abea610beb85 907 #endif
AnnaBridge 126:abea610beb85 908 return(__regCPSR);
AnnaBridge 126:abea610beb85 909 }
AnnaBridge 126:abea610beb85 910
AnnaBridge 126:abea610beb85 911 #if 0
AnnaBridge 126:abea610beb85 912 /** \brief Set Stack Pointer
AnnaBridge 126:abea610beb85 913
AnnaBridge 126:abea610beb85 914 This function assigns the given value to the current stack pointer.
AnnaBridge 126:abea610beb85 915
AnnaBridge 126:abea610beb85 916 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 126:abea610beb85 917 */
AnnaBridge 126:abea610beb85 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
AnnaBridge 126:abea610beb85 919 {
AnnaBridge 126:abea610beb85 920 register uint32_t __regSP __ASM("sp");
AnnaBridge 126:abea610beb85 921 __regSP = topOfStack;
AnnaBridge 126:abea610beb85 922 }
AnnaBridge 126:abea610beb85 923 #endif
AnnaBridge 126:abea610beb85 924
AnnaBridge 126:abea610beb85 925 /** \brief Get link register
AnnaBridge 126:abea610beb85 926
AnnaBridge 126:abea610beb85 927 This function returns the value of the link register
AnnaBridge 126:abea610beb85 928
AnnaBridge 126:abea610beb85 929 \return Value of link register
AnnaBridge 126:abea610beb85 930 */
AnnaBridge 126:abea610beb85 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
AnnaBridge 126:abea610beb85 932 {
AnnaBridge 126:abea610beb85 933 register uint32_t __reglr __ASM("lr");
AnnaBridge 126:abea610beb85 934 return(__reglr);
AnnaBridge 126:abea610beb85 935 }
AnnaBridge 126:abea610beb85 936
AnnaBridge 126:abea610beb85 937 #if 0
AnnaBridge 126:abea610beb85 938 /** \brief Set link register
AnnaBridge 126:abea610beb85 939
AnnaBridge 126:abea610beb85 940 This function sets the value of the link register
AnnaBridge 126:abea610beb85 941
AnnaBridge 126:abea610beb85 942 \param [in] lr LR value to set
AnnaBridge 126:abea610beb85 943 */
AnnaBridge 126:abea610beb85 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
AnnaBridge 126:abea610beb85 945 {
AnnaBridge 126:abea610beb85 946 register uint32_t __reglr __ASM("lr");
AnnaBridge 126:abea610beb85 947 __reglr = lr;
AnnaBridge 126:abea610beb85 948 }
AnnaBridge 126:abea610beb85 949 #endif
AnnaBridge 126:abea610beb85 950
AnnaBridge 126:abea610beb85 951 /** \brief Set Process Stack Pointer
AnnaBridge 126:abea610beb85 952
AnnaBridge 126:abea610beb85 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
AnnaBridge 126:abea610beb85 954
AnnaBridge 126:abea610beb85 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
AnnaBridge 126:abea610beb85 956 */
AnnaBridge 126:abea610beb85 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 126:abea610beb85 958 {
AnnaBridge 126:abea610beb85 959 __asm__ volatile (
AnnaBridge 126:abea610beb85 960 ".ARM;"
AnnaBridge 126:abea610beb85 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
AnnaBridge 126:abea610beb85 962
AnnaBridge 126:abea610beb85 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
AnnaBridge 126:abea610beb85 964 "MRS R1, CPSR;"
AnnaBridge 126:abea610beb85 965 "CPS %0;" /* ;no effect in USR mode */
AnnaBridge 126:abea610beb85 966 "MOV SP, R0;"
AnnaBridge 126:abea610beb85 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
AnnaBridge 126:abea610beb85 968 "ISB;"
AnnaBridge 126:abea610beb85 969 //"BX LR;"
AnnaBridge 126:abea610beb85 970 :
AnnaBridge 126:abea610beb85 971 : "i"(MODE_SYS)
AnnaBridge 126:abea610beb85 972 : "r0", "r1");
AnnaBridge 126:abea610beb85 973 return;
AnnaBridge 126:abea610beb85 974 }
AnnaBridge 126:abea610beb85 975
AnnaBridge 126:abea610beb85 976 /** \brief Set User Mode
AnnaBridge 126:abea610beb85 977
AnnaBridge 126:abea610beb85 978 This function changes the processor state to User Mode
AnnaBridge 126:abea610beb85 979 */
AnnaBridge 126:abea610beb85 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
AnnaBridge 126:abea610beb85 981 {
AnnaBridge 126:abea610beb85 982 __asm__ volatile (
AnnaBridge 126:abea610beb85 983 ".ARM;"
AnnaBridge 126:abea610beb85 984
AnnaBridge 126:abea610beb85 985 "CPS %0;"
AnnaBridge 126:abea610beb85 986 //"BX LR;"
AnnaBridge 126:abea610beb85 987 :
AnnaBridge 126:abea610beb85 988 : "i"(MODE_USR)
AnnaBridge 126:abea610beb85 989 : );
AnnaBridge 126:abea610beb85 990 return;
AnnaBridge 126:abea610beb85 991 }
AnnaBridge 126:abea610beb85 992
AnnaBridge 126:abea610beb85 993
AnnaBridge 126:abea610beb85 994 /** \brief Enable FIQ
AnnaBridge 126:abea610beb85 995
AnnaBridge 126:abea610beb85 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 126:abea610beb85 997 Can only be executed in Privileged modes.
AnnaBridge 126:abea610beb85 998 */
AnnaBridge 126:abea610beb85 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
AnnaBridge 126:abea610beb85 1000
AnnaBridge 126:abea610beb85 1001
AnnaBridge 126:abea610beb85 1002 /** \brief Disable FIQ
AnnaBridge 126:abea610beb85 1003
AnnaBridge 126:abea610beb85 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 126:abea610beb85 1005 Can only be executed in Privileged modes.
AnnaBridge 126:abea610beb85 1006 */
AnnaBridge 126:abea610beb85 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
AnnaBridge 126:abea610beb85 1008
AnnaBridge 126:abea610beb85 1009
AnnaBridge 126:abea610beb85 1010 /** \brief Get FPSCR
AnnaBridge 126:abea610beb85 1011
AnnaBridge 126:abea610beb85 1012 This function returns the current value of the Floating Point Status/Control register.
AnnaBridge 126:abea610beb85 1013
AnnaBridge 126:abea610beb85 1014 \return Floating Point Status/Control register value
AnnaBridge 126:abea610beb85 1015 */
AnnaBridge 126:abea610beb85 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 126:abea610beb85 1017 {
AnnaBridge 126:abea610beb85 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 126:abea610beb85 1019 #if 1
AnnaBridge 126:abea610beb85 1020 uint32_t result;
AnnaBridge 126:abea610beb85 1021
AnnaBridge 126:abea610beb85 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
AnnaBridge 126:abea610beb85 1023 return (result);
AnnaBridge 126:abea610beb85 1024 #else
AnnaBridge 126:abea610beb85 1025 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 126:abea610beb85 1026 return(__regfpscr);
AnnaBridge 126:abea610beb85 1027 #endif
AnnaBridge 126:abea610beb85 1028 #else
AnnaBridge 126:abea610beb85 1029 return(0);
AnnaBridge 126:abea610beb85 1030 #endif
AnnaBridge 126:abea610beb85 1031 }
AnnaBridge 126:abea610beb85 1032
AnnaBridge 126:abea610beb85 1033
AnnaBridge 126:abea610beb85 1034 /** \brief Set FPSCR
AnnaBridge 126:abea610beb85 1035
AnnaBridge 126:abea610beb85 1036 This function assigns the given value to the Floating Point Status/Control register.
AnnaBridge 126:abea610beb85 1037
AnnaBridge 126:abea610beb85 1038 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 126:abea610beb85 1039 */
AnnaBridge 126:abea610beb85 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 126:abea610beb85 1041 {
AnnaBridge 126:abea610beb85 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 126:abea610beb85 1043 #if 1
AnnaBridge 126:abea610beb85 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
AnnaBridge 126:abea610beb85 1045 #else
AnnaBridge 126:abea610beb85 1046 register uint32_t __regfpscr __ASM("fpscr");
AnnaBridge 126:abea610beb85 1047 __regfpscr = (fpscr);
AnnaBridge 126:abea610beb85 1048 #endif
AnnaBridge 126:abea610beb85 1049 #endif
AnnaBridge 126:abea610beb85 1050 }
AnnaBridge 126:abea610beb85 1051
AnnaBridge 126:abea610beb85 1052 /** \brief Get FPEXC
AnnaBridge 126:abea610beb85 1053
AnnaBridge 126:abea610beb85 1054 This function returns the current value of the Floating Point Exception Control register.
AnnaBridge 126:abea610beb85 1055
AnnaBridge 126:abea610beb85 1056 \return Floating Point Exception Control register value
AnnaBridge 126:abea610beb85 1057 */
AnnaBridge 126:abea610beb85 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
AnnaBridge 126:abea610beb85 1059 {
AnnaBridge 126:abea610beb85 1060 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 1061 #if 1
AnnaBridge 126:abea610beb85 1062 uint32_t result;
AnnaBridge 126:abea610beb85 1063
AnnaBridge 126:abea610beb85 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
AnnaBridge 126:abea610beb85 1065 return (result);
AnnaBridge 126:abea610beb85 1066 #else
AnnaBridge 126:abea610beb85 1067 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 126:abea610beb85 1068 return(__regfpexc);
AnnaBridge 126:abea610beb85 1069 #endif
AnnaBridge 126:abea610beb85 1070 #else
AnnaBridge 126:abea610beb85 1071 return(0);
AnnaBridge 126:abea610beb85 1072 #endif
AnnaBridge 126:abea610beb85 1073 }
AnnaBridge 126:abea610beb85 1074
AnnaBridge 126:abea610beb85 1075
AnnaBridge 126:abea610beb85 1076 /** \brief Set FPEXC
AnnaBridge 126:abea610beb85 1077
AnnaBridge 126:abea610beb85 1078 This function assigns the given value to the Floating Point Exception Control register.
AnnaBridge 126:abea610beb85 1079
AnnaBridge 126:abea610beb85 1080 \param [in] fpscr Floating Point Exception Control value to set
AnnaBridge 126:abea610beb85 1081 */
AnnaBridge 126:abea610beb85 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
AnnaBridge 126:abea610beb85 1083 {
AnnaBridge 126:abea610beb85 1084 #if (__FPU_PRESENT == 1)
AnnaBridge 126:abea610beb85 1085 #if 1
AnnaBridge 126:abea610beb85 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
AnnaBridge 126:abea610beb85 1087 #else
AnnaBridge 126:abea610beb85 1088 register uint32_t __regfpexc __ASM("fpexc");
AnnaBridge 126:abea610beb85 1089 __regfpexc = (fpexc);
AnnaBridge 126:abea610beb85 1090 #endif
AnnaBridge 126:abea610beb85 1091 #endif
AnnaBridge 126:abea610beb85 1092 }
AnnaBridge 126:abea610beb85 1093
AnnaBridge 126:abea610beb85 1094 /** \brief Get CPACR
AnnaBridge 126:abea610beb85 1095
AnnaBridge 126:abea610beb85 1096 This function returns the current value of the Coprocessor Access Control register.
AnnaBridge 126:abea610beb85 1097
AnnaBridge 126:abea610beb85 1098 \return Coprocessor Access Control register value
AnnaBridge 126:abea610beb85 1099 */
AnnaBridge 126:abea610beb85 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
AnnaBridge 126:abea610beb85 1101 {
AnnaBridge 126:abea610beb85 1102 #if 1
AnnaBridge 126:abea610beb85 1103 register uint32_t __regCPACR;
AnnaBridge 126:abea610beb85 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
AnnaBridge 126:abea610beb85 1105 #else
AnnaBridge 126:abea610beb85 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 126:abea610beb85 1107 #endif
AnnaBridge 126:abea610beb85 1108 return __regCPACR;
AnnaBridge 126:abea610beb85 1109 }
AnnaBridge 126:abea610beb85 1110
AnnaBridge 126:abea610beb85 1111 /** \brief Set CPACR
AnnaBridge 126:abea610beb85 1112
AnnaBridge 126:abea610beb85 1113 This function assigns the given value to the Coprocessor Access Control register.
AnnaBridge 126:abea610beb85 1114
AnnaBridge 126:abea610beb85 1115 \param [in] cpacr Coprocessor Acccess Control value to set
AnnaBridge 126:abea610beb85 1116 */
AnnaBridge 126:abea610beb85 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
AnnaBridge 126:abea610beb85 1118 {
AnnaBridge 126:abea610beb85 1119 #if 1
AnnaBridge 126:abea610beb85 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
AnnaBridge 126:abea610beb85 1121 #else
AnnaBridge 126:abea610beb85 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
AnnaBridge 126:abea610beb85 1123 __regCPACR = cpacr;
AnnaBridge 126:abea610beb85 1124 #endif
AnnaBridge 126:abea610beb85 1125 __ISB();
AnnaBridge 126:abea610beb85 1126 }
AnnaBridge 126:abea610beb85 1127
AnnaBridge 126:abea610beb85 1128 /** \brief Get CBAR
AnnaBridge 126:abea610beb85 1129
AnnaBridge 126:abea610beb85 1130 This function returns the value of the Configuration Base Address register.
AnnaBridge 126:abea610beb85 1131
AnnaBridge 126:abea610beb85 1132 \return Configuration Base Address register value
AnnaBridge 126:abea610beb85 1133 */
AnnaBridge 126:abea610beb85 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
AnnaBridge 126:abea610beb85 1135 #if 1
AnnaBridge 126:abea610beb85 1136 register uint32_t __regCBAR;
AnnaBridge 126:abea610beb85 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
AnnaBridge 126:abea610beb85 1138 #else
AnnaBridge 126:abea610beb85 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
AnnaBridge 126:abea610beb85 1140 #endif
AnnaBridge 126:abea610beb85 1141 return(__regCBAR);
AnnaBridge 126:abea610beb85 1142 }
AnnaBridge 126:abea610beb85 1143
AnnaBridge 126:abea610beb85 1144 /** \brief Get TTBR0
AnnaBridge 126:abea610beb85 1145
AnnaBridge 126:abea610beb85 1146 This function returns the value of the Translation Table Base Register 0.
AnnaBridge 126:abea610beb85 1147
AnnaBridge 126:abea610beb85 1148 \return Translation Table Base Register 0 value
AnnaBridge 126:abea610beb85 1149 */
AnnaBridge 126:abea610beb85 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
AnnaBridge 126:abea610beb85 1151 #if 1
AnnaBridge 126:abea610beb85 1152 register uint32_t __regTTBR0;
AnnaBridge 126:abea610beb85 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
AnnaBridge 126:abea610beb85 1154 #else
AnnaBridge 126:abea610beb85 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 126:abea610beb85 1156 #endif
AnnaBridge 126:abea610beb85 1157 return(__regTTBR0);
AnnaBridge 126:abea610beb85 1158 }
AnnaBridge 126:abea610beb85 1159
AnnaBridge 126:abea610beb85 1160 /** \brief Set TTBR0
AnnaBridge 126:abea610beb85 1161
AnnaBridge 126:abea610beb85 1162 This function assigns the given value to the Translation Table Base Register 0.
AnnaBridge 126:abea610beb85 1163
AnnaBridge 126:abea610beb85 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
AnnaBridge 126:abea610beb85 1165 */
AnnaBridge 126:abea610beb85 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
AnnaBridge 126:abea610beb85 1167 #if 1
AnnaBridge 126:abea610beb85 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
AnnaBridge 126:abea610beb85 1169 #else
AnnaBridge 126:abea610beb85 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
AnnaBridge 126:abea610beb85 1171 __regTTBR0 = ttbr0;
AnnaBridge 126:abea610beb85 1172 #endif
AnnaBridge 126:abea610beb85 1173 __ISB();
AnnaBridge 126:abea610beb85 1174 }
AnnaBridge 126:abea610beb85 1175
AnnaBridge 126:abea610beb85 1176 /** \brief Get DACR
AnnaBridge 126:abea610beb85 1177
AnnaBridge 126:abea610beb85 1178 This function returns the value of the Domain Access Control Register.
AnnaBridge 126:abea610beb85 1179
AnnaBridge 126:abea610beb85 1180 \return Domain Access Control Register value
AnnaBridge 126:abea610beb85 1181 */
AnnaBridge 126:abea610beb85 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
AnnaBridge 126:abea610beb85 1183 #if 1
AnnaBridge 126:abea610beb85 1184 register uint32_t __regDACR;
AnnaBridge 126:abea610beb85 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
AnnaBridge 126:abea610beb85 1186 #else
AnnaBridge 126:abea610beb85 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 126:abea610beb85 1188 #endif
AnnaBridge 126:abea610beb85 1189 return(__regDACR);
AnnaBridge 126:abea610beb85 1190 }
AnnaBridge 126:abea610beb85 1191
AnnaBridge 126:abea610beb85 1192 /** \brief Set DACR
AnnaBridge 126:abea610beb85 1193
AnnaBridge 126:abea610beb85 1194 This function assigns the given value to the Domain Access Control Register.
AnnaBridge 126:abea610beb85 1195
AnnaBridge 126:abea610beb85 1196 \param [in] dacr Domain Access Control Register value to set
AnnaBridge 126:abea610beb85 1197 */
AnnaBridge 126:abea610beb85 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
AnnaBridge 126:abea610beb85 1199 #if 1
AnnaBridge 126:abea610beb85 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
AnnaBridge 126:abea610beb85 1201 #else
AnnaBridge 126:abea610beb85 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
AnnaBridge 126:abea610beb85 1203 __regDACR = dacr;
AnnaBridge 126:abea610beb85 1204 #endif
AnnaBridge 126:abea610beb85 1205 __ISB();
AnnaBridge 126:abea610beb85 1206 }
AnnaBridge 126:abea610beb85 1207
AnnaBridge 126:abea610beb85 1208 /******************************** Cache and BTAC enable ****************************************************/
AnnaBridge 126:abea610beb85 1209
AnnaBridge 126:abea610beb85 1210 /** \brief Set SCTLR
AnnaBridge 126:abea610beb85 1211
AnnaBridge 126:abea610beb85 1212 This function assigns the given value to the System Control Register.
AnnaBridge 126:abea610beb85 1213
AnnaBridge 126:abea610beb85 1214 \param [in] sctlr System Control Register value to set
AnnaBridge 126:abea610beb85 1215 */
AnnaBridge 126:abea610beb85 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
AnnaBridge 126:abea610beb85 1217 {
AnnaBridge 126:abea610beb85 1218 #if 1
AnnaBridge 126:abea610beb85 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
AnnaBridge 126:abea610beb85 1220 #else
AnnaBridge 126:abea610beb85 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 126:abea610beb85 1222 __regSCTLR = sctlr;
AnnaBridge 126:abea610beb85 1223 #endif
AnnaBridge 126:abea610beb85 1224 }
AnnaBridge 126:abea610beb85 1225
AnnaBridge 126:abea610beb85 1226 /** \brief Get SCTLR
AnnaBridge 126:abea610beb85 1227
AnnaBridge 126:abea610beb85 1228 This function returns the value of the System Control Register.
AnnaBridge 126:abea610beb85 1229
AnnaBridge 126:abea610beb85 1230 \return System Control Register value
AnnaBridge 126:abea610beb85 1231 */
AnnaBridge 126:abea610beb85 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
AnnaBridge 126:abea610beb85 1233 #if 1
AnnaBridge 126:abea610beb85 1234 register uint32_t __regSCTLR;
AnnaBridge 126:abea610beb85 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
AnnaBridge 126:abea610beb85 1236 #else
AnnaBridge 126:abea610beb85 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
AnnaBridge 126:abea610beb85 1238 #endif
AnnaBridge 126:abea610beb85 1239 return(__regSCTLR);
AnnaBridge 126:abea610beb85 1240 }
AnnaBridge 126:abea610beb85 1241
AnnaBridge 126:abea610beb85 1242 /** \brief Enable Caches
AnnaBridge 126:abea610beb85 1243
AnnaBridge 126:abea610beb85 1244 Enable Caches
AnnaBridge 126:abea610beb85 1245 */
AnnaBridge 126:abea610beb85 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
AnnaBridge 126:abea610beb85 1247 // Set I bit 12 to enable I Cache
AnnaBridge 126:abea610beb85 1248 // Set C bit 2 to enable D Cache
AnnaBridge 126:abea610beb85 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
AnnaBridge 126:abea610beb85 1250 }
AnnaBridge 126:abea610beb85 1251
AnnaBridge 126:abea610beb85 1252 /** \brief Disable Caches
AnnaBridge 126:abea610beb85 1253
AnnaBridge 126:abea610beb85 1254 Disable Caches
AnnaBridge 126:abea610beb85 1255 */
AnnaBridge 126:abea610beb85 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
AnnaBridge 126:abea610beb85 1257 // Clear I bit 12 to disable I Cache
AnnaBridge 126:abea610beb85 1258 // Clear C bit 2 to disable D Cache
AnnaBridge 126:abea610beb85 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge 126:abea610beb85 1260 __ISB();
AnnaBridge 126:abea610beb85 1261 }
AnnaBridge 126:abea610beb85 1262
AnnaBridge 126:abea610beb85 1263 /** \brief Enable BTAC
AnnaBridge 126:abea610beb85 1264
AnnaBridge 126:abea610beb85 1265 Enable BTAC
AnnaBridge 126:abea610beb85 1266 */
AnnaBridge 126:abea610beb85 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
AnnaBridge 126:abea610beb85 1268 // Set Z bit 11 to enable branch prediction
AnnaBridge 126:abea610beb85 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
AnnaBridge 126:abea610beb85 1270 __ISB();
AnnaBridge 126:abea610beb85 1271 }
AnnaBridge 126:abea610beb85 1272
AnnaBridge 126:abea610beb85 1273 /** \brief Disable BTAC
AnnaBridge 126:abea610beb85 1274
AnnaBridge 126:abea610beb85 1275 Disable BTAC
AnnaBridge 126:abea610beb85 1276 */
AnnaBridge 126:abea610beb85 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
AnnaBridge 126:abea610beb85 1278 // Clear Z bit 11 to disable branch prediction
AnnaBridge 126:abea610beb85 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge 126:abea610beb85 1280 }
AnnaBridge 126:abea610beb85 1281
AnnaBridge 126:abea610beb85 1282
AnnaBridge 126:abea610beb85 1283 /** \brief Enable MMU
AnnaBridge 126:abea610beb85 1284
AnnaBridge 126:abea610beb85 1285 Enable MMU
AnnaBridge 126:abea610beb85 1286 */
AnnaBridge 126:abea610beb85 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
AnnaBridge 126:abea610beb85 1288 // Set M bit 0 to enable the MMU
AnnaBridge 126:abea610beb85 1289 // Set AFE bit to enable simplified access permissions model
AnnaBridge 126:abea610beb85 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge 126:abea610beb85 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
AnnaBridge 126:abea610beb85 1292 __ISB();
AnnaBridge 126:abea610beb85 1293 }
AnnaBridge 126:abea610beb85 1294
AnnaBridge 126:abea610beb85 1295 /** \brief Disable MMU
AnnaBridge 126:abea610beb85 1296
AnnaBridge 126:abea610beb85 1297 Disable MMU
AnnaBridge 126:abea610beb85 1298 */
AnnaBridge 126:abea610beb85 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
AnnaBridge 126:abea610beb85 1300 // Clear M bit 0 to disable the MMU
AnnaBridge 126:abea610beb85 1301 __set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge 126:abea610beb85 1302 __ISB();
AnnaBridge 126:abea610beb85 1303 }
AnnaBridge 126:abea610beb85 1304
AnnaBridge 126:abea610beb85 1305 /******************************** TLB maintenance operations ************************************************/
AnnaBridge 126:abea610beb85 1306 /** \brief Invalidate the whole tlb
AnnaBridge 126:abea610beb85 1307
AnnaBridge 126:abea610beb85 1308 TLBIALL. Invalidate the whole tlb
AnnaBridge 126:abea610beb85 1309 */
AnnaBridge 126:abea610beb85 1310
AnnaBridge 126:abea610beb85 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
AnnaBridge 126:abea610beb85 1312 #if 1
AnnaBridge 126:abea610beb85 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
AnnaBridge 126:abea610beb85 1314 #else
AnnaBridge 126:abea610beb85 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
AnnaBridge 126:abea610beb85 1316 __TLBIALL = 0;
AnnaBridge 126:abea610beb85 1317 #endif
AnnaBridge 126:abea610beb85 1318 __DSB();
AnnaBridge 126:abea610beb85 1319 __ISB();
AnnaBridge 126:abea610beb85 1320 }
AnnaBridge 126:abea610beb85 1321
AnnaBridge 126:abea610beb85 1322 /******************************** BTB maintenance operations ************************************************/
AnnaBridge 126:abea610beb85 1323 /** \brief Invalidate entire branch predictor array
AnnaBridge 126:abea610beb85 1324
AnnaBridge 126:abea610beb85 1325 BPIALL. Branch Predictor Invalidate All.
AnnaBridge 126:abea610beb85 1326 */
AnnaBridge 126:abea610beb85 1327
AnnaBridge 126:abea610beb85 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
AnnaBridge 126:abea610beb85 1329 #if 1
AnnaBridge 126:abea610beb85 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
AnnaBridge 126:abea610beb85 1331 #else
AnnaBridge 126:abea610beb85 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
AnnaBridge 126:abea610beb85 1333 __BPIALL = 0;
AnnaBridge 126:abea610beb85 1334 #endif
AnnaBridge 126:abea610beb85 1335 __DSB(); //ensure completion of the invalidation
AnnaBridge 126:abea610beb85 1336 __ISB(); //ensure instruction fetch path sees new state
AnnaBridge 126:abea610beb85 1337 }
AnnaBridge 126:abea610beb85 1338
AnnaBridge 126:abea610beb85 1339
AnnaBridge 126:abea610beb85 1340 /******************************** L1 cache operations ******************************************************/
AnnaBridge 126:abea610beb85 1341
AnnaBridge 126:abea610beb85 1342 /** \brief Invalidate the whole I$
AnnaBridge 126:abea610beb85 1343
AnnaBridge 126:abea610beb85 1344 ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge 126:abea610beb85 1345 */
AnnaBridge 126:abea610beb85 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
AnnaBridge 126:abea610beb85 1347 #if 1
AnnaBridge 126:abea610beb85 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
AnnaBridge 126:abea610beb85 1349 #else
AnnaBridge 126:abea610beb85 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
AnnaBridge 126:abea610beb85 1351 __ICIALLU = 0;
AnnaBridge 126:abea610beb85 1352 #endif
AnnaBridge 126:abea610beb85 1353 __DSB(); //ensure completion of the invalidation
AnnaBridge 126:abea610beb85 1354 __ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge 126:abea610beb85 1355 }
AnnaBridge 126:abea610beb85 1356
AnnaBridge 126:abea610beb85 1357 /** \brief Clean D$ by MVA
AnnaBridge 126:abea610beb85 1358
AnnaBridge 126:abea610beb85 1359 DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge 126:abea610beb85 1360 */
AnnaBridge 126:abea610beb85 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
AnnaBridge 126:abea610beb85 1362 #if 1
AnnaBridge 126:abea610beb85 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
AnnaBridge 126:abea610beb85 1364 #else
AnnaBridge 126:abea610beb85 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
AnnaBridge 126:abea610beb85 1366 __DCCMVAC = (uint32_t)va;
AnnaBridge 126:abea610beb85 1367 #endif
AnnaBridge 126:abea610beb85 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 126:abea610beb85 1369 }
AnnaBridge 126:abea610beb85 1370
AnnaBridge 126:abea610beb85 1371 /** \brief Invalidate D$ by MVA
AnnaBridge 126:abea610beb85 1372
AnnaBridge 126:abea610beb85 1373 DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge 126:abea610beb85 1374 */
AnnaBridge 126:abea610beb85 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
AnnaBridge 126:abea610beb85 1376 #if 1
AnnaBridge 126:abea610beb85 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
AnnaBridge 126:abea610beb85 1378 #else
AnnaBridge 126:abea610beb85 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
AnnaBridge 126:abea610beb85 1380 __DCIMVAC = (uint32_t)va;
AnnaBridge 126:abea610beb85 1381 #endif
AnnaBridge 126:abea610beb85 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 126:abea610beb85 1383 }
AnnaBridge 126:abea610beb85 1384
AnnaBridge 126:abea610beb85 1385 /** \brief Clean and Invalidate D$ by MVA
AnnaBridge 126:abea610beb85 1386
AnnaBridge 126:abea610beb85 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge 126:abea610beb85 1388 */
AnnaBridge 126:abea610beb85 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
AnnaBridge 126:abea610beb85 1390 #if 1
AnnaBridge 126:abea610beb85 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
AnnaBridge 126:abea610beb85 1392 #else
AnnaBridge 126:abea610beb85 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
AnnaBridge 126:abea610beb85 1394 __DCCIMVAC = (uint32_t)va;
AnnaBridge 126:abea610beb85 1395 #endif
AnnaBridge 126:abea610beb85 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge 126:abea610beb85 1397 }
AnnaBridge 126:abea610beb85 1398
AnnaBridge 126:abea610beb85 1399 /** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge 126:abea610beb85 1400
AnnaBridge 126:abea610beb85 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge 126:abea610beb85 1402 */
AnnaBridge 126:abea610beb85 1403 extern void __v7_all_cache(uint32_t op);
AnnaBridge 126:abea610beb85 1404
AnnaBridge 126:abea610beb85 1405
AnnaBridge 126:abea610beb85 1406 /** \brief Invalidate the whole D$
AnnaBridge 126:abea610beb85 1407
AnnaBridge 126:abea610beb85 1408 DCISW. Invalidate by Set/Way
AnnaBridge 126:abea610beb85 1409 */
AnnaBridge 126:abea610beb85 1410
AnnaBridge 126:abea610beb85 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
AnnaBridge 126:abea610beb85 1412 __v7_all_cache(0);
AnnaBridge 126:abea610beb85 1413 }
AnnaBridge 126:abea610beb85 1414
AnnaBridge 126:abea610beb85 1415 /** \brief Clean the whole D$
AnnaBridge 126:abea610beb85 1416
AnnaBridge 126:abea610beb85 1417 DCCSW. Clean by Set/Way
AnnaBridge 126:abea610beb85 1418 */
AnnaBridge 126:abea610beb85 1419
AnnaBridge 126:abea610beb85 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
AnnaBridge 126:abea610beb85 1421 __v7_all_cache(1);
AnnaBridge 126:abea610beb85 1422 }
AnnaBridge 126:abea610beb85 1423
AnnaBridge 126:abea610beb85 1424 /** \brief Clean and invalidate the whole D$
AnnaBridge 126:abea610beb85 1425
AnnaBridge 126:abea610beb85 1426 DCCISW. Clean and Invalidate by Set/Way
AnnaBridge 126:abea610beb85 1427 */
AnnaBridge 126:abea610beb85 1428
AnnaBridge 126:abea610beb85 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
AnnaBridge 126:abea610beb85 1430 __v7_all_cache(2);
AnnaBridge 126:abea610beb85 1431 }
AnnaBridge 126:abea610beb85 1432
AnnaBridge 126:abea610beb85 1433 #include "core_ca_mmu.h"
AnnaBridge 126:abea610beb85 1434
AnnaBridge 126:abea610beb85 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
AnnaBridge 126:abea610beb85 1436
AnnaBridge 126:abea610beb85 1437 #error TASKING Compiler support not implemented for Cortex-A
AnnaBridge 126:abea610beb85 1438
AnnaBridge 126:abea610beb85 1439 #endif
AnnaBridge 126:abea610beb85 1440
AnnaBridge 126:abea610beb85 1441 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 126:abea610beb85 1442
AnnaBridge 126:abea610beb85 1443
AnnaBridge 126:abea610beb85 1444 #endif /* __CORE_CAFUNC_H__ */