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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/core_cmFunc.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
135:176b8275d35d 
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**************************************************************************//**
<> 135:176b8275d35d 2 * @file core_cmFunc.h
<> 135:176b8275d35d 3 * @brief CMSIS Cortex-M Core Function Access Header File
<> 135:176b8275d35d 4 * @version V4.10
<> 135:176b8275d35d 5 * @date 18. March 2015
<> 135:176b8275d35d 6 *
<> 135:176b8275d35d 7 * @note
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 ******************************************************************************/
<> 135:176b8275d35d 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
<> 135:176b8275d35d 11
<> 135:176b8275d35d 12 All rights reserved.
<> 135:176b8275d35d 13 Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 14 modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 15 - Redistributions of source code must retain the above copyright
<> 135:176b8275d35d 16 notice, this list of conditions and the following disclaimer.
<> 135:176b8275d35d 17 - Redistributions in binary form must reproduce the above copyright
<> 135:176b8275d35d 18 notice, this list of conditions and the following disclaimer in the
<> 135:176b8275d35d 19 documentation and/or other materials provided with the distribution.
<> 135:176b8275d35d 20 - Neither the name of ARM nor the names of its contributors may be used
<> 135:176b8275d35d 21 to endorse or promote products derived from this software without
<> 135:176b8275d35d 22 specific prior written permission.
<> 135:176b8275d35d 23 *
<> 135:176b8275d35d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 135:176b8275d35d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 135:176b8275d35d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 135:176b8275d35d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 135:176b8275d35d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 135:176b8275d35d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 135:176b8275d35d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 135:176b8275d35d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 135:176b8275d35d 34 POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 35 ---------------------------------------------------------------------------*/
<> 135:176b8275d35d 36
<> 135:176b8275d35d 37
<> 135:176b8275d35d 38 #ifndef __CORE_CMFUNC_H
<> 135:176b8275d35d 39 #define __CORE_CMFUNC_H
<> 135:176b8275d35d 40
<> 135:176b8275d35d 41
<> 135:176b8275d35d 42 /* ########################### Core Function Access ########################### */
<> 135:176b8275d35d 43 /** \ingroup CMSIS_Core_FunctionInterface
<> 135:176b8275d35d 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
<> 135:176b8275d35d 45 @{
<> 135:176b8275d35d 46 */
<> 135:176b8275d35d 47
<> 135:176b8275d35d 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 135:176b8275d35d 49 /* ARM armcc specific functions */
<> 135:176b8275d35d 50
<> 135:176b8275d35d 51 #if (__ARMCC_VERSION < 400677)
<> 135:176b8275d35d 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
<> 135:176b8275d35d 53 #endif
<> 135:176b8275d35d 54
<> 135:176b8275d35d 55 /* intrinsic void __enable_irq(); */
<> 135:176b8275d35d 56 /* intrinsic void __disable_irq(); */
<> 135:176b8275d35d 57
<> 135:176b8275d35d 58 /** \brief Get Control Register
<> 135:176b8275d35d 59
<> 135:176b8275d35d 60 This function returns the content of the Control Register.
<> 135:176b8275d35d 61
<> 135:176b8275d35d 62 \return Control Register value
<> 135:176b8275d35d 63 */
<> 135:176b8275d35d 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 135:176b8275d35d 65 {
<> 135:176b8275d35d 66 register uint32_t __regControl __ASM("control");
<> 135:176b8275d35d 67 return(__regControl);
<> 135:176b8275d35d 68 }
<> 135:176b8275d35d 69
<> 135:176b8275d35d 70
<> 135:176b8275d35d 71 /** \brief Set Control Register
<> 135:176b8275d35d 72
<> 135:176b8275d35d 73 This function writes the given value to the Control Register.
<> 135:176b8275d35d 74
<> 135:176b8275d35d 75 \param [in] control Control Register value to set
<> 135:176b8275d35d 76 */
<> 135:176b8275d35d 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 135:176b8275d35d 78 {
<> 135:176b8275d35d 79 register uint32_t __regControl __ASM("control");
<> 135:176b8275d35d 80 __regControl = control;
<> 135:176b8275d35d 81 }
<> 135:176b8275d35d 82
<> 135:176b8275d35d 83
<> 135:176b8275d35d 84 /** \brief Get IPSR Register
<> 135:176b8275d35d 85
<> 135:176b8275d35d 86 This function returns the content of the IPSR Register.
<> 135:176b8275d35d 87
<> 135:176b8275d35d 88 \return IPSR Register value
<> 135:176b8275d35d 89 */
<> 135:176b8275d35d 90 __STATIC_INLINE uint32_t __get_IPSR(void)
<> 135:176b8275d35d 91 {
<> 135:176b8275d35d 92 register uint32_t __regIPSR __ASM("ipsr");
<> 135:176b8275d35d 93 return(__regIPSR);
<> 135:176b8275d35d 94 }
<> 135:176b8275d35d 95
<> 135:176b8275d35d 96
<> 135:176b8275d35d 97 /** \brief Get APSR Register
<> 135:176b8275d35d 98
<> 135:176b8275d35d 99 This function returns the content of the APSR Register.
<> 135:176b8275d35d 100
<> 135:176b8275d35d 101 \return APSR Register value
<> 135:176b8275d35d 102 */
<> 135:176b8275d35d 103 __STATIC_INLINE uint32_t __get_APSR(void)
<> 135:176b8275d35d 104 {
<> 135:176b8275d35d 105 register uint32_t __regAPSR __ASM("apsr");
<> 135:176b8275d35d 106 return(__regAPSR);
<> 135:176b8275d35d 107 }
<> 135:176b8275d35d 108
<> 135:176b8275d35d 109
<> 135:176b8275d35d 110 /** \brief Get xPSR Register
<> 135:176b8275d35d 111
<> 135:176b8275d35d 112 This function returns the content of the xPSR Register.
<> 135:176b8275d35d 113
<> 135:176b8275d35d 114 \return xPSR Register value
<> 135:176b8275d35d 115 */
<> 135:176b8275d35d 116 __STATIC_INLINE uint32_t __get_xPSR(void)
<> 135:176b8275d35d 117 {
<> 135:176b8275d35d 118 register uint32_t __regXPSR __ASM("xpsr");
<> 135:176b8275d35d 119 return(__regXPSR);
<> 135:176b8275d35d 120 }
<> 135:176b8275d35d 121
<> 135:176b8275d35d 122
<> 135:176b8275d35d 123 /** \brief Get Process Stack Pointer
<> 135:176b8275d35d 124
<> 135:176b8275d35d 125 This function returns the current value of the Process Stack Pointer (PSP).
<> 135:176b8275d35d 126
<> 135:176b8275d35d 127 \return PSP Register value
<> 135:176b8275d35d 128 */
<> 135:176b8275d35d 129 __STATIC_INLINE uint32_t __get_PSP(void)
<> 135:176b8275d35d 130 {
<> 135:176b8275d35d 131 register uint32_t __regProcessStackPointer __ASM("psp");
<> 135:176b8275d35d 132 return(__regProcessStackPointer);
<> 135:176b8275d35d 133 }
<> 135:176b8275d35d 134
<> 135:176b8275d35d 135
<> 135:176b8275d35d 136 /** \brief Set Process Stack Pointer
<> 135:176b8275d35d 137
<> 135:176b8275d35d 138 This function assigns the given value to the Process Stack Pointer (PSP).
<> 135:176b8275d35d 139
<> 135:176b8275d35d 140 \param [in] topOfProcStack Process Stack Pointer value to set
<> 135:176b8275d35d 141 */
<> 135:176b8275d35d 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 135:176b8275d35d 143 {
<> 135:176b8275d35d 144 register uint32_t __regProcessStackPointer __ASM("psp");
<> 135:176b8275d35d 145 __regProcessStackPointer = topOfProcStack;
<> 135:176b8275d35d 146 }
<> 135:176b8275d35d 147
<> 135:176b8275d35d 148
<> 135:176b8275d35d 149 /** \brief Get Main Stack Pointer
<> 135:176b8275d35d 150
<> 135:176b8275d35d 151 This function returns the current value of the Main Stack Pointer (MSP).
<> 135:176b8275d35d 152
<> 135:176b8275d35d 153 \return MSP Register value
<> 135:176b8275d35d 154 */
<> 135:176b8275d35d 155 __STATIC_INLINE uint32_t __get_MSP(void)
<> 135:176b8275d35d 156 {
<> 135:176b8275d35d 157 register uint32_t __regMainStackPointer __ASM("msp");
<> 135:176b8275d35d 158 return(__regMainStackPointer);
<> 135:176b8275d35d 159 }
<> 135:176b8275d35d 160
<> 135:176b8275d35d 161
<> 135:176b8275d35d 162 /** \brief Set Main Stack Pointer
<> 135:176b8275d35d 163
<> 135:176b8275d35d 164 This function assigns the given value to the Main Stack Pointer (MSP).
<> 135:176b8275d35d 165
<> 135:176b8275d35d 166 \param [in] topOfMainStack Main Stack Pointer value to set
<> 135:176b8275d35d 167 */
<> 135:176b8275d35d 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 135:176b8275d35d 169 {
<> 135:176b8275d35d 170 register uint32_t __regMainStackPointer __ASM("msp");
<> 135:176b8275d35d 171 __regMainStackPointer = topOfMainStack;
<> 135:176b8275d35d 172 }
<> 135:176b8275d35d 173
<> 135:176b8275d35d 174
<> 135:176b8275d35d 175 /** \brief Get Priority Mask
<> 135:176b8275d35d 176
<> 135:176b8275d35d 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 135:176b8275d35d 178
<> 135:176b8275d35d 179 \return Priority Mask value
<> 135:176b8275d35d 180 */
<> 135:176b8275d35d 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 135:176b8275d35d 182 {
<> 135:176b8275d35d 183 register uint32_t __regPriMask __ASM("primask");
<> 135:176b8275d35d 184 return(__regPriMask);
<> 135:176b8275d35d 185 }
<> 135:176b8275d35d 186
<> 135:176b8275d35d 187
<> 135:176b8275d35d 188 /** \brief Set Priority Mask
<> 135:176b8275d35d 189
<> 135:176b8275d35d 190 This function assigns the given value to the Priority Mask Register.
<> 135:176b8275d35d 191
<> 135:176b8275d35d 192 \param [in] priMask Priority Mask
<> 135:176b8275d35d 193 */
<> 135:176b8275d35d 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 135:176b8275d35d 195 {
<> 135:176b8275d35d 196 register uint32_t __regPriMask __ASM("primask");
<> 135:176b8275d35d 197 __regPriMask = (priMask);
<> 135:176b8275d35d 198 }
<> 135:176b8275d35d 199
<> 135:176b8275d35d 200
<> 135:176b8275d35d 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
<> 135:176b8275d35d 202
<> 135:176b8275d35d 203 /** \brief Enable FIQ
<> 135:176b8275d35d 204
<> 135:176b8275d35d 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 135:176b8275d35d 206 Can only be executed in Privileged modes.
<> 135:176b8275d35d 207 */
<> 135:176b8275d35d 208 #define __enable_fault_irq __enable_fiq
<> 135:176b8275d35d 209
<> 135:176b8275d35d 210
<> 135:176b8275d35d 211 /** \brief Disable FIQ
<> 135:176b8275d35d 212
<> 135:176b8275d35d 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 135:176b8275d35d 214 Can only be executed in Privileged modes.
<> 135:176b8275d35d 215 */
<> 135:176b8275d35d 216 #define __disable_fault_irq __disable_fiq
<> 135:176b8275d35d 217
<> 135:176b8275d35d 218
<> 135:176b8275d35d 219 /** \brief Get Base Priority
<> 135:176b8275d35d 220
<> 135:176b8275d35d 221 This function returns the current value of the Base Priority register.
<> 135:176b8275d35d 222
<> 135:176b8275d35d 223 \return Base Priority register value
<> 135:176b8275d35d 224 */
<> 135:176b8275d35d 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 135:176b8275d35d 226 {
<> 135:176b8275d35d 227 register uint32_t __regBasePri __ASM("basepri");
<> 135:176b8275d35d 228 return(__regBasePri);
<> 135:176b8275d35d 229 }
<> 135:176b8275d35d 230
<> 135:176b8275d35d 231
<> 135:176b8275d35d 232 /** \brief Set Base Priority
<> 135:176b8275d35d 233
<> 135:176b8275d35d 234 This function assigns the given value to the Base Priority register.
<> 135:176b8275d35d 235
<> 135:176b8275d35d 236 \param [in] basePri Base Priority value to set
<> 135:176b8275d35d 237 */
<> 135:176b8275d35d 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
<> 135:176b8275d35d 239 {
<> 135:176b8275d35d 240 register uint32_t __regBasePri __ASM("basepri");
<> 135:176b8275d35d 241 __regBasePri = (basePri & 0xff);
<> 135:176b8275d35d 242 }
<> 135:176b8275d35d 243
<> 135:176b8275d35d 244
<> 135:176b8275d35d 245 /** \brief Set Base Priority with condition
<> 135:176b8275d35d 246
<> 135:176b8275d35d 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 135:176b8275d35d 248 or the new value increases the BASEPRI priority level.
<> 135:176b8275d35d 249
<> 135:176b8275d35d 250 \param [in] basePri Base Priority value to set
<> 135:176b8275d35d 251 */
<> 135:176b8275d35d 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
<> 135:176b8275d35d 253 {
<> 135:176b8275d35d 254 register uint32_t __regBasePriMax __ASM("basepri_max");
<> 135:176b8275d35d 255 __regBasePriMax = (basePri & 0xff);
<> 135:176b8275d35d 256 }
<> 135:176b8275d35d 257
<> 135:176b8275d35d 258
<> 135:176b8275d35d 259 /** \brief Get Fault Mask
<> 135:176b8275d35d 260
<> 135:176b8275d35d 261 This function returns the current value of the Fault Mask register.
<> 135:176b8275d35d 262
<> 135:176b8275d35d 263 \return Fault Mask register value
<> 135:176b8275d35d 264 */
<> 135:176b8275d35d 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 135:176b8275d35d 266 {
<> 135:176b8275d35d 267 register uint32_t __regFaultMask __ASM("faultmask");
<> 135:176b8275d35d 268 return(__regFaultMask);
<> 135:176b8275d35d 269 }
<> 135:176b8275d35d 270
<> 135:176b8275d35d 271
<> 135:176b8275d35d 272 /** \brief Set Fault Mask
<> 135:176b8275d35d 273
<> 135:176b8275d35d 274 This function assigns the given value to the Fault Mask register.
<> 135:176b8275d35d 275
<> 135:176b8275d35d 276 \param [in] faultMask Fault Mask value to set
<> 135:176b8275d35d 277 */
<> 135:176b8275d35d 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 135:176b8275d35d 279 {
<> 135:176b8275d35d 280 register uint32_t __regFaultMask __ASM("faultmask");
<> 135:176b8275d35d 281 __regFaultMask = (faultMask & (uint32_t)1);
<> 135:176b8275d35d 282 }
<> 135:176b8275d35d 283
<> 135:176b8275d35d 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
<> 135:176b8275d35d 285
<> 135:176b8275d35d 286
<> 135:176b8275d35d 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 135:176b8275d35d 288
<> 135:176b8275d35d 289 /** \brief Get FPSCR
<> 135:176b8275d35d 290
<> 135:176b8275d35d 291 This function returns the current value of the Floating Point Status/Control register.
<> 135:176b8275d35d 292
<> 135:176b8275d35d 293 \return Floating Point Status/Control register value
<> 135:176b8275d35d 294 */
<> 135:176b8275d35d 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 135:176b8275d35d 296 {
<> 135:176b8275d35d 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 135:176b8275d35d 298 register uint32_t __regfpscr __ASM("fpscr");
<> 135:176b8275d35d 299 return(__regfpscr);
<> 135:176b8275d35d 300 #else
<> 135:176b8275d35d 301 return(0);
<> 135:176b8275d35d 302 #endif
<> 135:176b8275d35d 303 }
<> 135:176b8275d35d 304
<> 135:176b8275d35d 305
<> 135:176b8275d35d 306 /** \brief Set FPSCR
<> 135:176b8275d35d 307
<> 135:176b8275d35d 308 This function assigns the given value to the Floating Point Status/Control register.
<> 135:176b8275d35d 309
<> 135:176b8275d35d 310 \param [in] fpscr Floating Point Status/Control value to set
<> 135:176b8275d35d 311 */
<> 135:176b8275d35d 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 135:176b8275d35d 313 {
<> 135:176b8275d35d 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 135:176b8275d35d 315 register uint32_t __regfpscr __ASM("fpscr");
<> 135:176b8275d35d 316 __regfpscr = (fpscr);
<> 135:176b8275d35d 317 #endif
<> 135:176b8275d35d 318 }
<> 135:176b8275d35d 319
<> 135:176b8275d35d 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 135:176b8275d35d 321
<> 135:176b8275d35d 322
<> 135:176b8275d35d 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 135:176b8275d35d 324 /* GNU gcc specific functions */
<> 135:176b8275d35d 325
<> 135:176b8275d35d 326 /** \brief Enable IRQ Interrupts
<> 135:176b8275d35d 327
<> 135:176b8275d35d 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
<> 135:176b8275d35d 329 Can only be executed in Privileged modes.
<> 135:176b8275d35d 330 */
<> 135:176b8275d35d 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
<> 135:176b8275d35d 332 {
<> 135:176b8275d35d 333 __ASM volatile ("cpsie i" : : : "memory");
<> 135:176b8275d35d 334 }
<> 135:176b8275d35d 335
<> 135:176b8275d35d 336
<> 135:176b8275d35d 337 /** \brief Disable IRQ Interrupts
<> 135:176b8275d35d 338
<> 135:176b8275d35d 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
<> 135:176b8275d35d 340 Can only be executed in Privileged modes.
<> 135:176b8275d35d 341 */
<> 135:176b8275d35d 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
<> 135:176b8275d35d 343 {
<> 135:176b8275d35d 344 __ASM volatile ("cpsid i" : : : "memory");
<> 135:176b8275d35d 345 }
<> 135:176b8275d35d 346
<> 135:176b8275d35d 347
<> 135:176b8275d35d 348 /** \brief Get Control Register
<> 135:176b8275d35d 349
<> 135:176b8275d35d 350 This function returns the content of the Control Register.
<> 135:176b8275d35d 351
<> 135:176b8275d35d 352 \return Control Register value
<> 135:176b8275d35d 353 */
<> 135:176b8275d35d 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
<> 135:176b8275d35d 355 {
<> 135:176b8275d35d 356 uint32_t result;
<> 135:176b8275d35d 357
<> 135:176b8275d35d 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
<> 135:176b8275d35d 359 return(result);
<> 135:176b8275d35d 360 }
<> 135:176b8275d35d 361
<> 135:176b8275d35d 362
<> 135:176b8275d35d 363 /** \brief Set Control Register
<> 135:176b8275d35d 364
<> 135:176b8275d35d 365 This function writes the given value to the Control Register.
<> 135:176b8275d35d 366
<> 135:176b8275d35d 367 \param [in] control Control Register value to set
<> 135:176b8275d35d 368 */
<> 135:176b8275d35d 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
<> 135:176b8275d35d 370 {
<> 135:176b8275d35d 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
<> 135:176b8275d35d 372 }
<> 135:176b8275d35d 373
<> 135:176b8275d35d 374
<> 135:176b8275d35d 375 /** \brief Get IPSR Register
<> 135:176b8275d35d 376
<> 135:176b8275d35d 377 This function returns the content of the IPSR Register.
<> 135:176b8275d35d 378
<> 135:176b8275d35d 379 \return IPSR Register value
<> 135:176b8275d35d 380 */
<> 135:176b8275d35d 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
<> 135:176b8275d35d 382 {
<> 135:176b8275d35d 383 uint32_t result;
<> 135:176b8275d35d 384
<> 135:176b8275d35d 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
<> 135:176b8275d35d 386 return(result);
<> 135:176b8275d35d 387 }
<> 135:176b8275d35d 388
<> 135:176b8275d35d 389
<> 135:176b8275d35d 390 /** \brief Get APSR Register
<> 135:176b8275d35d 391
<> 135:176b8275d35d 392 This function returns the content of the APSR Register.
<> 135:176b8275d35d 393
<> 135:176b8275d35d 394 \return APSR Register value
<> 135:176b8275d35d 395 */
<> 135:176b8275d35d 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
<> 135:176b8275d35d 397 {
<> 135:176b8275d35d 398 uint32_t result;
<> 135:176b8275d35d 399
<> 135:176b8275d35d 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
<> 135:176b8275d35d 401 return(result);
<> 135:176b8275d35d 402 }
<> 135:176b8275d35d 403
<> 135:176b8275d35d 404
<> 135:176b8275d35d 405 /** \brief Get xPSR Register
<> 135:176b8275d35d 406
<> 135:176b8275d35d 407 This function returns the content of the xPSR Register.
<> 135:176b8275d35d 408
<> 135:176b8275d35d 409 \return xPSR Register value
<> 135:176b8275d35d 410 */
<> 135:176b8275d35d 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
<> 135:176b8275d35d 412 {
<> 135:176b8275d35d 413 uint32_t result;
<> 135:176b8275d35d 414
<> 135:176b8275d35d 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
<> 135:176b8275d35d 416 return(result);
<> 135:176b8275d35d 417 }
<> 135:176b8275d35d 418
<> 135:176b8275d35d 419
<> 135:176b8275d35d 420 /** \brief Get Process Stack Pointer
<> 135:176b8275d35d 421
<> 135:176b8275d35d 422 This function returns the current value of the Process Stack Pointer (PSP).
<> 135:176b8275d35d 423
<> 135:176b8275d35d 424 \return PSP Register value
<> 135:176b8275d35d 425 */
<> 135:176b8275d35d 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
<> 135:176b8275d35d 427 {
<> 135:176b8275d35d 428 register uint32_t result;
<> 135:176b8275d35d 429
<> 135:176b8275d35d 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
<> 135:176b8275d35d 431 return(result);
<> 135:176b8275d35d 432 }
<> 135:176b8275d35d 433
<> 135:176b8275d35d 434
<> 135:176b8275d35d 435 /** \brief Set Process Stack Pointer
<> 135:176b8275d35d 436
<> 135:176b8275d35d 437 This function assigns the given value to the Process Stack Pointer (PSP).
<> 135:176b8275d35d 438
<> 135:176b8275d35d 439 \param [in] topOfProcStack Process Stack Pointer value to set
<> 135:176b8275d35d 440 */
<> 135:176b8275d35d 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
<> 135:176b8275d35d 442 {
<> 135:176b8275d35d 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
<> 135:176b8275d35d 444 }
<> 135:176b8275d35d 445
<> 135:176b8275d35d 446
<> 135:176b8275d35d 447 /** \brief Get Main Stack Pointer
<> 135:176b8275d35d 448
<> 135:176b8275d35d 449 This function returns the current value of the Main Stack Pointer (MSP).
<> 135:176b8275d35d 450
<> 135:176b8275d35d 451 \return MSP Register value
<> 135:176b8275d35d 452 */
<> 135:176b8275d35d 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
<> 135:176b8275d35d 454 {
<> 135:176b8275d35d 455 register uint32_t result;
<> 135:176b8275d35d 456
<> 135:176b8275d35d 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
<> 135:176b8275d35d 458 return(result);
<> 135:176b8275d35d 459 }
<> 135:176b8275d35d 460
<> 135:176b8275d35d 461
<> 135:176b8275d35d 462 /** \brief Set Main Stack Pointer
<> 135:176b8275d35d 463
<> 135:176b8275d35d 464 This function assigns the given value to the Main Stack Pointer (MSP).
<> 135:176b8275d35d 465
<> 135:176b8275d35d 466 \param [in] topOfMainStack Main Stack Pointer value to set
<> 135:176b8275d35d 467 */
<> 135:176b8275d35d 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
<> 135:176b8275d35d 469 {
<> 135:176b8275d35d 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
<> 135:176b8275d35d 471 }
<> 135:176b8275d35d 472
<> 135:176b8275d35d 473
<> 135:176b8275d35d 474 /** \brief Get Priority Mask
<> 135:176b8275d35d 475
<> 135:176b8275d35d 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
<> 135:176b8275d35d 477
<> 135:176b8275d35d 478 \return Priority Mask value
<> 135:176b8275d35d 479 */
<> 135:176b8275d35d 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
<> 135:176b8275d35d 481 {
<> 135:176b8275d35d 482 uint32_t result;
<> 135:176b8275d35d 483
<> 135:176b8275d35d 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
<> 135:176b8275d35d 485 return(result);
<> 135:176b8275d35d 486 }
<> 135:176b8275d35d 487
<> 135:176b8275d35d 488
<> 135:176b8275d35d 489 /** \brief Set Priority Mask
<> 135:176b8275d35d 490
<> 135:176b8275d35d 491 This function assigns the given value to the Priority Mask Register.
<> 135:176b8275d35d 492
<> 135:176b8275d35d 493 \param [in] priMask Priority Mask
<> 135:176b8275d35d 494 */
<> 135:176b8275d35d 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
<> 135:176b8275d35d 496 {
<> 135:176b8275d35d 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
<> 135:176b8275d35d 498 }
<> 135:176b8275d35d 499
<> 135:176b8275d35d 500
<> 135:176b8275d35d 501 #if (__CORTEX_M >= 0x03)
<> 135:176b8275d35d 502
<> 135:176b8275d35d 503 /** \brief Enable FIQ
<> 135:176b8275d35d 504
<> 135:176b8275d35d 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
<> 135:176b8275d35d 506 Can only be executed in Privileged modes.
<> 135:176b8275d35d 507 */
<> 135:176b8275d35d 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
<> 135:176b8275d35d 509 {
<> 135:176b8275d35d 510 __ASM volatile ("cpsie f" : : : "memory");
<> 135:176b8275d35d 511 }
<> 135:176b8275d35d 512
<> 135:176b8275d35d 513
<> 135:176b8275d35d 514 /** \brief Disable FIQ
<> 135:176b8275d35d 515
<> 135:176b8275d35d 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
<> 135:176b8275d35d 517 Can only be executed in Privileged modes.
<> 135:176b8275d35d 518 */
<> 135:176b8275d35d 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
<> 135:176b8275d35d 520 {
<> 135:176b8275d35d 521 __ASM volatile ("cpsid f" : : : "memory");
<> 135:176b8275d35d 522 }
<> 135:176b8275d35d 523
<> 135:176b8275d35d 524
<> 135:176b8275d35d 525 /** \brief Get Base Priority
<> 135:176b8275d35d 526
<> 135:176b8275d35d 527 This function returns the current value of the Base Priority register.
<> 135:176b8275d35d 528
<> 135:176b8275d35d 529 \return Base Priority register value
<> 135:176b8275d35d 530 */
<> 135:176b8275d35d 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
<> 135:176b8275d35d 532 {
<> 135:176b8275d35d 533 uint32_t result;
<> 135:176b8275d35d 534
<> 135:176b8275d35d 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
<> 135:176b8275d35d 536 return(result);
<> 135:176b8275d35d 537 }
<> 135:176b8275d35d 538
<> 135:176b8275d35d 539
<> 135:176b8275d35d 540 /** \brief Set Base Priority
<> 135:176b8275d35d 541
<> 135:176b8275d35d 542 This function assigns the given value to the Base Priority register.
<> 135:176b8275d35d 543
<> 135:176b8275d35d 544 \param [in] basePri Base Priority value to set
<> 135:176b8275d35d 545 */
<> 135:176b8275d35d 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
<> 135:176b8275d35d 547 {
<> 135:176b8275d35d 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
<> 135:176b8275d35d 549 }
<> 135:176b8275d35d 550
<> 135:176b8275d35d 551
<> 135:176b8275d35d 552 /** \brief Set Base Priority with condition
<> 135:176b8275d35d 553
<> 135:176b8275d35d 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
<> 135:176b8275d35d 555 or the new value increases the BASEPRI priority level.
<> 135:176b8275d35d 556
<> 135:176b8275d35d 557 \param [in] basePri Base Priority value to set
<> 135:176b8275d35d 558 */
<> 135:176b8275d35d 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
<> 135:176b8275d35d 560 {
<> 135:176b8275d35d 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
<> 135:176b8275d35d 562 }
<> 135:176b8275d35d 563
<> 135:176b8275d35d 564
<> 135:176b8275d35d 565 /** \brief Get Fault Mask
<> 135:176b8275d35d 566
<> 135:176b8275d35d 567 This function returns the current value of the Fault Mask register.
<> 135:176b8275d35d 568
<> 135:176b8275d35d 569 \return Fault Mask register value
<> 135:176b8275d35d 570 */
<> 135:176b8275d35d 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
<> 135:176b8275d35d 572 {
<> 135:176b8275d35d 573 uint32_t result;
<> 135:176b8275d35d 574
<> 135:176b8275d35d 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
<> 135:176b8275d35d 576 return(result);
<> 135:176b8275d35d 577 }
<> 135:176b8275d35d 578
<> 135:176b8275d35d 579
<> 135:176b8275d35d 580 /** \brief Set Fault Mask
<> 135:176b8275d35d 581
<> 135:176b8275d35d 582 This function assigns the given value to the Fault Mask register.
<> 135:176b8275d35d 583
<> 135:176b8275d35d 584 \param [in] faultMask Fault Mask value to set
<> 135:176b8275d35d 585 */
<> 135:176b8275d35d 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
<> 135:176b8275d35d 587 {
<> 135:176b8275d35d 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
<> 135:176b8275d35d 589 }
<> 135:176b8275d35d 590
<> 135:176b8275d35d 591 #endif /* (__CORTEX_M >= 0x03) */
<> 135:176b8275d35d 592
<> 135:176b8275d35d 593
<> 135:176b8275d35d 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
<> 135:176b8275d35d 595
<> 135:176b8275d35d 596 /** \brief Get FPSCR
<> 135:176b8275d35d 597
<> 135:176b8275d35d 598 This function returns the current value of the Floating Point Status/Control register.
<> 135:176b8275d35d 599
<> 135:176b8275d35d 600 \return Floating Point Status/Control register value
<> 135:176b8275d35d 601 */
<> 135:176b8275d35d 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
<> 135:176b8275d35d 603 {
<> 135:176b8275d35d 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 135:176b8275d35d 605 uint32_t result;
<> 135:176b8275d35d 606
<> 135:176b8275d35d 607 /* Empty asm statement works as a scheduling barrier */
<> 135:176b8275d35d 608 __ASM volatile ("");
<> 135:176b8275d35d 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
<> 135:176b8275d35d 610 __ASM volatile ("");
<> 135:176b8275d35d 611 return(result);
<> 135:176b8275d35d 612 #else
<> 135:176b8275d35d 613 return(0);
<> 135:176b8275d35d 614 #endif
<> 135:176b8275d35d 615 }
<> 135:176b8275d35d 616
<> 135:176b8275d35d 617
<> 135:176b8275d35d 618 /** \brief Set FPSCR
<> 135:176b8275d35d 619
<> 135:176b8275d35d 620 This function assigns the given value to the Floating Point Status/Control register.
<> 135:176b8275d35d 621
<> 135:176b8275d35d 622 \param [in] fpscr Floating Point Status/Control value to set
<> 135:176b8275d35d 623 */
<> 135:176b8275d35d 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
<> 135:176b8275d35d 625 {
<> 135:176b8275d35d 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 135:176b8275d35d 627 /* Empty asm statement works as a scheduling barrier */
<> 135:176b8275d35d 628 __ASM volatile ("");
<> 135:176b8275d35d 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
<> 135:176b8275d35d 630 __ASM volatile ("");
<> 135:176b8275d35d 631 #endif
<> 135:176b8275d35d 632 }
<> 135:176b8275d35d 633
<> 135:176b8275d35d 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
<> 135:176b8275d35d 635
<> 135:176b8275d35d 636
<> 135:176b8275d35d 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 135:176b8275d35d 638 /* IAR iccarm specific functions */
<> 135:176b8275d35d 639 #include <cmsis_iar.h>
<> 135:176b8275d35d 640
<> 135:176b8275d35d 641
<> 135:176b8275d35d 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 135:176b8275d35d 643 /* TI CCS specific functions */
<> 135:176b8275d35d 644 #include <cmsis_ccs.h>
<> 135:176b8275d35d 645
<> 135:176b8275d35d 646
<> 135:176b8275d35d 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 135:176b8275d35d 648 /* TASKING carm specific functions */
<> 135:176b8275d35d 649 /*
<> 135:176b8275d35d 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
<> 135:176b8275d35d 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
<> 135:176b8275d35d 652 * Including the CMSIS ones.
<> 135:176b8275d35d 653 */
<> 135:176b8275d35d 654
<> 135:176b8275d35d 655
<> 135:176b8275d35d 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 135:176b8275d35d 657 /* Cosmic specific functions */
<> 135:176b8275d35d 658 #include <cmsis_csm.h>
<> 135:176b8275d35d 659
<> 135:176b8275d35d 660 #endif
<> 135:176b8275d35d 661
<> 135:176b8275d35d 662 /*@} end of CMSIS_Core_RegAccFunctions */
<> 135:176b8275d35d 663
<> 135:176b8275d35d 664 #endif /* __CORE_CMFUNC_H */