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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/core_ca9.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
135:176b8275d35d 
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 135:176b8275d35d 1 /**************************************************************************//**
<> 135:176b8275d35d 2 * @file core_ca9.h
<> 135:176b8275d35d 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
<> 135:176b8275d35d 4 * @version
<> 135:176b8275d35d 5 * @date 25 March 2013
<> 135:176b8275d35d 6 *
<> 135:176b8275d35d 7 * @note
<> 135:176b8275d35d 8 *
<> 135:176b8275d35d 9 ******************************************************************************/
<> 135:176b8275d35d 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
<> 135:176b8275d35d 11
<> 135:176b8275d35d 12 All rights reserved.
<> 135:176b8275d35d 13 Redistribution and use in source and binary forms, with or without
<> 135:176b8275d35d 14 modification, are permitted provided that the following conditions are met:
<> 135:176b8275d35d 15 - Redistributions of source code must retain the above copyright
<> 135:176b8275d35d 16 notice, this list of conditions and the following disclaimer.
<> 135:176b8275d35d 17 - Redistributions in binary form must reproduce the above copyright
<> 135:176b8275d35d 18 notice, this list of conditions and the following disclaimer in the
<> 135:176b8275d35d 19 documentation and/or other materials provided with the distribution.
<> 135:176b8275d35d 20 - Neither the name of ARM nor the names of its contributors may be used
<> 135:176b8275d35d 21 to endorse or promote products derived from this software without
<> 135:176b8275d35d 22 specific prior written permission.
<> 135:176b8275d35d 23 *
<> 135:176b8275d35d 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 135:176b8275d35d 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 135:176b8275d35d 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 135:176b8275d35d 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 135:176b8275d35d 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 135:176b8275d35d 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 135:176b8275d35d 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 135:176b8275d35d 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 135:176b8275d35d 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 135:176b8275d35d 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 135:176b8275d35d 34 POSSIBILITY OF SUCH DAMAGE.
<> 135:176b8275d35d 35 ---------------------------------------------------------------------------*/
<> 135:176b8275d35d 36
<> 135:176b8275d35d 37
<> 135:176b8275d35d 38 #if defined ( __ICCARM__ )
<> 135:176b8275d35d 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 135:176b8275d35d 40 #endif
<> 135:176b8275d35d 41
<> 135:176b8275d35d 42 #ifdef __cplusplus
<> 135:176b8275d35d 43 extern "C" {
<> 135:176b8275d35d 44 #endif
<> 135:176b8275d35d 45
<> 135:176b8275d35d 46 #ifndef __CORE_CA9_H_GENERIC
<> 135:176b8275d35d 47 #define __CORE_CA9_H_GENERIC
<> 135:176b8275d35d 48
<> 135:176b8275d35d 49
<> 135:176b8275d35d 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 135:176b8275d35d 51 CMSIS violates the following MISRA-C:2004 rules:
<> 135:176b8275d35d 52
<> 135:176b8275d35d 53 \li Required Rule 8.5, object/function definition in header file.<br>
<> 135:176b8275d35d 54 Function definitions in header files are used to allow 'inlining'.
<> 135:176b8275d35d 55
<> 135:176b8275d35d 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 135:176b8275d35d 57 Unions are used for effective representation of core registers.
<> 135:176b8275d35d 58
<> 135:176b8275d35d 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 135:176b8275d35d 60 Function-like macros are used to allow more efficient code.
<> 135:176b8275d35d 61 */
<> 135:176b8275d35d 62
<> 135:176b8275d35d 63
<> 135:176b8275d35d 64 /*******************************************************************************
<> 135:176b8275d35d 65 * CMSIS definitions
<> 135:176b8275d35d 66 ******************************************************************************/
<> 135:176b8275d35d 67 /** \ingroup Cortex_A9
<> 135:176b8275d35d 68 @{
<> 135:176b8275d35d 69 */
<> 135:176b8275d35d 70
<> 135:176b8275d35d 71 /* CMSIS CA9 definitions */
<> 135:176b8275d35d 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
<> 135:176b8275d35d 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
<> 135:176b8275d35d 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
<> 135:176b8275d35d 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 135:176b8275d35d 76
<> 135:176b8275d35d 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
<> 135:176b8275d35d 78
<> 135:176b8275d35d 79
<> 135:176b8275d35d 80 #if defined ( __CC_ARM )
<> 135:176b8275d35d 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 135:176b8275d35d 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 135:176b8275d35d 83 #define __STATIC_INLINE static __inline
<> 135:176b8275d35d 84 #define __STATIC_ASM static __asm
<> 135:176b8275d35d 85
<> 135:176b8275d35d 86 #elif defined ( __ICCARM__ )
<> 135:176b8275d35d 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 135:176b8275d35d 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 135:176b8275d35d 89 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 90 #define __STATIC_ASM static __asm
<> 135:176b8275d35d 91
<> 135:176b8275d35d 92 #include <stdint.h>
<> 135:176b8275d35d 93 inline uint32_t __get_PSR(void) {
<> 135:176b8275d35d 94 __ASM("mrs r0, cpsr");
<> 135:176b8275d35d 95 }
<> 135:176b8275d35d 96
<> 135:176b8275d35d 97 #elif defined ( __TMS470__ )
<> 135:176b8275d35d 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 135:176b8275d35d 99 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 100 #define __STATIC_ASM static __asm
<> 135:176b8275d35d 101
<> 135:176b8275d35d 102 #elif defined ( __GNUC__ )
<> 135:176b8275d35d 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 135:176b8275d35d 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 135:176b8275d35d 105 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 106 #define __STATIC_ASM static __asm
<> 135:176b8275d35d 107
<> 135:176b8275d35d 108 #elif defined ( __TASKING__ )
<> 135:176b8275d35d 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 135:176b8275d35d 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 135:176b8275d35d 111 #define __STATIC_INLINE static inline
<> 135:176b8275d35d 112 #define __STATIC_ASM static __asm
<> 135:176b8275d35d 113
<> 135:176b8275d35d 114 #endif
<> 135:176b8275d35d 115
<> 135:176b8275d35d 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<> 135:176b8275d35d 117 */
<> 135:176b8275d35d 118 #if defined ( __CC_ARM )
<> 135:176b8275d35d 119 #if defined __TARGET_FPU_VFP
<> 135:176b8275d35d 120 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 121 #define __FPU_USED 1
<> 135:176b8275d35d 122 #else
<> 135:176b8275d35d 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 124 #define __FPU_USED 0
<> 135:176b8275d35d 125 #endif
<> 135:176b8275d35d 126 #else
<> 135:176b8275d35d 127 #define __FPU_USED 0
<> 135:176b8275d35d 128 #endif
<> 135:176b8275d35d 129
<> 135:176b8275d35d 130 #elif defined ( __ICCARM__ )
<> 135:176b8275d35d 131 #if defined __ARMVFP__
<> 135:176b8275d35d 132 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 133 #define __FPU_USED 1
<> 135:176b8275d35d 134 #else
<> 135:176b8275d35d 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 136 #define __FPU_USED 0
<> 135:176b8275d35d 137 #endif
<> 135:176b8275d35d 138 #else
<> 135:176b8275d35d 139 #define __FPU_USED 0
<> 135:176b8275d35d 140 #endif
<> 135:176b8275d35d 141
<> 135:176b8275d35d 142 #elif defined ( __TMS470__ )
<> 135:176b8275d35d 143 #if defined __TI_VFP_SUPPORT__
<> 135:176b8275d35d 144 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 145 #define __FPU_USED 1
<> 135:176b8275d35d 146 #else
<> 135:176b8275d35d 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 148 #define __FPU_USED 0
<> 135:176b8275d35d 149 #endif
<> 135:176b8275d35d 150 #else
<> 135:176b8275d35d 151 #define __FPU_USED 0
<> 135:176b8275d35d 152 #endif
<> 135:176b8275d35d 153
<> 135:176b8275d35d 154 #elif defined ( __GNUC__ )
<> 135:176b8275d35d 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 135:176b8275d35d 156 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 157 #define __FPU_USED 1
<> 135:176b8275d35d 158 #else
<> 135:176b8275d35d 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 160 #define __FPU_USED 0
<> 135:176b8275d35d 161 #endif
<> 135:176b8275d35d 162 #else
<> 135:176b8275d35d 163 #define __FPU_USED 0
<> 135:176b8275d35d 164 #endif
<> 135:176b8275d35d 165
<> 135:176b8275d35d 166 #elif defined ( __TASKING__ )
<> 135:176b8275d35d 167 #if defined __FPU_VFP__
<> 135:176b8275d35d 168 #if (__FPU_PRESENT == 1)
<> 135:176b8275d35d 169 #define __FPU_USED 1
<> 135:176b8275d35d 170 #else
<> 135:176b8275d35d 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 135:176b8275d35d 172 #define __FPU_USED 0
<> 135:176b8275d35d 173 #endif
<> 135:176b8275d35d 174 #else
<> 135:176b8275d35d 175 #define __FPU_USED 0
<> 135:176b8275d35d 176 #endif
<> 135:176b8275d35d 177 #endif
<> 135:176b8275d35d 178
<> 135:176b8275d35d 179 #include <stdint.h> /*!< standard types definitions */
<> 135:176b8275d35d 180 #include "core_caInstr.h" /*!< Core Instruction Access */
<> 135:176b8275d35d 181 #include "core_caFunc.h" /*!< Core Function Access */
<> 135:176b8275d35d 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
<> 135:176b8275d35d 183
<> 135:176b8275d35d 184 #endif /* __CORE_CA9_H_GENERIC */
<> 135:176b8275d35d 185
<> 135:176b8275d35d 186 #ifndef __CMSIS_GENERIC
<> 135:176b8275d35d 187
<> 135:176b8275d35d 188 #ifndef __CORE_CA9_H_DEPENDANT
<> 135:176b8275d35d 189 #define __CORE_CA9_H_DEPENDANT
<> 135:176b8275d35d 190
<> 135:176b8275d35d 191 /* check device defines and use defaults */
<> 135:176b8275d35d 192 #if defined __CHECK_DEVICE_DEFINES
<> 135:176b8275d35d 193 #ifndef __CA9_REV
<> 135:176b8275d35d 194 #define __CA9_REV 0x0000
<> 135:176b8275d35d 195 #warning "__CA9_REV not defined in device header file; using default!"
<> 135:176b8275d35d 196 #endif
<> 135:176b8275d35d 197
<> 135:176b8275d35d 198 #ifndef __FPU_PRESENT
<> 135:176b8275d35d 199 #define __FPU_PRESENT 1
<> 135:176b8275d35d 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
<> 135:176b8275d35d 201 #endif
<> 135:176b8275d35d 202
<> 135:176b8275d35d 203 #ifndef __Vendor_SysTickConfig
<> 135:176b8275d35d 204 #define __Vendor_SysTickConfig 1
<> 135:176b8275d35d 205 #endif
<> 135:176b8275d35d 206
<> 135:176b8275d35d 207 #if __Vendor_SysTickConfig == 0
<> 135:176b8275d35d 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
<> 135:176b8275d35d 209 #endif
<> 135:176b8275d35d 210 #endif
<> 135:176b8275d35d 211
<> 135:176b8275d35d 212 /* IO definitions (access restrictions to peripheral registers) */
<> 135:176b8275d35d 213 /**
<> 135:176b8275d35d 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 135:176b8275d35d 215
<> 135:176b8275d35d 216 <strong>IO Type Qualifiers</strong> are used
<> 135:176b8275d35d 217 \li to specify the access to peripheral variables.
<> 135:176b8275d35d 218 \li for automatic generation of peripheral register debug information.
<> 135:176b8275d35d 219 */
<> 135:176b8275d35d 220 #ifdef __cplusplus
<> 135:176b8275d35d 221 #define __I volatile /*!< Defines 'read only' permissions */
<> 135:176b8275d35d 222 #else
<> 135:176b8275d35d 223 #define __I volatile const /*!< Defines 'read only' permissions */
<> 135:176b8275d35d 224 #endif
<> 135:176b8275d35d 225 #define __O volatile /*!< Defines 'write only' permissions */
<> 135:176b8275d35d 226 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 135:176b8275d35d 227
<> 135:176b8275d35d 228 /*@} end of group Cortex_A9 */
<> 135:176b8275d35d 229
<> 135:176b8275d35d 230
<> 135:176b8275d35d 231 /*******************************************************************************
<> 135:176b8275d35d 232 * Register Abstraction
<> 135:176b8275d35d 233 ******************************************************************************/
<> 135:176b8275d35d 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 135:176b8275d35d 235 \brief Type definitions and defines for Cortex-A processor based devices.
<> 135:176b8275d35d 236 */
<> 135:176b8275d35d 237
<> 135:176b8275d35d 238 /** \ingroup CMSIS_core_register
<> 135:176b8275d35d 239 \defgroup CMSIS_CORE Status and Control Registers
<> 135:176b8275d35d 240 \brief Core Register type definitions.
<> 135:176b8275d35d 241 @{
<> 135:176b8275d35d 242 */
<> 135:176b8275d35d 243
<> 135:176b8275d35d 244 /** \brief Union type to access the Application Program Status Register (APSR).
<> 135:176b8275d35d 245 */
<> 135:176b8275d35d 246 typedef union
<> 135:176b8275d35d 247 {
<> 135:176b8275d35d 248 struct
<> 135:176b8275d35d 249 {
<> 135:176b8275d35d 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
<> 135:176b8275d35d 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
<> 135:176b8275d35d 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
<> 135:176b8275d35d 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 135:176b8275d35d 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 135:176b8275d35d 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 135:176b8275d35d 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 135:176b8275d35d 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 135:176b8275d35d 258 } b; /*!< Structure used for bit access */
<> 135:176b8275d35d 259 uint32_t w; /*!< Type used for word access */
<> 135:176b8275d35d 260 } APSR_Type;
<> 135:176b8275d35d 261
<> 135:176b8275d35d 262
<> 135:176b8275d35d 263 /*@} end of group CMSIS_CORE */
<> 135:176b8275d35d 264
<> 135:176b8275d35d 265 /*@} end of CMSIS_Core_FPUFunctions */
<> 135:176b8275d35d 266
<> 135:176b8275d35d 267
<> 135:176b8275d35d 268 #endif /* __CORE_CA9_H_GENERIC */
<> 135:176b8275d35d 269
<> 135:176b8275d35d 270 #endif /* __CMSIS_GENERIC */
<> 135:176b8275d35d 271
<> 135:176b8275d35d 272 #ifdef __cplusplus
<> 135:176b8275d35d 273 }
<> 135:176b8275d35d 274
<> 135:176b8275d35d 275
<> 135:176b8275d35d 276 #endif