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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_HRM1017/core_cm0.h@136:ef9c61f8c49f, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 11:24:20 2017 +0000
Revision:
136:ef9c61f8c49f
Parent:
131:faff56e089b2
Child:
145:64910690c574
Release 136 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3432: Target STM USBHOST support https://github.com/ARMmbed/mbed-os/pull/3432

3181: NUCLEO_F207ZG extending PeripheralPins.c: all available alternate functions can be used now https://github.com/ARMmbed/mbed-os/pull/3181

3626: NUCLEO_F412ZG : Add USB Device +Host https://github.com/ARMmbed/mbed-os/pull/3626

3628: Fix warnings https://github.com/ARMmbed/mbed-os/pull/3628

3629: STM32: L0 LL layer https://github.com/ARMmbed/mbed-os/pull/3629

3632: IDE Export support for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3632

3642: Missing IRQ pin fix for platform VK_RZ_A1H https://github.com/ARMmbed/mbed-os/pull/3642

3664: Fix ncs36510 sleep definitions https://github.com/ARMmbed/mbed-os/pull/3664

3655: [STM32F4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3655

3657: [STM32L4] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3657

3658: [STM32F3] Modify folder structure https://github.com/ARMmbed/mbed-os/pull/3658

3685: STM32: I2C: reset state machine https://github.com/ARMmbed/mbed-os/pull/3685

3692: uVisor: Standardize available legacy heap and stack https://github.com/ARMmbed/mbed-os/pull/3692

3621: Fix for #2884, LPC824: export to LPCXpresso, target running with wron https://github.com/ARMmbed/mbed-os/pull/3621

3649: [STM32F7] Modify folder structure  https://github.com/ARMmbed/mbed-os/pull/3649

3695: Enforce device_name is valid in targets.json https://github.com/ARMmbed/mbed-os/pull/3695

3723: NCS36510: spi_format function bug fix https://github.com/ARMmbed/mbed-os/pull/3723

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 87:6213f644d804 1 /**************************************************************************//**
bogdanm 87:6213f644d804 2 * @file core_cm0.h
bogdanm 87:6213f644d804 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 87:6213f644d804 6 *
bogdanm 87:6213f644d804 7 * @note
bogdanm 87:6213f644d804 8 *
bogdanm 87:6213f644d804 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 87:6213f644d804 11
bogdanm 87:6213f644d804 12 All rights reserved.
bogdanm 87:6213f644d804 13 Redistribution and use in source and binary forms, with or without
bogdanm 87:6213f644d804 14 modification, are permitted provided that the following conditions are met:
bogdanm 87:6213f644d804 15 - Redistributions of source code must retain the above copyright
bogdanm 87:6213f644d804 16 notice, this list of conditions and the following disclaimer.
bogdanm 87:6213f644d804 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 87:6213f644d804 18 notice, this list of conditions and the following disclaimer in the
bogdanm 87:6213f644d804 19 documentation and/or other materials provided with the distribution.
bogdanm 87:6213f644d804 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 87:6213f644d804 21 to endorse or promote products derived from this software without
bogdanm 87:6213f644d804 22 specific prior written permission.
bogdanm 87:6213f644d804 23 *
bogdanm 87:6213f644d804 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 87:6213f644d804 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 87:6213f644d804 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 87:6213f644d804 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 87:6213f644d804 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 87:6213f644d804 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 87:6213f644d804 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 87:6213f644d804 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 87:6213f644d804 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 87:6213f644d804 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 87:6213f644d804 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 87:6213f644d804 35 ---------------------------------------------------------------------------*/
bogdanm 87:6213f644d804 36
bogdanm 87:6213f644d804 37
bogdanm 87:6213f644d804 38 #if defined ( __ICCARM__ )
bogdanm 87:6213f644d804 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 87:6213f644d804 40 #endif
bogdanm 87:6213f644d804 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 87:6213f644d804 45 #ifdef __cplusplus
bogdanm 87:6213f644d804 46 extern "C" {
bogdanm 87:6213f644d804 47 #endif
bogdanm 87:6213f644d804 48
bogdanm 87:6213f644d804 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 87:6213f644d804 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 87:6213f644d804 51
bogdanm 87:6213f644d804 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 87:6213f644d804 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 87:6213f644d804 54
bogdanm 87:6213f644d804 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 87:6213f644d804 56 Unions are used for effective representation of core registers.
bogdanm 87:6213f644d804 57
bogdanm 87:6213f644d804 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 87:6213f644d804 59 Function-like macros are used to allow more efficient code.
bogdanm 87:6213f644d804 60 */
bogdanm 87:6213f644d804 61
bogdanm 87:6213f644d804 62
bogdanm 87:6213f644d804 63 /*******************************************************************************
bogdanm 87:6213f644d804 64 * CMSIS definitions
bogdanm 87:6213f644d804 65 ******************************************************************************/
bogdanm 87:6213f644d804 66 /** \ingroup Cortex_M0
bogdanm 87:6213f644d804 67 @{
bogdanm 87:6213f644d804 68 */
bogdanm 87:6213f644d804 69
bogdanm 87:6213f644d804 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 87:6213f644d804 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
bogdanm 87:6213f644d804 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 87:6213f644d804 75
bogdanm 87:6213f644d804 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 87:6213f644d804 77
bogdanm 87:6213f644d804 78
bogdanm 87:6213f644d804 79 #if defined ( __CC_ARM )
bogdanm 87:6213f644d804 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 87:6213f644d804 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 87:6213f644d804 82 #define __STATIC_INLINE static __inline
bogdanm 87:6213f644d804 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 87:6213f644d804 89 #elif defined ( __ICCARM__ )
bogdanm 87:6213f644d804 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 87:6213f644d804 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 87:6213f644d804 92 #define __STATIC_INLINE static inline
bogdanm 87:6213f644d804 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 87:6213f644d804 96 #define __STATIC_INLINE static inline
bogdanm 87:6213f644d804 97
bogdanm 87:6213f644d804 98 #elif defined ( __TASKING__ )
bogdanm 87:6213f644d804 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 87:6213f644d804 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 87:6213f644d804 101 #define __STATIC_INLINE static inline
bogdanm 87:6213f644d804 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 87:6213f644d804 109 #endif
bogdanm 87:6213f644d804 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 87:6213f644d804 113 */
bogdanm 87:6213f644d804 114 #define __FPU_USED 0
bogdanm 87:6213f644d804 115
bogdanm 87:6213f644d804 116 #if defined ( __CC_ARM )
bogdanm 87:6213f644d804 117 #if defined __TARGET_FPU_VFP
bogdanm 87:6213f644d804 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 87:6213f644d804 119 #endif
bogdanm 87:6213f644d804 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 87:6213f644d804 126 #elif defined ( __ICCARM__ )
bogdanm 87:6213f644d804 127 #if defined __ARMVFP__
bogdanm 87:6213f644d804 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 87:6213f644d804 129 #endif
bogdanm 87:6213f644d804 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
bogdanm 87:6213f644d804 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 87:6213f644d804 134 #endif
bogdanm 87:6213f644d804 135
bogdanm 87:6213f644d804 136 #elif defined ( __TASKING__ )
bogdanm 87:6213f644d804 137 #if defined __FPU_VFP__
bogdanm 87:6213f644d804 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 87:6213f644d804 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
bogdanm 87:6213f644d804 145 #endif
bogdanm 87:6213f644d804 146
bogdanm 87:6213f644d804 147 #include <stdint.h> /* standard types definitions */
bogdanm 87:6213f644d804 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 87:6213f644d804 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 87:6213f644d804 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 87:6213f644d804 155 #endif /* __CORE_CM0_H_GENERIC */
bogdanm 87:6213f644d804 156
bogdanm 87:6213f644d804 157 #ifndef __CMSIS_GENERIC
bogdanm 87:6213f644d804 158
bogdanm 87:6213f644d804 159 #ifndef __CORE_CM0_H_DEPENDANT
bogdanm 87:6213f644d804 160 #define __CORE_CM0_H_DEPENDANT
bogdanm 87:6213f644d804 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 87:6213f644d804 166 /* check device defines and use defaults */
bogdanm 87:6213f644d804 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 87:6213f644d804 168 #ifndef __CM0_REV
bogdanm 87:6213f644d804 169 #define __CM0_REV 0x0000
bogdanm 87:6213f644d804 170 #warning "__CM0_REV not defined in device header file; using default!"
bogdanm 87:6213f644d804 171 #endif
bogdanm 87:6213f644d804 172
bogdanm 87:6213f644d804 173 #ifndef __NVIC_PRIO_BITS
bogdanm 87:6213f644d804 174 #define __NVIC_PRIO_BITS 2
bogdanm 87:6213f644d804 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 87:6213f644d804 176 #endif
bogdanm 87:6213f644d804 177
bogdanm 87:6213f644d804 178 #ifndef __Vendor_SysTickConfig
bogdanm 87:6213f644d804 179 #define __Vendor_SysTickConfig 0
bogdanm 87:6213f644d804 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 87:6213f644d804 181 #endif
bogdanm 87:6213f644d804 182 #endif
bogdanm 87:6213f644d804 183
bogdanm 87:6213f644d804 184 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 87:6213f644d804 185 /**
bogdanm 87:6213f644d804 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 87:6213f644d804 187
bogdanm 87:6213f644d804 188 <strong>IO Type Qualifiers</strong> are used
bogdanm 87:6213f644d804 189 \li to specify the access to peripheral variables.
bogdanm 87:6213f644d804 190 \li for automatic generation of peripheral register debug information.
bogdanm 87:6213f644d804 191 */
bogdanm 87:6213f644d804 192 #ifdef __cplusplus
bogdanm 87:6213f644d804 193 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 87:6213f644d804 194 #else
bogdanm 87:6213f644d804 195 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 87:6213f644d804 196 #endif
bogdanm 87:6213f644d804 197 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 87:6213f644d804 198 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 87:6213f644d804 199
<> 128:9bcdf88f62b0 200 #ifdef __cplusplus
<> 128:9bcdf88f62b0 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 202 #else
<> 128:9bcdf88f62b0 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #endif
<> 128:9bcdf88f62b0 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 207
bogdanm 87:6213f644d804 208 /*@} end of group Cortex_M0 */
bogdanm 87:6213f644d804 209
bogdanm 87:6213f644d804 210
bogdanm 87:6213f644d804 211
bogdanm 87:6213f644d804 212 /*******************************************************************************
bogdanm 87:6213f644d804 213 * Register Abstraction
bogdanm 87:6213f644d804 214 Core Register contain:
bogdanm 87:6213f644d804 215 - Core Register
bogdanm 87:6213f644d804 216 - Core NVIC Register
bogdanm 87:6213f644d804 217 - Core SCB Register
bogdanm 87:6213f644d804 218 - Core SysTick Register
bogdanm 87:6213f644d804 219 ******************************************************************************/
bogdanm 87:6213f644d804 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 87:6213f644d804 221 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 87:6213f644d804 222 */
bogdanm 87:6213f644d804 223
bogdanm 87:6213f644d804 224 /** \ingroup CMSIS_core_register
bogdanm 87:6213f644d804 225 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 87:6213f644d804 226 \brief Core Register type definitions.
bogdanm 87:6213f644d804 227 @{
bogdanm 87:6213f644d804 228 */
bogdanm 87:6213f644d804 229
bogdanm 87:6213f644d804 230 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 87:6213f644d804 231 */
bogdanm 87:6213f644d804 232 typedef union
bogdanm 87:6213f644d804 233 {
bogdanm 87:6213f644d804 234 struct
bogdanm 87:6213f644d804 235 {
Kojto 110:165afa46840b 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 87:6213f644d804 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 87:6213f644d804 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 87:6213f644d804 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 87:6213f644d804 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 87:6213f644d804 241 } b; /*!< Structure used for bit access */
bogdanm 87:6213f644d804 242 uint32_t w; /*!< Type used for word access */
bogdanm 87:6213f644d804 243 } APSR_Type;
bogdanm 87:6213f644d804 244
Kojto 110:165afa46840b 245 /* APSR Register Definitions */
Kojto 110:165afa46840b 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 248
Kojto 110:165afa46840b 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 257
bogdanm 87:6213f644d804 258
bogdanm 87:6213f644d804 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 87:6213f644d804 260 */
bogdanm 87:6213f644d804 261 typedef union
bogdanm 87:6213f644d804 262 {
bogdanm 87:6213f644d804 263 struct
bogdanm 87:6213f644d804 264 {
bogdanm 87:6213f644d804 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 87:6213f644d804 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 87:6213f644d804 267 } b; /*!< Structure used for bit access */
bogdanm 87:6213f644d804 268 uint32_t w; /*!< Type used for word access */
bogdanm 87:6213f644d804 269 } IPSR_Type;
bogdanm 87:6213f644d804 270
Kojto 110:165afa46840b 271 /* IPSR Register Definitions */
Kojto 110:165afa46840b 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 274
bogdanm 87:6213f644d804 275
bogdanm 87:6213f644d804 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 87:6213f644d804 277 */
bogdanm 87:6213f644d804 278 typedef union
bogdanm 87:6213f644d804 279 {
bogdanm 87:6213f644d804 280 struct
bogdanm 87:6213f644d804 281 {
bogdanm 87:6213f644d804 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 87:6213f644d804 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 87:6213f644d804 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 87:6213f644d804 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 87:6213f644d804 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 87:6213f644d804 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 87:6213f644d804 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 87:6213f644d804 290 } b; /*!< Structure used for bit access */
bogdanm 87:6213f644d804 291 uint32_t w; /*!< Type used for word access */
bogdanm 87:6213f644d804 292 } xPSR_Type;
bogdanm 87:6213f644d804 293
Kojto 110:165afa46840b 294 /* xPSR Register Definitions */
Kojto 110:165afa46840b 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 297
Kojto 110:165afa46840b 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 312
bogdanm 87:6213f644d804 313
bogdanm 87:6213f644d804 314 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 87:6213f644d804 315 */
bogdanm 87:6213f644d804 316 typedef union
bogdanm 87:6213f644d804 317 {
bogdanm 87:6213f644d804 318 struct
bogdanm 87:6213f644d804 319 {
Kojto 110:165afa46840b 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
bogdanm 87:6213f644d804 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 87:6213f644d804 323 } b; /*!< Structure used for bit access */
bogdanm 87:6213f644d804 324 uint32_t w; /*!< Type used for word access */
bogdanm 87:6213f644d804 325 } CONTROL_Type;
bogdanm 87:6213f644d804 326
Kojto 110:165afa46840b 327 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 330
bogdanm 87:6213f644d804 331 /*@} end of group CMSIS_CORE */
bogdanm 87:6213f644d804 332
bogdanm 87:6213f644d804 333
bogdanm 87:6213f644d804 334 /** \ingroup CMSIS_core_register
bogdanm 87:6213f644d804 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 87:6213f644d804 336 \brief Type definitions for the NVIC Registers
bogdanm 87:6213f644d804 337 @{
bogdanm 87:6213f644d804 338 */
bogdanm 87:6213f644d804 339
bogdanm 87:6213f644d804 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 87:6213f644d804 341 */
bogdanm 87:6213f644d804 342 typedef struct
bogdanm 87:6213f644d804 343 {
bogdanm 87:6213f644d804 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 87:6213f644d804 345 uint32_t RESERVED0[31];
bogdanm 87:6213f644d804 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 87:6213f644d804 347 uint32_t RSERVED1[31];
bogdanm 87:6213f644d804 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 87:6213f644d804 349 uint32_t RESERVED2[31];
bogdanm 87:6213f644d804 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 87:6213f644d804 351 uint32_t RESERVED3[31];
bogdanm 87:6213f644d804 352 uint32_t RESERVED4[64];
bogdanm 87:6213f644d804 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 87:6213f644d804 354 } NVIC_Type;
bogdanm 87:6213f644d804 355
bogdanm 87:6213f644d804 356 /*@} end of group CMSIS_NVIC */
bogdanm 87:6213f644d804 357
bogdanm 87:6213f644d804 358
bogdanm 87:6213f644d804 359 /** \ingroup CMSIS_core_register
bogdanm 87:6213f644d804 360 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 87:6213f644d804 361 \brief Type definitions for the System Control Block Registers
bogdanm 87:6213f644d804 362 @{
bogdanm 87:6213f644d804 363 */
bogdanm 87:6213f644d804 364
bogdanm 87:6213f644d804 365 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 87:6213f644d804 366 */
bogdanm 87:6213f644d804 367 typedef struct
bogdanm 87:6213f644d804 368 {
bogdanm 87:6213f644d804 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 87:6213f644d804 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 87:6213f644d804 371 uint32_t RESERVED0;
bogdanm 87:6213f644d804 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 87:6213f644d804 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 87:6213f644d804 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 87:6213f644d804 375 uint32_t RESERVED1;
bogdanm 87:6213f644d804 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 87:6213f644d804 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 87:6213f644d804 378 } SCB_Type;
bogdanm 87:6213f644d804 379
bogdanm 87:6213f644d804 380 /* SCB CPUID Register Definitions */
bogdanm 87:6213f644d804 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 87:6213f644d804 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 87:6213f644d804 383
bogdanm 87:6213f644d804 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 87:6213f644d804 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 87:6213f644d804 386
bogdanm 87:6213f644d804 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 87:6213f644d804 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 87:6213f644d804 389
bogdanm 87:6213f644d804 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 87:6213f644d804 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 87:6213f644d804 392
bogdanm 87:6213f644d804 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 87:6213f644d804 395
bogdanm 87:6213f644d804 396 /* SCB Interrupt Control State Register Definitions */
bogdanm 87:6213f644d804 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 87:6213f644d804 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 87:6213f644d804 399
bogdanm 87:6213f644d804 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 87:6213f644d804 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 87:6213f644d804 402
bogdanm 87:6213f644d804 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 87:6213f644d804 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 87:6213f644d804 405
bogdanm 87:6213f644d804 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 87:6213f644d804 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 87:6213f644d804 408
bogdanm 87:6213f644d804 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 87:6213f644d804 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 87:6213f644d804 411
bogdanm 87:6213f644d804 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 87:6213f644d804 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 87:6213f644d804 414
bogdanm 87:6213f644d804 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 87:6213f644d804 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 87:6213f644d804 417
bogdanm 87:6213f644d804 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 87:6213f644d804 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 87:6213f644d804 420
bogdanm 87:6213f644d804 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 87:6213f644d804 423
bogdanm 87:6213f644d804 424 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 87:6213f644d804 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 87:6213f644d804 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 87:6213f644d804 427
bogdanm 87:6213f644d804 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 87:6213f644d804 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 87:6213f644d804 430
bogdanm 87:6213f644d804 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 87:6213f644d804 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 87:6213f644d804 433
bogdanm 87:6213f644d804 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 87:6213f644d804 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 87:6213f644d804 436
bogdanm 87:6213f644d804 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 87:6213f644d804 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 87:6213f644d804 439
bogdanm 87:6213f644d804 440 /* SCB System Control Register Definitions */
bogdanm 87:6213f644d804 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 87:6213f644d804 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 87:6213f644d804 443
bogdanm 87:6213f644d804 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 87:6213f644d804 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 87:6213f644d804 446
bogdanm 87:6213f644d804 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 87:6213f644d804 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 87:6213f644d804 449
bogdanm 87:6213f644d804 450 /* SCB Configuration Control Register Definitions */
bogdanm 87:6213f644d804 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 87:6213f644d804 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 87:6213f644d804 453
bogdanm 87:6213f644d804 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 87:6213f644d804 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 87:6213f644d804 456
bogdanm 87:6213f644d804 457 /* SCB System Handler Control and State Register Definitions */
bogdanm 87:6213f644d804 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 87:6213f644d804 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 87:6213f644d804 460
bogdanm 87:6213f644d804 461 /*@} end of group CMSIS_SCB */
bogdanm 87:6213f644d804 462
bogdanm 87:6213f644d804 463
bogdanm 87:6213f644d804 464 /** \ingroup CMSIS_core_register
bogdanm 87:6213f644d804 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 87:6213f644d804 466 \brief Type definitions for the System Timer Registers.
bogdanm 87:6213f644d804 467 @{
bogdanm 87:6213f644d804 468 */
bogdanm 87:6213f644d804 469
bogdanm 87:6213f644d804 470 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 87:6213f644d804 471 */
bogdanm 87:6213f644d804 472 typedef struct
bogdanm 87:6213f644d804 473 {
bogdanm 87:6213f644d804 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 87:6213f644d804 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 87:6213f644d804 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 87:6213f644d804 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 87:6213f644d804 478 } SysTick_Type;
bogdanm 87:6213f644d804 479
bogdanm 87:6213f644d804 480 /* SysTick Control / Status Register Definitions */
bogdanm 87:6213f644d804 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 87:6213f644d804 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 87:6213f644d804 483
bogdanm 87:6213f644d804 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 87:6213f644d804 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 87:6213f644d804 486
bogdanm 87:6213f644d804 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 87:6213f644d804 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 87:6213f644d804 489
bogdanm 87:6213f644d804 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 87:6213f644d804 492
bogdanm 87:6213f644d804 493 /* SysTick Reload Register Definitions */
bogdanm 87:6213f644d804 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 87:6213f644d804 496
bogdanm 87:6213f644d804 497 /* SysTick Current Register Definitions */
bogdanm 87:6213f644d804 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 87:6213f644d804 500
bogdanm 87:6213f644d804 501 /* SysTick Calibration Register Definitions */
bogdanm 87:6213f644d804 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 87:6213f644d804 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 87:6213f644d804 504
bogdanm 87:6213f644d804 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 87:6213f644d804 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 87:6213f644d804 507
bogdanm 87:6213f644d804 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 87:6213f644d804 510
bogdanm 87:6213f644d804 511 /*@} end of group CMSIS_SysTick */
bogdanm 87:6213f644d804 512
bogdanm 87:6213f644d804 513
bogdanm 87:6213f644d804 514 /** \ingroup CMSIS_core_register
bogdanm 87:6213f644d804 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 87:6213f644d804 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 87:6213f644d804 517 are only accessible over DAP and not via processor. Therefore
bogdanm 87:6213f644d804 518 they are not covered by the Cortex-M0 header file.
bogdanm 87:6213f644d804 519 @{
bogdanm 87:6213f644d804 520 */
bogdanm 87:6213f644d804 521 /*@} end of group CMSIS_CoreDebug */
bogdanm 87:6213f644d804 522
bogdanm 87:6213f644d804 523
bogdanm 87:6213f644d804 524 /** \ingroup CMSIS_core_register
bogdanm 87:6213f644d804 525 \defgroup CMSIS_core_base Core Definitions
bogdanm 87:6213f644d804 526 \brief Definitions for base addresses, unions, and structures.
bogdanm 87:6213f644d804 527 @{
bogdanm 87:6213f644d804 528 */
bogdanm 87:6213f644d804 529
bogdanm 87:6213f644d804 530 /* Memory mapping of Cortex-M0 Hardware */
bogdanm 87:6213f644d804 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 87:6213f644d804 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 87:6213f644d804 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 87:6213f644d804 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 87:6213f644d804 535
bogdanm 87:6213f644d804 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 87:6213f644d804 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 87:6213f644d804 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 87:6213f644d804 539
bogdanm 87:6213f644d804 540
bogdanm 87:6213f644d804 541 /*@} */
bogdanm 87:6213f644d804 542
bogdanm 87:6213f644d804 543
bogdanm 87:6213f644d804 544
bogdanm 87:6213f644d804 545 /*******************************************************************************
bogdanm 87:6213f644d804 546 * Hardware Abstraction Layer
bogdanm 87:6213f644d804 547 Core Function Interface contains:
bogdanm 87:6213f644d804 548 - Core NVIC Functions
bogdanm 87:6213f644d804 549 - Core SysTick Functions
bogdanm 87:6213f644d804 550 - Core Register Access Functions
bogdanm 87:6213f644d804 551 ******************************************************************************/
bogdanm 87:6213f644d804 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 87:6213f644d804 553 */
bogdanm 87:6213f644d804 554
bogdanm 87:6213f644d804 555
bogdanm 87:6213f644d804 556
bogdanm 87:6213f644d804 557 /* ########################## NVIC functions #################################### */
bogdanm 87:6213f644d804 558 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 87:6213f644d804 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 87:6213f644d804 560 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 87:6213f644d804 561 @{
bogdanm 87:6213f644d804 562 */
bogdanm 87:6213f644d804 563
bogdanm 87:6213f644d804 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 87:6213f644d804 565 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 87:6213f644d804 569
bogdanm 87:6213f644d804 570
bogdanm 87:6213f644d804 571 /** \brief Enable External Interrupt
bogdanm 87:6213f644d804 572
bogdanm 87:6213f644d804 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 87:6213f644d804 574
bogdanm 87:6213f644d804 575 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 87:6213f644d804 576 */
bogdanm 87:6213f644d804 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 87:6213f644d804 578 {
Kojto 110:165afa46840b 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 87:6213f644d804 580 }
bogdanm 87:6213f644d804 581
bogdanm 87:6213f644d804 582
bogdanm 87:6213f644d804 583 /** \brief Disable External Interrupt
bogdanm 87:6213f644d804 584
bogdanm 87:6213f644d804 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 87:6213f644d804 586
bogdanm 87:6213f644d804 587 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 87:6213f644d804 588 */
bogdanm 87:6213f644d804 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 87:6213f644d804 590 {
Kojto 110:165afa46840b 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 592 __DSB();
<> 131:faff56e089b2 593 __ISB();
bogdanm 87:6213f644d804 594 }
bogdanm 87:6213f644d804 595
bogdanm 87:6213f644d804 596
bogdanm 87:6213f644d804 597 /** \brief Get Pending Interrupt
bogdanm 87:6213f644d804 598
bogdanm 87:6213f644d804 599 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 87:6213f644d804 600 for the specified interrupt.
bogdanm 87:6213f644d804 601
bogdanm 87:6213f644d804 602 \param [in] IRQn Interrupt number.
bogdanm 87:6213f644d804 603
bogdanm 87:6213f644d804 604 \return 0 Interrupt status is not pending.
bogdanm 87:6213f644d804 605 \return 1 Interrupt status is pending.
bogdanm 87:6213f644d804 606 */
bogdanm 87:6213f644d804 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 87:6213f644d804 608 {
Kojto 110:165afa46840b 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 87:6213f644d804 610 }
bogdanm 87:6213f644d804 611
bogdanm 87:6213f644d804 612
bogdanm 87:6213f644d804 613 /** \brief Set Pending Interrupt
bogdanm 87:6213f644d804 614
bogdanm 87:6213f644d804 615 The function sets the pending bit of an external interrupt.
bogdanm 87:6213f644d804 616
bogdanm 87:6213f644d804 617 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 87:6213f644d804 618 */
bogdanm 87:6213f644d804 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 87:6213f644d804 620 {
Kojto 110:165afa46840b 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 87:6213f644d804 622 }
bogdanm 87:6213f644d804 623
bogdanm 87:6213f644d804 624
bogdanm 87:6213f644d804 625 /** \brief Clear Pending Interrupt
bogdanm 87:6213f644d804 626
bogdanm 87:6213f644d804 627 The function clears the pending bit of an external interrupt.
bogdanm 87:6213f644d804 628
bogdanm 87:6213f644d804 629 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 87:6213f644d804 630 */
bogdanm 87:6213f644d804 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 87:6213f644d804 632 {
Kojto 110:165afa46840b 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 87:6213f644d804 634 }
bogdanm 87:6213f644d804 635
bogdanm 87:6213f644d804 636
bogdanm 87:6213f644d804 637 /** \brief Set Interrupt Priority
bogdanm 87:6213f644d804 638
bogdanm 87:6213f644d804 639 The function sets the priority of an interrupt.
bogdanm 87:6213f644d804 640
bogdanm 87:6213f644d804 641 \note The priority cannot be set for every core interrupt.
bogdanm 87:6213f644d804 642
bogdanm 87:6213f644d804 643 \param [in] IRQn Interrupt number.
bogdanm 87:6213f644d804 644 \param [in] priority Priority to set.
bogdanm 87:6213f644d804 645 */
bogdanm 87:6213f644d804 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 87:6213f644d804 647 {
Kojto 110:165afa46840b 648 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 651 }
bogdanm 87:6213f644d804 652 else {
Kojto 110:165afa46840b 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 655 }
bogdanm 87:6213f644d804 656 }
bogdanm 87:6213f644d804 657
bogdanm 87:6213f644d804 658
bogdanm 87:6213f644d804 659 /** \brief Get Interrupt Priority
bogdanm 87:6213f644d804 660
bogdanm 87:6213f644d804 661 The function reads the priority of an interrupt. The interrupt
bogdanm 87:6213f644d804 662 number can be positive to specify an external (device specific)
bogdanm 87:6213f644d804 663 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 87:6213f644d804 664
bogdanm 87:6213f644d804 665
bogdanm 87:6213f644d804 666 \param [in] IRQn Interrupt number.
bogdanm 87:6213f644d804 667 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 87:6213f644d804 668 priority bits of the microcontroller.
bogdanm 87:6213f644d804 669 */
bogdanm 87:6213f644d804 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 87:6213f644d804 671 {
bogdanm 87:6213f644d804 672
Kojto 110:165afa46840b 673 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 675 }
bogdanm 87:6213f644d804 676 else {
Kojto 110:165afa46840b 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 678 }
bogdanm 87:6213f644d804 679 }
bogdanm 87:6213f644d804 680
bogdanm 87:6213f644d804 681
bogdanm 87:6213f644d804 682 /** \brief System Reset
bogdanm 87:6213f644d804 683
bogdanm 87:6213f644d804 684 The function initiates a system reset request to reset the MCU.
bogdanm 87:6213f644d804 685 */
bogdanm 87:6213f644d804 686 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 87:6213f644d804 687 {
bogdanm 87:6213f644d804 688 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 87:6213f644d804 689 buffered write are completed before reset */
Kojto 110:165afa46840b 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 87:6213f644d804 691 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 87:6213f644d804 692 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 693 while(1) { __NOP(); } /* wait until reset */
bogdanm 87:6213f644d804 694 }
bogdanm 87:6213f644d804 695
bogdanm 87:6213f644d804 696 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 87:6213f644d804 697
bogdanm 87:6213f644d804 698
bogdanm 87:6213f644d804 699
bogdanm 87:6213f644d804 700 /* ################################## SysTick function ############################################ */
bogdanm 87:6213f644d804 701 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 87:6213f644d804 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 87:6213f644d804 703 \brief Functions that configure the System.
bogdanm 87:6213f644d804 704 @{
bogdanm 87:6213f644d804 705 */
bogdanm 87:6213f644d804 706
bogdanm 87:6213f644d804 707 #if (__Vendor_SysTickConfig == 0)
bogdanm 87:6213f644d804 708
bogdanm 87:6213f644d804 709 /** \brief System Tick Configuration
bogdanm 87:6213f644d804 710
bogdanm 87:6213f644d804 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 87:6213f644d804 712 Counter is in free running mode to generate periodic interrupts.
bogdanm 87:6213f644d804 713
bogdanm 87:6213f644d804 714 \param [in] ticks Number of ticks between two interrupts.
bogdanm 87:6213f644d804 715
bogdanm 87:6213f644d804 716 \return 0 Function succeeded.
bogdanm 87:6213f644d804 717 \return 1 Function failed.
bogdanm 87:6213f644d804 718
bogdanm 87:6213f644d804 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 87:6213f644d804 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 87:6213f644d804 721 must contain a vendor-specific implementation of this function.
bogdanm 87:6213f644d804 722
bogdanm 87:6213f644d804 723 */
bogdanm 87:6213f644d804 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 87:6213f644d804 725 {
Kojto 110:165afa46840b 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
bogdanm 87:6213f644d804 727
Kojto 110:165afa46840b 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 87:6213f644d804 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 87:6213f644d804 732 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 734 return (0UL); /* Function successful */
bogdanm 87:6213f644d804 735 }
bogdanm 87:6213f644d804 736
bogdanm 87:6213f644d804 737 #endif
bogdanm 87:6213f644d804 738
bogdanm 87:6213f644d804 739 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 87:6213f644d804 740
bogdanm 87:6213f644d804 741
bogdanm 87:6213f644d804 742
bogdanm 87:6213f644d804 743
Kojto 110:165afa46840b 744 #ifdef __cplusplus
Kojto 110:165afa46840b 745 }
Kojto 110:165afa46840b 746 #endif
Kojto 110:165afa46840b 747
bogdanm 87:6213f644d804 748 #endif /* __CORE_CM0_H_DEPENDANT */
bogdanm 87:6213f644d804 749
bogdanm 87:6213f644d804 750 #endif /* __CMSIS_GENERIC */