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TARGET_DISCO_F334C8/core_cm4.h@100:cbbeb26dbd92, 2015-05-27 (annotated)

Committer:: Kojto
Date:: Wed May 27 08:07:35 2015 +0100
Revision:: 100:cbbeb26dbd92
Child:: 110:165afa46840b

Release 100 of the mbed library



Changes:

 - new  target: DISCOF334C8

 - API: Ticker/Timer bugfix with constness

 - Silabs: RTC, PWM, Serial clocks bufixes

 - Renesas: i2c bugfix

 - Maxim: 326000 - pin definitions for v2, spi freq fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	100:cbbeb26dbd92	1	/************************************************************************//
Kojto	100:cbbeb26dbd92	2	* @file core_cm4.h
Kojto	100:cbbeb26dbd92	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Kojto	100:cbbeb26dbd92	4	* @version V3.20
Kojto	100:cbbeb26dbd92	5	* @date 25. February 2013
Kojto	100:cbbeb26dbd92	6	*
Kojto	100:cbbeb26dbd92	7	* @note
Kojto	100:cbbeb26dbd92	8	*
Kojto	100:cbbeb26dbd92	9	******************************************************************************/
Kojto	100:cbbeb26dbd92	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto	100:cbbeb26dbd92	11
Kojto	100:cbbeb26dbd92	12	All rights reserved.
Kojto	100:cbbeb26dbd92	13	Redistribution and use in source and binary forms, with or without
Kojto	100:cbbeb26dbd92	14	modification, are permitted provided that the following conditions are met:
Kojto	100:cbbeb26dbd92	15	- Redistributions of source code must retain the above copyright
Kojto	100:cbbeb26dbd92	16	notice, this list of conditions and the following disclaimer.
Kojto	100:cbbeb26dbd92	17	- Redistributions in binary form must reproduce the above copyright
Kojto	100:cbbeb26dbd92	18	notice, this list of conditions and the following disclaimer in the
Kojto	100:cbbeb26dbd92	19	documentation and/or other materials provided with the distribution.
Kojto	100:cbbeb26dbd92	20	- Neither the name of ARM nor the names of its contributors may be used
Kojto	100:cbbeb26dbd92	21	to endorse or promote products derived from this software without
Kojto	100:cbbeb26dbd92	22	specific prior written permission.
Kojto	100:cbbeb26dbd92	23	*
Kojto	100:cbbeb26dbd92	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	100:cbbeb26dbd92	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	100:cbbeb26dbd92	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto	100:cbbeb26dbd92	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto	100:cbbeb26dbd92	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto	100:cbbeb26dbd92	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto	100:cbbeb26dbd92	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto	100:cbbeb26dbd92	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto	100:cbbeb26dbd92	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto	100:cbbeb26dbd92	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto	100:cbbeb26dbd92	34	POSSIBILITY OF SUCH DAMAGE.
Kojto	100:cbbeb26dbd92	35	---------------------------------------------------------------------------*/
Kojto	100:cbbeb26dbd92	36
Kojto	100:cbbeb26dbd92	37
Kojto	100:cbbeb26dbd92	38	#if defined ( __ICCARM__ )
Kojto	100:cbbeb26dbd92	39	#pragma system_include /* treat file as system include file for MISRA check */
Kojto	100:cbbeb26dbd92	40	#endif
Kojto	100:cbbeb26dbd92	41
Kojto	100:cbbeb26dbd92	42	#ifdef __cplusplus
Kojto	100:cbbeb26dbd92	43	extern "C" {
Kojto	100:cbbeb26dbd92	44	#endif
Kojto	100:cbbeb26dbd92	45
Kojto	100:cbbeb26dbd92	46	#ifndef __CORE_CM4_H_GENERIC
Kojto	100:cbbeb26dbd92	47	#define __CORE_CM4_H_GENERIC
Kojto	100:cbbeb26dbd92	48
Kojto	100:cbbeb26dbd92	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto	100:cbbeb26dbd92	50	CMSIS violates the following MISRA-C:2004 rules:
Kojto	100:cbbeb26dbd92	51
Kojto	100:cbbeb26dbd92	52	\li Required Rule 8.5, object/function definition in header file.<br>
Kojto	100:cbbeb26dbd92	53	Function definitions in header files are used to allow 'inlining'.
Kojto	100:cbbeb26dbd92	54
Kojto	100:cbbeb26dbd92	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto	100:cbbeb26dbd92	56	Unions are used for effective representation of core registers.
Kojto	100:cbbeb26dbd92	57
Kojto	100:cbbeb26dbd92	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto	100:cbbeb26dbd92	59	Function-like macros are used to allow more efficient code.
Kojto	100:cbbeb26dbd92	60	*/
Kojto	100:cbbeb26dbd92	61
Kojto	100:cbbeb26dbd92	62
Kojto	100:cbbeb26dbd92	63	/*******************************************************************************
Kojto	100:cbbeb26dbd92	64	* CMSIS definitions
Kojto	100:cbbeb26dbd92	65	******************************************************************************/
Kojto	100:cbbeb26dbd92	66	/** \ingroup Cortex_M4
Kojto	100:cbbeb26dbd92	67	@{
Kojto	100:cbbeb26dbd92	68	*/
Kojto	100:cbbeb26dbd92	69
Kojto	100:cbbeb26dbd92	70	/* CMSIS CM4 definitions */
Kojto	100:cbbeb26dbd92	71	#define __CM4_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
Kojto	100:cbbeb26dbd92	72	#define __CM4_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
Kojto	100:cbbeb26dbd92	73	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) \| \
Kojto	100:cbbeb26dbd92	74	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Kojto	100:cbbeb26dbd92	75
Kojto	100:cbbeb26dbd92	76	#define __CORTEX_M (0x04) /!< Cortex-M Core /
Kojto	100:cbbeb26dbd92	77
Kojto	100:cbbeb26dbd92	78
Kojto	100:cbbeb26dbd92	79	#if defined ( __CC_ARM )
Kojto	100:cbbeb26dbd92	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Kojto	100:cbbeb26dbd92	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Kojto	100:cbbeb26dbd92	82	#define __STATIC_INLINE static __inline
Kojto	100:cbbeb26dbd92	83
Kojto	100:cbbeb26dbd92	84	#elif defined ( __ICCARM__ )
Kojto	100:cbbeb26dbd92	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
Kojto	100:cbbeb26dbd92	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Kojto	100:cbbeb26dbd92	87	#define __STATIC_INLINE static inline
Kojto	100:cbbeb26dbd92	88
Kojto	100:cbbeb26dbd92	89	#elif defined ( __TMS470__ )
Kojto	100:cbbeb26dbd92	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Kojto	100:cbbeb26dbd92	91	#define __STATIC_INLINE static inline
Kojto	100:cbbeb26dbd92	92
Kojto	100:cbbeb26dbd92	93	#elif defined ( __GNUC__ )
Kojto	100:cbbeb26dbd92	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	100:cbbeb26dbd92	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	100:cbbeb26dbd92	96	#define __STATIC_INLINE static inline
Kojto	100:cbbeb26dbd92	97
Kojto	100:cbbeb26dbd92	98	#elif defined ( __TASKING__ )
Kojto	100:cbbeb26dbd92	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Kojto	100:cbbeb26dbd92	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Kojto	100:cbbeb26dbd92	101	#define __STATIC_INLINE static inline
Kojto	100:cbbeb26dbd92	102
Kojto	100:cbbeb26dbd92	103	#endif
Kojto	100:cbbeb26dbd92	104
Kojto	100:cbbeb26dbd92	105	/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
Kojto	100:cbbeb26dbd92	106	*/
Kojto	100:cbbeb26dbd92	107	#if defined ( __CC_ARM )
Kojto	100:cbbeb26dbd92	108	#if defined __TARGET_FPU_VFP
Kojto	100:cbbeb26dbd92	109	#if (__FPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	110	#define __FPU_USED 1
Kojto	100:cbbeb26dbd92	111	#else
Kojto	100:cbbeb26dbd92	112	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	100:cbbeb26dbd92	113	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	114	#endif
Kojto	100:cbbeb26dbd92	115	#else
Kojto	100:cbbeb26dbd92	116	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	117	#endif
Kojto	100:cbbeb26dbd92	118
Kojto	100:cbbeb26dbd92	119	#elif defined ( __ICCARM__ )
Kojto	100:cbbeb26dbd92	120	#if defined __ARMVFP__
Kojto	100:cbbeb26dbd92	121	#if (__FPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	122	#define __FPU_USED 1
Kojto	100:cbbeb26dbd92	123	#else
Kojto	100:cbbeb26dbd92	124	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	100:cbbeb26dbd92	125	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	126	#endif
Kojto	100:cbbeb26dbd92	127	#else
Kojto	100:cbbeb26dbd92	128	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	129	#endif
Kojto	100:cbbeb26dbd92	130
Kojto	100:cbbeb26dbd92	131	#elif defined ( __TMS470__ )
Kojto	100:cbbeb26dbd92	132	#if defined __TI_VFP_SUPPORT__
Kojto	100:cbbeb26dbd92	133	#if (__FPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	134	#define __FPU_USED 1
Kojto	100:cbbeb26dbd92	135	#else
Kojto	100:cbbeb26dbd92	136	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	100:cbbeb26dbd92	137	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	138	#endif
Kojto	100:cbbeb26dbd92	139	#else
Kojto	100:cbbeb26dbd92	140	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	141	#endif
Kojto	100:cbbeb26dbd92	142
Kojto	100:cbbeb26dbd92	143	#elif defined ( __GNUC__ )
Kojto	100:cbbeb26dbd92	144	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	100:cbbeb26dbd92	145	#if (__FPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	146	#define __FPU_USED 1
Kojto	100:cbbeb26dbd92	147	#else
Kojto	100:cbbeb26dbd92	148	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	100:cbbeb26dbd92	149	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	150	#endif
Kojto	100:cbbeb26dbd92	151	#else
Kojto	100:cbbeb26dbd92	152	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	153	#endif
Kojto	100:cbbeb26dbd92	154
Kojto	100:cbbeb26dbd92	155	#elif defined ( __TASKING__ )
Kojto	100:cbbeb26dbd92	156	#if defined __FPU_VFP__
Kojto	100:cbbeb26dbd92	157	#if (__FPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	158	#define __FPU_USED 1
Kojto	100:cbbeb26dbd92	159	#else
Kojto	100:cbbeb26dbd92	160	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	100:cbbeb26dbd92	161	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	162	#endif
Kojto	100:cbbeb26dbd92	163	#else
Kojto	100:cbbeb26dbd92	164	#define __FPU_USED 0
Kojto	100:cbbeb26dbd92	165	#endif
Kojto	100:cbbeb26dbd92	166	#endif
Kojto	100:cbbeb26dbd92	167
Kojto	100:cbbeb26dbd92	168	#include <stdint.h> /* standard types definitions */
Kojto	100:cbbeb26dbd92	169	#include <core_cmInstr.h> /* Core Instruction Access */
Kojto	100:cbbeb26dbd92	170	#include <core_cmFunc.h> /* Core Function Access */
Kojto	100:cbbeb26dbd92	171	#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
Kojto	100:cbbeb26dbd92	172
Kojto	100:cbbeb26dbd92	173	#endif /* __CORE_CM4_H_GENERIC */
Kojto	100:cbbeb26dbd92	174
Kojto	100:cbbeb26dbd92	175	#ifndef __CMSIS_GENERIC
Kojto	100:cbbeb26dbd92	176
Kojto	100:cbbeb26dbd92	177	#ifndef __CORE_CM4_H_DEPENDANT
Kojto	100:cbbeb26dbd92	178	#define __CORE_CM4_H_DEPENDANT
Kojto	100:cbbeb26dbd92	179
Kojto	100:cbbeb26dbd92	180	/* check device defines and use defaults */
Kojto	100:cbbeb26dbd92	181	#if defined __CHECK_DEVICE_DEFINES
Kojto	100:cbbeb26dbd92	182	#ifndef __CM4_REV
Kojto	100:cbbeb26dbd92	183	#define __CM4_REV 0x0000
Kojto	100:cbbeb26dbd92	184	#warning "__CM4_REV not defined in device header file; using default!"
Kojto	100:cbbeb26dbd92	185	#endif
Kojto	100:cbbeb26dbd92	186
Kojto	100:cbbeb26dbd92	187	#ifndef __FPU_PRESENT
Kojto	100:cbbeb26dbd92	188	#define __FPU_PRESENT 0
Kojto	100:cbbeb26dbd92	189	#warning "__FPU_PRESENT not defined in device header file; using default!"
Kojto	100:cbbeb26dbd92	190	#endif
Kojto	100:cbbeb26dbd92	191
Kojto	100:cbbeb26dbd92	192	#ifndef __MPU_PRESENT
Kojto	100:cbbeb26dbd92	193	#define __MPU_PRESENT 0
Kojto	100:cbbeb26dbd92	194	#warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto	100:cbbeb26dbd92	195	#endif
Kojto	100:cbbeb26dbd92	196
Kojto	100:cbbeb26dbd92	197	#ifndef __NVIC_PRIO_BITS
Kojto	100:cbbeb26dbd92	198	#define __NVIC_PRIO_BITS 4
Kojto	100:cbbeb26dbd92	199	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto	100:cbbeb26dbd92	200	#endif
Kojto	100:cbbeb26dbd92	201
Kojto	100:cbbeb26dbd92	202	#ifndef __Vendor_SysTickConfig
Kojto	100:cbbeb26dbd92	203	#define __Vendor_SysTickConfig 0
Kojto	100:cbbeb26dbd92	204	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto	100:cbbeb26dbd92	205	#endif
Kojto	100:cbbeb26dbd92	206	#endif
Kojto	100:cbbeb26dbd92	207
Kojto	100:cbbeb26dbd92	208	/* IO definitions (access restrictions to peripheral registers) */
Kojto	100:cbbeb26dbd92	209	/**
Kojto	100:cbbeb26dbd92	210	\defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto	100:cbbeb26dbd92	211
Kojto	100:cbbeb26dbd92	212	<strong>IO Type Qualifiers</strong> are used
Kojto	100:cbbeb26dbd92	213	\li to specify the access to peripheral variables.
Kojto	100:cbbeb26dbd92	214	\li for automatic generation of peripheral register debug information.
Kojto	100:cbbeb26dbd92	215	*/
Kojto	100:cbbeb26dbd92	216	#ifdef __cplusplus
Kojto	100:cbbeb26dbd92	217	#define __I volatile /!< Defines 'read only' permissions /
Kojto	100:cbbeb26dbd92	218	#else
Kojto	100:cbbeb26dbd92	219	#define __I volatile const /!< Defines 'read only' permissions /
Kojto	100:cbbeb26dbd92	220	#endif
Kojto	100:cbbeb26dbd92	221	#define __O volatile /!< Defines 'write only' permissions /
Kojto	100:cbbeb26dbd92	222	#define __IO volatile /!< Defines 'read / write' permissions /
Kojto	100:cbbeb26dbd92	223
Kojto	100:cbbeb26dbd92	224	/@} end of group Cortex_M4 /
Kojto	100:cbbeb26dbd92	225
Kojto	100:cbbeb26dbd92	226
Kojto	100:cbbeb26dbd92	227
Kojto	100:cbbeb26dbd92	228	/*******************************************************************************
Kojto	100:cbbeb26dbd92	229	* Register Abstraction
Kojto	100:cbbeb26dbd92	230	Core Register contain:
Kojto	100:cbbeb26dbd92	231	- Core Register
Kojto	100:cbbeb26dbd92	232	- Core NVIC Register
Kojto	100:cbbeb26dbd92	233	- Core SCB Register
Kojto	100:cbbeb26dbd92	234	- Core SysTick Register
Kojto	100:cbbeb26dbd92	235	- Core Debug Register
Kojto	100:cbbeb26dbd92	236	- Core MPU Register
Kojto	100:cbbeb26dbd92	237	- Core FPU Register
Kojto	100:cbbeb26dbd92	238	******************************************************************************/
Kojto	100:cbbeb26dbd92	239	/** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto	100:cbbeb26dbd92	240	\brief Type definitions and defines for Cortex-M processor based devices.
Kojto	100:cbbeb26dbd92	241	*/
Kojto	100:cbbeb26dbd92	242
Kojto	100:cbbeb26dbd92	243	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	244	\defgroup CMSIS_CORE Status and Control Registers
Kojto	100:cbbeb26dbd92	245	\brief Core Register type definitions.
Kojto	100:cbbeb26dbd92	246	@{
Kojto	100:cbbeb26dbd92	247	*/
Kojto	100:cbbeb26dbd92	248
Kojto	100:cbbeb26dbd92	249	/** \brief Union type to access the Application Program Status Register (APSR).
Kojto	100:cbbeb26dbd92	250	*/
Kojto	100:cbbeb26dbd92	251	typedef union
Kojto	100:cbbeb26dbd92	252	{
Kojto	100:cbbeb26dbd92	253	struct
Kojto	100:cbbeb26dbd92	254	{
Kojto	100:cbbeb26dbd92	255	#if (__CORTEX_M != 0x04)
Kojto	100:cbbeb26dbd92	256	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
Kojto	100:cbbeb26dbd92	257	#else
Kojto	100:cbbeb26dbd92	258	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Kojto	100:cbbeb26dbd92	259	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	100:cbbeb26dbd92	260	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Kojto	100:cbbeb26dbd92	261	#endif
Kojto	100:cbbeb26dbd92	262	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	100:cbbeb26dbd92	263	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	100:cbbeb26dbd92	264	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	100:cbbeb26dbd92	265	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	100:cbbeb26dbd92	266	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	100:cbbeb26dbd92	267	} b; /!< Structure used for bit access /
Kojto	100:cbbeb26dbd92	268	uint32_t w; /!< Type used for word access /
Kojto	100:cbbeb26dbd92	269	} APSR_Type;
Kojto	100:cbbeb26dbd92	270
Kojto	100:cbbeb26dbd92	271
Kojto	100:cbbeb26dbd92	272	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto	100:cbbeb26dbd92	273	*/
Kojto	100:cbbeb26dbd92	274	typedef union
Kojto	100:cbbeb26dbd92	275	{
Kojto	100:cbbeb26dbd92	276	struct
Kojto	100:cbbeb26dbd92	277	{
Kojto	100:cbbeb26dbd92	278	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	100:cbbeb26dbd92	279	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Kojto	100:cbbeb26dbd92	280	} b; /!< Structure used for bit access /
Kojto	100:cbbeb26dbd92	281	uint32_t w; /!< Type used for word access /
Kojto	100:cbbeb26dbd92	282	} IPSR_Type;
Kojto	100:cbbeb26dbd92	283
Kojto	100:cbbeb26dbd92	284
Kojto	100:cbbeb26dbd92	285	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto	100:cbbeb26dbd92	286	*/
Kojto	100:cbbeb26dbd92	287	typedef union
Kojto	100:cbbeb26dbd92	288	{
Kojto	100:cbbeb26dbd92	289	struct
Kojto	100:cbbeb26dbd92	290	{
Kojto	100:cbbeb26dbd92	291	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	100:cbbeb26dbd92	292	#if (__CORTEX_M != 0x04)
Kojto	100:cbbeb26dbd92	293	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
Kojto	100:cbbeb26dbd92	294	#else
Kojto	100:cbbeb26dbd92	295	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Kojto	100:cbbeb26dbd92	296	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	100:cbbeb26dbd92	297	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Kojto	100:cbbeb26dbd92	298	#endif
Kojto	100:cbbeb26dbd92	299	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Kojto	100:cbbeb26dbd92	300	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Kojto	100:cbbeb26dbd92	301	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	100:cbbeb26dbd92	302	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	100:cbbeb26dbd92	303	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	100:cbbeb26dbd92	304	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	100:cbbeb26dbd92	305	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	100:cbbeb26dbd92	306	} b; /!< Structure used for bit access /
Kojto	100:cbbeb26dbd92	307	uint32_t w; /!< Type used for word access /
Kojto	100:cbbeb26dbd92	308	} xPSR_Type;
Kojto	100:cbbeb26dbd92	309
Kojto	100:cbbeb26dbd92	310
Kojto	100:cbbeb26dbd92	311	/** \brief Union type to access the Control Registers (CONTROL).
Kojto	100:cbbeb26dbd92	312	*/
Kojto	100:cbbeb26dbd92	313	typedef union
Kojto	100:cbbeb26dbd92	314	{
Kojto	100:cbbeb26dbd92	315	struct
Kojto	100:cbbeb26dbd92	316	{
Kojto	100:cbbeb26dbd92	317	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Kojto	100:cbbeb26dbd92	318	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Kojto	100:cbbeb26dbd92	319	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Kojto	100:cbbeb26dbd92	320	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Kojto	100:cbbeb26dbd92	321	} b; /!< Structure used for bit access /
Kojto	100:cbbeb26dbd92	322	uint32_t w; /!< Type used for word access /
Kojto	100:cbbeb26dbd92	323	} CONTROL_Type;
Kojto	100:cbbeb26dbd92	324
Kojto	100:cbbeb26dbd92	325	/@} end of group CMSIS_CORE /
Kojto	100:cbbeb26dbd92	326
Kojto	100:cbbeb26dbd92	327
Kojto	100:cbbeb26dbd92	328	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	329	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto	100:cbbeb26dbd92	330	\brief Type definitions for the NVIC Registers
Kojto	100:cbbeb26dbd92	331	@{
Kojto	100:cbbeb26dbd92	332	*/
Kojto	100:cbbeb26dbd92	333
Kojto	100:cbbeb26dbd92	334	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto	100:cbbeb26dbd92	335	*/
Kojto	100:cbbeb26dbd92	336	typedef struct
Kojto	100:cbbeb26dbd92	337	{
Kojto	100:cbbeb26dbd92	338	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Kojto	100:cbbeb26dbd92	339	uint32_t RESERVED0[24];
Kojto	100:cbbeb26dbd92	340	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Kojto	100:cbbeb26dbd92	341	uint32_t RSERVED1[24];
Kojto	100:cbbeb26dbd92	342	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Kojto	100:cbbeb26dbd92	343	uint32_t RESERVED2[24];
Kojto	100:cbbeb26dbd92	344	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Kojto	100:cbbeb26dbd92	345	uint32_t RESERVED3[24];
Kojto	100:cbbeb26dbd92	346	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Kojto	100:cbbeb26dbd92	347	uint32_t RESERVED4[56];
Kojto	100:cbbeb26dbd92	348	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Kojto	100:cbbeb26dbd92	349	uint32_t RESERVED5[644];
Kojto	100:cbbeb26dbd92	350	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Kojto	100:cbbeb26dbd92	351	} NVIC_Type;
Kojto	100:cbbeb26dbd92	352
Kojto	100:cbbeb26dbd92	353	/* Software Triggered Interrupt Register Definitions */
Kojto	100:cbbeb26dbd92	354	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	100:cbbeb26dbd92	355	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
Kojto	100:cbbeb26dbd92	356
Kojto	100:cbbeb26dbd92	357	/@} end of group CMSIS_NVIC /
Kojto	100:cbbeb26dbd92	358
Kojto	100:cbbeb26dbd92	359
Kojto	100:cbbeb26dbd92	360	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	361	\defgroup CMSIS_SCB System Control Block (SCB)
Kojto	100:cbbeb26dbd92	362	\brief Type definitions for the System Control Block Registers
Kojto	100:cbbeb26dbd92	363	@{
Kojto	100:cbbeb26dbd92	364	*/
Kojto	100:cbbeb26dbd92	365
Kojto	100:cbbeb26dbd92	366	/** \brief Structure type to access the System Control Block (SCB).
Kojto	100:cbbeb26dbd92	367	*/
Kojto	100:cbbeb26dbd92	368	typedef struct
Kojto	100:cbbeb26dbd92	369	{
Kojto	100:cbbeb26dbd92	370	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Kojto	100:cbbeb26dbd92	371	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Kojto	100:cbbeb26dbd92	372	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Kojto	100:cbbeb26dbd92	373	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Kojto	100:cbbeb26dbd92	374	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Kojto	100:cbbeb26dbd92	375	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Kojto	100:cbbeb26dbd92	376	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Kojto	100:cbbeb26dbd92	377	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Kojto	100:cbbeb26dbd92	378	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Kojto	100:cbbeb26dbd92	379	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Kojto	100:cbbeb26dbd92	380	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Kojto	100:cbbeb26dbd92	381	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Kojto	100:cbbeb26dbd92	382	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Kojto	100:cbbeb26dbd92	383	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Kojto	100:cbbeb26dbd92	384	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Kojto	100:cbbeb26dbd92	385	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Kojto	100:cbbeb26dbd92	386	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Kojto	100:cbbeb26dbd92	387	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Kojto	100:cbbeb26dbd92	388	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Kojto	100:cbbeb26dbd92	389	uint32_t RESERVED0[5];
Kojto	100:cbbeb26dbd92	390	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Kojto	100:cbbeb26dbd92	391	} SCB_Type;
Kojto	100:cbbeb26dbd92	392
Kojto	100:cbbeb26dbd92	393	/* SCB CPUID Register Definitions */
Kojto	100:cbbeb26dbd92	394	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Kojto	100:cbbeb26dbd92	395	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Kojto	100:cbbeb26dbd92	396
Kojto	100:cbbeb26dbd92	397	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Kojto	100:cbbeb26dbd92	398	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Kojto	100:cbbeb26dbd92	399
Kojto	100:cbbeb26dbd92	400	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Kojto	100:cbbeb26dbd92	401	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Kojto	100:cbbeb26dbd92	402
Kojto	100:cbbeb26dbd92	403	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Kojto	100:cbbeb26dbd92	404	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Kojto	100:cbbeb26dbd92	405
Kojto	100:cbbeb26dbd92	406	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	100:cbbeb26dbd92	407	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
Kojto	100:cbbeb26dbd92	408
Kojto	100:cbbeb26dbd92	409	/* SCB Interrupt Control State Register Definitions */
Kojto	100:cbbeb26dbd92	410	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Kojto	100:cbbeb26dbd92	411	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Kojto	100:cbbeb26dbd92	412
Kojto	100:cbbeb26dbd92	413	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Kojto	100:cbbeb26dbd92	414	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Kojto	100:cbbeb26dbd92	415
Kojto	100:cbbeb26dbd92	416	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Kojto	100:cbbeb26dbd92	417	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Kojto	100:cbbeb26dbd92	418
Kojto	100:cbbeb26dbd92	419	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Kojto	100:cbbeb26dbd92	420	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Kojto	100:cbbeb26dbd92	421
Kojto	100:cbbeb26dbd92	422	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Kojto	100:cbbeb26dbd92	423	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Kojto	100:cbbeb26dbd92	424
Kojto	100:cbbeb26dbd92	425	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Kojto	100:cbbeb26dbd92	426	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Kojto	100:cbbeb26dbd92	427
Kojto	100:cbbeb26dbd92	428	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Kojto	100:cbbeb26dbd92	429	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Kojto	100:cbbeb26dbd92	430
Kojto	100:cbbeb26dbd92	431	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Kojto	100:cbbeb26dbd92	432	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Kojto	100:cbbeb26dbd92	433
Kojto	100:cbbeb26dbd92	434	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Kojto	100:cbbeb26dbd92	435	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Kojto	100:cbbeb26dbd92	436
Kojto	100:cbbeb26dbd92	437	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	100:cbbeb26dbd92	438	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
Kojto	100:cbbeb26dbd92	439
Kojto	100:cbbeb26dbd92	440	/* SCB Vector Table Offset Register Definitions */
Kojto	100:cbbeb26dbd92	441	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Kojto	100:cbbeb26dbd92	442	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	100:cbbeb26dbd92	443
Kojto	100:cbbeb26dbd92	444	/* SCB Application Interrupt and Reset Control Register Definitions */
Kojto	100:cbbeb26dbd92	445	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Kojto	100:cbbeb26dbd92	446	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Kojto	100:cbbeb26dbd92	447
Kojto	100:cbbeb26dbd92	448	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Kojto	100:cbbeb26dbd92	449	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Kojto	100:cbbeb26dbd92	450
Kojto	100:cbbeb26dbd92	451	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Kojto	100:cbbeb26dbd92	452	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Kojto	100:cbbeb26dbd92	453
Kojto	100:cbbeb26dbd92	454	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Kojto	100:cbbeb26dbd92	455	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Kojto	100:cbbeb26dbd92	456
Kojto	100:cbbeb26dbd92	457	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Kojto	100:cbbeb26dbd92	458	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Kojto	100:cbbeb26dbd92	459
Kojto	100:cbbeb26dbd92	460	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Kojto	100:cbbeb26dbd92	461	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Kojto	100:cbbeb26dbd92	462
Kojto	100:cbbeb26dbd92	463	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	100:cbbeb26dbd92	464	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
Kojto	100:cbbeb26dbd92	465
Kojto	100:cbbeb26dbd92	466	/* SCB System Control Register Definitions */
Kojto	100:cbbeb26dbd92	467	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Kojto	100:cbbeb26dbd92	468	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Kojto	100:cbbeb26dbd92	469
Kojto	100:cbbeb26dbd92	470	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Kojto	100:cbbeb26dbd92	471	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Kojto	100:cbbeb26dbd92	472
Kojto	100:cbbeb26dbd92	473	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Kojto	100:cbbeb26dbd92	474	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Kojto	100:cbbeb26dbd92	475
Kojto	100:cbbeb26dbd92	476	/* SCB Configuration Control Register Definitions */
Kojto	100:cbbeb26dbd92	477	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Kojto	100:cbbeb26dbd92	478	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Kojto	100:cbbeb26dbd92	479
Kojto	100:cbbeb26dbd92	480	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Kojto	100:cbbeb26dbd92	481	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Kojto	100:cbbeb26dbd92	482
Kojto	100:cbbeb26dbd92	483	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Kojto	100:cbbeb26dbd92	484	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Kojto	100:cbbeb26dbd92	485
Kojto	100:cbbeb26dbd92	486	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Kojto	100:cbbeb26dbd92	487	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Kojto	100:cbbeb26dbd92	488
Kojto	100:cbbeb26dbd92	489	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Kojto	100:cbbeb26dbd92	490	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Kojto	100:cbbeb26dbd92	491
Kojto	100:cbbeb26dbd92	492	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	100:cbbeb26dbd92	493	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
Kojto	100:cbbeb26dbd92	494
Kojto	100:cbbeb26dbd92	495	/* SCB System Handler Control and State Register Definitions */
Kojto	100:cbbeb26dbd92	496	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Kojto	100:cbbeb26dbd92	497	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Kojto	100:cbbeb26dbd92	498
Kojto	100:cbbeb26dbd92	499	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Kojto	100:cbbeb26dbd92	500	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Kojto	100:cbbeb26dbd92	501
Kojto	100:cbbeb26dbd92	502	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Kojto	100:cbbeb26dbd92	503	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Kojto	100:cbbeb26dbd92	504
Kojto	100:cbbeb26dbd92	505	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Kojto	100:cbbeb26dbd92	506	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Kojto	100:cbbeb26dbd92	507
Kojto	100:cbbeb26dbd92	508	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Kojto	100:cbbeb26dbd92	509	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Kojto	100:cbbeb26dbd92	510
Kojto	100:cbbeb26dbd92	511	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Kojto	100:cbbeb26dbd92	512	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Kojto	100:cbbeb26dbd92	513
Kojto	100:cbbeb26dbd92	514	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Kojto	100:cbbeb26dbd92	515	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Kojto	100:cbbeb26dbd92	516
Kojto	100:cbbeb26dbd92	517	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Kojto	100:cbbeb26dbd92	518	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Kojto	100:cbbeb26dbd92	519
Kojto	100:cbbeb26dbd92	520	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Kojto	100:cbbeb26dbd92	521	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Kojto	100:cbbeb26dbd92	522
Kojto	100:cbbeb26dbd92	523	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Kojto	100:cbbeb26dbd92	524	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Kojto	100:cbbeb26dbd92	525
Kojto	100:cbbeb26dbd92	526	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Kojto	100:cbbeb26dbd92	527	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Kojto	100:cbbeb26dbd92	528
Kojto	100:cbbeb26dbd92	529	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Kojto	100:cbbeb26dbd92	530	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Kojto	100:cbbeb26dbd92	531
Kojto	100:cbbeb26dbd92	532	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Kojto	100:cbbeb26dbd92	533	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Kojto	100:cbbeb26dbd92	534
Kojto	100:cbbeb26dbd92	535	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	100:cbbeb26dbd92	536	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
Kojto	100:cbbeb26dbd92	537
Kojto	100:cbbeb26dbd92	538	/* SCB Configurable Fault Status Registers Definitions */
Kojto	100:cbbeb26dbd92	539	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Kojto	100:cbbeb26dbd92	540	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Kojto	100:cbbeb26dbd92	541
Kojto	100:cbbeb26dbd92	542	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Kojto	100:cbbeb26dbd92	543	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Kojto	100:cbbeb26dbd92	544
Kojto	100:cbbeb26dbd92	545	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	100:cbbeb26dbd92	546	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Kojto	100:cbbeb26dbd92	547
Kojto	100:cbbeb26dbd92	548	/* SCB Hard Fault Status Registers Definitions */
Kojto	100:cbbeb26dbd92	549	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Kojto	100:cbbeb26dbd92	550	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Kojto	100:cbbeb26dbd92	551
Kojto	100:cbbeb26dbd92	552	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Kojto	100:cbbeb26dbd92	553	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Kojto	100:cbbeb26dbd92	554
Kojto	100:cbbeb26dbd92	555	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Kojto	100:cbbeb26dbd92	556	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Kojto	100:cbbeb26dbd92	557
Kojto	100:cbbeb26dbd92	558	/* SCB Debug Fault Status Register Definitions */
Kojto	100:cbbeb26dbd92	559	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Kojto	100:cbbeb26dbd92	560	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Kojto	100:cbbeb26dbd92	561
Kojto	100:cbbeb26dbd92	562	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Kojto	100:cbbeb26dbd92	563	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Kojto	100:cbbeb26dbd92	564
Kojto	100:cbbeb26dbd92	565	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Kojto	100:cbbeb26dbd92	566	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Kojto	100:cbbeb26dbd92	567
Kojto	100:cbbeb26dbd92	568	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Kojto	100:cbbeb26dbd92	569	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Kojto	100:cbbeb26dbd92	570
Kojto	100:cbbeb26dbd92	571	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	100:cbbeb26dbd92	572	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
Kojto	100:cbbeb26dbd92	573
Kojto	100:cbbeb26dbd92	574	/@} end of group CMSIS_SCB /
Kojto	100:cbbeb26dbd92	575
Kojto	100:cbbeb26dbd92	576
Kojto	100:cbbeb26dbd92	577	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	578	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto	100:cbbeb26dbd92	579	\brief Type definitions for the System Control and ID Register not in the SCB
Kojto	100:cbbeb26dbd92	580	@{
Kojto	100:cbbeb26dbd92	581	*/
Kojto	100:cbbeb26dbd92	582
Kojto	100:cbbeb26dbd92	583	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto	100:cbbeb26dbd92	584	*/
Kojto	100:cbbeb26dbd92	585	typedef struct
Kojto	100:cbbeb26dbd92	586	{
Kojto	100:cbbeb26dbd92	587	uint32_t RESERVED0[1];
Kojto	100:cbbeb26dbd92	588	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Kojto	100:cbbeb26dbd92	589	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Kojto	100:cbbeb26dbd92	590	} SCnSCB_Type;
Kojto	100:cbbeb26dbd92	591
Kojto	100:cbbeb26dbd92	592	/* Interrupt Controller Type Register Definitions */
Kojto	100:cbbeb26dbd92	593	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	100:cbbeb26dbd92	594	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
Kojto	100:cbbeb26dbd92	595
Kojto	100:cbbeb26dbd92	596	/* Auxiliary Control Register Definitions */
Kojto	100:cbbeb26dbd92	597	#define SCnSCB_ACTLR_DISOOFP_Pos 9 /!< ACTLR: DISOOFP Position /
Kojto	100:cbbeb26dbd92	598	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
Kojto	100:cbbeb26dbd92	599
Kojto	100:cbbeb26dbd92	600	#define SCnSCB_ACTLR_DISFPCA_Pos 8 /!< ACTLR: DISFPCA Position /
Kojto	100:cbbeb26dbd92	601	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
Kojto	100:cbbeb26dbd92	602
Kojto	100:cbbeb26dbd92	603	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Kojto	100:cbbeb26dbd92	604	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Kojto	100:cbbeb26dbd92	605
Kojto	100:cbbeb26dbd92	606	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
Kojto	100:cbbeb26dbd92	607	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
Kojto	100:cbbeb26dbd92	608
Kojto	100:cbbeb26dbd92	609	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Kojto	100:cbbeb26dbd92	610	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
Kojto	100:cbbeb26dbd92	611
Kojto	100:cbbeb26dbd92	612	/@} end of group CMSIS_SCnotSCB /
Kojto	100:cbbeb26dbd92	613
Kojto	100:cbbeb26dbd92	614
Kojto	100:cbbeb26dbd92	615	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	616	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto	100:cbbeb26dbd92	617	\brief Type definitions for the System Timer Registers.
Kojto	100:cbbeb26dbd92	618	@{
Kojto	100:cbbeb26dbd92	619	*/
Kojto	100:cbbeb26dbd92	620
Kojto	100:cbbeb26dbd92	621	/** \brief Structure type to access the System Timer (SysTick).
Kojto	100:cbbeb26dbd92	622	*/
Kojto	100:cbbeb26dbd92	623	typedef struct
Kojto	100:cbbeb26dbd92	624	{
Kojto	100:cbbeb26dbd92	625	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Kojto	100:cbbeb26dbd92	626	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Kojto	100:cbbeb26dbd92	627	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Kojto	100:cbbeb26dbd92	628	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Kojto	100:cbbeb26dbd92	629	} SysTick_Type;
Kojto	100:cbbeb26dbd92	630
Kojto	100:cbbeb26dbd92	631	/* SysTick Control / Status Register Definitions */
Kojto	100:cbbeb26dbd92	632	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Kojto	100:cbbeb26dbd92	633	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Kojto	100:cbbeb26dbd92	634
Kojto	100:cbbeb26dbd92	635	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Kojto	100:cbbeb26dbd92	636	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Kojto	100:cbbeb26dbd92	637
Kojto	100:cbbeb26dbd92	638	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Kojto	100:cbbeb26dbd92	639	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Kojto	100:cbbeb26dbd92	640
Kojto	100:cbbeb26dbd92	641	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	100:cbbeb26dbd92	642	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
Kojto	100:cbbeb26dbd92	643
Kojto	100:cbbeb26dbd92	644	/* SysTick Reload Register Definitions */
Kojto	100:cbbeb26dbd92	645	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	100:cbbeb26dbd92	646	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
Kojto	100:cbbeb26dbd92	647
Kojto	100:cbbeb26dbd92	648	/* SysTick Current Register Definitions */
Kojto	100:cbbeb26dbd92	649	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	100:cbbeb26dbd92	650	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
Kojto	100:cbbeb26dbd92	651
Kojto	100:cbbeb26dbd92	652	/* SysTick Calibration Register Definitions */
Kojto	100:cbbeb26dbd92	653	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Kojto	100:cbbeb26dbd92	654	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Kojto	100:cbbeb26dbd92	655
Kojto	100:cbbeb26dbd92	656	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Kojto	100:cbbeb26dbd92	657	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Kojto	100:cbbeb26dbd92	658
Kojto	100:cbbeb26dbd92	659	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	100:cbbeb26dbd92	660	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
Kojto	100:cbbeb26dbd92	661
Kojto	100:cbbeb26dbd92	662	/@} end of group CMSIS_SysTick /
Kojto	100:cbbeb26dbd92	663
Kojto	100:cbbeb26dbd92	664
Kojto	100:cbbeb26dbd92	665	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	666	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto	100:cbbeb26dbd92	667	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto	100:cbbeb26dbd92	668	@{
Kojto	100:cbbeb26dbd92	669	*/
Kojto	100:cbbeb26dbd92	670
Kojto	100:cbbeb26dbd92	671	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto	100:cbbeb26dbd92	672	*/
Kojto	100:cbbeb26dbd92	673	typedef struct
Kojto	100:cbbeb26dbd92	674	{
Kojto	100:cbbeb26dbd92	675	__O union
Kojto	100:cbbeb26dbd92	676	{
Kojto	100:cbbeb26dbd92	677	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Kojto	100:cbbeb26dbd92	678	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Kojto	100:cbbeb26dbd92	679	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Kojto	100:cbbeb26dbd92	680	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Kojto	100:cbbeb26dbd92	681	uint32_t RESERVED0[864];
Kojto	100:cbbeb26dbd92	682	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Kojto	100:cbbeb26dbd92	683	uint32_t RESERVED1[15];
Kojto	100:cbbeb26dbd92	684	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Kojto	100:cbbeb26dbd92	685	uint32_t RESERVED2[15];
Kojto	100:cbbeb26dbd92	686	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Kojto	100:cbbeb26dbd92	687	uint32_t RESERVED3[29];
Kojto	100:cbbeb26dbd92	688	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Kojto	100:cbbeb26dbd92	689	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Kojto	100:cbbeb26dbd92	690	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Kojto	100:cbbeb26dbd92	691	uint32_t RESERVED4[43];
Kojto	100:cbbeb26dbd92	692	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Kojto	100:cbbeb26dbd92	693	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Kojto	100:cbbeb26dbd92	694	uint32_t RESERVED5[6];
Kojto	100:cbbeb26dbd92	695	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Kojto	100:cbbeb26dbd92	696	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Kojto	100:cbbeb26dbd92	697	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Kojto	100:cbbeb26dbd92	698	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Kojto	100:cbbeb26dbd92	699	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Kojto	100:cbbeb26dbd92	700	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Kojto	100:cbbeb26dbd92	701	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Kojto	100:cbbeb26dbd92	702	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Kojto	100:cbbeb26dbd92	703	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Kojto	100:cbbeb26dbd92	704	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Kojto	100:cbbeb26dbd92	705	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Kojto	100:cbbeb26dbd92	706	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Kojto	100:cbbeb26dbd92	707	} ITM_Type;
Kojto	100:cbbeb26dbd92	708
Kojto	100:cbbeb26dbd92	709	/* ITM Trace Privilege Register Definitions */
Kojto	100:cbbeb26dbd92	710	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	100:cbbeb26dbd92	711	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
Kojto	100:cbbeb26dbd92	712
Kojto	100:cbbeb26dbd92	713	/* ITM Trace Control Register Definitions */
Kojto	100:cbbeb26dbd92	714	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Kojto	100:cbbeb26dbd92	715	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Kojto	100:cbbeb26dbd92	716
Kojto	100:cbbeb26dbd92	717	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Kojto	100:cbbeb26dbd92	718	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Kojto	100:cbbeb26dbd92	719
Kojto	100:cbbeb26dbd92	720	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Kojto	100:cbbeb26dbd92	721	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Kojto	100:cbbeb26dbd92	722
Kojto	100:cbbeb26dbd92	723	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Kojto	100:cbbeb26dbd92	724	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Kojto	100:cbbeb26dbd92	725
Kojto	100:cbbeb26dbd92	726	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Kojto	100:cbbeb26dbd92	727	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Kojto	100:cbbeb26dbd92	728
Kojto	100:cbbeb26dbd92	729	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Kojto	100:cbbeb26dbd92	730	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Kojto	100:cbbeb26dbd92	731
Kojto	100:cbbeb26dbd92	732	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Kojto	100:cbbeb26dbd92	733	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Kojto	100:cbbeb26dbd92	734
Kojto	100:cbbeb26dbd92	735	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Kojto	100:cbbeb26dbd92	736	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Kojto	100:cbbeb26dbd92	737
Kojto	100:cbbeb26dbd92	738	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	100:cbbeb26dbd92	739	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
Kojto	100:cbbeb26dbd92	740
Kojto	100:cbbeb26dbd92	741	/* ITM Integration Write Register Definitions */
Kojto	100:cbbeb26dbd92	742	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	100:cbbeb26dbd92	743	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
Kojto	100:cbbeb26dbd92	744
Kojto	100:cbbeb26dbd92	745	/* ITM Integration Read Register Definitions */
Kojto	100:cbbeb26dbd92	746	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	100:cbbeb26dbd92	747	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
Kojto	100:cbbeb26dbd92	748
Kojto	100:cbbeb26dbd92	749	/* ITM Integration Mode Control Register Definitions */
Kojto	100:cbbeb26dbd92	750	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	100:cbbeb26dbd92	751	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
Kojto	100:cbbeb26dbd92	752
Kojto	100:cbbeb26dbd92	753	/* ITM Lock Status Register Definitions */
Kojto	100:cbbeb26dbd92	754	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Kojto	100:cbbeb26dbd92	755	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Kojto	100:cbbeb26dbd92	756
Kojto	100:cbbeb26dbd92	757	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Kojto	100:cbbeb26dbd92	758	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Kojto	100:cbbeb26dbd92	759
Kojto	100:cbbeb26dbd92	760	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	100:cbbeb26dbd92	761	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
Kojto	100:cbbeb26dbd92	762
Kojto	100:cbbeb26dbd92	763	/@}/ /* end of group CMSIS_ITM */
Kojto	100:cbbeb26dbd92	764
Kojto	100:cbbeb26dbd92	765
Kojto	100:cbbeb26dbd92	766	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	767	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto	100:cbbeb26dbd92	768	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto	100:cbbeb26dbd92	769	@{
Kojto	100:cbbeb26dbd92	770	*/
Kojto	100:cbbeb26dbd92	771
Kojto	100:cbbeb26dbd92	772	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto	100:cbbeb26dbd92	773	*/
Kojto	100:cbbeb26dbd92	774	typedef struct
Kojto	100:cbbeb26dbd92	775	{
Kojto	100:cbbeb26dbd92	776	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Kojto	100:cbbeb26dbd92	777	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Kojto	100:cbbeb26dbd92	778	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Kojto	100:cbbeb26dbd92	779	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Kojto	100:cbbeb26dbd92	780	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Kojto	100:cbbeb26dbd92	781	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Kojto	100:cbbeb26dbd92	782	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Kojto	100:cbbeb26dbd92	783	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Kojto	100:cbbeb26dbd92	784	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Kojto	100:cbbeb26dbd92	785	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Kojto	100:cbbeb26dbd92	786	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Kojto	100:cbbeb26dbd92	787	uint32_t RESERVED0[1];
Kojto	100:cbbeb26dbd92	788	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Kojto	100:cbbeb26dbd92	789	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Kojto	100:cbbeb26dbd92	790	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Kojto	100:cbbeb26dbd92	791	uint32_t RESERVED1[1];
Kojto	100:cbbeb26dbd92	792	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Kojto	100:cbbeb26dbd92	793	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Kojto	100:cbbeb26dbd92	794	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Kojto	100:cbbeb26dbd92	795	uint32_t RESERVED2[1];
Kojto	100:cbbeb26dbd92	796	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Kojto	100:cbbeb26dbd92	797	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Kojto	100:cbbeb26dbd92	798	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Kojto	100:cbbeb26dbd92	799	} DWT_Type;
Kojto	100:cbbeb26dbd92	800
Kojto	100:cbbeb26dbd92	801	/* DWT Control Register Definitions */
Kojto	100:cbbeb26dbd92	802	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Kojto	100:cbbeb26dbd92	803	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Kojto	100:cbbeb26dbd92	804
Kojto	100:cbbeb26dbd92	805	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Kojto	100:cbbeb26dbd92	806	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Kojto	100:cbbeb26dbd92	807
Kojto	100:cbbeb26dbd92	808	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Kojto	100:cbbeb26dbd92	809	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Kojto	100:cbbeb26dbd92	810
Kojto	100:cbbeb26dbd92	811	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Kojto	100:cbbeb26dbd92	812	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Kojto	100:cbbeb26dbd92	813
Kojto	100:cbbeb26dbd92	814	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Kojto	100:cbbeb26dbd92	815	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Kojto	100:cbbeb26dbd92	816
Kojto	100:cbbeb26dbd92	817	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Kojto	100:cbbeb26dbd92	818	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Kojto	100:cbbeb26dbd92	819
Kojto	100:cbbeb26dbd92	820	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Kojto	100:cbbeb26dbd92	821	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Kojto	100:cbbeb26dbd92	822
Kojto	100:cbbeb26dbd92	823	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Kojto	100:cbbeb26dbd92	824	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Kojto	100:cbbeb26dbd92	825
Kojto	100:cbbeb26dbd92	826	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Kojto	100:cbbeb26dbd92	827	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Kojto	100:cbbeb26dbd92	828
Kojto	100:cbbeb26dbd92	829	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Kojto	100:cbbeb26dbd92	830	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Kojto	100:cbbeb26dbd92	831
Kojto	100:cbbeb26dbd92	832	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Kojto	100:cbbeb26dbd92	833	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Kojto	100:cbbeb26dbd92	834
Kojto	100:cbbeb26dbd92	835	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Kojto	100:cbbeb26dbd92	836	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Kojto	100:cbbeb26dbd92	837
Kojto	100:cbbeb26dbd92	838	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Kojto	100:cbbeb26dbd92	839	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Kojto	100:cbbeb26dbd92	840
Kojto	100:cbbeb26dbd92	841	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Kojto	100:cbbeb26dbd92	842	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Kojto	100:cbbeb26dbd92	843
Kojto	100:cbbeb26dbd92	844	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Kojto	100:cbbeb26dbd92	845	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Kojto	100:cbbeb26dbd92	846
Kojto	100:cbbeb26dbd92	847	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Kojto	100:cbbeb26dbd92	848	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Kojto	100:cbbeb26dbd92	849
Kojto	100:cbbeb26dbd92	850	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Kojto	100:cbbeb26dbd92	851	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Kojto	100:cbbeb26dbd92	852
Kojto	100:cbbeb26dbd92	853	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	100:cbbeb26dbd92	854	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
Kojto	100:cbbeb26dbd92	855
Kojto	100:cbbeb26dbd92	856	/* DWT CPI Count Register Definitions */
Kojto	100:cbbeb26dbd92	857	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	100:cbbeb26dbd92	858	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
Kojto	100:cbbeb26dbd92	859
Kojto	100:cbbeb26dbd92	860	/* DWT Exception Overhead Count Register Definitions */
Kojto	100:cbbeb26dbd92	861	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	100:cbbeb26dbd92	862	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
Kojto	100:cbbeb26dbd92	863
Kojto	100:cbbeb26dbd92	864	/* DWT Sleep Count Register Definitions */
Kojto	100:cbbeb26dbd92	865	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	100:cbbeb26dbd92	866	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Kojto	100:cbbeb26dbd92	867
Kojto	100:cbbeb26dbd92	868	/* DWT LSU Count Register Definitions */
Kojto	100:cbbeb26dbd92	869	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	100:cbbeb26dbd92	870	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
Kojto	100:cbbeb26dbd92	871
Kojto	100:cbbeb26dbd92	872	/* DWT Folded-instruction Count Register Definitions */
Kojto	100:cbbeb26dbd92	873	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	100:cbbeb26dbd92	874	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
Kojto	100:cbbeb26dbd92	875
Kojto	100:cbbeb26dbd92	876	/* DWT Comparator Mask Register Definitions */
Kojto	100:cbbeb26dbd92	877	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	100:cbbeb26dbd92	878	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
Kojto	100:cbbeb26dbd92	879
Kojto	100:cbbeb26dbd92	880	/* DWT Comparator Function Register Definitions */
Kojto	100:cbbeb26dbd92	881	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Kojto	100:cbbeb26dbd92	882	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Kojto	100:cbbeb26dbd92	883
Kojto	100:cbbeb26dbd92	884	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Kojto	100:cbbeb26dbd92	885	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Kojto	100:cbbeb26dbd92	886
Kojto	100:cbbeb26dbd92	887	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Kojto	100:cbbeb26dbd92	888	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Kojto	100:cbbeb26dbd92	889
Kojto	100:cbbeb26dbd92	890	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Kojto	100:cbbeb26dbd92	891	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Kojto	100:cbbeb26dbd92	892
Kojto	100:cbbeb26dbd92	893	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Kojto	100:cbbeb26dbd92	894	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Kojto	100:cbbeb26dbd92	895
Kojto	100:cbbeb26dbd92	896	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Kojto	100:cbbeb26dbd92	897	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Kojto	100:cbbeb26dbd92	898
Kojto	100:cbbeb26dbd92	899	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Kojto	100:cbbeb26dbd92	900	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Kojto	100:cbbeb26dbd92	901
Kojto	100:cbbeb26dbd92	902	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Kojto	100:cbbeb26dbd92	903	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Kojto	100:cbbeb26dbd92	904
Kojto	100:cbbeb26dbd92	905	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	100:cbbeb26dbd92	906	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
Kojto	100:cbbeb26dbd92	907
Kojto	100:cbbeb26dbd92	908	/@}/ /* end of group CMSIS_DWT */
Kojto	100:cbbeb26dbd92	909
Kojto	100:cbbeb26dbd92	910
Kojto	100:cbbeb26dbd92	911	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	912	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto	100:cbbeb26dbd92	913	\brief Type definitions for the Trace Port Interface (TPI)
Kojto	100:cbbeb26dbd92	914	@{
Kojto	100:cbbeb26dbd92	915	*/
Kojto	100:cbbeb26dbd92	916
Kojto	100:cbbeb26dbd92	917	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto	100:cbbeb26dbd92	918	*/
Kojto	100:cbbeb26dbd92	919	typedef struct
Kojto	100:cbbeb26dbd92	920	{
Kojto	100:cbbeb26dbd92	921	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Kojto	100:cbbeb26dbd92	922	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Kojto	100:cbbeb26dbd92	923	uint32_t RESERVED0[2];
Kojto	100:cbbeb26dbd92	924	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Kojto	100:cbbeb26dbd92	925	uint32_t RESERVED1[55];
Kojto	100:cbbeb26dbd92	926	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Kojto	100:cbbeb26dbd92	927	uint32_t RESERVED2[131];
Kojto	100:cbbeb26dbd92	928	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Kojto	100:cbbeb26dbd92	929	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Kojto	100:cbbeb26dbd92	930	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Kojto	100:cbbeb26dbd92	931	uint32_t RESERVED3[759];
Kojto	100:cbbeb26dbd92	932	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Kojto	100:cbbeb26dbd92	933	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Kojto	100:cbbeb26dbd92	934	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Kojto	100:cbbeb26dbd92	935	uint32_t RESERVED4[1];
Kojto	100:cbbeb26dbd92	936	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Kojto	100:cbbeb26dbd92	937	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Kojto	100:cbbeb26dbd92	938	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Kojto	100:cbbeb26dbd92	939	uint32_t RESERVED5[39];
Kojto	100:cbbeb26dbd92	940	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Kojto	100:cbbeb26dbd92	941	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Kojto	100:cbbeb26dbd92	942	uint32_t RESERVED7[8];
Kojto	100:cbbeb26dbd92	943	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Kojto	100:cbbeb26dbd92	944	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Kojto	100:cbbeb26dbd92	945	} TPI_Type;
Kojto	100:cbbeb26dbd92	946
Kojto	100:cbbeb26dbd92	947	/* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto	100:cbbeb26dbd92	948	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	100:cbbeb26dbd92	949	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
Kojto	100:cbbeb26dbd92	950
Kojto	100:cbbeb26dbd92	951	/* TPI Selected Pin Protocol Register Definitions */
Kojto	100:cbbeb26dbd92	952	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	100:cbbeb26dbd92	953	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
Kojto	100:cbbeb26dbd92	954
Kojto	100:cbbeb26dbd92	955	/* TPI Formatter and Flush Status Register Definitions */
Kojto	100:cbbeb26dbd92	956	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Kojto	100:cbbeb26dbd92	957	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Kojto	100:cbbeb26dbd92	958
Kojto	100:cbbeb26dbd92	959	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Kojto	100:cbbeb26dbd92	960	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Kojto	100:cbbeb26dbd92	961
Kojto	100:cbbeb26dbd92	962	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Kojto	100:cbbeb26dbd92	963	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Kojto	100:cbbeb26dbd92	964
Kojto	100:cbbeb26dbd92	965	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	100:cbbeb26dbd92	966	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
Kojto	100:cbbeb26dbd92	967
Kojto	100:cbbeb26dbd92	968	/* TPI Formatter and Flush Control Register Definitions */
Kojto	100:cbbeb26dbd92	969	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Kojto	100:cbbeb26dbd92	970	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Kojto	100:cbbeb26dbd92	971
Kojto	100:cbbeb26dbd92	972	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Kojto	100:cbbeb26dbd92	973	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Kojto	100:cbbeb26dbd92	974
Kojto	100:cbbeb26dbd92	975	/* TPI TRIGGER Register Definitions */
Kojto	100:cbbeb26dbd92	976	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	100:cbbeb26dbd92	977	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
Kojto	100:cbbeb26dbd92	978
Kojto	100:cbbeb26dbd92	979	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto	100:cbbeb26dbd92	980	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Kojto	100:cbbeb26dbd92	981	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Kojto	100:cbbeb26dbd92	982
Kojto	100:cbbeb26dbd92	983	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Kojto	100:cbbeb26dbd92	984	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Kojto	100:cbbeb26dbd92	985
Kojto	100:cbbeb26dbd92	986	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Kojto	100:cbbeb26dbd92	987	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Kojto	100:cbbeb26dbd92	988
Kojto	100:cbbeb26dbd92	989	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Kojto	100:cbbeb26dbd92	990	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Kojto	100:cbbeb26dbd92	991
Kojto	100:cbbeb26dbd92	992	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Kojto	100:cbbeb26dbd92	993	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Kojto	100:cbbeb26dbd92	994
Kojto	100:cbbeb26dbd92	995	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Kojto	100:cbbeb26dbd92	996	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Kojto	100:cbbeb26dbd92	997
Kojto	100:cbbeb26dbd92	998	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	100:cbbeb26dbd92	999	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
Kojto	100:cbbeb26dbd92	1000
Kojto	100:cbbeb26dbd92	1001	/* TPI ITATBCTR2 Register Definitions */
Kojto	100:cbbeb26dbd92	1002	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	100:cbbeb26dbd92	1003	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
Kojto	100:cbbeb26dbd92	1004
Kojto	100:cbbeb26dbd92	1005	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto	100:cbbeb26dbd92	1006	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Kojto	100:cbbeb26dbd92	1007	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Kojto	100:cbbeb26dbd92	1008
Kojto	100:cbbeb26dbd92	1009	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Kojto	100:cbbeb26dbd92	1010	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Kojto	100:cbbeb26dbd92	1011
Kojto	100:cbbeb26dbd92	1012	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Kojto	100:cbbeb26dbd92	1013	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Kojto	100:cbbeb26dbd92	1014
Kojto	100:cbbeb26dbd92	1015	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Kojto	100:cbbeb26dbd92	1016	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Kojto	100:cbbeb26dbd92	1017
Kojto	100:cbbeb26dbd92	1018	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Kojto	100:cbbeb26dbd92	1019	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Kojto	100:cbbeb26dbd92	1020
Kojto	100:cbbeb26dbd92	1021	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Kojto	100:cbbeb26dbd92	1022	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Kojto	100:cbbeb26dbd92	1023
Kojto	100:cbbeb26dbd92	1024	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	100:cbbeb26dbd92	1025	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
Kojto	100:cbbeb26dbd92	1026
Kojto	100:cbbeb26dbd92	1027	/* TPI ITATBCTR0 Register Definitions */
Kojto	100:cbbeb26dbd92	1028	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	100:cbbeb26dbd92	1029	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
Kojto	100:cbbeb26dbd92	1030
Kojto	100:cbbeb26dbd92	1031	/* TPI Integration Mode Control Register Definitions */
Kojto	100:cbbeb26dbd92	1032	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	100:cbbeb26dbd92	1033	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
Kojto	100:cbbeb26dbd92	1034
Kojto	100:cbbeb26dbd92	1035	/* TPI DEVID Register Definitions */
Kojto	100:cbbeb26dbd92	1036	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Kojto	100:cbbeb26dbd92	1037	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Kojto	100:cbbeb26dbd92	1038
Kojto	100:cbbeb26dbd92	1039	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Kojto	100:cbbeb26dbd92	1040	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Kojto	100:cbbeb26dbd92	1041
Kojto	100:cbbeb26dbd92	1042	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Kojto	100:cbbeb26dbd92	1043	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Kojto	100:cbbeb26dbd92	1044
Kojto	100:cbbeb26dbd92	1045	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Kojto	100:cbbeb26dbd92	1046	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Kojto	100:cbbeb26dbd92	1047
Kojto	100:cbbeb26dbd92	1048	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Kojto	100:cbbeb26dbd92	1049	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Kojto	100:cbbeb26dbd92	1050
Kojto	100:cbbeb26dbd92	1051	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	100:cbbeb26dbd92	1052	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
Kojto	100:cbbeb26dbd92	1053
Kojto	100:cbbeb26dbd92	1054	/* TPI DEVTYPE Register Definitions */
Kojto	100:cbbeb26dbd92	1055	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	100:cbbeb26dbd92	1056	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
Kojto	100:cbbeb26dbd92	1057
Kojto	100:cbbeb26dbd92	1058	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Kojto	100:cbbeb26dbd92	1059	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Kojto	100:cbbeb26dbd92	1060
Kojto	100:cbbeb26dbd92	1061	/@}/ /* end of group CMSIS_TPI */
Kojto	100:cbbeb26dbd92	1062
Kojto	100:cbbeb26dbd92	1063
Kojto	100:cbbeb26dbd92	1064	#if (__MPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	1065	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	1066	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto	100:cbbeb26dbd92	1067	\brief Type definitions for the Memory Protection Unit (MPU)
Kojto	100:cbbeb26dbd92	1068	@{
Kojto	100:cbbeb26dbd92	1069	*/
Kojto	100:cbbeb26dbd92	1070
Kojto	100:cbbeb26dbd92	1071	/** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto	100:cbbeb26dbd92	1072	*/
Kojto	100:cbbeb26dbd92	1073	typedef struct
Kojto	100:cbbeb26dbd92	1074	{
Kojto	100:cbbeb26dbd92	1075	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Kojto	100:cbbeb26dbd92	1076	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Kojto	100:cbbeb26dbd92	1077	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Kojto	100:cbbeb26dbd92	1078	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Kojto	100:cbbeb26dbd92	1079	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Kojto	100:cbbeb26dbd92	1080	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Kojto	100:cbbeb26dbd92	1081	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Kojto	100:cbbeb26dbd92	1082	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Kojto	100:cbbeb26dbd92	1083	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Kojto	100:cbbeb26dbd92	1084	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Kojto	100:cbbeb26dbd92	1085	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Kojto	100:cbbeb26dbd92	1086	} MPU_Type;
Kojto	100:cbbeb26dbd92	1087
Kojto	100:cbbeb26dbd92	1088	/* MPU Type Register */
Kojto	100:cbbeb26dbd92	1089	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Kojto	100:cbbeb26dbd92	1090	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Kojto	100:cbbeb26dbd92	1091
Kojto	100:cbbeb26dbd92	1092	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Kojto	100:cbbeb26dbd92	1093	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Kojto	100:cbbeb26dbd92	1094
Kojto	100:cbbeb26dbd92	1095	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	100:cbbeb26dbd92	1096	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
Kojto	100:cbbeb26dbd92	1097
Kojto	100:cbbeb26dbd92	1098	/* MPU Control Register */
Kojto	100:cbbeb26dbd92	1099	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Kojto	100:cbbeb26dbd92	1100	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Kojto	100:cbbeb26dbd92	1101
Kojto	100:cbbeb26dbd92	1102	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Kojto	100:cbbeb26dbd92	1103	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Kojto	100:cbbeb26dbd92	1104
Kojto	100:cbbeb26dbd92	1105	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	100:cbbeb26dbd92	1106	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
Kojto	100:cbbeb26dbd92	1107
Kojto	100:cbbeb26dbd92	1108	/* MPU Region Number Register */
Kojto	100:cbbeb26dbd92	1109	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	100:cbbeb26dbd92	1110	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
Kojto	100:cbbeb26dbd92	1111
Kojto	100:cbbeb26dbd92	1112	/* MPU Region Base Address Register */
Kojto	100:cbbeb26dbd92	1113	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Kojto	100:cbbeb26dbd92	1114	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Kojto	100:cbbeb26dbd92	1115
Kojto	100:cbbeb26dbd92	1116	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Kojto	100:cbbeb26dbd92	1117	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Kojto	100:cbbeb26dbd92	1118
Kojto	100:cbbeb26dbd92	1119	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	100:cbbeb26dbd92	1120	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
Kojto	100:cbbeb26dbd92	1121
Kojto	100:cbbeb26dbd92	1122	/* MPU Region Attribute and Size Register */
Kojto	100:cbbeb26dbd92	1123	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Kojto	100:cbbeb26dbd92	1124	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Kojto	100:cbbeb26dbd92	1125
Kojto	100:cbbeb26dbd92	1126	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Kojto	100:cbbeb26dbd92	1127	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Kojto	100:cbbeb26dbd92	1128
Kojto	100:cbbeb26dbd92	1129	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Kojto	100:cbbeb26dbd92	1130	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Kojto	100:cbbeb26dbd92	1131
Kojto	100:cbbeb26dbd92	1132	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Kojto	100:cbbeb26dbd92	1133	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Kojto	100:cbbeb26dbd92	1134
Kojto	100:cbbeb26dbd92	1135	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Kojto	100:cbbeb26dbd92	1136	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Kojto	100:cbbeb26dbd92	1137
Kojto	100:cbbeb26dbd92	1138	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Kojto	100:cbbeb26dbd92	1139	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Kojto	100:cbbeb26dbd92	1140
Kojto	100:cbbeb26dbd92	1141	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Kojto	100:cbbeb26dbd92	1142	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Kojto	100:cbbeb26dbd92	1143
Kojto	100:cbbeb26dbd92	1144	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Kojto	100:cbbeb26dbd92	1145	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Kojto	100:cbbeb26dbd92	1146
Kojto	100:cbbeb26dbd92	1147	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Kojto	100:cbbeb26dbd92	1148	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Kojto	100:cbbeb26dbd92	1149
Kojto	100:cbbeb26dbd92	1150	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	100:cbbeb26dbd92	1151	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
Kojto	100:cbbeb26dbd92	1152
Kojto	100:cbbeb26dbd92	1153	/@} end of group CMSIS_MPU /
Kojto	100:cbbeb26dbd92	1154	#endif
Kojto	100:cbbeb26dbd92	1155
Kojto	100:cbbeb26dbd92	1156
Kojto	100:cbbeb26dbd92	1157	#if (__FPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	1158	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	1159	\defgroup CMSIS_FPU Floating Point Unit (FPU)
Kojto	100:cbbeb26dbd92	1160	\brief Type definitions for the Floating Point Unit (FPU)
Kojto	100:cbbeb26dbd92	1161	@{
Kojto	100:cbbeb26dbd92	1162	*/
Kojto	100:cbbeb26dbd92	1163
Kojto	100:cbbeb26dbd92	1164	/** \brief Structure type to access the Floating Point Unit (FPU).
Kojto	100:cbbeb26dbd92	1165	*/
Kojto	100:cbbeb26dbd92	1166	typedef struct
Kojto	100:cbbeb26dbd92	1167	{
Kojto	100:cbbeb26dbd92	1168	uint32_t RESERVED0[1];
Kojto	100:cbbeb26dbd92	1169	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
Kojto	100:cbbeb26dbd92	1170	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
Kojto	100:cbbeb26dbd92	1171	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
Kojto	100:cbbeb26dbd92	1172	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
Kojto	100:cbbeb26dbd92	1173	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
Kojto	100:cbbeb26dbd92	1174	} FPU_Type;
Kojto	100:cbbeb26dbd92	1175
Kojto	100:cbbeb26dbd92	1176	/* Floating-Point Context Control Register */
Kojto	100:cbbeb26dbd92	1177	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
Kojto	100:cbbeb26dbd92	1178	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
Kojto	100:cbbeb26dbd92	1179
Kojto	100:cbbeb26dbd92	1180	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
Kojto	100:cbbeb26dbd92	1181	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
Kojto	100:cbbeb26dbd92	1182
Kojto	100:cbbeb26dbd92	1183	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
Kojto	100:cbbeb26dbd92	1184	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
Kojto	100:cbbeb26dbd92	1185
Kojto	100:cbbeb26dbd92	1186	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
Kojto	100:cbbeb26dbd92	1187	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
Kojto	100:cbbeb26dbd92	1188
Kojto	100:cbbeb26dbd92	1189	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
Kojto	100:cbbeb26dbd92	1190	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
Kojto	100:cbbeb26dbd92	1191
Kojto	100:cbbeb26dbd92	1192	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
Kojto	100:cbbeb26dbd92	1193	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
Kojto	100:cbbeb26dbd92	1194
Kojto	100:cbbeb26dbd92	1195	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
Kojto	100:cbbeb26dbd92	1196	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
Kojto	100:cbbeb26dbd92	1197
Kojto	100:cbbeb26dbd92	1198	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
Kojto	100:cbbeb26dbd92	1199	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
Kojto	100:cbbeb26dbd92	1200
Kojto	100:cbbeb26dbd92	1201	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
Kojto	100:cbbeb26dbd92	1202	#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /!< FPCCR: Lazy state preservation active bit Mask /
Kojto	100:cbbeb26dbd92	1203
Kojto	100:cbbeb26dbd92	1204	/* Floating-Point Context Address Register */
Kojto	100:cbbeb26dbd92	1205	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
Kojto	100:cbbeb26dbd92	1206	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
Kojto	100:cbbeb26dbd92	1207
Kojto	100:cbbeb26dbd92	1208	/* Floating-Point Default Status Control Register */
Kojto	100:cbbeb26dbd92	1209	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
Kojto	100:cbbeb26dbd92	1210	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
Kojto	100:cbbeb26dbd92	1211
Kojto	100:cbbeb26dbd92	1212	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
Kojto	100:cbbeb26dbd92	1213	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
Kojto	100:cbbeb26dbd92	1214
Kojto	100:cbbeb26dbd92	1215	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
Kojto	100:cbbeb26dbd92	1216	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
Kojto	100:cbbeb26dbd92	1217
Kojto	100:cbbeb26dbd92	1218	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
Kojto	100:cbbeb26dbd92	1219	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
Kojto	100:cbbeb26dbd92	1220
Kojto	100:cbbeb26dbd92	1221	/* Media and FP Feature Register 0 */
Kojto	100:cbbeb26dbd92	1222	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
Kojto	100:cbbeb26dbd92	1223	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
Kojto	100:cbbeb26dbd92	1224
Kojto	100:cbbeb26dbd92	1225	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
Kojto	100:cbbeb26dbd92	1226	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
Kojto	100:cbbeb26dbd92	1227
Kojto	100:cbbeb26dbd92	1228	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
Kojto	100:cbbeb26dbd92	1229	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
Kojto	100:cbbeb26dbd92	1230
Kojto	100:cbbeb26dbd92	1231	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
Kojto	100:cbbeb26dbd92	1232	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
Kojto	100:cbbeb26dbd92	1233
Kojto	100:cbbeb26dbd92	1234	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
Kojto	100:cbbeb26dbd92	1235	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
Kojto	100:cbbeb26dbd92	1236
Kojto	100:cbbeb26dbd92	1237	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
Kojto	100:cbbeb26dbd92	1238	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
Kojto	100:cbbeb26dbd92	1239
Kojto	100:cbbeb26dbd92	1240	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
Kojto	100:cbbeb26dbd92	1241	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
Kojto	100:cbbeb26dbd92	1242
Kojto	100:cbbeb26dbd92	1243	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
Kojto	100:cbbeb26dbd92	1244	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /!< MVFR0: A_SIMD registers bits Mask /
Kojto	100:cbbeb26dbd92	1245
Kojto	100:cbbeb26dbd92	1246	/* Media and FP Feature Register 1 */
Kojto	100:cbbeb26dbd92	1247	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
Kojto	100:cbbeb26dbd92	1248	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
Kojto	100:cbbeb26dbd92	1249
Kojto	100:cbbeb26dbd92	1250	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
Kojto	100:cbbeb26dbd92	1251	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
Kojto	100:cbbeb26dbd92	1252
Kojto	100:cbbeb26dbd92	1253	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
Kojto	100:cbbeb26dbd92	1254	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
Kojto	100:cbbeb26dbd92	1255
Kojto	100:cbbeb26dbd92	1256	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
Kojto	100:cbbeb26dbd92	1257	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /!< MVFR1: FtZ mode bits Mask /
Kojto	100:cbbeb26dbd92	1258
Kojto	100:cbbeb26dbd92	1259	/@} end of group CMSIS_FPU /
Kojto	100:cbbeb26dbd92	1260	#endif
Kojto	100:cbbeb26dbd92	1261
Kojto	100:cbbeb26dbd92	1262
Kojto	100:cbbeb26dbd92	1263	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	1264	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto	100:cbbeb26dbd92	1265	\brief Type definitions for the Core Debug Registers
Kojto	100:cbbeb26dbd92	1266	@{
Kojto	100:cbbeb26dbd92	1267	*/
Kojto	100:cbbeb26dbd92	1268
Kojto	100:cbbeb26dbd92	1269	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto	100:cbbeb26dbd92	1270	*/
Kojto	100:cbbeb26dbd92	1271	typedef struct
Kojto	100:cbbeb26dbd92	1272	{
Kojto	100:cbbeb26dbd92	1273	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Kojto	100:cbbeb26dbd92	1274	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Kojto	100:cbbeb26dbd92	1275	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Kojto	100:cbbeb26dbd92	1276	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Kojto	100:cbbeb26dbd92	1277	} CoreDebug_Type;
Kojto	100:cbbeb26dbd92	1278
Kojto	100:cbbeb26dbd92	1279	/* Debug Halting Control and Status Register */
Kojto	100:cbbeb26dbd92	1280	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Kojto	100:cbbeb26dbd92	1281	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Kojto	100:cbbeb26dbd92	1282
Kojto	100:cbbeb26dbd92	1283	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Kojto	100:cbbeb26dbd92	1284	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Kojto	100:cbbeb26dbd92	1285
Kojto	100:cbbeb26dbd92	1286	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Kojto	100:cbbeb26dbd92	1287	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Kojto	100:cbbeb26dbd92	1288
Kojto	100:cbbeb26dbd92	1289	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Kojto	100:cbbeb26dbd92	1290	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Kojto	100:cbbeb26dbd92	1291
Kojto	100:cbbeb26dbd92	1292	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Kojto	100:cbbeb26dbd92	1293	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Kojto	100:cbbeb26dbd92	1294
Kojto	100:cbbeb26dbd92	1295	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Kojto	100:cbbeb26dbd92	1296	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Kojto	100:cbbeb26dbd92	1297
Kojto	100:cbbeb26dbd92	1298	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Kojto	100:cbbeb26dbd92	1299	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Kojto	100:cbbeb26dbd92	1300
Kojto	100:cbbeb26dbd92	1301	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Kojto	100:cbbeb26dbd92	1302	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Kojto	100:cbbeb26dbd92	1303
Kojto	100:cbbeb26dbd92	1304	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Kojto	100:cbbeb26dbd92	1305	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Kojto	100:cbbeb26dbd92	1306
Kojto	100:cbbeb26dbd92	1307	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Kojto	100:cbbeb26dbd92	1308	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Kojto	100:cbbeb26dbd92	1309
Kojto	100:cbbeb26dbd92	1310	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Kojto	100:cbbeb26dbd92	1311	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Kojto	100:cbbeb26dbd92	1312
Kojto	100:cbbeb26dbd92	1313	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	100:cbbeb26dbd92	1314	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Kojto	100:cbbeb26dbd92	1315
Kojto	100:cbbeb26dbd92	1316	/* Debug Core Register Selector Register */
Kojto	100:cbbeb26dbd92	1317	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Kojto	100:cbbeb26dbd92	1318	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Kojto	100:cbbeb26dbd92	1319
Kojto	100:cbbeb26dbd92	1320	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	100:cbbeb26dbd92	1321	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
Kojto	100:cbbeb26dbd92	1322
Kojto	100:cbbeb26dbd92	1323	/* Debug Exception and Monitor Control Register */
Kojto	100:cbbeb26dbd92	1324	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Kojto	100:cbbeb26dbd92	1325	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Kojto	100:cbbeb26dbd92	1326
Kojto	100:cbbeb26dbd92	1327	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Kojto	100:cbbeb26dbd92	1328	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Kojto	100:cbbeb26dbd92	1329
Kojto	100:cbbeb26dbd92	1330	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Kojto	100:cbbeb26dbd92	1331	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Kojto	100:cbbeb26dbd92	1332
Kojto	100:cbbeb26dbd92	1333	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Kojto	100:cbbeb26dbd92	1334	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Kojto	100:cbbeb26dbd92	1335
Kojto	100:cbbeb26dbd92	1336	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Kojto	100:cbbeb26dbd92	1337	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Kojto	100:cbbeb26dbd92	1338
Kojto	100:cbbeb26dbd92	1339	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Kojto	100:cbbeb26dbd92	1340	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Kojto	100:cbbeb26dbd92	1341
Kojto	100:cbbeb26dbd92	1342	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Kojto	100:cbbeb26dbd92	1343	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Kojto	100:cbbeb26dbd92	1344
Kojto	100:cbbeb26dbd92	1345	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Kojto	100:cbbeb26dbd92	1346	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Kojto	100:cbbeb26dbd92	1347
Kojto	100:cbbeb26dbd92	1348	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Kojto	100:cbbeb26dbd92	1349	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Kojto	100:cbbeb26dbd92	1350
Kojto	100:cbbeb26dbd92	1351	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Kojto	100:cbbeb26dbd92	1352	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Kojto	100:cbbeb26dbd92	1353
Kojto	100:cbbeb26dbd92	1354	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Kojto	100:cbbeb26dbd92	1355	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Kojto	100:cbbeb26dbd92	1356
Kojto	100:cbbeb26dbd92	1357	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Kojto	100:cbbeb26dbd92	1358	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Kojto	100:cbbeb26dbd92	1359
Kojto	100:cbbeb26dbd92	1360	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	100:cbbeb26dbd92	1361	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Kojto	100:cbbeb26dbd92	1362
Kojto	100:cbbeb26dbd92	1363	/@} end of group CMSIS_CoreDebug /
Kojto	100:cbbeb26dbd92	1364
Kojto	100:cbbeb26dbd92	1365
Kojto	100:cbbeb26dbd92	1366	/** \ingroup CMSIS_core_register
Kojto	100:cbbeb26dbd92	1367	\defgroup CMSIS_core_base Core Definitions
Kojto	100:cbbeb26dbd92	1368	\brief Definitions for base addresses, unions, and structures.
Kojto	100:cbbeb26dbd92	1369	@{
Kojto	100:cbbeb26dbd92	1370	*/
Kojto	100:cbbeb26dbd92	1371
Kojto	100:cbbeb26dbd92	1372	/* Memory mapping of Cortex-M4 Hardware */
Kojto	100:cbbeb26dbd92	1373	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Kojto	100:cbbeb26dbd92	1374	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Kojto	100:cbbeb26dbd92	1375	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Kojto	100:cbbeb26dbd92	1376	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Kojto	100:cbbeb26dbd92	1377	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Kojto	100:cbbeb26dbd92	1378	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Kojto	100:cbbeb26dbd92	1379	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Kojto	100:cbbeb26dbd92	1380	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Kojto	100:cbbeb26dbd92	1381
Kojto	100:cbbeb26dbd92	1382	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Kojto	100:cbbeb26dbd92	1383	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Kojto	100:cbbeb26dbd92	1384	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Kojto	100:cbbeb26dbd92	1385	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Kojto	100:cbbeb26dbd92	1386	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Kojto	100:cbbeb26dbd92	1387	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Kojto	100:cbbeb26dbd92	1388	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Kojto	100:cbbeb26dbd92	1389	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Kojto	100:cbbeb26dbd92	1390
Kojto	100:cbbeb26dbd92	1391	#if (__MPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	1392	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Kojto	100:cbbeb26dbd92	1393	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Kojto	100:cbbeb26dbd92	1394	#endif
Kojto	100:cbbeb26dbd92	1395
Kojto	100:cbbeb26dbd92	1396	#if (__FPU_PRESENT == 1)
Kojto	100:cbbeb26dbd92	1397	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
Kojto	100:cbbeb26dbd92	1398	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
Kojto	100:cbbeb26dbd92	1399	#endif
Kojto	100:cbbeb26dbd92	1400
Kojto	100:cbbeb26dbd92	1401	/@} /
Kojto	100:cbbeb26dbd92	1402
Kojto	100:cbbeb26dbd92	1403
Kojto	100:cbbeb26dbd92	1404
Kojto	100:cbbeb26dbd92	1405	/*******************************************************************************
Kojto	100:cbbeb26dbd92	1406	* Hardware Abstraction Layer
Kojto	100:cbbeb26dbd92	1407	Core Function Interface contains:
Kojto	100:cbbeb26dbd92	1408	- Core NVIC Functions
Kojto	100:cbbeb26dbd92	1409	- Core SysTick Functions
Kojto	100:cbbeb26dbd92	1410	- Core Debug Functions
Kojto	100:cbbeb26dbd92	1411	- Core Register Access Functions
Kojto	100:cbbeb26dbd92	1412	******************************************************************************/
Kojto	100:cbbeb26dbd92	1413	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto	100:cbbeb26dbd92	1414	*/
Kojto	100:cbbeb26dbd92	1415
Kojto	100:cbbeb26dbd92	1416
Kojto	100:cbbeb26dbd92	1417
Kojto	100:cbbeb26dbd92	1418	/* ########################## NVIC functions #################################### */
Kojto	100:cbbeb26dbd92	1419	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	100:cbbeb26dbd92	1420	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto	100:cbbeb26dbd92	1421	\brief Functions that manage interrupts and exceptions via the NVIC.
Kojto	100:cbbeb26dbd92	1422	@{
Kojto	100:cbbeb26dbd92	1423	*/
Kojto	100:cbbeb26dbd92	1424
Kojto	100:cbbeb26dbd92	1425	/** \brief Set Priority Grouping
Kojto	100:cbbeb26dbd92	1426
Kojto	100:cbbeb26dbd92	1427	The function sets the priority grouping field using the required unlock sequence.
Kojto	100:cbbeb26dbd92	1428	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto	100:cbbeb26dbd92	1429	Only values from 0..7 are used.
Kojto	100:cbbeb26dbd92	1430	In case of a conflict between priority grouping and available
Kojto	100:cbbeb26dbd92	1431	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	100:cbbeb26dbd92	1432
Kojto	100:cbbeb26dbd92	1433	\param [in] PriorityGroup Priority grouping field.
Kojto	100:cbbeb26dbd92	1434	*/
Kojto	100:cbbeb26dbd92	1435	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto	100:cbbeb26dbd92	1436	{
Kojto	100:cbbeb26dbd92	1437	uint32_t reg_value;
Kojto	100:cbbeb26dbd92	1438	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
Kojto	100:cbbeb26dbd92	1439
Kojto	100:cbbeb26dbd92	1440	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	100:cbbeb26dbd92	1441	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
Kojto	100:cbbeb26dbd92	1442	reg_value = (reg_value \|
Kojto	100:cbbeb26dbd92	1443	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	100:cbbeb26dbd92	1444	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
Kojto	100:cbbeb26dbd92	1445	SCB->AIRCR = reg_value;
Kojto	100:cbbeb26dbd92	1446	}
Kojto	100:cbbeb26dbd92	1447
Kojto	100:cbbeb26dbd92	1448
Kojto	100:cbbeb26dbd92	1449	/** \brief Get Priority Grouping
Kojto	100:cbbeb26dbd92	1450
Kojto	100:cbbeb26dbd92	1451	The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto	100:cbbeb26dbd92	1452
Kojto	100:cbbeb26dbd92	1453	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto	100:cbbeb26dbd92	1454	*/
Kojto	100:cbbeb26dbd92	1455	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto	100:cbbeb26dbd92	1456	{
Kojto	100:cbbeb26dbd92	1457	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
Kojto	100:cbbeb26dbd92	1458	}
Kojto	100:cbbeb26dbd92	1459
Kojto	100:cbbeb26dbd92	1460
Kojto	100:cbbeb26dbd92	1461	/** \brief Enable External Interrupt
Kojto	100:cbbeb26dbd92	1462
Kojto	100:cbbeb26dbd92	1463	The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto	100:cbbeb26dbd92	1464
Kojto	100:cbbeb26dbd92	1465	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	100:cbbeb26dbd92	1466	*/
Kojto	100:cbbeb26dbd92	1467	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto	100:cbbeb26dbd92	1468	{
Kojto	100:cbbeb26dbd92	1469	/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
Kojto	100:cbbeb26dbd92	1470	NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
Kojto	100:cbbeb26dbd92	1471	}
Kojto	100:cbbeb26dbd92	1472
Kojto	100:cbbeb26dbd92	1473
Kojto	100:cbbeb26dbd92	1474	/** \brief Disable External Interrupt
Kojto	100:cbbeb26dbd92	1475
Kojto	100:cbbeb26dbd92	1476	The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto	100:cbbeb26dbd92	1477
Kojto	100:cbbeb26dbd92	1478	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	100:cbbeb26dbd92	1479	*/
Kojto	100:cbbeb26dbd92	1480	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto	100:cbbeb26dbd92	1481	{
Kojto	100:cbbeb26dbd92	1482	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
Kojto	100:cbbeb26dbd92	1483	}
Kojto	100:cbbeb26dbd92	1484
Kojto	100:cbbeb26dbd92	1485
Kojto	100:cbbeb26dbd92	1486	/** \brief Get Pending Interrupt
Kojto	100:cbbeb26dbd92	1487
Kojto	100:cbbeb26dbd92	1488	The function reads the pending register in the NVIC and returns the pending bit
Kojto	100:cbbeb26dbd92	1489	for the specified interrupt.
Kojto	100:cbbeb26dbd92	1490
Kojto	100:cbbeb26dbd92	1491	\param [in] IRQn Interrupt number.
Kojto	100:cbbeb26dbd92	1492
Kojto	100:cbbeb26dbd92	1493	\return 0 Interrupt status is not pending.
Kojto	100:cbbeb26dbd92	1494	\return 1 Interrupt status is pending.
Kojto	100:cbbeb26dbd92	1495	*/
Kojto	100:cbbeb26dbd92	1496	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto	100:cbbeb26dbd92	1497	{
Kojto	100:cbbeb26dbd92	1498	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
Kojto	100:cbbeb26dbd92	1499	}
Kojto	100:cbbeb26dbd92	1500
Kojto	100:cbbeb26dbd92	1501
Kojto	100:cbbeb26dbd92	1502	/** \brief Set Pending Interrupt
Kojto	100:cbbeb26dbd92	1503
Kojto	100:cbbeb26dbd92	1504	The function sets the pending bit of an external interrupt.
Kojto	100:cbbeb26dbd92	1505
Kojto	100:cbbeb26dbd92	1506	\param [in] IRQn Interrupt number. Value cannot be negative.
Kojto	100:cbbeb26dbd92	1507	*/
Kojto	100:cbbeb26dbd92	1508	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto	100:cbbeb26dbd92	1509	{
Kojto	100:cbbeb26dbd92	1510	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
Kojto	100:cbbeb26dbd92	1511	}
Kojto	100:cbbeb26dbd92	1512
Kojto	100:cbbeb26dbd92	1513
Kojto	100:cbbeb26dbd92	1514	/** \brief Clear Pending Interrupt
Kojto	100:cbbeb26dbd92	1515
Kojto	100:cbbeb26dbd92	1516	The function clears the pending bit of an external interrupt.
Kojto	100:cbbeb26dbd92	1517
Kojto	100:cbbeb26dbd92	1518	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	100:cbbeb26dbd92	1519	*/
Kojto	100:cbbeb26dbd92	1520	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto	100:cbbeb26dbd92	1521	{
Kojto	100:cbbeb26dbd92	1522	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto	100:cbbeb26dbd92	1523	}
Kojto	100:cbbeb26dbd92	1524
Kojto	100:cbbeb26dbd92	1525
Kojto	100:cbbeb26dbd92	1526	/** \brief Get Active Interrupt
Kojto	100:cbbeb26dbd92	1527
Kojto	100:cbbeb26dbd92	1528	The function reads the active register in NVIC and returns the active bit.
Kojto	100:cbbeb26dbd92	1529
Kojto	100:cbbeb26dbd92	1530	\param [in] IRQn Interrupt number.
Kojto	100:cbbeb26dbd92	1531
Kojto	100:cbbeb26dbd92	1532	\return 0 Interrupt status is not active.
Kojto	100:cbbeb26dbd92	1533	\return 1 Interrupt status is active.
Kojto	100:cbbeb26dbd92	1534	*/
Kojto	100:cbbeb26dbd92	1535	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto	100:cbbeb26dbd92	1536	{
Kojto	100:cbbeb26dbd92	1537	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
Kojto	100:cbbeb26dbd92	1538	}
Kojto	100:cbbeb26dbd92	1539
Kojto	100:cbbeb26dbd92	1540
Kojto	100:cbbeb26dbd92	1541	/** \brief Set Interrupt Priority
Kojto	100:cbbeb26dbd92	1542
Kojto	100:cbbeb26dbd92	1543	The function sets the priority of an interrupt.
Kojto	100:cbbeb26dbd92	1544
Kojto	100:cbbeb26dbd92	1545	\note The priority cannot be set for every core interrupt.
Kojto	100:cbbeb26dbd92	1546
Kojto	100:cbbeb26dbd92	1547	\param [in] IRQn Interrupt number.
Kojto	100:cbbeb26dbd92	1548	\param [in] priority Priority to set.
Kojto	100:cbbeb26dbd92	1549	*/
Kojto	100:cbbeb26dbd92	1550	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto	100:cbbeb26dbd92	1551	{
Kojto	100:cbbeb26dbd92	1552	if(IRQn < 0) {
Kojto	100:cbbeb26dbd92	1553	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
Kojto	100:cbbeb26dbd92	1554	else {
Kojto	100:cbbeb26dbd92	1555	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
Kojto	100:cbbeb26dbd92	1556	}
Kojto	100:cbbeb26dbd92	1557
Kojto	100:cbbeb26dbd92	1558
Kojto	100:cbbeb26dbd92	1559	/** \brief Get Interrupt Priority
Kojto	100:cbbeb26dbd92	1560
Kojto	100:cbbeb26dbd92	1561	The function reads the priority of an interrupt. The interrupt
Kojto	100:cbbeb26dbd92	1562	number can be positive to specify an external (device specific)
Kojto	100:cbbeb26dbd92	1563	interrupt, or negative to specify an internal (core) interrupt.
Kojto	100:cbbeb26dbd92	1564
Kojto	100:cbbeb26dbd92	1565
Kojto	100:cbbeb26dbd92	1566	\param [in] IRQn Interrupt number.
Kojto	100:cbbeb26dbd92	1567	\return Interrupt Priority. Value is aligned automatically to the implemented
Kojto	100:cbbeb26dbd92	1568	priority bits of the microcontroller.
Kojto	100:cbbeb26dbd92	1569	*/
Kojto	100:cbbeb26dbd92	1570	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto	100:cbbeb26dbd92	1571	{
Kojto	100:cbbeb26dbd92	1572
Kojto	100:cbbeb26dbd92	1573	if(IRQn < 0) {
Kojto	100:cbbeb26dbd92	1574	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
Kojto	100:cbbeb26dbd92	1575	else {
Kojto	100:cbbeb26dbd92	1576	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto	100:cbbeb26dbd92	1577	}
Kojto	100:cbbeb26dbd92	1578
Kojto	100:cbbeb26dbd92	1579
Kojto	100:cbbeb26dbd92	1580	/** \brief Encode Priority
Kojto	100:cbbeb26dbd92	1581
Kojto	100:cbbeb26dbd92	1582	The function encodes the priority for an interrupt with the given priority group,
Kojto	100:cbbeb26dbd92	1583	preemptive priority value, and subpriority value.
Kojto	100:cbbeb26dbd92	1584	In case of a conflict between priority grouping and available
Kojto	100:cbbeb26dbd92	1585	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
Kojto	100:cbbeb26dbd92	1586
Kojto	100:cbbeb26dbd92	1587	\param [in] PriorityGroup Used priority group.
Kojto	100:cbbeb26dbd92	1588	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto	100:cbbeb26dbd92	1589	\param [in] SubPriority Subpriority value (starting from 0).
Kojto	100:cbbeb26dbd92	1590	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto	100:cbbeb26dbd92	1591	*/
Kojto	100:cbbeb26dbd92	1592	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto	100:cbbeb26dbd92	1593	{
Kojto	100:cbbeb26dbd92	1594	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kojto	100:cbbeb26dbd92	1595	uint32_t PreemptPriorityBits;
Kojto	100:cbbeb26dbd92	1596	uint32_t SubPriorityBits;
Kojto	100:cbbeb26dbd92	1597
Kojto	100:cbbeb26dbd92	1598	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kojto	100:cbbeb26dbd92	1599	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kojto	100:cbbeb26dbd92	1600
Kojto	100:cbbeb26dbd92	1601	return (
Kojto	100:cbbeb26dbd92	1602	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
Kojto	100:cbbeb26dbd92	1603	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
Kojto	100:cbbeb26dbd92	1604	);
Kojto	100:cbbeb26dbd92	1605	}
Kojto	100:cbbeb26dbd92	1606
Kojto	100:cbbeb26dbd92	1607
Kojto	100:cbbeb26dbd92	1608	/** \brief Decode Priority
Kojto	100:cbbeb26dbd92	1609
Kojto	100:cbbeb26dbd92	1610	The function decodes an interrupt priority value with a given priority group to
Kojto	100:cbbeb26dbd92	1611	preemptive priority value and subpriority value.
Kojto	100:cbbeb26dbd92	1612	In case of a conflict between priority grouping and available
Kojto	100:cbbeb26dbd92	1613	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Kojto	100:cbbeb26dbd92	1614
Kojto	100:cbbeb26dbd92	1615	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto	100:cbbeb26dbd92	1616	\param [in] PriorityGroup Used priority group.
Kojto	100:cbbeb26dbd92	1617	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto	100:cbbeb26dbd92	1618	\param [out] pSubPriority Subpriority value (starting from 0).
Kojto	100:cbbeb26dbd92	1619	*/
Kojto	100:cbbeb26dbd92	1620	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto	100:cbbeb26dbd92	1621	{
Kojto	100:cbbeb26dbd92	1622	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kojto	100:cbbeb26dbd92	1623	uint32_t PreemptPriorityBits;
Kojto	100:cbbeb26dbd92	1624	uint32_t SubPriorityBits;
Kojto	100:cbbeb26dbd92	1625
Kojto	100:cbbeb26dbd92	1626	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kojto	100:cbbeb26dbd92	1627	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kojto	100:cbbeb26dbd92	1628
Kojto	100:cbbeb26dbd92	1629	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
Kojto	100:cbbeb26dbd92	1630	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
Kojto	100:cbbeb26dbd92	1631	}
Kojto	100:cbbeb26dbd92	1632
Kojto	100:cbbeb26dbd92	1633
Kojto	100:cbbeb26dbd92	1634	/** \brief System Reset
Kojto	100:cbbeb26dbd92	1635
Kojto	100:cbbeb26dbd92	1636	The function initiates a system reset request to reset the MCU.
Kojto	100:cbbeb26dbd92	1637	*/
Kojto	100:cbbeb26dbd92	1638	__STATIC_INLINE void NVIC_SystemReset(void)
Kojto	100:cbbeb26dbd92	1639	{
Kojto	100:cbbeb26dbd92	1640	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	100:cbbeb26dbd92	1641	buffered write are completed before reset */
Kojto	100:cbbeb26dbd92	1642	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	100:cbbeb26dbd92	1643	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	100:cbbeb26dbd92	1644	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
Kojto	100:cbbeb26dbd92	1645	__DSB(); /* Ensure completion of memory access */
Kojto	100:cbbeb26dbd92	1646	while(1); /* wait until reset */
Kojto	100:cbbeb26dbd92	1647	}
Kojto	100:cbbeb26dbd92	1648
Kojto	100:cbbeb26dbd92	1649	/@} end of CMSIS_Core_NVICFunctions /
Kojto	100:cbbeb26dbd92	1650
Kojto	100:cbbeb26dbd92	1651
Kojto	100:cbbeb26dbd92	1652
Kojto	100:cbbeb26dbd92	1653	/* ################################## SysTick function ############################################ */
Kojto	100:cbbeb26dbd92	1654	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	100:cbbeb26dbd92	1655	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto	100:cbbeb26dbd92	1656	\brief Functions that configure the System.
Kojto	100:cbbeb26dbd92	1657	@{
Kojto	100:cbbeb26dbd92	1658	*/
Kojto	100:cbbeb26dbd92	1659
Kojto	100:cbbeb26dbd92	1660	#if (__Vendor_SysTickConfig == 0)
Kojto	100:cbbeb26dbd92	1661
Kojto	100:cbbeb26dbd92	1662	/** \brief System Tick Configuration
Kojto	100:cbbeb26dbd92	1663
Kojto	100:cbbeb26dbd92	1664	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto	100:cbbeb26dbd92	1665	Counter is in free running mode to generate periodic interrupts.
Kojto	100:cbbeb26dbd92	1666
Kojto	100:cbbeb26dbd92	1667	\param [in] ticks Number of ticks between two interrupts.
Kojto	100:cbbeb26dbd92	1668
Kojto	100:cbbeb26dbd92	1669	\return 0 Function succeeded.
Kojto	100:cbbeb26dbd92	1670	\return 1 Function failed.
Kojto	100:cbbeb26dbd92	1671
Kojto	100:cbbeb26dbd92	1672	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	100:cbbeb26dbd92	1673	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	100:cbbeb26dbd92	1674	must contain a vendor-specific implementation of this function.
Kojto	100:cbbeb26dbd92	1675
Kojto	100:cbbeb26dbd92	1676	*/
Kojto	100:cbbeb26dbd92	1677	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto	100:cbbeb26dbd92	1678	{
Kojto	100:cbbeb26dbd92	1679	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto	100:cbbeb26dbd92	1680
Kojto	100:cbbeb26dbd92	1681	SysTick->LOAD = ticks - 1; /* set reload register */
Kojto	100:cbbeb26dbd92	1682	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto	100:cbbeb26dbd92	1683	SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto	100:cbbeb26dbd92	1684	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	100:cbbeb26dbd92	1685	SysTick_CTRL_TICKINT_Msk \|
Kojto	100:cbbeb26dbd92	1686	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	100:cbbeb26dbd92	1687	return (0); /* Function successful */
Kojto	100:cbbeb26dbd92	1688	}
Kojto	100:cbbeb26dbd92	1689
Kojto	100:cbbeb26dbd92	1690	#endif
Kojto	100:cbbeb26dbd92	1691
Kojto	100:cbbeb26dbd92	1692	/@} end of CMSIS_Core_SysTickFunctions /
Kojto	100:cbbeb26dbd92	1693
Kojto	100:cbbeb26dbd92	1694
Kojto	100:cbbeb26dbd92	1695
Kojto	100:cbbeb26dbd92	1696	/* ##################################### Debug In/Output function ########################################### */
Kojto	100:cbbeb26dbd92	1697	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	100:cbbeb26dbd92	1698	\defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto	100:cbbeb26dbd92	1699	\brief Functions that access the ITM debug interface.
Kojto	100:cbbeb26dbd92	1700	@{
Kojto	100:cbbeb26dbd92	1701	*/
Kojto	100:cbbeb26dbd92	1702
Kojto	100:cbbeb26dbd92	1703	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Kojto	100:cbbeb26dbd92	1704	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Kojto	100:cbbeb26dbd92	1705
Kojto	100:cbbeb26dbd92	1706
Kojto	100:cbbeb26dbd92	1707	/** \brief ITM Send Character
Kojto	100:cbbeb26dbd92	1708
Kojto	100:cbbeb26dbd92	1709	The function transmits a character via the ITM channel 0, and
Kojto	100:cbbeb26dbd92	1710	\li Just returns when no debugger is connected that has booked the output.
Kojto	100:cbbeb26dbd92	1711	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto	100:cbbeb26dbd92	1712
Kojto	100:cbbeb26dbd92	1713	\param [in] ch Character to transmit.
Kojto	100:cbbeb26dbd92	1714
Kojto	100:cbbeb26dbd92	1715	\returns Character to transmit.
Kojto	100:cbbeb26dbd92	1716	*/
Kojto	100:cbbeb26dbd92	1717	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto	100:cbbeb26dbd92	1718	{
Kojto	100:cbbeb26dbd92	1719	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
Kojto	100:cbbeb26dbd92	1720	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
Kojto	100:cbbeb26dbd92	1721	{
Kojto	100:cbbeb26dbd92	1722	while (ITM->PORT[0].u32 == 0);
Kojto	100:cbbeb26dbd92	1723	ITM->PORT[0].u8 = (uint8_t) ch;
Kojto	100:cbbeb26dbd92	1724	}
Kojto	100:cbbeb26dbd92	1725	return (ch);
Kojto	100:cbbeb26dbd92	1726	}
Kojto	100:cbbeb26dbd92	1727
Kojto	100:cbbeb26dbd92	1728
Kojto	100:cbbeb26dbd92	1729	/** \brief ITM Receive Character
Kojto	100:cbbeb26dbd92	1730
Kojto	100:cbbeb26dbd92	1731	The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto	100:cbbeb26dbd92	1732
Kojto	100:cbbeb26dbd92	1733	\return Received character.
Kojto	100:cbbeb26dbd92	1734	\return -1 No character pending.
Kojto	100:cbbeb26dbd92	1735	*/
Kojto	100:cbbeb26dbd92	1736	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto	100:cbbeb26dbd92	1737	int32_t ch = -1; /* no character available */
Kojto	100:cbbeb26dbd92	1738
Kojto	100:cbbeb26dbd92	1739	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto	100:cbbeb26dbd92	1740	ch = ITM_RxBuffer;
Kojto	100:cbbeb26dbd92	1741	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto	100:cbbeb26dbd92	1742	}
Kojto	100:cbbeb26dbd92	1743
Kojto	100:cbbeb26dbd92	1744	return (ch);
Kojto	100:cbbeb26dbd92	1745	}
Kojto	100:cbbeb26dbd92	1746
Kojto	100:cbbeb26dbd92	1747
Kojto	100:cbbeb26dbd92	1748	/** \brief ITM Check Character
Kojto	100:cbbeb26dbd92	1749
Kojto	100:cbbeb26dbd92	1750	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto	100:cbbeb26dbd92	1751
Kojto	100:cbbeb26dbd92	1752	\return 0 No character available.
Kojto	100:cbbeb26dbd92	1753	\return 1 Character available.
Kojto	100:cbbeb26dbd92	1754	*/
Kojto	100:cbbeb26dbd92	1755	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto	100:cbbeb26dbd92	1756
Kojto	100:cbbeb26dbd92	1757	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto	100:cbbeb26dbd92	1758	return (0); /* no character available */
Kojto	100:cbbeb26dbd92	1759	} else {
Kojto	100:cbbeb26dbd92	1760	return (1); /* character available */
Kojto	100:cbbeb26dbd92	1761	}
Kojto	100:cbbeb26dbd92	1762	}
Kojto	100:cbbeb26dbd92	1763
Kojto	100:cbbeb26dbd92	1764	/@} end of CMSIS_core_DebugFunctions /
Kojto	100:cbbeb26dbd92	1765
Kojto	100:cbbeb26dbd92	1766	#endif /* __CORE_CM4_H_DEPENDANT */
Kojto	100:cbbeb26dbd92	1767
Kojto	100:cbbeb26dbd92	1768	#endif /* __CMSIS_GENERIC */
Kojto	100:cbbeb26dbd92	1769
Kojto	100:cbbeb26dbd92	1770	#ifdef __cplusplus
Kojto	100:cbbeb26dbd92	1771	}
Kojto	100:cbbeb26dbd92	1772	#endif