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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
Kojto
Date:
Wed May 27 08:07:35 2015 +0100
Revision:
100:cbbeb26dbd92
Child:
110:165afa46840b
Release 100 of the mbed library

Changes:
- new target: DISCOF334C8
- API: Ticker/Timer bugfix with constness
- Silabs: RTC, PWM, Serial clocks bufixes
- Renesas: i2c bugfix
- Maxim: 326000 - pin definitions for v2, spi freq fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 100:cbbeb26dbd92 1 /**************************************************************************//**
Kojto 100:cbbeb26dbd92 2 * @file core_cm0.h
Kojto 100:cbbeb26dbd92 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 100:cbbeb26dbd92 4 * @version V3.20
Kojto 100:cbbeb26dbd92 5 * @date 25. February 2013
Kojto 100:cbbeb26dbd92 6 *
Kojto 100:cbbeb26dbd92 7 * @note
Kojto 100:cbbeb26dbd92 8 *
Kojto 100:cbbeb26dbd92 9 ******************************************************************************/
Kojto 100:cbbeb26dbd92 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 100:cbbeb26dbd92 11
Kojto 100:cbbeb26dbd92 12 All rights reserved.
Kojto 100:cbbeb26dbd92 13 Redistribution and use in source and binary forms, with or without
Kojto 100:cbbeb26dbd92 14 modification, are permitted provided that the following conditions are met:
Kojto 100:cbbeb26dbd92 15 - Redistributions of source code must retain the above copyright
Kojto 100:cbbeb26dbd92 16 notice, this list of conditions and the following disclaimer.
Kojto 100:cbbeb26dbd92 17 - Redistributions in binary form must reproduce the above copyright
Kojto 100:cbbeb26dbd92 18 notice, this list of conditions and the following disclaimer in the
Kojto 100:cbbeb26dbd92 19 documentation and/or other materials provided with the distribution.
Kojto 100:cbbeb26dbd92 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 100:cbbeb26dbd92 21 to endorse or promote products derived from this software without
Kojto 100:cbbeb26dbd92 22 specific prior written permission.
Kojto 100:cbbeb26dbd92 23 *
Kojto 100:cbbeb26dbd92 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 100:cbbeb26dbd92 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 100:cbbeb26dbd92 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 100:cbbeb26dbd92 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 100:cbbeb26dbd92 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 100:cbbeb26dbd92 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 100:cbbeb26dbd92 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 100:cbbeb26dbd92 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 100:cbbeb26dbd92 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 100:cbbeb26dbd92 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 100:cbbeb26dbd92 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 100:cbbeb26dbd92 35 ---------------------------------------------------------------------------*/
Kojto 100:cbbeb26dbd92 36
Kojto 100:cbbeb26dbd92 37
Kojto 100:cbbeb26dbd92 38 #if defined ( __ICCARM__ )
Kojto 100:cbbeb26dbd92 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 100:cbbeb26dbd92 40 #endif
Kojto 100:cbbeb26dbd92 41
Kojto 100:cbbeb26dbd92 42 #ifdef __cplusplus
Kojto 100:cbbeb26dbd92 43 extern "C" {
Kojto 100:cbbeb26dbd92 44 #endif
Kojto 100:cbbeb26dbd92 45
Kojto 100:cbbeb26dbd92 46 #ifndef __CORE_CM0_H_GENERIC
Kojto 100:cbbeb26dbd92 47 #define __CORE_CM0_H_GENERIC
Kojto 100:cbbeb26dbd92 48
Kojto 100:cbbeb26dbd92 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 100:cbbeb26dbd92 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 100:cbbeb26dbd92 51
Kojto 100:cbbeb26dbd92 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 100:cbbeb26dbd92 53 Function definitions in header files are used to allow 'inlining'.
Kojto 100:cbbeb26dbd92 54
Kojto 100:cbbeb26dbd92 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 100:cbbeb26dbd92 56 Unions are used for effective representation of core registers.
Kojto 100:cbbeb26dbd92 57
Kojto 100:cbbeb26dbd92 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 100:cbbeb26dbd92 59 Function-like macros are used to allow more efficient code.
Kojto 100:cbbeb26dbd92 60 */
Kojto 100:cbbeb26dbd92 61
Kojto 100:cbbeb26dbd92 62
Kojto 100:cbbeb26dbd92 63 /*******************************************************************************
Kojto 100:cbbeb26dbd92 64 * CMSIS definitions
Kojto 100:cbbeb26dbd92 65 ******************************************************************************/
Kojto 100:cbbeb26dbd92 66 /** \ingroup Cortex_M0
Kojto 100:cbbeb26dbd92 67 @{
Kojto 100:cbbeb26dbd92 68 */
Kojto 100:cbbeb26dbd92 69
Kojto 100:cbbeb26dbd92 70 /* CMSIS CM0 definitions */
Kojto 100:cbbeb26dbd92 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 100:cbbeb26dbd92 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 100:cbbeb26dbd92 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
Kojto 100:cbbeb26dbd92 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 100:cbbeb26dbd92 75
Kojto 100:cbbeb26dbd92 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 100:cbbeb26dbd92 77
Kojto 100:cbbeb26dbd92 78
Kojto 100:cbbeb26dbd92 79 #if defined ( __CC_ARM )
Kojto 100:cbbeb26dbd92 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 100:cbbeb26dbd92 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 100:cbbeb26dbd92 82 #define __STATIC_INLINE static __inline
Kojto 100:cbbeb26dbd92 83
Kojto 100:cbbeb26dbd92 84 #elif defined ( __ICCARM__ )
Kojto 100:cbbeb26dbd92 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 100:cbbeb26dbd92 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 100:cbbeb26dbd92 87 #define __STATIC_INLINE static inline
Kojto 100:cbbeb26dbd92 88
Kojto 100:cbbeb26dbd92 89 #elif defined ( __GNUC__ )
Kojto 100:cbbeb26dbd92 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 100:cbbeb26dbd92 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 100:cbbeb26dbd92 92 #define __STATIC_INLINE static inline
Kojto 100:cbbeb26dbd92 93
Kojto 100:cbbeb26dbd92 94 #elif defined ( __TASKING__ )
Kojto 100:cbbeb26dbd92 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 100:cbbeb26dbd92 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 100:cbbeb26dbd92 97 #define __STATIC_INLINE static inline
Kojto 100:cbbeb26dbd92 98
Kojto 100:cbbeb26dbd92 99 #endif
Kojto 100:cbbeb26dbd92 100
Kojto 100:cbbeb26dbd92 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 100:cbbeb26dbd92 102 */
Kojto 100:cbbeb26dbd92 103 #define __FPU_USED 0
Kojto 100:cbbeb26dbd92 104
Kojto 100:cbbeb26dbd92 105 #if defined ( __CC_ARM )
Kojto 100:cbbeb26dbd92 106 #if defined __TARGET_FPU_VFP
Kojto 100:cbbeb26dbd92 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 100:cbbeb26dbd92 108 #endif
Kojto 100:cbbeb26dbd92 109
Kojto 100:cbbeb26dbd92 110 #elif defined ( __ICCARM__ )
Kojto 100:cbbeb26dbd92 111 #if defined __ARMVFP__
Kojto 100:cbbeb26dbd92 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 100:cbbeb26dbd92 113 #endif
Kojto 100:cbbeb26dbd92 114
Kojto 100:cbbeb26dbd92 115 #elif defined ( __GNUC__ )
Kojto 100:cbbeb26dbd92 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 100:cbbeb26dbd92 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 100:cbbeb26dbd92 118 #endif
Kojto 100:cbbeb26dbd92 119
Kojto 100:cbbeb26dbd92 120 #elif defined ( __TASKING__ )
Kojto 100:cbbeb26dbd92 121 #if defined __FPU_VFP__
Kojto 100:cbbeb26dbd92 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 100:cbbeb26dbd92 123 #endif
Kojto 100:cbbeb26dbd92 124 #endif
Kojto 100:cbbeb26dbd92 125
Kojto 100:cbbeb26dbd92 126 #include <stdint.h> /* standard types definitions */
Kojto 100:cbbeb26dbd92 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 100:cbbeb26dbd92 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 100:cbbeb26dbd92 129
Kojto 100:cbbeb26dbd92 130 #endif /* __CORE_CM0_H_GENERIC */
Kojto 100:cbbeb26dbd92 131
Kojto 100:cbbeb26dbd92 132 #ifndef __CMSIS_GENERIC
Kojto 100:cbbeb26dbd92 133
Kojto 100:cbbeb26dbd92 134 #ifndef __CORE_CM0_H_DEPENDANT
Kojto 100:cbbeb26dbd92 135 #define __CORE_CM0_H_DEPENDANT
Kojto 100:cbbeb26dbd92 136
Kojto 100:cbbeb26dbd92 137 /* check device defines and use defaults */
Kojto 100:cbbeb26dbd92 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 100:cbbeb26dbd92 139 #ifndef __CM0_REV
Kojto 100:cbbeb26dbd92 140 #define __CM0_REV 0x0000
Kojto 100:cbbeb26dbd92 141 #warning "__CM0_REV not defined in device header file; using default!"
Kojto 100:cbbeb26dbd92 142 #endif
Kojto 100:cbbeb26dbd92 143
Kojto 100:cbbeb26dbd92 144 #ifndef __NVIC_PRIO_BITS
Kojto 100:cbbeb26dbd92 145 #define __NVIC_PRIO_BITS 2
Kojto 100:cbbeb26dbd92 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 100:cbbeb26dbd92 147 #endif
Kojto 100:cbbeb26dbd92 148
Kojto 100:cbbeb26dbd92 149 #ifndef __Vendor_SysTickConfig
Kojto 100:cbbeb26dbd92 150 #define __Vendor_SysTickConfig 0
Kojto 100:cbbeb26dbd92 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 100:cbbeb26dbd92 152 #endif
Kojto 100:cbbeb26dbd92 153 #endif
Kojto 100:cbbeb26dbd92 154
Kojto 100:cbbeb26dbd92 155 /* IO definitions (access restrictions to peripheral registers) */
Kojto 100:cbbeb26dbd92 156 /**
Kojto 100:cbbeb26dbd92 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 100:cbbeb26dbd92 158
Kojto 100:cbbeb26dbd92 159 <strong>IO Type Qualifiers</strong> are used
Kojto 100:cbbeb26dbd92 160 \li to specify the access to peripheral variables.
Kojto 100:cbbeb26dbd92 161 \li for automatic generation of peripheral register debug information.
Kojto 100:cbbeb26dbd92 162 */
Kojto 100:cbbeb26dbd92 163 #ifdef __cplusplus
Kojto 100:cbbeb26dbd92 164 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 100:cbbeb26dbd92 165 #else
Kojto 100:cbbeb26dbd92 166 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 100:cbbeb26dbd92 167 #endif
Kojto 100:cbbeb26dbd92 168 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 100:cbbeb26dbd92 169 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 100:cbbeb26dbd92 170
Kojto 100:cbbeb26dbd92 171 /*@} end of group Cortex_M0 */
Kojto 100:cbbeb26dbd92 172
Kojto 100:cbbeb26dbd92 173
Kojto 100:cbbeb26dbd92 174
Kojto 100:cbbeb26dbd92 175 /*******************************************************************************
Kojto 100:cbbeb26dbd92 176 * Register Abstraction
Kojto 100:cbbeb26dbd92 177 Core Register contain:
Kojto 100:cbbeb26dbd92 178 - Core Register
Kojto 100:cbbeb26dbd92 179 - Core NVIC Register
Kojto 100:cbbeb26dbd92 180 - Core SCB Register
Kojto 100:cbbeb26dbd92 181 - Core SysTick Register
Kojto 100:cbbeb26dbd92 182 ******************************************************************************/
Kojto 100:cbbeb26dbd92 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 100:cbbeb26dbd92 184 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 100:cbbeb26dbd92 185 */
Kojto 100:cbbeb26dbd92 186
Kojto 100:cbbeb26dbd92 187 /** \ingroup CMSIS_core_register
Kojto 100:cbbeb26dbd92 188 \defgroup CMSIS_CORE Status and Control Registers
Kojto 100:cbbeb26dbd92 189 \brief Core Register type definitions.
Kojto 100:cbbeb26dbd92 190 @{
Kojto 100:cbbeb26dbd92 191 */
Kojto 100:cbbeb26dbd92 192
Kojto 100:cbbeb26dbd92 193 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 100:cbbeb26dbd92 194 */
Kojto 100:cbbeb26dbd92 195 typedef union
Kojto 100:cbbeb26dbd92 196 {
Kojto 100:cbbeb26dbd92 197 struct
Kojto 100:cbbeb26dbd92 198 {
Kojto 100:cbbeb26dbd92 199 #if (__CORTEX_M != 0x04)
Kojto 100:cbbeb26dbd92 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 100:cbbeb26dbd92 201 #else
Kojto 100:cbbeb26dbd92 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 100:cbbeb26dbd92 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 100:cbbeb26dbd92 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 100:cbbeb26dbd92 205 #endif
Kojto 100:cbbeb26dbd92 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 100:cbbeb26dbd92 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 100:cbbeb26dbd92 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 100:cbbeb26dbd92 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 100:cbbeb26dbd92 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 100:cbbeb26dbd92 211 } b; /*!< Structure used for bit access */
Kojto 100:cbbeb26dbd92 212 uint32_t w; /*!< Type used for word access */
Kojto 100:cbbeb26dbd92 213 } APSR_Type;
Kojto 100:cbbeb26dbd92 214
Kojto 100:cbbeb26dbd92 215
Kojto 100:cbbeb26dbd92 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 100:cbbeb26dbd92 217 */
Kojto 100:cbbeb26dbd92 218 typedef union
Kojto 100:cbbeb26dbd92 219 {
Kojto 100:cbbeb26dbd92 220 struct
Kojto 100:cbbeb26dbd92 221 {
Kojto 100:cbbeb26dbd92 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 100:cbbeb26dbd92 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 100:cbbeb26dbd92 224 } b; /*!< Structure used for bit access */
Kojto 100:cbbeb26dbd92 225 uint32_t w; /*!< Type used for word access */
Kojto 100:cbbeb26dbd92 226 } IPSR_Type;
Kojto 100:cbbeb26dbd92 227
Kojto 100:cbbeb26dbd92 228
Kojto 100:cbbeb26dbd92 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 100:cbbeb26dbd92 230 */
Kojto 100:cbbeb26dbd92 231 typedef union
Kojto 100:cbbeb26dbd92 232 {
Kojto 100:cbbeb26dbd92 233 struct
Kojto 100:cbbeb26dbd92 234 {
Kojto 100:cbbeb26dbd92 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 100:cbbeb26dbd92 236 #if (__CORTEX_M != 0x04)
Kojto 100:cbbeb26dbd92 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 100:cbbeb26dbd92 238 #else
Kojto 100:cbbeb26dbd92 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 100:cbbeb26dbd92 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 100:cbbeb26dbd92 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 100:cbbeb26dbd92 242 #endif
Kojto 100:cbbeb26dbd92 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 100:cbbeb26dbd92 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 100:cbbeb26dbd92 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 100:cbbeb26dbd92 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 100:cbbeb26dbd92 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 100:cbbeb26dbd92 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 100:cbbeb26dbd92 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 100:cbbeb26dbd92 250 } b; /*!< Structure used for bit access */
Kojto 100:cbbeb26dbd92 251 uint32_t w; /*!< Type used for word access */
Kojto 100:cbbeb26dbd92 252 } xPSR_Type;
Kojto 100:cbbeb26dbd92 253
Kojto 100:cbbeb26dbd92 254
Kojto 100:cbbeb26dbd92 255 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 100:cbbeb26dbd92 256 */
Kojto 100:cbbeb26dbd92 257 typedef union
Kojto 100:cbbeb26dbd92 258 {
Kojto 100:cbbeb26dbd92 259 struct
Kojto 100:cbbeb26dbd92 260 {
Kojto 100:cbbeb26dbd92 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 100:cbbeb26dbd92 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 100:cbbeb26dbd92 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 100:cbbeb26dbd92 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 100:cbbeb26dbd92 265 } b; /*!< Structure used for bit access */
Kojto 100:cbbeb26dbd92 266 uint32_t w; /*!< Type used for word access */
Kojto 100:cbbeb26dbd92 267 } CONTROL_Type;
Kojto 100:cbbeb26dbd92 268
Kojto 100:cbbeb26dbd92 269 /*@} end of group CMSIS_CORE */
Kojto 100:cbbeb26dbd92 270
Kojto 100:cbbeb26dbd92 271
Kojto 100:cbbeb26dbd92 272 /** \ingroup CMSIS_core_register
Kojto 100:cbbeb26dbd92 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 100:cbbeb26dbd92 274 \brief Type definitions for the NVIC Registers
Kojto 100:cbbeb26dbd92 275 @{
Kojto 100:cbbeb26dbd92 276 */
Kojto 100:cbbeb26dbd92 277
Kojto 100:cbbeb26dbd92 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 100:cbbeb26dbd92 279 */
Kojto 100:cbbeb26dbd92 280 typedef struct
Kojto 100:cbbeb26dbd92 281 {
Kojto 100:cbbeb26dbd92 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 100:cbbeb26dbd92 283 uint32_t RESERVED0[31];
Kojto 100:cbbeb26dbd92 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 100:cbbeb26dbd92 285 uint32_t RSERVED1[31];
Kojto 100:cbbeb26dbd92 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 100:cbbeb26dbd92 287 uint32_t RESERVED2[31];
Kojto 100:cbbeb26dbd92 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 100:cbbeb26dbd92 289 uint32_t RESERVED3[31];
Kojto 100:cbbeb26dbd92 290 uint32_t RESERVED4[64];
Kojto 100:cbbeb26dbd92 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 100:cbbeb26dbd92 292 } NVIC_Type;
Kojto 100:cbbeb26dbd92 293
Kojto 100:cbbeb26dbd92 294 /*@} end of group CMSIS_NVIC */
Kojto 100:cbbeb26dbd92 295
Kojto 100:cbbeb26dbd92 296
Kojto 100:cbbeb26dbd92 297 /** \ingroup CMSIS_core_register
Kojto 100:cbbeb26dbd92 298 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 100:cbbeb26dbd92 299 \brief Type definitions for the System Control Block Registers
Kojto 100:cbbeb26dbd92 300 @{
Kojto 100:cbbeb26dbd92 301 */
Kojto 100:cbbeb26dbd92 302
Kojto 100:cbbeb26dbd92 303 /** \brief Structure type to access the System Control Block (SCB).
Kojto 100:cbbeb26dbd92 304 */
Kojto 100:cbbeb26dbd92 305 typedef struct
Kojto 100:cbbeb26dbd92 306 {
Kojto 100:cbbeb26dbd92 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 100:cbbeb26dbd92 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 100:cbbeb26dbd92 309 uint32_t RESERVED0;
Kojto 100:cbbeb26dbd92 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 100:cbbeb26dbd92 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 100:cbbeb26dbd92 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 100:cbbeb26dbd92 313 uint32_t RESERVED1;
Kojto 100:cbbeb26dbd92 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 100:cbbeb26dbd92 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 100:cbbeb26dbd92 316 } SCB_Type;
Kojto 100:cbbeb26dbd92 317
Kojto 100:cbbeb26dbd92 318 /* SCB CPUID Register Definitions */
Kojto 100:cbbeb26dbd92 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 100:cbbeb26dbd92 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 100:cbbeb26dbd92 321
Kojto 100:cbbeb26dbd92 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 100:cbbeb26dbd92 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 100:cbbeb26dbd92 324
Kojto 100:cbbeb26dbd92 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 100:cbbeb26dbd92 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 100:cbbeb26dbd92 327
Kojto 100:cbbeb26dbd92 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 100:cbbeb26dbd92 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 100:cbbeb26dbd92 330
Kojto 100:cbbeb26dbd92 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 100:cbbeb26dbd92 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 100:cbbeb26dbd92 333
Kojto 100:cbbeb26dbd92 334 /* SCB Interrupt Control State Register Definitions */
Kojto 100:cbbeb26dbd92 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 100:cbbeb26dbd92 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 100:cbbeb26dbd92 337
Kojto 100:cbbeb26dbd92 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 100:cbbeb26dbd92 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 100:cbbeb26dbd92 340
Kojto 100:cbbeb26dbd92 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 100:cbbeb26dbd92 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 100:cbbeb26dbd92 343
Kojto 100:cbbeb26dbd92 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 100:cbbeb26dbd92 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 100:cbbeb26dbd92 346
Kojto 100:cbbeb26dbd92 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 100:cbbeb26dbd92 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 100:cbbeb26dbd92 349
Kojto 100:cbbeb26dbd92 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 100:cbbeb26dbd92 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 100:cbbeb26dbd92 352
Kojto 100:cbbeb26dbd92 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 100:cbbeb26dbd92 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 100:cbbeb26dbd92 355
Kojto 100:cbbeb26dbd92 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 100:cbbeb26dbd92 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 100:cbbeb26dbd92 358
Kojto 100:cbbeb26dbd92 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 100:cbbeb26dbd92 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 100:cbbeb26dbd92 361
Kojto 100:cbbeb26dbd92 362 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 100:cbbeb26dbd92 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 100:cbbeb26dbd92 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 100:cbbeb26dbd92 365
Kojto 100:cbbeb26dbd92 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 100:cbbeb26dbd92 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 100:cbbeb26dbd92 368
Kojto 100:cbbeb26dbd92 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 100:cbbeb26dbd92 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 100:cbbeb26dbd92 371
Kojto 100:cbbeb26dbd92 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 100:cbbeb26dbd92 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 100:cbbeb26dbd92 374
Kojto 100:cbbeb26dbd92 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 100:cbbeb26dbd92 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 100:cbbeb26dbd92 377
Kojto 100:cbbeb26dbd92 378 /* SCB System Control Register Definitions */
Kojto 100:cbbeb26dbd92 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 100:cbbeb26dbd92 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 100:cbbeb26dbd92 381
Kojto 100:cbbeb26dbd92 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 100:cbbeb26dbd92 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 100:cbbeb26dbd92 384
Kojto 100:cbbeb26dbd92 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 100:cbbeb26dbd92 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 100:cbbeb26dbd92 387
Kojto 100:cbbeb26dbd92 388 /* SCB Configuration Control Register Definitions */
Kojto 100:cbbeb26dbd92 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 100:cbbeb26dbd92 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 100:cbbeb26dbd92 391
Kojto 100:cbbeb26dbd92 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 100:cbbeb26dbd92 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 100:cbbeb26dbd92 394
Kojto 100:cbbeb26dbd92 395 /* SCB System Handler Control and State Register Definitions */
Kojto 100:cbbeb26dbd92 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 100:cbbeb26dbd92 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 100:cbbeb26dbd92 398
Kojto 100:cbbeb26dbd92 399 /*@} end of group CMSIS_SCB */
Kojto 100:cbbeb26dbd92 400
Kojto 100:cbbeb26dbd92 401
Kojto 100:cbbeb26dbd92 402 /** \ingroup CMSIS_core_register
Kojto 100:cbbeb26dbd92 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 100:cbbeb26dbd92 404 \brief Type definitions for the System Timer Registers.
Kojto 100:cbbeb26dbd92 405 @{
Kojto 100:cbbeb26dbd92 406 */
Kojto 100:cbbeb26dbd92 407
Kojto 100:cbbeb26dbd92 408 /** \brief Structure type to access the System Timer (SysTick).
Kojto 100:cbbeb26dbd92 409 */
Kojto 100:cbbeb26dbd92 410 typedef struct
Kojto 100:cbbeb26dbd92 411 {
Kojto 100:cbbeb26dbd92 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 100:cbbeb26dbd92 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 100:cbbeb26dbd92 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 100:cbbeb26dbd92 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 100:cbbeb26dbd92 416 } SysTick_Type;
Kojto 100:cbbeb26dbd92 417
Kojto 100:cbbeb26dbd92 418 /* SysTick Control / Status Register Definitions */
Kojto 100:cbbeb26dbd92 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 100:cbbeb26dbd92 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 100:cbbeb26dbd92 421
Kojto 100:cbbeb26dbd92 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 100:cbbeb26dbd92 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 100:cbbeb26dbd92 424
Kojto 100:cbbeb26dbd92 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 100:cbbeb26dbd92 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 100:cbbeb26dbd92 427
Kojto 100:cbbeb26dbd92 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 100:cbbeb26dbd92 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 100:cbbeb26dbd92 430
Kojto 100:cbbeb26dbd92 431 /* SysTick Reload Register Definitions */
Kojto 100:cbbeb26dbd92 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 100:cbbeb26dbd92 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 100:cbbeb26dbd92 434
Kojto 100:cbbeb26dbd92 435 /* SysTick Current Register Definitions */
Kojto 100:cbbeb26dbd92 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 100:cbbeb26dbd92 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 100:cbbeb26dbd92 438
Kojto 100:cbbeb26dbd92 439 /* SysTick Calibration Register Definitions */
Kojto 100:cbbeb26dbd92 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 100:cbbeb26dbd92 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 100:cbbeb26dbd92 442
Kojto 100:cbbeb26dbd92 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 100:cbbeb26dbd92 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 100:cbbeb26dbd92 445
Kojto 100:cbbeb26dbd92 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 100:cbbeb26dbd92 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 100:cbbeb26dbd92 448
Kojto 100:cbbeb26dbd92 449 /*@} end of group CMSIS_SysTick */
Kojto 100:cbbeb26dbd92 450
Kojto 100:cbbeb26dbd92 451
Kojto 100:cbbeb26dbd92 452 /** \ingroup CMSIS_core_register
Kojto 100:cbbeb26dbd92 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 100:cbbeb26dbd92 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 100:cbbeb26dbd92 455 are only accessible over DAP and not via processor. Therefore
Kojto 100:cbbeb26dbd92 456 they are not covered by the Cortex-M0 header file.
Kojto 100:cbbeb26dbd92 457 @{
Kojto 100:cbbeb26dbd92 458 */
Kojto 100:cbbeb26dbd92 459 /*@} end of group CMSIS_CoreDebug */
Kojto 100:cbbeb26dbd92 460
Kojto 100:cbbeb26dbd92 461
Kojto 100:cbbeb26dbd92 462 /** \ingroup CMSIS_core_register
Kojto 100:cbbeb26dbd92 463 \defgroup CMSIS_core_base Core Definitions
Kojto 100:cbbeb26dbd92 464 \brief Definitions for base addresses, unions, and structures.
Kojto 100:cbbeb26dbd92 465 @{
Kojto 100:cbbeb26dbd92 466 */
Kojto 100:cbbeb26dbd92 467
Kojto 100:cbbeb26dbd92 468 /* Memory mapping of Cortex-M0 Hardware */
Kojto 100:cbbeb26dbd92 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 100:cbbeb26dbd92 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 100:cbbeb26dbd92 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 100:cbbeb26dbd92 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 100:cbbeb26dbd92 473
Kojto 100:cbbeb26dbd92 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 100:cbbeb26dbd92 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 100:cbbeb26dbd92 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 100:cbbeb26dbd92 477
Kojto 100:cbbeb26dbd92 478
Kojto 100:cbbeb26dbd92 479 /*@} */
Kojto 100:cbbeb26dbd92 480
Kojto 100:cbbeb26dbd92 481
Kojto 100:cbbeb26dbd92 482
Kojto 100:cbbeb26dbd92 483 /*******************************************************************************
Kojto 100:cbbeb26dbd92 484 * Hardware Abstraction Layer
Kojto 100:cbbeb26dbd92 485 Core Function Interface contains:
Kojto 100:cbbeb26dbd92 486 - Core NVIC Functions
Kojto 100:cbbeb26dbd92 487 - Core SysTick Functions
Kojto 100:cbbeb26dbd92 488 - Core Register Access Functions
Kojto 100:cbbeb26dbd92 489 ******************************************************************************/
Kojto 100:cbbeb26dbd92 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 100:cbbeb26dbd92 491 */
Kojto 100:cbbeb26dbd92 492
Kojto 100:cbbeb26dbd92 493
Kojto 100:cbbeb26dbd92 494
Kojto 100:cbbeb26dbd92 495 /* ########################## NVIC functions #################################### */
Kojto 100:cbbeb26dbd92 496 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 100:cbbeb26dbd92 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 100:cbbeb26dbd92 498 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 100:cbbeb26dbd92 499 @{
Kojto 100:cbbeb26dbd92 500 */
Kojto 100:cbbeb26dbd92 501
Kojto 100:cbbeb26dbd92 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 100:cbbeb26dbd92 503 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 100:cbbeb26dbd92 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 100:cbbeb26dbd92 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 100:cbbeb26dbd92 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 100:cbbeb26dbd92 507
Kojto 100:cbbeb26dbd92 508
Kojto 100:cbbeb26dbd92 509 /** \brief Enable External Interrupt
Kojto 100:cbbeb26dbd92 510
Kojto 100:cbbeb26dbd92 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 100:cbbeb26dbd92 512
Kojto 100:cbbeb26dbd92 513 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 100:cbbeb26dbd92 514 */
Kojto 100:cbbeb26dbd92 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 100:cbbeb26dbd92 516 {
Kojto 100:cbbeb26dbd92 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 100:cbbeb26dbd92 518 }
Kojto 100:cbbeb26dbd92 519
Kojto 100:cbbeb26dbd92 520
Kojto 100:cbbeb26dbd92 521 /** \brief Disable External Interrupt
Kojto 100:cbbeb26dbd92 522
Kojto 100:cbbeb26dbd92 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 100:cbbeb26dbd92 524
Kojto 100:cbbeb26dbd92 525 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 100:cbbeb26dbd92 526 */
Kojto 100:cbbeb26dbd92 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 100:cbbeb26dbd92 528 {
Kojto 100:cbbeb26dbd92 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 100:cbbeb26dbd92 530 }
Kojto 100:cbbeb26dbd92 531
Kojto 100:cbbeb26dbd92 532
Kojto 100:cbbeb26dbd92 533 /** \brief Get Pending Interrupt
Kojto 100:cbbeb26dbd92 534
Kojto 100:cbbeb26dbd92 535 The function reads the pending register in the NVIC and returns the pending bit
Kojto 100:cbbeb26dbd92 536 for the specified interrupt.
Kojto 100:cbbeb26dbd92 537
Kojto 100:cbbeb26dbd92 538 \param [in] IRQn Interrupt number.
Kojto 100:cbbeb26dbd92 539
Kojto 100:cbbeb26dbd92 540 \return 0 Interrupt status is not pending.
Kojto 100:cbbeb26dbd92 541 \return 1 Interrupt status is pending.
Kojto 100:cbbeb26dbd92 542 */
Kojto 100:cbbeb26dbd92 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 100:cbbeb26dbd92 544 {
Kojto 100:cbbeb26dbd92 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 100:cbbeb26dbd92 546 }
Kojto 100:cbbeb26dbd92 547
Kojto 100:cbbeb26dbd92 548
Kojto 100:cbbeb26dbd92 549 /** \brief Set Pending Interrupt
Kojto 100:cbbeb26dbd92 550
Kojto 100:cbbeb26dbd92 551 The function sets the pending bit of an external interrupt.
Kojto 100:cbbeb26dbd92 552
Kojto 100:cbbeb26dbd92 553 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 100:cbbeb26dbd92 554 */
Kojto 100:cbbeb26dbd92 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 100:cbbeb26dbd92 556 {
Kojto 100:cbbeb26dbd92 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 100:cbbeb26dbd92 558 }
Kojto 100:cbbeb26dbd92 559
Kojto 100:cbbeb26dbd92 560
Kojto 100:cbbeb26dbd92 561 /** \brief Clear Pending Interrupt
Kojto 100:cbbeb26dbd92 562
Kojto 100:cbbeb26dbd92 563 The function clears the pending bit of an external interrupt.
Kojto 100:cbbeb26dbd92 564
Kojto 100:cbbeb26dbd92 565 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 100:cbbeb26dbd92 566 */
Kojto 100:cbbeb26dbd92 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 100:cbbeb26dbd92 568 {
Kojto 100:cbbeb26dbd92 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 100:cbbeb26dbd92 570 }
Kojto 100:cbbeb26dbd92 571
Kojto 100:cbbeb26dbd92 572
Kojto 100:cbbeb26dbd92 573 /** \brief Set Interrupt Priority
Kojto 100:cbbeb26dbd92 574
Kojto 100:cbbeb26dbd92 575 The function sets the priority of an interrupt.
Kojto 100:cbbeb26dbd92 576
Kojto 100:cbbeb26dbd92 577 \note The priority cannot be set for every core interrupt.
Kojto 100:cbbeb26dbd92 578
Kojto 100:cbbeb26dbd92 579 \param [in] IRQn Interrupt number.
Kojto 100:cbbeb26dbd92 580 \param [in] priority Priority to set.
Kojto 100:cbbeb26dbd92 581 */
Kojto 100:cbbeb26dbd92 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 100:cbbeb26dbd92 583 {
Kojto 100:cbbeb26dbd92 584 if(IRQn < 0) {
Kojto 100:cbbeb26dbd92 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 100:cbbeb26dbd92 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 100:cbbeb26dbd92 587 else {
Kojto 100:cbbeb26dbd92 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 100:cbbeb26dbd92 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 100:cbbeb26dbd92 590 }
Kojto 100:cbbeb26dbd92 591
Kojto 100:cbbeb26dbd92 592
Kojto 100:cbbeb26dbd92 593 /** \brief Get Interrupt Priority
Kojto 100:cbbeb26dbd92 594
Kojto 100:cbbeb26dbd92 595 The function reads the priority of an interrupt. The interrupt
Kojto 100:cbbeb26dbd92 596 number can be positive to specify an external (device specific)
Kojto 100:cbbeb26dbd92 597 interrupt, or negative to specify an internal (core) interrupt.
Kojto 100:cbbeb26dbd92 598
Kojto 100:cbbeb26dbd92 599
Kojto 100:cbbeb26dbd92 600 \param [in] IRQn Interrupt number.
Kojto 100:cbbeb26dbd92 601 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 100:cbbeb26dbd92 602 priority bits of the microcontroller.
Kojto 100:cbbeb26dbd92 603 */
Kojto 100:cbbeb26dbd92 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 100:cbbeb26dbd92 605 {
Kojto 100:cbbeb26dbd92 606
Kojto 100:cbbeb26dbd92 607 if(IRQn < 0) {
Kojto 100:cbbeb26dbd92 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 100:cbbeb26dbd92 609 else {
Kojto 100:cbbeb26dbd92 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 100:cbbeb26dbd92 611 }
Kojto 100:cbbeb26dbd92 612
Kojto 100:cbbeb26dbd92 613
Kojto 100:cbbeb26dbd92 614 /** \brief System Reset
Kojto 100:cbbeb26dbd92 615
Kojto 100:cbbeb26dbd92 616 The function initiates a system reset request to reset the MCU.
Kojto 100:cbbeb26dbd92 617 */
Kojto 100:cbbeb26dbd92 618 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 100:cbbeb26dbd92 619 {
Kojto 100:cbbeb26dbd92 620 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 100:cbbeb26dbd92 621 buffered write are completed before reset */
Kojto 100:cbbeb26dbd92 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 100:cbbeb26dbd92 623 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 100:cbbeb26dbd92 624 __DSB(); /* Ensure completion of memory access */
Kojto 100:cbbeb26dbd92 625 while(1); /* wait until reset */
Kojto 100:cbbeb26dbd92 626 }
Kojto 100:cbbeb26dbd92 627
Kojto 100:cbbeb26dbd92 628 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 100:cbbeb26dbd92 629
Kojto 100:cbbeb26dbd92 630
Kojto 100:cbbeb26dbd92 631
Kojto 100:cbbeb26dbd92 632 /* ################################## SysTick function ############################################ */
Kojto 100:cbbeb26dbd92 633 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 100:cbbeb26dbd92 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 100:cbbeb26dbd92 635 \brief Functions that configure the System.
Kojto 100:cbbeb26dbd92 636 @{
Kojto 100:cbbeb26dbd92 637 */
Kojto 100:cbbeb26dbd92 638
Kojto 100:cbbeb26dbd92 639 #if (__Vendor_SysTickConfig == 0)
Kojto 100:cbbeb26dbd92 640
Kojto 100:cbbeb26dbd92 641 /** \brief System Tick Configuration
Kojto 100:cbbeb26dbd92 642
Kojto 100:cbbeb26dbd92 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 100:cbbeb26dbd92 644 Counter is in free running mode to generate periodic interrupts.
Kojto 100:cbbeb26dbd92 645
Kojto 100:cbbeb26dbd92 646 \param [in] ticks Number of ticks between two interrupts.
Kojto 100:cbbeb26dbd92 647
Kojto 100:cbbeb26dbd92 648 \return 0 Function succeeded.
Kojto 100:cbbeb26dbd92 649 \return 1 Function failed.
Kojto 100:cbbeb26dbd92 650
Kojto 100:cbbeb26dbd92 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 100:cbbeb26dbd92 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 100:cbbeb26dbd92 653 must contain a vendor-specific implementation of this function.
Kojto 100:cbbeb26dbd92 654
Kojto 100:cbbeb26dbd92 655 */
Kojto 100:cbbeb26dbd92 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 100:cbbeb26dbd92 657 {
Kojto 100:cbbeb26dbd92 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 100:cbbeb26dbd92 659
Kojto 100:cbbeb26dbd92 660 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 100:cbbeb26dbd92 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 100:cbbeb26dbd92 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 100:cbbeb26dbd92 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 100:cbbeb26dbd92 664 SysTick_CTRL_TICKINT_Msk |
Kojto 100:cbbeb26dbd92 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 100:cbbeb26dbd92 666 return (0); /* Function successful */
Kojto 100:cbbeb26dbd92 667 }
Kojto 100:cbbeb26dbd92 668
Kojto 100:cbbeb26dbd92 669 #endif
Kojto 100:cbbeb26dbd92 670
Kojto 100:cbbeb26dbd92 671 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 100:cbbeb26dbd92 672
Kojto 100:cbbeb26dbd92 673
Kojto 100:cbbeb26dbd92 674
Kojto 100:cbbeb26dbd92 675
Kojto 100:cbbeb26dbd92 676 #endif /* __CORE_CM0_H_DEPENDANT */
Kojto 100:cbbeb26dbd92 677
Kojto 100:cbbeb26dbd92 678 #endif /* __CMSIS_GENERIC */
Kojto 100:cbbeb26dbd92 679
Kojto 100:cbbeb26dbd92 680 #ifdef __cplusplus
Kojto 100:cbbeb26dbd92 681 }
Kojto 100:cbbeb26dbd92 682 #endif