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mbed 2

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TARGET_NRF51_MICROBIT/core_cm3.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Child:
110:165afa46840b
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 104:b9ad9a133dc7 1 /**************************************************************************//**
Kojto 104:b9ad9a133dc7 2 * @file core_cm3.h
Kojto 104:b9ad9a133dc7 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kojto 104:b9ad9a133dc7 4 * @version V3.20
Kojto 104:b9ad9a133dc7 5 * @date 25. February 2013
Kojto 104:b9ad9a133dc7 6 *
Kojto 104:b9ad9a133dc7 7 * @note
Kojto 104:b9ad9a133dc7 8 *
Kojto 104:b9ad9a133dc7 9 ******************************************************************************/
Kojto 104:b9ad9a133dc7 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 104:b9ad9a133dc7 11
Kojto 104:b9ad9a133dc7 12 All rights reserved.
Kojto 104:b9ad9a133dc7 13 Redistribution and use in source and binary forms, with or without
Kojto 104:b9ad9a133dc7 14 modification, are permitted provided that the following conditions are met:
Kojto 104:b9ad9a133dc7 15 - Redistributions of source code must retain the above copyright
Kojto 104:b9ad9a133dc7 16 notice, this list of conditions and the following disclaimer.
Kojto 104:b9ad9a133dc7 17 - Redistributions in binary form must reproduce the above copyright
Kojto 104:b9ad9a133dc7 18 notice, this list of conditions and the following disclaimer in the
Kojto 104:b9ad9a133dc7 19 documentation and/or other materials provided with the distribution.
Kojto 104:b9ad9a133dc7 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 104:b9ad9a133dc7 21 to endorse or promote products derived from this software without
Kojto 104:b9ad9a133dc7 22 specific prior written permission.
Kojto 104:b9ad9a133dc7 23 *
Kojto 104:b9ad9a133dc7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 104:b9ad9a133dc7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 104:b9ad9a133dc7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 104:b9ad9a133dc7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 104:b9ad9a133dc7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 104:b9ad9a133dc7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 104:b9ad9a133dc7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 104:b9ad9a133dc7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 104:b9ad9a133dc7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 104:b9ad9a133dc7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 104:b9ad9a133dc7 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 104:b9ad9a133dc7 35 ---------------------------------------------------------------------------*/
Kojto 104:b9ad9a133dc7 36
Kojto 104:b9ad9a133dc7 37
Kojto 104:b9ad9a133dc7 38 #if defined ( __ICCARM__ )
Kojto 104:b9ad9a133dc7 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 104:b9ad9a133dc7 40 #endif
Kojto 104:b9ad9a133dc7 41
Kojto 104:b9ad9a133dc7 42 #ifdef __cplusplus
Kojto 104:b9ad9a133dc7 43 extern "C" {
Kojto 104:b9ad9a133dc7 44 #endif
Kojto 104:b9ad9a133dc7 45
Kojto 104:b9ad9a133dc7 46 #ifndef __CORE_CM3_H_GENERIC
Kojto 104:b9ad9a133dc7 47 #define __CORE_CM3_H_GENERIC
Kojto 104:b9ad9a133dc7 48
Kojto 104:b9ad9a133dc7 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 104:b9ad9a133dc7 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 104:b9ad9a133dc7 51
Kojto 104:b9ad9a133dc7 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 104:b9ad9a133dc7 53 Function definitions in header files are used to allow 'inlining'.
Kojto 104:b9ad9a133dc7 54
Kojto 104:b9ad9a133dc7 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 104:b9ad9a133dc7 56 Unions are used for effective representation of core registers.
Kojto 104:b9ad9a133dc7 57
Kojto 104:b9ad9a133dc7 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 104:b9ad9a133dc7 59 Function-like macros are used to allow more efficient code.
Kojto 104:b9ad9a133dc7 60 */
Kojto 104:b9ad9a133dc7 61
Kojto 104:b9ad9a133dc7 62
Kojto 104:b9ad9a133dc7 63 /*******************************************************************************
Kojto 104:b9ad9a133dc7 64 * CMSIS definitions
Kojto 104:b9ad9a133dc7 65 ******************************************************************************/
Kojto 104:b9ad9a133dc7 66 /** \ingroup Cortex_M3
Kojto 104:b9ad9a133dc7 67 @{
Kojto 104:b9ad9a133dc7 68 */
Kojto 104:b9ad9a133dc7 69
Kojto 104:b9ad9a133dc7 70 /* CMSIS CM3 definitions */
Kojto 104:b9ad9a133dc7 71 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 104:b9ad9a133dc7 72 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 104:b9ad9a133dc7 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
Kojto 104:b9ad9a133dc7 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 104:b9ad9a133dc7 75
Kojto 104:b9ad9a133dc7 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
Kojto 104:b9ad9a133dc7 77
Kojto 104:b9ad9a133dc7 78
Kojto 104:b9ad9a133dc7 79 #if defined ( __CC_ARM )
Kojto 104:b9ad9a133dc7 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 104:b9ad9a133dc7 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 104:b9ad9a133dc7 82 #define __STATIC_INLINE static __inline
Kojto 104:b9ad9a133dc7 83
Kojto 104:b9ad9a133dc7 84 #elif defined ( __ICCARM__ )
Kojto 104:b9ad9a133dc7 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 104:b9ad9a133dc7 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 104:b9ad9a133dc7 87 #define __STATIC_INLINE static inline
Kojto 104:b9ad9a133dc7 88
Kojto 104:b9ad9a133dc7 89 #elif defined ( __TMS470__ )
Kojto 104:b9ad9a133dc7 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
Kojto 104:b9ad9a133dc7 91 #define __STATIC_INLINE static inline
Kojto 104:b9ad9a133dc7 92
Kojto 104:b9ad9a133dc7 93 #elif defined ( __GNUC__ )
Kojto 104:b9ad9a133dc7 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 104:b9ad9a133dc7 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 104:b9ad9a133dc7 96 #define __STATIC_INLINE static inline
Kojto 104:b9ad9a133dc7 97
Kojto 104:b9ad9a133dc7 98 #elif defined ( __TASKING__ )
Kojto 104:b9ad9a133dc7 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 104:b9ad9a133dc7 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 104:b9ad9a133dc7 101 #define __STATIC_INLINE static inline
Kojto 104:b9ad9a133dc7 102
Kojto 104:b9ad9a133dc7 103 #endif
Kojto 104:b9ad9a133dc7 104
Kojto 104:b9ad9a133dc7 105 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 104:b9ad9a133dc7 106 */
Kojto 104:b9ad9a133dc7 107 #define __FPU_USED 0
Kojto 104:b9ad9a133dc7 108
Kojto 104:b9ad9a133dc7 109 #if defined ( __CC_ARM )
Kojto 104:b9ad9a133dc7 110 #if defined __TARGET_FPU_VFP
Kojto 104:b9ad9a133dc7 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 112 #endif
Kojto 104:b9ad9a133dc7 113
Kojto 104:b9ad9a133dc7 114 #elif defined ( __ICCARM__ )
Kojto 104:b9ad9a133dc7 115 #if defined __ARMVFP__
Kojto 104:b9ad9a133dc7 116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 117 #endif
Kojto 104:b9ad9a133dc7 118
Kojto 104:b9ad9a133dc7 119 #elif defined ( __TMS470__ )
Kojto 104:b9ad9a133dc7 120 #if defined __TI__VFP_SUPPORT____
Kojto 104:b9ad9a133dc7 121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 122 #endif
Kojto 104:b9ad9a133dc7 123
Kojto 104:b9ad9a133dc7 124 #elif defined ( __GNUC__ )
Kojto 104:b9ad9a133dc7 125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 104:b9ad9a133dc7 126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 127 #endif
Kojto 104:b9ad9a133dc7 128
Kojto 104:b9ad9a133dc7 129 #elif defined ( __TASKING__ )
Kojto 104:b9ad9a133dc7 130 #if defined __FPU_VFP__
Kojto 104:b9ad9a133dc7 131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 104:b9ad9a133dc7 132 #endif
Kojto 104:b9ad9a133dc7 133 #endif
Kojto 104:b9ad9a133dc7 134
Kojto 104:b9ad9a133dc7 135 #include <stdint.h> /* standard types definitions */
Kojto 104:b9ad9a133dc7 136 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 104:b9ad9a133dc7 137 #include <core_cmFunc.h> /* Core Function Access */
Kojto 104:b9ad9a133dc7 138
Kojto 104:b9ad9a133dc7 139 #endif /* __CORE_CM3_H_GENERIC */
Kojto 104:b9ad9a133dc7 140
Kojto 104:b9ad9a133dc7 141 #ifndef __CMSIS_GENERIC
Kojto 104:b9ad9a133dc7 142
Kojto 104:b9ad9a133dc7 143 #ifndef __CORE_CM3_H_DEPENDANT
Kojto 104:b9ad9a133dc7 144 #define __CORE_CM3_H_DEPENDANT
Kojto 104:b9ad9a133dc7 145
Kojto 104:b9ad9a133dc7 146 /* check device defines and use defaults */
Kojto 104:b9ad9a133dc7 147 #if defined __CHECK_DEVICE_DEFINES
Kojto 104:b9ad9a133dc7 148 #ifndef __CM3_REV
Kojto 104:b9ad9a133dc7 149 #define __CM3_REV 0x0200
Kojto 104:b9ad9a133dc7 150 #warning "__CM3_REV not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 151 #endif
Kojto 104:b9ad9a133dc7 152
Kojto 104:b9ad9a133dc7 153 #ifndef __MPU_PRESENT
Kojto 104:b9ad9a133dc7 154 #define __MPU_PRESENT 0
Kojto 104:b9ad9a133dc7 155 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 156 #endif
Kojto 104:b9ad9a133dc7 157
Kojto 104:b9ad9a133dc7 158 #ifndef __NVIC_PRIO_BITS
Kojto 104:b9ad9a133dc7 159 #define __NVIC_PRIO_BITS 4
Kojto 104:b9ad9a133dc7 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 161 #endif
Kojto 104:b9ad9a133dc7 162
Kojto 104:b9ad9a133dc7 163 #ifndef __Vendor_SysTickConfig
Kojto 104:b9ad9a133dc7 164 #define __Vendor_SysTickConfig 0
Kojto 104:b9ad9a133dc7 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 104:b9ad9a133dc7 166 #endif
Kojto 104:b9ad9a133dc7 167 #endif
Kojto 104:b9ad9a133dc7 168
Kojto 104:b9ad9a133dc7 169 /* IO definitions (access restrictions to peripheral registers) */
Kojto 104:b9ad9a133dc7 170 /**
Kojto 104:b9ad9a133dc7 171 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 104:b9ad9a133dc7 172
Kojto 104:b9ad9a133dc7 173 <strong>IO Type Qualifiers</strong> are used
Kojto 104:b9ad9a133dc7 174 \li to specify the access to peripheral variables.
Kojto 104:b9ad9a133dc7 175 \li for automatic generation of peripheral register debug information.
Kojto 104:b9ad9a133dc7 176 */
Kojto 104:b9ad9a133dc7 177 #ifdef __cplusplus
Kojto 104:b9ad9a133dc7 178 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 104:b9ad9a133dc7 179 #else
Kojto 104:b9ad9a133dc7 180 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 104:b9ad9a133dc7 181 #endif
Kojto 104:b9ad9a133dc7 182 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 104:b9ad9a133dc7 183 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 104:b9ad9a133dc7 184
Kojto 104:b9ad9a133dc7 185 /*@} end of group Cortex_M3 */
Kojto 104:b9ad9a133dc7 186
Kojto 104:b9ad9a133dc7 187
Kojto 104:b9ad9a133dc7 188
Kojto 104:b9ad9a133dc7 189 /*******************************************************************************
Kojto 104:b9ad9a133dc7 190 * Register Abstraction
Kojto 104:b9ad9a133dc7 191 Core Register contain:
Kojto 104:b9ad9a133dc7 192 - Core Register
Kojto 104:b9ad9a133dc7 193 - Core NVIC Register
Kojto 104:b9ad9a133dc7 194 - Core SCB Register
Kojto 104:b9ad9a133dc7 195 - Core SysTick Register
Kojto 104:b9ad9a133dc7 196 - Core Debug Register
Kojto 104:b9ad9a133dc7 197 - Core MPU Register
Kojto 104:b9ad9a133dc7 198 ******************************************************************************/
Kojto 104:b9ad9a133dc7 199 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 104:b9ad9a133dc7 200 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 104:b9ad9a133dc7 201 */
Kojto 104:b9ad9a133dc7 202
Kojto 104:b9ad9a133dc7 203 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 204 \defgroup CMSIS_CORE Status and Control Registers
Kojto 104:b9ad9a133dc7 205 \brief Core Register type definitions.
Kojto 104:b9ad9a133dc7 206 @{
Kojto 104:b9ad9a133dc7 207 */
Kojto 104:b9ad9a133dc7 208
Kojto 104:b9ad9a133dc7 209 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 104:b9ad9a133dc7 210 */
Kojto 104:b9ad9a133dc7 211 typedef union
Kojto 104:b9ad9a133dc7 212 {
Kojto 104:b9ad9a133dc7 213 struct
Kojto 104:b9ad9a133dc7 214 {
Kojto 104:b9ad9a133dc7 215 #if (__CORTEX_M != 0x04)
Kojto 104:b9ad9a133dc7 216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 104:b9ad9a133dc7 217 #else
Kojto 104:b9ad9a133dc7 218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 104:b9ad9a133dc7 219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 104:b9ad9a133dc7 220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 104:b9ad9a133dc7 221 #endif
Kojto 104:b9ad9a133dc7 222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 104:b9ad9a133dc7 223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 104:b9ad9a133dc7 224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 104:b9ad9a133dc7 225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 104:b9ad9a133dc7 226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 104:b9ad9a133dc7 227 } b; /*!< Structure used for bit access */
Kojto 104:b9ad9a133dc7 228 uint32_t w; /*!< Type used for word access */
Kojto 104:b9ad9a133dc7 229 } APSR_Type;
Kojto 104:b9ad9a133dc7 230
Kojto 104:b9ad9a133dc7 231
Kojto 104:b9ad9a133dc7 232 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 104:b9ad9a133dc7 233 */
Kojto 104:b9ad9a133dc7 234 typedef union
Kojto 104:b9ad9a133dc7 235 {
Kojto 104:b9ad9a133dc7 236 struct
Kojto 104:b9ad9a133dc7 237 {
Kojto 104:b9ad9a133dc7 238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 104:b9ad9a133dc7 239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 104:b9ad9a133dc7 240 } b; /*!< Structure used for bit access */
Kojto 104:b9ad9a133dc7 241 uint32_t w; /*!< Type used for word access */
Kojto 104:b9ad9a133dc7 242 } IPSR_Type;
Kojto 104:b9ad9a133dc7 243
Kojto 104:b9ad9a133dc7 244
Kojto 104:b9ad9a133dc7 245 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 104:b9ad9a133dc7 246 */
Kojto 104:b9ad9a133dc7 247 typedef union
Kojto 104:b9ad9a133dc7 248 {
Kojto 104:b9ad9a133dc7 249 struct
Kojto 104:b9ad9a133dc7 250 {
Kojto 104:b9ad9a133dc7 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 104:b9ad9a133dc7 252 #if (__CORTEX_M != 0x04)
Kojto 104:b9ad9a133dc7 253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 104:b9ad9a133dc7 254 #else
Kojto 104:b9ad9a133dc7 255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 104:b9ad9a133dc7 256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 104:b9ad9a133dc7 257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 104:b9ad9a133dc7 258 #endif
Kojto 104:b9ad9a133dc7 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 104:b9ad9a133dc7 260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 104:b9ad9a133dc7 261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 104:b9ad9a133dc7 262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 104:b9ad9a133dc7 263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 104:b9ad9a133dc7 264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 104:b9ad9a133dc7 265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 104:b9ad9a133dc7 266 } b; /*!< Structure used for bit access */
Kojto 104:b9ad9a133dc7 267 uint32_t w; /*!< Type used for word access */
Kojto 104:b9ad9a133dc7 268 } xPSR_Type;
Kojto 104:b9ad9a133dc7 269
Kojto 104:b9ad9a133dc7 270
Kojto 104:b9ad9a133dc7 271 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 104:b9ad9a133dc7 272 */
Kojto 104:b9ad9a133dc7 273 typedef union
Kojto 104:b9ad9a133dc7 274 {
Kojto 104:b9ad9a133dc7 275 struct
Kojto 104:b9ad9a133dc7 276 {
Kojto 104:b9ad9a133dc7 277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 104:b9ad9a133dc7 278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 104:b9ad9a133dc7 279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 104:b9ad9a133dc7 280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 104:b9ad9a133dc7 281 } b; /*!< Structure used for bit access */
Kojto 104:b9ad9a133dc7 282 uint32_t w; /*!< Type used for word access */
Kojto 104:b9ad9a133dc7 283 } CONTROL_Type;
Kojto 104:b9ad9a133dc7 284
Kojto 104:b9ad9a133dc7 285 /*@} end of group CMSIS_CORE */
Kojto 104:b9ad9a133dc7 286
Kojto 104:b9ad9a133dc7 287
Kojto 104:b9ad9a133dc7 288 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 104:b9ad9a133dc7 290 \brief Type definitions for the NVIC Registers
Kojto 104:b9ad9a133dc7 291 @{
Kojto 104:b9ad9a133dc7 292 */
Kojto 104:b9ad9a133dc7 293
Kojto 104:b9ad9a133dc7 294 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 104:b9ad9a133dc7 295 */
Kojto 104:b9ad9a133dc7 296 typedef struct
Kojto 104:b9ad9a133dc7 297 {
Kojto 104:b9ad9a133dc7 298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 104:b9ad9a133dc7 299 uint32_t RESERVED0[24];
Kojto 104:b9ad9a133dc7 300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 104:b9ad9a133dc7 301 uint32_t RSERVED1[24];
Kojto 104:b9ad9a133dc7 302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 104:b9ad9a133dc7 303 uint32_t RESERVED2[24];
Kojto 104:b9ad9a133dc7 304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 104:b9ad9a133dc7 305 uint32_t RESERVED3[24];
Kojto 104:b9ad9a133dc7 306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
Kojto 104:b9ad9a133dc7 307 uint32_t RESERVED4[56];
Kojto 104:b9ad9a133dc7 308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
Kojto 104:b9ad9a133dc7 309 uint32_t RESERVED5[644];
Kojto 104:b9ad9a133dc7 310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
Kojto 104:b9ad9a133dc7 311 } NVIC_Type;
Kojto 104:b9ad9a133dc7 312
Kojto 104:b9ad9a133dc7 313 /* Software Triggered Interrupt Register Definitions */
Kojto 104:b9ad9a133dc7 314 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 104:b9ad9a133dc7 315 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
Kojto 104:b9ad9a133dc7 316
Kojto 104:b9ad9a133dc7 317 /*@} end of group CMSIS_NVIC */
Kojto 104:b9ad9a133dc7 318
Kojto 104:b9ad9a133dc7 319
Kojto 104:b9ad9a133dc7 320 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 321 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 104:b9ad9a133dc7 322 \brief Type definitions for the System Control Block Registers
Kojto 104:b9ad9a133dc7 323 @{
Kojto 104:b9ad9a133dc7 324 */
Kojto 104:b9ad9a133dc7 325
Kojto 104:b9ad9a133dc7 326 /** \brief Structure type to access the System Control Block (SCB).
Kojto 104:b9ad9a133dc7 327 */
Kojto 104:b9ad9a133dc7 328 typedef struct
Kojto 104:b9ad9a133dc7 329 {
Kojto 104:b9ad9a133dc7 330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 104:b9ad9a133dc7 331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 104:b9ad9a133dc7 332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 104:b9ad9a133dc7 333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 104:b9ad9a133dc7 334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 104:b9ad9a133dc7 335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 104:b9ad9a133dc7 336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
Kojto 104:b9ad9a133dc7 337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 104:b9ad9a133dc7 338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
Kojto 104:b9ad9a133dc7 339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
Kojto 104:b9ad9a133dc7 340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
Kojto 104:b9ad9a133dc7 341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
Kojto 104:b9ad9a133dc7 342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
Kojto 104:b9ad9a133dc7 343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
Kojto 104:b9ad9a133dc7 344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
Kojto 104:b9ad9a133dc7 345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
Kojto 104:b9ad9a133dc7 346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
Kojto 104:b9ad9a133dc7 347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
Kojto 104:b9ad9a133dc7 348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
Kojto 104:b9ad9a133dc7 349 uint32_t RESERVED0[5];
Kojto 104:b9ad9a133dc7 350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
Kojto 104:b9ad9a133dc7 351 } SCB_Type;
Kojto 104:b9ad9a133dc7 352
Kojto 104:b9ad9a133dc7 353 /* SCB CPUID Register Definitions */
Kojto 104:b9ad9a133dc7 354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 104:b9ad9a133dc7 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 104:b9ad9a133dc7 356
Kojto 104:b9ad9a133dc7 357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 104:b9ad9a133dc7 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 104:b9ad9a133dc7 359
Kojto 104:b9ad9a133dc7 360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 104:b9ad9a133dc7 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 104:b9ad9a133dc7 362
Kojto 104:b9ad9a133dc7 363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 104:b9ad9a133dc7 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 104:b9ad9a133dc7 365
Kojto 104:b9ad9a133dc7 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 104:b9ad9a133dc7 367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 104:b9ad9a133dc7 368
Kojto 104:b9ad9a133dc7 369 /* SCB Interrupt Control State Register Definitions */
Kojto 104:b9ad9a133dc7 370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 104:b9ad9a133dc7 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 104:b9ad9a133dc7 372
Kojto 104:b9ad9a133dc7 373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 104:b9ad9a133dc7 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 104:b9ad9a133dc7 375
Kojto 104:b9ad9a133dc7 376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 104:b9ad9a133dc7 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 104:b9ad9a133dc7 378
Kojto 104:b9ad9a133dc7 379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 104:b9ad9a133dc7 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 104:b9ad9a133dc7 381
Kojto 104:b9ad9a133dc7 382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 104:b9ad9a133dc7 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 104:b9ad9a133dc7 384
Kojto 104:b9ad9a133dc7 385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 104:b9ad9a133dc7 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 104:b9ad9a133dc7 387
Kojto 104:b9ad9a133dc7 388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 104:b9ad9a133dc7 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 104:b9ad9a133dc7 390
Kojto 104:b9ad9a133dc7 391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 104:b9ad9a133dc7 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 104:b9ad9a133dc7 393
Kojto 104:b9ad9a133dc7 394 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
Kojto 104:b9ad9a133dc7 395 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
Kojto 104:b9ad9a133dc7 396
Kojto 104:b9ad9a133dc7 397 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 104:b9ad9a133dc7 398 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 104:b9ad9a133dc7 399
Kojto 104:b9ad9a133dc7 400 /* SCB Vector Table Offset Register Definitions */
Kojto 104:b9ad9a133dc7 401 #if (__CM3_REV < 0x0201) /* core r2p1 */
Kojto 104:b9ad9a133dc7 402 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
Kojto 104:b9ad9a133dc7 403 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
Kojto 104:b9ad9a133dc7 404
Kojto 104:b9ad9a133dc7 405 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 104:b9ad9a133dc7 406 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 104:b9ad9a133dc7 407 #else
Kojto 104:b9ad9a133dc7 408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
Kojto 104:b9ad9a133dc7 409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 104:b9ad9a133dc7 410 #endif
Kojto 104:b9ad9a133dc7 411
Kojto 104:b9ad9a133dc7 412 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 104:b9ad9a133dc7 413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 104:b9ad9a133dc7 414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 104:b9ad9a133dc7 415
Kojto 104:b9ad9a133dc7 416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 104:b9ad9a133dc7 417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 104:b9ad9a133dc7 418
Kojto 104:b9ad9a133dc7 419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 104:b9ad9a133dc7 420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 104:b9ad9a133dc7 421
Kojto 104:b9ad9a133dc7 422 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
Kojto 104:b9ad9a133dc7 423 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
Kojto 104:b9ad9a133dc7 424
Kojto 104:b9ad9a133dc7 425 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 104:b9ad9a133dc7 426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 104:b9ad9a133dc7 427
Kojto 104:b9ad9a133dc7 428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 104:b9ad9a133dc7 429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 104:b9ad9a133dc7 430
Kojto 104:b9ad9a133dc7 431 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 104:b9ad9a133dc7 432 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
Kojto 104:b9ad9a133dc7 433
Kojto 104:b9ad9a133dc7 434 /* SCB System Control Register Definitions */
Kojto 104:b9ad9a133dc7 435 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 104:b9ad9a133dc7 436 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 104:b9ad9a133dc7 437
Kojto 104:b9ad9a133dc7 438 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 104:b9ad9a133dc7 439 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 104:b9ad9a133dc7 440
Kojto 104:b9ad9a133dc7 441 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 104:b9ad9a133dc7 442 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 104:b9ad9a133dc7 443
Kojto 104:b9ad9a133dc7 444 /* SCB Configuration Control Register Definitions */
Kojto 104:b9ad9a133dc7 445 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 104:b9ad9a133dc7 446 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 104:b9ad9a133dc7 447
Kojto 104:b9ad9a133dc7 448 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
Kojto 104:b9ad9a133dc7 449 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
Kojto 104:b9ad9a133dc7 450
Kojto 104:b9ad9a133dc7 451 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
Kojto 104:b9ad9a133dc7 452 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
Kojto 104:b9ad9a133dc7 453
Kojto 104:b9ad9a133dc7 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 104:b9ad9a133dc7 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 104:b9ad9a133dc7 456
Kojto 104:b9ad9a133dc7 457 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
Kojto 104:b9ad9a133dc7 458 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
Kojto 104:b9ad9a133dc7 459
Kojto 104:b9ad9a133dc7 460 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 104:b9ad9a133dc7 461 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
Kojto 104:b9ad9a133dc7 462
Kojto 104:b9ad9a133dc7 463 /* SCB System Handler Control and State Register Definitions */
Kojto 104:b9ad9a133dc7 464 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
Kojto 104:b9ad9a133dc7 465 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
Kojto 104:b9ad9a133dc7 466
Kojto 104:b9ad9a133dc7 467 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
Kojto 104:b9ad9a133dc7 468 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
Kojto 104:b9ad9a133dc7 469
Kojto 104:b9ad9a133dc7 470 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
Kojto 104:b9ad9a133dc7 471 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
Kojto 104:b9ad9a133dc7 472
Kojto 104:b9ad9a133dc7 473 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 104:b9ad9a133dc7 474 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 104:b9ad9a133dc7 475
Kojto 104:b9ad9a133dc7 476 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
Kojto 104:b9ad9a133dc7 477 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
Kojto 104:b9ad9a133dc7 478
Kojto 104:b9ad9a133dc7 479 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
Kojto 104:b9ad9a133dc7 480 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
Kojto 104:b9ad9a133dc7 481
Kojto 104:b9ad9a133dc7 482 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
Kojto 104:b9ad9a133dc7 483 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
Kojto 104:b9ad9a133dc7 484
Kojto 104:b9ad9a133dc7 485 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
Kojto 104:b9ad9a133dc7 486 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
Kojto 104:b9ad9a133dc7 487
Kojto 104:b9ad9a133dc7 488 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
Kojto 104:b9ad9a133dc7 489 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
Kojto 104:b9ad9a133dc7 490
Kojto 104:b9ad9a133dc7 491 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
Kojto 104:b9ad9a133dc7 492 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
Kojto 104:b9ad9a133dc7 493
Kojto 104:b9ad9a133dc7 494 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
Kojto 104:b9ad9a133dc7 495 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
Kojto 104:b9ad9a133dc7 496
Kojto 104:b9ad9a133dc7 497 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
Kojto 104:b9ad9a133dc7 498 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
Kojto 104:b9ad9a133dc7 499
Kojto 104:b9ad9a133dc7 500 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
Kojto 104:b9ad9a133dc7 501 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
Kojto 104:b9ad9a133dc7 502
Kojto 104:b9ad9a133dc7 503 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 104:b9ad9a133dc7 504 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
Kojto 104:b9ad9a133dc7 505
Kojto 104:b9ad9a133dc7 506 /* SCB Configurable Fault Status Registers Definitions */
Kojto 104:b9ad9a133dc7 507 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
Kojto 104:b9ad9a133dc7 508 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
Kojto 104:b9ad9a133dc7 509
Kojto 104:b9ad9a133dc7 510 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
Kojto 104:b9ad9a133dc7 511 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
Kojto 104:b9ad9a133dc7 512
Kojto 104:b9ad9a133dc7 513 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 104:b9ad9a133dc7 514 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
Kojto 104:b9ad9a133dc7 515
Kojto 104:b9ad9a133dc7 516 /* SCB Hard Fault Status Registers Definitions */
Kojto 104:b9ad9a133dc7 517 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
Kojto 104:b9ad9a133dc7 518 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
Kojto 104:b9ad9a133dc7 519
Kojto 104:b9ad9a133dc7 520 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
Kojto 104:b9ad9a133dc7 521 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
Kojto 104:b9ad9a133dc7 522
Kojto 104:b9ad9a133dc7 523 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
Kojto 104:b9ad9a133dc7 524 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
Kojto 104:b9ad9a133dc7 525
Kojto 104:b9ad9a133dc7 526 /* SCB Debug Fault Status Register Definitions */
Kojto 104:b9ad9a133dc7 527 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
Kojto 104:b9ad9a133dc7 528 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
Kojto 104:b9ad9a133dc7 529
Kojto 104:b9ad9a133dc7 530 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
Kojto 104:b9ad9a133dc7 531 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
Kojto 104:b9ad9a133dc7 532
Kojto 104:b9ad9a133dc7 533 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
Kojto 104:b9ad9a133dc7 534 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
Kojto 104:b9ad9a133dc7 535
Kojto 104:b9ad9a133dc7 536 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
Kojto 104:b9ad9a133dc7 537 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
Kojto 104:b9ad9a133dc7 538
Kojto 104:b9ad9a133dc7 539 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 104:b9ad9a133dc7 540 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
Kojto 104:b9ad9a133dc7 541
Kojto 104:b9ad9a133dc7 542 /*@} end of group CMSIS_SCB */
Kojto 104:b9ad9a133dc7 543
Kojto 104:b9ad9a133dc7 544
Kojto 104:b9ad9a133dc7 545 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto 104:b9ad9a133dc7 547 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 104:b9ad9a133dc7 548 @{
Kojto 104:b9ad9a133dc7 549 */
Kojto 104:b9ad9a133dc7 550
Kojto 104:b9ad9a133dc7 551 /** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 104:b9ad9a133dc7 552 */
Kojto 104:b9ad9a133dc7 553 typedef struct
Kojto 104:b9ad9a133dc7 554 {
Kojto 104:b9ad9a133dc7 555 uint32_t RESERVED0[1];
Kojto 104:b9ad9a133dc7 556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Kojto 104:b9ad9a133dc7 557 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Kojto 104:b9ad9a133dc7 558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 104:b9ad9a133dc7 559 #else
Kojto 104:b9ad9a133dc7 560 uint32_t RESERVED1[1];
Kojto 104:b9ad9a133dc7 561 #endif
Kojto 104:b9ad9a133dc7 562 } SCnSCB_Type;
Kojto 104:b9ad9a133dc7 563
Kojto 104:b9ad9a133dc7 564 /* Interrupt Controller Type Register Definitions */
Kojto 104:b9ad9a133dc7 565 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 104:b9ad9a133dc7 566 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
Kojto 104:b9ad9a133dc7 567
Kojto 104:b9ad9a133dc7 568 /* Auxiliary Control Register Definitions */
Kojto 104:b9ad9a133dc7 569
Kojto 104:b9ad9a133dc7 570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
Kojto 104:b9ad9a133dc7 571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
Kojto 104:b9ad9a133dc7 572
Kojto 104:b9ad9a133dc7 573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
Kojto 104:b9ad9a133dc7 574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
Kojto 104:b9ad9a133dc7 575
Kojto 104:b9ad9a133dc7 576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 104:b9ad9a133dc7 577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
Kojto 104:b9ad9a133dc7 578
Kojto 104:b9ad9a133dc7 579 /*@} end of group CMSIS_SCnotSCB */
Kojto 104:b9ad9a133dc7 580
Kojto 104:b9ad9a133dc7 581
Kojto 104:b9ad9a133dc7 582 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 583 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 104:b9ad9a133dc7 584 \brief Type definitions for the System Timer Registers.
Kojto 104:b9ad9a133dc7 585 @{
Kojto 104:b9ad9a133dc7 586 */
Kojto 104:b9ad9a133dc7 587
Kojto 104:b9ad9a133dc7 588 /** \brief Structure type to access the System Timer (SysTick).
Kojto 104:b9ad9a133dc7 589 */
Kojto 104:b9ad9a133dc7 590 typedef struct
Kojto 104:b9ad9a133dc7 591 {
Kojto 104:b9ad9a133dc7 592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 104:b9ad9a133dc7 593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 104:b9ad9a133dc7 594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 104:b9ad9a133dc7 595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 104:b9ad9a133dc7 596 } SysTick_Type;
Kojto 104:b9ad9a133dc7 597
Kojto 104:b9ad9a133dc7 598 /* SysTick Control / Status Register Definitions */
Kojto 104:b9ad9a133dc7 599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 104:b9ad9a133dc7 600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 104:b9ad9a133dc7 601
Kojto 104:b9ad9a133dc7 602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 104:b9ad9a133dc7 603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 104:b9ad9a133dc7 604
Kojto 104:b9ad9a133dc7 605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 104:b9ad9a133dc7 606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 104:b9ad9a133dc7 607
Kojto 104:b9ad9a133dc7 608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 104:b9ad9a133dc7 609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 104:b9ad9a133dc7 610
Kojto 104:b9ad9a133dc7 611 /* SysTick Reload Register Definitions */
Kojto 104:b9ad9a133dc7 612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 104:b9ad9a133dc7 613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 104:b9ad9a133dc7 614
Kojto 104:b9ad9a133dc7 615 /* SysTick Current Register Definitions */
Kojto 104:b9ad9a133dc7 616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 104:b9ad9a133dc7 617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 104:b9ad9a133dc7 618
Kojto 104:b9ad9a133dc7 619 /* SysTick Calibration Register Definitions */
Kojto 104:b9ad9a133dc7 620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 104:b9ad9a133dc7 621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 104:b9ad9a133dc7 622
Kojto 104:b9ad9a133dc7 623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 104:b9ad9a133dc7 624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 104:b9ad9a133dc7 625
Kojto 104:b9ad9a133dc7 626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 104:b9ad9a133dc7 627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 104:b9ad9a133dc7 628
Kojto 104:b9ad9a133dc7 629 /*@} end of group CMSIS_SysTick */
Kojto 104:b9ad9a133dc7 630
Kojto 104:b9ad9a133dc7 631
Kojto 104:b9ad9a133dc7 632 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto 104:b9ad9a133dc7 634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto 104:b9ad9a133dc7 635 @{
Kojto 104:b9ad9a133dc7 636 */
Kojto 104:b9ad9a133dc7 637
Kojto 104:b9ad9a133dc7 638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto 104:b9ad9a133dc7 639 */
Kojto 104:b9ad9a133dc7 640 typedef struct
Kojto 104:b9ad9a133dc7 641 {
Kojto 104:b9ad9a133dc7 642 __O union
Kojto 104:b9ad9a133dc7 643 {
Kojto 104:b9ad9a133dc7 644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
Kojto 104:b9ad9a133dc7 645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
Kojto 104:b9ad9a133dc7 646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
Kojto 104:b9ad9a133dc7 647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
Kojto 104:b9ad9a133dc7 648 uint32_t RESERVED0[864];
Kojto 104:b9ad9a133dc7 649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
Kojto 104:b9ad9a133dc7 650 uint32_t RESERVED1[15];
Kojto 104:b9ad9a133dc7 651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
Kojto 104:b9ad9a133dc7 652 uint32_t RESERVED2[15];
Kojto 104:b9ad9a133dc7 653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
Kojto 104:b9ad9a133dc7 654 uint32_t RESERVED3[29];
Kojto 104:b9ad9a133dc7 655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
Kojto 104:b9ad9a133dc7 656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
Kojto 104:b9ad9a133dc7 657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
Kojto 104:b9ad9a133dc7 658 uint32_t RESERVED4[43];
Kojto 104:b9ad9a133dc7 659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
Kojto 104:b9ad9a133dc7 660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
Kojto 104:b9ad9a133dc7 661 uint32_t RESERVED5[6];
Kojto 104:b9ad9a133dc7 662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
Kojto 104:b9ad9a133dc7 663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
Kojto 104:b9ad9a133dc7 664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
Kojto 104:b9ad9a133dc7 665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
Kojto 104:b9ad9a133dc7 666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
Kojto 104:b9ad9a133dc7 667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
Kojto 104:b9ad9a133dc7 668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
Kojto 104:b9ad9a133dc7 669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
Kojto 104:b9ad9a133dc7 670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
Kojto 104:b9ad9a133dc7 671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
Kojto 104:b9ad9a133dc7 672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
Kojto 104:b9ad9a133dc7 673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
Kojto 104:b9ad9a133dc7 674 } ITM_Type;
Kojto 104:b9ad9a133dc7 675
Kojto 104:b9ad9a133dc7 676 /* ITM Trace Privilege Register Definitions */
Kojto 104:b9ad9a133dc7 677 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 104:b9ad9a133dc7 678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
Kojto 104:b9ad9a133dc7 679
Kojto 104:b9ad9a133dc7 680 /* ITM Trace Control Register Definitions */
Kojto 104:b9ad9a133dc7 681 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
Kojto 104:b9ad9a133dc7 682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
Kojto 104:b9ad9a133dc7 683
Kojto 104:b9ad9a133dc7 684 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
Kojto 104:b9ad9a133dc7 685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
Kojto 104:b9ad9a133dc7 686
Kojto 104:b9ad9a133dc7 687 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
Kojto 104:b9ad9a133dc7 688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
Kojto 104:b9ad9a133dc7 689
Kojto 104:b9ad9a133dc7 690 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
Kojto 104:b9ad9a133dc7 691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
Kojto 104:b9ad9a133dc7 692
Kojto 104:b9ad9a133dc7 693 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
Kojto 104:b9ad9a133dc7 694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
Kojto 104:b9ad9a133dc7 695
Kojto 104:b9ad9a133dc7 696 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
Kojto 104:b9ad9a133dc7 697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
Kojto 104:b9ad9a133dc7 698
Kojto 104:b9ad9a133dc7 699 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
Kojto 104:b9ad9a133dc7 700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
Kojto 104:b9ad9a133dc7 701
Kojto 104:b9ad9a133dc7 702 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
Kojto 104:b9ad9a133dc7 703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
Kojto 104:b9ad9a133dc7 704
Kojto 104:b9ad9a133dc7 705 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 104:b9ad9a133dc7 706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
Kojto 104:b9ad9a133dc7 707
Kojto 104:b9ad9a133dc7 708 /* ITM Integration Write Register Definitions */
Kojto 104:b9ad9a133dc7 709 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 104:b9ad9a133dc7 710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
Kojto 104:b9ad9a133dc7 711
Kojto 104:b9ad9a133dc7 712 /* ITM Integration Read Register Definitions */
Kojto 104:b9ad9a133dc7 713 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 104:b9ad9a133dc7 714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
Kojto 104:b9ad9a133dc7 715
Kojto 104:b9ad9a133dc7 716 /* ITM Integration Mode Control Register Definitions */
Kojto 104:b9ad9a133dc7 717 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 104:b9ad9a133dc7 718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
Kojto 104:b9ad9a133dc7 719
Kojto 104:b9ad9a133dc7 720 /* ITM Lock Status Register Definitions */
Kojto 104:b9ad9a133dc7 721 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
Kojto 104:b9ad9a133dc7 722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
Kojto 104:b9ad9a133dc7 723
Kojto 104:b9ad9a133dc7 724 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
Kojto 104:b9ad9a133dc7 725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
Kojto 104:b9ad9a133dc7 726
Kojto 104:b9ad9a133dc7 727 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 104:b9ad9a133dc7 728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
Kojto 104:b9ad9a133dc7 729
Kojto 104:b9ad9a133dc7 730 /*@}*/ /* end of group CMSIS_ITM */
Kojto 104:b9ad9a133dc7 731
Kojto 104:b9ad9a133dc7 732
Kojto 104:b9ad9a133dc7 733 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto 104:b9ad9a133dc7 735 \brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto 104:b9ad9a133dc7 736 @{
Kojto 104:b9ad9a133dc7 737 */
Kojto 104:b9ad9a133dc7 738
Kojto 104:b9ad9a133dc7 739 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto 104:b9ad9a133dc7 740 */
Kojto 104:b9ad9a133dc7 741 typedef struct
Kojto 104:b9ad9a133dc7 742 {
Kojto 104:b9ad9a133dc7 743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
Kojto 104:b9ad9a133dc7 744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
Kojto 104:b9ad9a133dc7 745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
Kojto 104:b9ad9a133dc7 746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
Kojto 104:b9ad9a133dc7 747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
Kojto 104:b9ad9a133dc7 748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
Kojto 104:b9ad9a133dc7 749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
Kojto 104:b9ad9a133dc7 750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
Kojto 104:b9ad9a133dc7 751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
Kojto 104:b9ad9a133dc7 752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
Kojto 104:b9ad9a133dc7 753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
Kojto 104:b9ad9a133dc7 754 uint32_t RESERVED0[1];
Kojto 104:b9ad9a133dc7 755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
Kojto 104:b9ad9a133dc7 756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
Kojto 104:b9ad9a133dc7 757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
Kojto 104:b9ad9a133dc7 758 uint32_t RESERVED1[1];
Kojto 104:b9ad9a133dc7 759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
Kojto 104:b9ad9a133dc7 760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
Kojto 104:b9ad9a133dc7 761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
Kojto 104:b9ad9a133dc7 762 uint32_t RESERVED2[1];
Kojto 104:b9ad9a133dc7 763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
Kojto 104:b9ad9a133dc7 764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
Kojto 104:b9ad9a133dc7 765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
Kojto 104:b9ad9a133dc7 766 } DWT_Type;
Kojto 104:b9ad9a133dc7 767
Kojto 104:b9ad9a133dc7 768 /* DWT Control Register Definitions */
Kojto 104:b9ad9a133dc7 769 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
Kojto 104:b9ad9a133dc7 770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
Kojto 104:b9ad9a133dc7 771
Kojto 104:b9ad9a133dc7 772 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
Kojto 104:b9ad9a133dc7 773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
Kojto 104:b9ad9a133dc7 774
Kojto 104:b9ad9a133dc7 775 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
Kojto 104:b9ad9a133dc7 776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
Kojto 104:b9ad9a133dc7 777
Kojto 104:b9ad9a133dc7 778 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
Kojto 104:b9ad9a133dc7 779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
Kojto 104:b9ad9a133dc7 780
Kojto 104:b9ad9a133dc7 781 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
Kojto 104:b9ad9a133dc7 782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
Kojto 104:b9ad9a133dc7 783
Kojto 104:b9ad9a133dc7 784 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
Kojto 104:b9ad9a133dc7 785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
Kojto 104:b9ad9a133dc7 786
Kojto 104:b9ad9a133dc7 787 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
Kojto 104:b9ad9a133dc7 788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
Kojto 104:b9ad9a133dc7 789
Kojto 104:b9ad9a133dc7 790 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
Kojto 104:b9ad9a133dc7 791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
Kojto 104:b9ad9a133dc7 792
Kojto 104:b9ad9a133dc7 793 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
Kojto 104:b9ad9a133dc7 794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
Kojto 104:b9ad9a133dc7 795
Kojto 104:b9ad9a133dc7 796 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
Kojto 104:b9ad9a133dc7 797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
Kojto 104:b9ad9a133dc7 798
Kojto 104:b9ad9a133dc7 799 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
Kojto 104:b9ad9a133dc7 800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
Kojto 104:b9ad9a133dc7 801
Kojto 104:b9ad9a133dc7 802 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
Kojto 104:b9ad9a133dc7 803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
Kojto 104:b9ad9a133dc7 804
Kojto 104:b9ad9a133dc7 805 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
Kojto 104:b9ad9a133dc7 806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
Kojto 104:b9ad9a133dc7 807
Kojto 104:b9ad9a133dc7 808 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
Kojto 104:b9ad9a133dc7 809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
Kojto 104:b9ad9a133dc7 810
Kojto 104:b9ad9a133dc7 811 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
Kojto 104:b9ad9a133dc7 812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
Kojto 104:b9ad9a133dc7 813
Kojto 104:b9ad9a133dc7 814 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
Kojto 104:b9ad9a133dc7 815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
Kojto 104:b9ad9a133dc7 816
Kojto 104:b9ad9a133dc7 817 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
Kojto 104:b9ad9a133dc7 818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
Kojto 104:b9ad9a133dc7 819
Kojto 104:b9ad9a133dc7 820 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 104:b9ad9a133dc7 821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
Kojto 104:b9ad9a133dc7 822
Kojto 104:b9ad9a133dc7 823 /* DWT CPI Count Register Definitions */
Kojto 104:b9ad9a133dc7 824 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 104:b9ad9a133dc7 825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
Kojto 104:b9ad9a133dc7 826
Kojto 104:b9ad9a133dc7 827 /* DWT Exception Overhead Count Register Definitions */
Kojto 104:b9ad9a133dc7 828 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 104:b9ad9a133dc7 829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
Kojto 104:b9ad9a133dc7 830
Kojto 104:b9ad9a133dc7 831 /* DWT Sleep Count Register Definitions */
Kojto 104:b9ad9a133dc7 832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 104:b9ad9a133dc7 833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
Kojto 104:b9ad9a133dc7 834
Kojto 104:b9ad9a133dc7 835 /* DWT LSU Count Register Definitions */
Kojto 104:b9ad9a133dc7 836 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 104:b9ad9a133dc7 837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
Kojto 104:b9ad9a133dc7 838
Kojto 104:b9ad9a133dc7 839 /* DWT Folded-instruction Count Register Definitions */
Kojto 104:b9ad9a133dc7 840 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 104:b9ad9a133dc7 841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
Kojto 104:b9ad9a133dc7 842
Kojto 104:b9ad9a133dc7 843 /* DWT Comparator Mask Register Definitions */
Kojto 104:b9ad9a133dc7 844 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 104:b9ad9a133dc7 845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
Kojto 104:b9ad9a133dc7 846
Kojto 104:b9ad9a133dc7 847 /* DWT Comparator Function Register Definitions */
Kojto 104:b9ad9a133dc7 848 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
Kojto 104:b9ad9a133dc7 849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
Kojto 104:b9ad9a133dc7 850
Kojto 104:b9ad9a133dc7 851 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
Kojto 104:b9ad9a133dc7 852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
Kojto 104:b9ad9a133dc7 853
Kojto 104:b9ad9a133dc7 854 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
Kojto 104:b9ad9a133dc7 855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
Kojto 104:b9ad9a133dc7 856
Kojto 104:b9ad9a133dc7 857 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
Kojto 104:b9ad9a133dc7 858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
Kojto 104:b9ad9a133dc7 859
Kojto 104:b9ad9a133dc7 860 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
Kojto 104:b9ad9a133dc7 861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
Kojto 104:b9ad9a133dc7 862
Kojto 104:b9ad9a133dc7 863 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
Kojto 104:b9ad9a133dc7 864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
Kojto 104:b9ad9a133dc7 865
Kojto 104:b9ad9a133dc7 866 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
Kojto 104:b9ad9a133dc7 867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
Kojto 104:b9ad9a133dc7 868
Kojto 104:b9ad9a133dc7 869 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
Kojto 104:b9ad9a133dc7 870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
Kojto 104:b9ad9a133dc7 871
Kojto 104:b9ad9a133dc7 872 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 104:b9ad9a133dc7 873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
Kojto 104:b9ad9a133dc7 874
Kojto 104:b9ad9a133dc7 875 /*@}*/ /* end of group CMSIS_DWT */
Kojto 104:b9ad9a133dc7 876
Kojto 104:b9ad9a133dc7 877
Kojto 104:b9ad9a133dc7 878 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 879 \defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto 104:b9ad9a133dc7 880 \brief Type definitions for the Trace Port Interface (TPI)
Kojto 104:b9ad9a133dc7 881 @{
Kojto 104:b9ad9a133dc7 882 */
Kojto 104:b9ad9a133dc7 883
Kojto 104:b9ad9a133dc7 884 /** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto 104:b9ad9a133dc7 885 */
Kojto 104:b9ad9a133dc7 886 typedef struct
Kojto 104:b9ad9a133dc7 887 {
Kojto 104:b9ad9a133dc7 888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
Kojto 104:b9ad9a133dc7 889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
Kojto 104:b9ad9a133dc7 890 uint32_t RESERVED0[2];
Kojto 104:b9ad9a133dc7 891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
Kojto 104:b9ad9a133dc7 892 uint32_t RESERVED1[55];
Kojto 104:b9ad9a133dc7 893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
Kojto 104:b9ad9a133dc7 894 uint32_t RESERVED2[131];
Kojto 104:b9ad9a133dc7 895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
Kojto 104:b9ad9a133dc7 896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
Kojto 104:b9ad9a133dc7 897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
Kojto 104:b9ad9a133dc7 898 uint32_t RESERVED3[759];
Kojto 104:b9ad9a133dc7 899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
Kojto 104:b9ad9a133dc7 900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
Kojto 104:b9ad9a133dc7 901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
Kojto 104:b9ad9a133dc7 902 uint32_t RESERVED4[1];
Kojto 104:b9ad9a133dc7 903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
Kojto 104:b9ad9a133dc7 904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
Kojto 104:b9ad9a133dc7 905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
Kojto 104:b9ad9a133dc7 906 uint32_t RESERVED5[39];
Kojto 104:b9ad9a133dc7 907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
Kojto 104:b9ad9a133dc7 908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
Kojto 104:b9ad9a133dc7 909 uint32_t RESERVED7[8];
Kojto 104:b9ad9a133dc7 910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
Kojto 104:b9ad9a133dc7 911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
Kojto 104:b9ad9a133dc7 912 } TPI_Type;
Kojto 104:b9ad9a133dc7 913
Kojto 104:b9ad9a133dc7 914 /* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto 104:b9ad9a133dc7 915 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 104:b9ad9a133dc7 916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
Kojto 104:b9ad9a133dc7 917
Kojto 104:b9ad9a133dc7 918 /* TPI Selected Pin Protocol Register Definitions */
Kojto 104:b9ad9a133dc7 919 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 104:b9ad9a133dc7 920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
Kojto 104:b9ad9a133dc7 921
Kojto 104:b9ad9a133dc7 922 /* TPI Formatter and Flush Status Register Definitions */
Kojto 104:b9ad9a133dc7 923 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
Kojto 104:b9ad9a133dc7 924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
Kojto 104:b9ad9a133dc7 925
Kojto 104:b9ad9a133dc7 926 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
Kojto 104:b9ad9a133dc7 927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
Kojto 104:b9ad9a133dc7 928
Kojto 104:b9ad9a133dc7 929 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
Kojto 104:b9ad9a133dc7 930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
Kojto 104:b9ad9a133dc7 931
Kojto 104:b9ad9a133dc7 932 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 104:b9ad9a133dc7 933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
Kojto 104:b9ad9a133dc7 934
Kojto 104:b9ad9a133dc7 935 /* TPI Formatter and Flush Control Register Definitions */
Kojto 104:b9ad9a133dc7 936 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
Kojto 104:b9ad9a133dc7 937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
Kojto 104:b9ad9a133dc7 938
Kojto 104:b9ad9a133dc7 939 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
Kojto 104:b9ad9a133dc7 940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
Kojto 104:b9ad9a133dc7 941
Kojto 104:b9ad9a133dc7 942 /* TPI TRIGGER Register Definitions */
Kojto 104:b9ad9a133dc7 943 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 104:b9ad9a133dc7 944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
Kojto 104:b9ad9a133dc7 945
Kojto 104:b9ad9a133dc7 946 /* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto 104:b9ad9a133dc7 947 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
Kojto 104:b9ad9a133dc7 948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
Kojto 104:b9ad9a133dc7 949
Kojto 104:b9ad9a133dc7 950 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
Kojto 104:b9ad9a133dc7 951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
Kojto 104:b9ad9a133dc7 952
Kojto 104:b9ad9a133dc7 953 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
Kojto 104:b9ad9a133dc7 954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
Kojto 104:b9ad9a133dc7 955
Kojto 104:b9ad9a133dc7 956 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
Kojto 104:b9ad9a133dc7 957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
Kojto 104:b9ad9a133dc7 958
Kojto 104:b9ad9a133dc7 959 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
Kojto 104:b9ad9a133dc7 960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
Kojto 104:b9ad9a133dc7 961
Kojto 104:b9ad9a133dc7 962 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
Kojto 104:b9ad9a133dc7 963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
Kojto 104:b9ad9a133dc7 964
Kojto 104:b9ad9a133dc7 965 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 104:b9ad9a133dc7 966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
Kojto 104:b9ad9a133dc7 967
Kojto 104:b9ad9a133dc7 968 /* TPI ITATBCTR2 Register Definitions */
Kojto 104:b9ad9a133dc7 969 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 104:b9ad9a133dc7 970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
Kojto 104:b9ad9a133dc7 971
Kojto 104:b9ad9a133dc7 972 /* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto 104:b9ad9a133dc7 973 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
Kojto 104:b9ad9a133dc7 974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
Kojto 104:b9ad9a133dc7 975
Kojto 104:b9ad9a133dc7 976 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
Kojto 104:b9ad9a133dc7 977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
Kojto 104:b9ad9a133dc7 978
Kojto 104:b9ad9a133dc7 979 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
Kojto 104:b9ad9a133dc7 980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
Kojto 104:b9ad9a133dc7 981
Kojto 104:b9ad9a133dc7 982 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
Kojto 104:b9ad9a133dc7 983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
Kojto 104:b9ad9a133dc7 984
Kojto 104:b9ad9a133dc7 985 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
Kojto 104:b9ad9a133dc7 986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
Kojto 104:b9ad9a133dc7 987
Kojto 104:b9ad9a133dc7 988 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
Kojto 104:b9ad9a133dc7 989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
Kojto 104:b9ad9a133dc7 990
Kojto 104:b9ad9a133dc7 991 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 104:b9ad9a133dc7 992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
Kojto 104:b9ad9a133dc7 993
Kojto 104:b9ad9a133dc7 994 /* TPI ITATBCTR0 Register Definitions */
Kojto 104:b9ad9a133dc7 995 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 104:b9ad9a133dc7 996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
Kojto 104:b9ad9a133dc7 997
Kojto 104:b9ad9a133dc7 998 /* TPI Integration Mode Control Register Definitions */
Kojto 104:b9ad9a133dc7 999 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 104:b9ad9a133dc7 1000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
Kojto 104:b9ad9a133dc7 1001
Kojto 104:b9ad9a133dc7 1002 /* TPI DEVID Register Definitions */
Kojto 104:b9ad9a133dc7 1003 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
Kojto 104:b9ad9a133dc7 1004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
Kojto 104:b9ad9a133dc7 1005
Kojto 104:b9ad9a133dc7 1006 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
Kojto 104:b9ad9a133dc7 1007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
Kojto 104:b9ad9a133dc7 1008
Kojto 104:b9ad9a133dc7 1009 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
Kojto 104:b9ad9a133dc7 1010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
Kojto 104:b9ad9a133dc7 1011
Kojto 104:b9ad9a133dc7 1012 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
Kojto 104:b9ad9a133dc7 1013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
Kojto 104:b9ad9a133dc7 1014
Kojto 104:b9ad9a133dc7 1015 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
Kojto 104:b9ad9a133dc7 1016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
Kojto 104:b9ad9a133dc7 1017
Kojto 104:b9ad9a133dc7 1018 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 104:b9ad9a133dc7 1019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
Kojto 104:b9ad9a133dc7 1020
Kojto 104:b9ad9a133dc7 1021 /* TPI DEVTYPE Register Definitions */
Kojto 104:b9ad9a133dc7 1022 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 104:b9ad9a133dc7 1023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
Kojto 104:b9ad9a133dc7 1024
Kojto 104:b9ad9a133dc7 1025 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
Kojto 104:b9ad9a133dc7 1026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
Kojto 104:b9ad9a133dc7 1027
Kojto 104:b9ad9a133dc7 1028 /*@}*/ /* end of group CMSIS_TPI */
Kojto 104:b9ad9a133dc7 1029
Kojto 104:b9ad9a133dc7 1030
Kojto 104:b9ad9a133dc7 1031 #if (__MPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 1032 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 1033 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 104:b9ad9a133dc7 1034 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 104:b9ad9a133dc7 1035 @{
Kojto 104:b9ad9a133dc7 1036 */
Kojto 104:b9ad9a133dc7 1037
Kojto 104:b9ad9a133dc7 1038 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 104:b9ad9a133dc7 1039 */
Kojto 104:b9ad9a133dc7 1040 typedef struct
Kojto 104:b9ad9a133dc7 1041 {
Kojto 104:b9ad9a133dc7 1042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 104:b9ad9a133dc7 1043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 104:b9ad9a133dc7 1044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 104:b9ad9a133dc7 1045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 104:b9ad9a133dc7 1046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 104:b9ad9a133dc7 1047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
Kojto 104:b9ad9a133dc7 1048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
Kojto 104:b9ad9a133dc7 1049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
Kojto 104:b9ad9a133dc7 1050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
Kojto 104:b9ad9a133dc7 1051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
Kojto 104:b9ad9a133dc7 1052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
Kojto 104:b9ad9a133dc7 1053 } MPU_Type;
Kojto 104:b9ad9a133dc7 1054
Kojto 104:b9ad9a133dc7 1055 /* MPU Type Register */
Kojto 104:b9ad9a133dc7 1056 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 104:b9ad9a133dc7 1057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 104:b9ad9a133dc7 1058
Kojto 104:b9ad9a133dc7 1059 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 104:b9ad9a133dc7 1060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 104:b9ad9a133dc7 1061
Kojto 104:b9ad9a133dc7 1062 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 104:b9ad9a133dc7 1063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Kojto 104:b9ad9a133dc7 1064
Kojto 104:b9ad9a133dc7 1065 /* MPU Control Register */
Kojto 104:b9ad9a133dc7 1066 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 104:b9ad9a133dc7 1067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 104:b9ad9a133dc7 1068
Kojto 104:b9ad9a133dc7 1069 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 104:b9ad9a133dc7 1070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 104:b9ad9a133dc7 1071
Kojto 104:b9ad9a133dc7 1072 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 104:b9ad9a133dc7 1073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Kojto 104:b9ad9a133dc7 1074
Kojto 104:b9ad9a133dc7 1075 /* MPU Region Number Register */
Kojto 104:b9ad9a133dc7 1076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 104:b9ad9a133dc7 1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Kojto 104:b9ad9a133dc7 1078
Kojto 104:b9ad9a133dc7 1079 /* MPU Region Base Address Register */
Kojto 104:b9ad9a133dc7 1080 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
Kojto 104:b9ad9a133dc7 1081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 104:b9ad9a133dc7 1082
Kojto 104:b9ad9a133dc7 1083 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 104:b9ad9a133dc7 1084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 104:b9ad9a133dc7 1085
Kojto 104:b9ad9a133dc7 1086 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 104:b9ad9a133dc7 1087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Kojto 104:b9ad9a133dc7 1088
Kojto 104:b9ad9a133dc7 1089 /* MPU Region Attribute and Size Register */
Kojto 104:b9ad9a133dc7 1090 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 104:b9ad9a133dc7 1091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 104:b9ad9a133dc7 1092
Kojto 104:b9ad9a133dc7 1093 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 104:b9ad9a133dc7 1094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 104:b9ad9a133dc7 1095
Kojto 104:b9ad9a133dc7 1096 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 104:b9ad9a133dc7 1097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 104:b9ad9a133dc7 1098
Kojto 104:b9ad9a133dc7 1099 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 104:b9ad9a133dc7 1100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 104:b9ad9a133dc7 1101
Kojto 104:b9ad9a133dc7 1102 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 104:b9ad9a133dc7 1103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 104:b9ad9a133dc7 1104
Kojto 104:b9ad9a133dc7 1105 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 104:b9ad9a133dc7 1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 104:b9ad9a133dc7 1107
Kojto 104:b9ad9a133dc7 1108 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 104:b9ad9a133dc7 1109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 104:b9ad9a133dc7 1110
Kojto 104:b9ad9a133dc7 1111 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 104:b9ad9a133dc7 1112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 104:b9ad9a133dc7 1113
Kojto 104:b9ad9a133dc7 1114 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 104:b9ad9a133dc7 1115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 104:b9ad9a133dc7 1116
Kojto 104:b9ad9a133dc7 1117 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 104:b9ad9a133dc7 1118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 104:b9ad9a133dc7 1119
Kojto 104:b9ad9a133dc7 1120 /*@} end of group CMSIS_MPU */
Kojto 104:b9ad9a133dc7 1121 #endif
Kojto 104:b9ad9a133dc7 1122
Kojto 104:b9ad9a133dc7 1123
Kojto 104:b9ad9a133dc7 1124 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 1125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 104:b9ad9a133dc7 1126 \brief Type definitions for the Core Debug Registers
Kojto 104:b9ad9a133dc7 1127 @{
Kojto 104:b9ad9a133dc7 1128 */
Kojto 104:b9ad9a133dc7 1129
Kojto 104:b9ad9a133dc7 1130 /** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto 104:b9ad9a133dc7 1131 */
Kojto 104:b9ad9a133dc7 1132 typedef struct
Kojto 104:b9ad9a133dc7 1133 {
Kojto 104:b9ad9a133dc7 1134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
Kojto 104:b9ad9a133dc7 1135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
Kojto 104:b9ad9a133dc7 1136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
Kojto 104:b9ad9a133dc7 1137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
Kojto 104:b9ad9a133dc7 1138 } CoreDebug_Type;
Kojto 104:b9ad9a133dc7 1139
Kojto 104:b9ad9a133dc7 1140 /* Debug Halting Control and Status Register */
Kojto 104:b9ad9a133dc7 1141 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
Kojto 104:b9ad9a133dc7 1142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
Kojto 104:b9ad9a133dc7 1143
Kojto 104:b9ad9a133dc7 1144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
Kojto 104:b9ad9a133dc7 1145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
Kojto 104:b9ad9a133dc7 1146
Kojto 104:b9ad9a133dc7 1147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
Kojto 104:b9ad9a133dc7 1148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
Kojto 104:b9ad9a133dc7 1149
Kojto 104:b9ad9a133dc7 1150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
Kojto 104:b9ad9a133dc7 1151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
Kojto 104:b9ad9a133dc7 1152
Kojto 104:b9ad9a133dc7 1153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
Kojto 104:b9ad9a133dc7 1154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
Kojto 104:b9ad9a133dc7 1155
Kojto 104:b9ad9a133dc7 1156 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
Kojto 104:b9ad9a133dc7 1157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
Kojto 104:b9ad9a133dc7 1158
Kojto 104:b9ad9a133dc7 1159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
Kojto 104:b9ad9a133dc7 1160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
Kojto 104:b9ad9a133dc7 1161
Kojto 104:b9ad9a133dc7 1162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
Kojto 104:b9ad9a133dc7 1163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
Kojto 104:b9ad9a133dc7 1164
Kojto 104:b9ad9a133dc7 1165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
Kojto 104:b9ad9a133dc7 1166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
Kojto 104:b9ad9a133dc7 1167
Kojto 104:b9ad9a133dc7 1168 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
Kojto 104:b9ad9a133dc7 1169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
Kojto 104:b9ad9a133dc7 1170
Kojto 104:b9ad9a133dc7 1171 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
Kojto 104:b9ad9a133dc7 1172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
Kojto 104:b9ad9a133dc7 1173
Kojto 104:b9ad9a133dc7 1174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 104:b9ad9a133dc7 1175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
Kojto 104:b9ad9a133dc7 1176
Kojto 104:b9ad9a133dc7 1177 /* Debug Core Register Selector Register */
Kojto 104:b9ad9a133dc7 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
Kojto 104:b9ad9a133dc7 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
Kojto 104:b9ad9a133dc7 1180
Kojto 104:b9ad9a133dc7 1181 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 104:b9ad9a133dc7 1182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
Kojto 104:b9ad9a133dc7 1183
Kojto 104:b9ad9a133dc7 1184 /* Debug Exception and Monitor Control Register */
Kojto 104:b9ad9a133dc7 1185 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
Kojto 104:b9ad9a133dc7 1186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
Kojto 104:b9ad9a133dc7 1187
Kojto 104:b9ad9a133dc7 1188 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
Kojto 104:b9ad9a133dc7 1189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
Kojto 104:b9ad9a133dc7 1190
Kojto 104:b9ad9a133dc7 1191 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
Kojto 104:b9ad9a133dc7 1192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
Kojto 104:b9ad9a133dc7 1193
Kojto 104:b9ad9a133dc7 1194 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
Kojto 104:b9ad9a133dc7 1195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
Kojto 104:b9ad9a133dc7 1196
Kojto 104:b9ad9a133dc7 1197 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
Kojto 104:b9ad9a133dc7 1198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
Kojto 104:b9ad9a133dc7 1199
Kojto 104:b9ad9a133dc7 1200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
Kojto 104:b9ad9a133dc7 1201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
Kojto 104:b9ad9a133dc7 1202
Kojto 104:b9ad9a133dc7 1203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
Kojto 104:b9ad9a133dc7 1204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
Kojto 104:b9ad9a133dc7 1205
Kojto 104:b9ad9a133dc7 1206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
Kojto 104:b9ad9a133dc7 1207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
Kojto 104:b9ad9a133dc7 1208
Kojto 104:b9ad9a133dc7 1209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
Kojto 104:b9ad9a133dc7 1210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
Kojto 104:b9ad9a133dc7 1211
Kojto 104:b9ad9a133dc7 1212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
Kojto 104:b9ad9a133dc7 1213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
Kojto 104:b9ad9a133dc7 1214
Kojto 104:b9ad9a133dc7 1215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
Kojto 104:b9ad9a133dc7 1216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
Kojto 104:b9ad9a133dc7 1217
Kojto 104:b9ad9a133dc7 1218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
Kojto 104:b9ad9a133dc7 1219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
Kojto 104:b9ad9a133dc7 1220
Kojto 104:b9ad9a133dc7 1221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 104:b9ad9a133dc7 1222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
Kojto 104:b9ad9a133dc7 1223
Kojto 104:b9ad9a133dc7 1224 /*@} end of group CMSIS_CoreDebug */
Kojto 104:b9ad9a133dc7 1225
Kojto 104:b9ad9a133dc7 1226
Kojto 104:b9ad9a133dc7 1227 /** \ingroup CMSIS_core_register
Kojto 104:b9ad9a133dc7 1228 \defgroup CMSIS_core_base Core Definitions
Kojto 104:b9ad9a133dc7 1229 \brief Definitions for base addresses, unions, and structures.
Kojto 104:b9ad9a133dc7 1230 @{
Kojto 104:b9ad9a133dc7 1231 */
Kojto 104:b9ad9a133dc7 1232
Kojto 104:b9ad9a133dc7 1233 /* Memory mapping of Cortex-M3 Hardware */
Kojto 104:b9ad9a133dc7 1234 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 104:b9ad9a133dc7 1235 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
Kojto 104:b9ad9a133dc7 1236 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
Kojto 104:b9ad9a133dc7 1237 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
Kojto 104:b9ad9a133dc7 1238 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
Kojto 104:b9ad9a133dc7 1239 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 104:b9ad9a133dc7 1240 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 104:b9ad9a133dc7 1241 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 104:b9ad9a133dc7 1242
Kojto 104:b9ad9a133dc7 1243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
Kojto 104:b9ad9a133dc7 1244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 104:b9ad9a133dc7 1245 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 104:b9ad9a133dc7 1246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 104:b9ad9a133dc7 1247 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
Kojto 104:b9ad9a133dc7 1248 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
Kojto 104:b9ad9a133dc7 1249 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
Kojto 104:b9ad9a133dc7 1250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Kojto 104:b9ad9a133dc7 1251
Kojto 104:b9ad9a133dc7 1252 #if (__MPU_PRESENT == 1)
Kojto 104:b9ad9a133dc7 1253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 104:b9ad9a133dc7 1254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 104:b9ad9a133dc7 1255 #endif
Kojto 104:b9ad9a133dc7 1256
Kojto 104:b9ad9a133dc7 1257 /*@} */
Kojto 104:b9ad9a133dc7 1258
Kojto 104:b9ad9a133dc7 1259
Kojto 104:b9ad9a133dc7 1260
Kojto 104:b9ad9a133dc7 1261 /*******************************************************************************
Kojto 104:b9ad9a133dc7 1262 * Hardware Abstraction Layer
Kojto 104:b9ad9a133dc7 1263 Core Function Interface contains:
Kojto 104:b9ad9a133dc7 1264 - Core NVIC Functions
Kojto 104:b9ad9a133dc7 1265 - Core SysTick Functions
Kojto 104:b9ad9a133dc7 1266 - Core Debug Functions
Kojto 104:b9ad9a133dc7 1267 - Core Register Access Functions
Kojto 104:b9ad9a133dc7 1268 ******************************************************************************/
Kojto 104:b9ad9a133dc7 1269 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 104:b9ad9a133dc7 1270 */
Kojto 104:b9ad9a133dc7 1271
Kojto 104:b9ad9a133dc7 1272
Kojto 104:b9ad9a133dc7 1273
Kojto 104:b9ad9a133dc7 1274 /* ########################## NVIC functions #################################### */
Kojto 104:b9ad9a133dc7 1275 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 104:b9ad9a133dc7 1276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 104:b9ad9a133dc7 1277 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 104:b9ad9a133dc7 1278 @{
Kojto 104:b9ad9a133dc7 1279 */
Kojto 104:b9ad9a133dc7 1280
Kojto 104:b9ad9a133dc7 1281 /** \brief Set Priority Grouping
Kojto 104:b9ad9a133dc7 1282
Kojto 104:b9ad9a133dc7 1283 The function sets the priority grouping field using the required unlock sequence.
Kojto 104:b9ad9a133dc7 1284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto 104:b9ad9a133dc7 1285 Only values from 0..7 are used.
Kojto 104:b9ad9a133dc7 1286 In case of a conflict between priority grouping and available
Kojto 104:b9ad9a133dc7 1287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto 104:b9ad9a133dc7 1288
Kojto 104:b9ad9a133dc7 1289 \param [in] PriorityGroup Priority grouping field.
Kojto 104:b9ad9a133dc7 1290 */
Kojto 104:b9ad9a133dc7 1291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto 104:b9ad9a133dc7 1292 {
Kojto 104:b9ad9a133dc7 1293 uint32_t reg_value;
Kojto 104:b9ad9a133dc7 1294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
Kojto 104:b9ad9a133dc7 1295
Kojto 104:b9ad9a133dc7 1296 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 104:b9ad9a133dc7 1297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
Kojto 104:b9ad9a133dc7 1298 reg_value = (reg_value |
Kojto 104:b9ad9a133dc7 1299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 104:b9ad9a133dc7 1300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
Kojto 104:b9ad9a133dc7 1301 SCB->AIRCR = reg_value;
Kojto 104:b9ad9a133dc7 1302 }
Kojto 104:b9ad9a133dc7 1303
Kojto 104:b9ad9a133dc7 1304
Kojto 104:b9ad9a133dc7 1305 /** \brief Get Priority Grouping
Kojto 104:b9ad9a133dc7 1306
Kojto 104:b9ad9a133dc7 1307 The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto 104:b9ad9a133dc7 1308
Kojto 104:b9ad9a133dc7 1309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto 104:b9ad9a133dc7 1310 */
Kojto 104:b9ad9a133dc7 1311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto 104:b9ad9a133dc7 1312 {
Kojto 104:b9ad9a133dc7 1313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
Kojto 104:b9ad9a133dc7 1314 }
Kojto 104:b9ad9a133dc7 1315
Kojto 104:b9ad9a133dc7 1316
Kojto 104:b9ad9a133dc7 1317 /** \brief Enable External Interrupt
Kojto 104:b9ad9a133dc7 1318
Kojto 104:b9ad9a133dc7 1319 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 104:b9ad9a133dc7 1320
Kojto 104:b9ad9a133dc7 1321 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 104:b9ad9a133dc7 1322 */
Kojto 104:b9ad9a133dc7 1323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 1324 {
Kojto 104:b9ad9a133dc7 1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
Kojto 104:b9ad9a133dc7 1326 }
Kojto 104:b9ad9a133dc7 1327
Kojto 104:b9ad9a133dc7 1328
Kojto 104:b9ad9a133dc7 1329 /** \brief Disable External Interrupt
Kojto 104:b9ad9a133dc7 1330
Kojto 104:b9ad9a133dc7 1331 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 104:b9ad9a133dc7 1332
Kojto 104:b9ad9a133dc7 1333 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 104:b9ad9a133dc7 1334 */
Kojto 104:b9ad9a133dc7 1335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 1336 {
Kojto 104:b9ad9a133dc7 1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
Kojto 104:b9ad9a133dc7 1338 }
Kojto 104:b9ad9a133dc7 1339
Kojto 104:b9ad9a133dc7 1340
Kojto 104:b9ad9a133dc7 1341 /** \brief Get Pending Interrupt
Kojto 104:b9ad9a133dc7 1342
Kojto 104:b9ad9a133dc7 1343 The function reads the pending register in the NVIC and returns the pending bit
Kojto 104:b9ad9a133dc7 1344 for the specified interrupt.
Kojto 104:b9ad9a133dc7 1345
Kojto 104:b9ad9a133dc7 1346 \param [in] IRQn Interrupt number.
Kojto 104:b9ad9a133dc7 1347
Kojto 104:b9ad9a133dc7 1348 \return 0 Interrupt status is not pending.
Kojto 104:b9ad9a133dc7 1349 \return 1 Interrupt status is pending.
Kojto 104:b9ad9a133dc7 1350 */
Kojto 104:b9ad9a133dc7 1351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 1352 {
Kojto 104:b9ad9a133dc7 1353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
Kojto 104:b9ad9a133dc7 1354 }
Kojto 104:b9ad9a133dc7 1355
Kojto 104:b9ad9a133dc7 1356
Kojto 104:b9ad9a133dc7 1357 /** \brief Set Pending Interrupt
Kojto 104:b9ad9a133dc7 1358
Kojto 104:b9ad9a133dc7 1359 The function sets the pending bit of an external interrupt.
Kojto 104:b9ad9a133dc7 1360
Kojto 104:b9ad9a133dc7 1361 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 104:b9ad9a133dc7 1362 */
Kojto 104:b9ad9a133dc7 1363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 1364 {
Kojto 104:b9ad9a133dc7 1365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
Kojto 104:b9ad9a133dc7 1366 }
Kojto 104:b9ad9a133dc7 1367
Kojto 104:b9ad9a133dc7 1368
Kojto 104:b9ad9a133dc7 1369 /** \brief Clear Pending Interrupt
Kojto 104:b9ad9a133dc7 1370
Kojto 104:b9ad9a133dc7 1371 The function clears the pending bit of an external interrupt.
Kojto 104:b9ad9a133dc7 1372
Kojto 104:b9ad9a133dc7 1373 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 104:b9ad9a133dc7 1374 */
Kojto 104:b9ad9a133dc7 1375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 1376 {
Kojto 104:b9ad9a133dc7 1377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 104:b9ad9a133dc7 1378 }
Kojto 104:b9ad9a133dc7 1379
Kojto 104:b9ad9a133dc7 1380
Kojto 104:b9ad9a133dc7 1381 /** \brief Get Active Interrupt
Kojto 104:b9ad9a133dc7 1382
Kojto 104:b9ad9a133dc7 1383 The function reads the active register in NVIC and returns the active bit.
Kojto 104:b9ad9a133dc7 1384
Kojto 104:b9ad9a133dc7 1385 \param [in] IRQn Interrupt number.
Kojto 104:b9ad9a133dc7 1386
Kojto 104:b9ad9a133dc7 1387 \return 0 Interrupt status is not active.
Kojto 104:b9ad9a133dc7 1388 \return 1 Interrupt status is active.
Kojto 104:b9ad9a133dc7 1389 */
Kojto 104:b9ad9a133dc7 1390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 1391 {
Kojto 104:b9ad9a133dc7 1392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
Kojto 104:b9ad9a133dc7 1393 }
Kojto 104:b9ad9a133dc7 1394
Kojto 104:b9ad9a133dc7 1395
Kojto 104:b9ad9a133dc7 1396 /** \brief Set Interrupt Priority
Kojto 104:b9ad9a133dc7 1397
Kojto 104:b9ad9a133dc7 1398 The function sets the priority of an interrupt.
Kojto 104:b9ad9a133dc7 1399
Kojto 104:b9ad9a133dc7 1400 \note The priority cannot be set for every core interrupt.
Kojto 104:b9ad9a133dc7 1401
Kojto 104:b9ad9a133dc7 1402 \param [in] IRQn Interrupt number.
Kojto 104:b9ad9a133dc7 1403 \param [in] priority Priority to set.
Kojto 104:b9ad9a133dc7 1404 */
Kojto 104:b9ad9a133dc7 1405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 104:b9ad9a133dc7 1406 {
Kojto 104:b9ad9a133dc7 1407 if(IRQn < 0) {
Kojto 104:b9ad9a133dc7 1408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
Kojto 104:b9ad9a133dc7 1409 else {
Kojto 104:b9ad9a133dc7 1410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
Kojto 104:b9ad9a133dc7 1411 }
Kojto 104:b9ad9a133dc7 1412
Kojto 104:b9ad9a133dc7 1413
Kojto 104:b9ad9a133dc7 1414 /** \brief Get Interrupt Priority
Kojto 104:b9ad9a133dc7 1415
Kojto 104:b9ad9a133dc7 1416 The function reads the priority of an interrupt. The interrupt
Kojto 104:b9ad9a133dc7 1417 number can be positive to specify an external (device specific)
Kojto 104:b9ad9a133dc7 1418 interrupt, or negative to specify an internal (core) interrupt.
Kojto 104:b9ad9a133dc7 1419
Kojto 104:b9ad9a133dc7 1420
Kojto 104:b9ad9a133dc7 1421 \param [in] IRQn Interrupt number.
Kojto 104:b9ad9a133dc7 1422 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 104:b9ad9a133dc7 1423 priority bits of the microcontroller.
Kojto 104:b9ad9a133dc7 1424 */
Kojto 104:b9ad9a133dc7 1425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 104:b9ad9a133dc7 1426 {
Kojto 104:b9ad9a133dc7 1427
Kojto 104:b9ad9a133dc7 1428 if(IRQn < 0) {
Kojto 104:b9ad9a133dc7 1429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
Kojto 104:b9ad9a133dc7 1430 else {
Kojto 104:b9ad9a133dc7 1431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 104:b9ad9a133dc7 1432 }
Kojto 104:b9ad9a133dc7 1433
Kojto 104:b9ad9a133dc7 1434
Kojto 104:b9ad9a133dc7 1435 /** \brief Encode Priority
Kojto 104:b9ad9a133dc7 1436
Kojto 104:b9ad9a133dc7 1437 The function encodes the priority for an interrupt with the given priority group,
Kojto 104:b9ad9a133dc7 1438 preemptive priority value, and subpriority value.
Kojto 104:b9ad9a133dc7 1439 In case of a conflict between priority grouping and available
Kojto 104:b9ad9a133dc7 1440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
Kojto 104:b9ad9a133dc7 1441
Kojto 104:b9ad9a133dc7 1442 \param [in] PriorityGroup Used priority group.
Kojto 104:b9ad9a133dc7 1443 \param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto 104:b9ad9a133dc7 1444 \param [in] SubPriority Subpriority value (starting from 0).
Kojto 104:b9ad9a133dc7 1445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto 104:b9ad9a133dc7 1446 */
Kojto 104:b9ad9a133dc7 1447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto 104:b9ad9a133dc7 1448 {
Kojto 104:b9ad9a133dc7 1449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kojto 104:b9ad9a133dc7 1450 uint32_t PreemptPriorityBits;
Kojto 104:b9ad9a133dc7 1451 uint32_t SubPriorityBits;
Kojto 104:b9ad9a133dc7 1452
Kojto 104:b9ad9a133dc7 1453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kojto 104:b9ad9a133dc7 1454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kojto 104:b9ad9a133dc7 1455
Kojto 104:b9ad9a133dc7 1456 return (
Kojto 104:b9ad9a133dc7 1457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
Kojto 104:b9ad9a133dc7 1458 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
Kojto 104:b9ad9a133dc7 1459 );
Kojto 104:b9ad9a133dc7 1460 }
Kojto 104:b9ad9a133dc7 1461
Kojto 104:b9ad9a133dc7 1462
Kojto 104:b9ad9a133dc7 1463 /** \brief Decode Priority
Kojto 104:b9ad9a133dc7 1464
Kojto 104:b9ad9a133dc7 1465 The function decodes an interrupt priority value with a given priority group to
Kojto 104:b9ad9a133dc7 1466 preemptive priority value and subpriority value.
Kojto 104:b9ad9a133dc7 1467 In case of a conflict between priority grouping and available
Kojto 104:b9ad9a133dc7 1468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Kojto 104:b9ad9a133dc7 1469
Kojto 104:b9ad9a133dc7 1470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto 104:b9ad9a133dc7 1471 \param [in] PriorityGroup Used priority group.
Kojto 104:b9ad9a133dc7 1472 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto 104:b9ad9a133dc7 1473 \param [out] pSubPriority Subpriority value (starting from 0).
Kojto 104:b9ad9a133dc7 1474 */
Kojto 104:b9ad9a133dc7 1475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto 104:b9ad9a133dc7 1476 {
Kojto 104:b9ad9a133dc7 1477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kojto 104:b9ad9a133dc7 1478 uint32_t PreemptPriorityBits;
Kojto 104:b9ad9a133dc7 1479 uint32_t SubPriorityBits;
Kojto 104:b9ad9a133dc7 1480
Kojto 104:b9ad9a133dc7 1481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kojto 104:b9ad9a133dc7 1482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kojto 104:b9ad9a133dc7 1483
Kojto 104:b9ad9a133dc7 1484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
Kojto 104:b9ad9a133dc7 1485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
Kojto 104:b9ad9a133dc7 1486 }
Kojto 104:b9ad9a133dc7 1487
Kojto 104:b9ad9a133dc7 1488
Kojto 104:b9ad9a133dc7 1489 /** \brief System Reset
Kojto 104:b9ad9a133dc7 1490
Kojto 104:b9ad9a133dc7 1491 The function initiates a system reset request to reset the MCU.
Kojto 104:b9ad9a133dc7 1492 */
Kojto 104:b9ad9a133dc7 1493 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 104:b9ad9a133dc7 1494 {
Kojto 104:b9ad9a133dc7 1495 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 104:b9ad9a133dc7 1496 buffered write are completed before reset */
Kojto 104:b9ad9a133dc7 1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 104:b9ad9a133dc7 1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 104:b9ad9a133dc7 1499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
Kojto 104:b9ad9a133dc7 1500 __DSB(); /* Ensure completion of memory access */
Kojto 104:b9ad9a133dc7 1501 while(1); /* wait until reset */
Kojto 104:b9ad9a133dc7 1502 }
Kojto 104:b9ad9a133dc7 1503
Kojto 104:b9ad9a133dc7 1504 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 104:b9ad9a133dc7 1505
Kojto 104:b9ad9a133dc7 1506
Kojto 104:b9ad9a133dc7 1507
Kojto 104:b9ad9a133dc7 1508 /* ################################## SysTick function ############################################ */
Kojto 104:b9ad9a133dc7 1509 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 104:b9ad9a133dc7 1510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 104:b9ad9a133dc7 1511 \brief Functions that configure the System.
Kojto 104:b9ad9a133dc7 1512 @{
Kojto 104:b9ad9a133dc7 1513 */
Kojto 104:b9ad9a133dc7 1514
Kojto 104:b9ad9a133dc7 1515 #if (__Vendor_SysTickConfig == 0)
Kojto 104:b9ad9a133dc7 1516
Kojto 104:b9ad9a133dc7 1517 /** \brief System Tick Configuration
Kojto 104:b9ad9a133dc7 1518
Kojto 104:b9ad9a133dc7 1519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 104:b9ad9a133dc7 1520 Counter is in free running mode to generate periodic interrupts.
Kojto 104:b9ad9a133dc7 1521
Kojto 104:b9ad9a133dc7 1522 \param [in] ticks Number of ticks between two interrupts.
Kojto 104:b9ad9a133dc7 1523
Kojto 104:b9ad9a133dc7 1524 \return 0 Function succeeded.
Kojto 104:b9ad9a133dc7 1525 \return 1 Function failed.
Kojto 104:b9ad9a133dc7 1526
Kojto 104:b9ad9a133dc7 1527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 104:b9ad9a133dc7 1528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 104:b9ad9a133dc7 1529 must contain a vendor-specific implementation of this function.
Kojto 104:b9ad9a133dc7 1530
Kojto 104:b9ad9a133dc7 1531 */
Kojto 104:b9ad9a133dc7 1532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 104:b9ad9a133dc7 1533 {
Kojto 104:b9ad9a133dc7 1534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 104:b9ad9a133dc7 1535
Kojto 104:b9ad9a133dc7 1536 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 104:b9ad9a133dc7 1537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 104:b9ad9a133dc7 1538 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 104:b9ad9a133dc7 1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 104:b9ad9a133dc7 1540 SysTick_CTRL_TICKINT_Msk |
Kojto 104:b9ad9a133dc7 1541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 104:b9ad9a133dc7 1542 return (0); /* Function successful */
Kojto 104:b9ad9a133dc7 1543 }
Kojto 104:b9ad9a133dc7 1544
Kojto 104:b9ad9a133dc7 1545 #endif
Kojto 104:b9ad9a133dc7 1546
Kojto 104:b9ad9a133dc7 1547 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 104:b9ad9a133dc7 1548
Kojto 104:b9ad9a133dc7 1549
Kojto 104:b9ad9a133dc7 1550
Kojto 104:b9ad9a133dc7 1551 /* ##################################### Debug In/Output function ########################################### */
Kojto 104:b9ad9a133dc7 1552 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 104:b9ad9a133dc7 1553 \defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto 104:b9ad9a133dc7 1554 \brief Functions that access the ITM debug interface.
Kojto 104:b9ad9a133dc7 1555 @{
Kojto 104:b9ad9a133dc7 1556 */
Kojto 104:b9ad9a133dc7 1557
Kojto 104:b9ad9a133dc7 1558 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
Kojto 104:b9ad9a133dc7 1559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
Kojto 104:b9ad9a133dc7 1560
Kojto 104:b9ad9a133dc7 1561
Kojto 104:b9ad9a133dc7 1562 /** \brief ITM Send Character
Kojto 104:b9ad9a133dc7 1563
Kojto 104:b9ad9a133dc7 1564 The function transmits a character via the ITM channel 0, and
Kojto 104:b9ad9a133dc7 1565 \li Just returns when no debugger is connected that has booked the output.
Kojto 104:b9ad9a133dc7 1566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto 104:b9ad9a133dc7 1567
Kojto 104:b9ad9a133dc7 1568 \param [in] ch Character to transmit.
Kojto 104:b9ad9a133dc7 1569
Kojto 104:b9ad9a133dc7 1570 \returns Character to transmit.
Kojto 104:b9ad9a133dc7 1571 */
Kojto 104:b9ad9a133dc7 1572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto 104:b9ad9a133dc7 1573 {
Kojto 104:b9ad9a133dc7 1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
Kojto 104:b9ad9a133dc7 1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
Kojto 104:b9ad9a133dc7 1576 {
Kojto 104:b9ad9a133dc7 1577 while (ITM->PORT[0].u32 == 0);
Kojto 104:b9ad9a133dc7 1578 ITM->PORT[0].u8 = (uint8_t) ch;
Kojto 104:b9ad9a133dc7 1579 }
Kojto 104:b9ad9a133dc7 1580 return (ch);
Kojto 104:b9ad9a133dc7 1581 }
Kojto 104:b9ad9a133dc7 1582
Kojto 104:b9ad9a133dc7 1583
Kojto 104:b9ad9a133dc7 1584 /** \brief ITM Receive Character
Kojto 104:b9ad9a133dc7 1585
Kojto 104:b9ad9a133dc7 1586 The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto 104:b9ad9a133dc7 1587
Kojto 104:b9ad9a133dc7 1588 \return Received character.
Kojto 104:b9ad9a133dc7 1589 \return -1 No character pending.
Kojto 104:b9ad9a133dc7 1590 */
Kojto 104:b9ad9a133dc7 1591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto 104:b9ad9a133dc7 1592 int32_t ch = -1; /* no character available */
Kojto 104:b9ad9a133dc7 1593
Kojto 104:b9ad9a133dc7 1594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto 104:b9ad9a133dc7 1595 ch = ITM_RxBuffer;
Kojto 104:b9ad9a133dc7 1596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto 104:b9ad9a133dc7 1597 }
Kojto 104:b9ad9a133dc7 1598
Kojto 104:b9ad9a133dc7 1599 return (ch);
Kojto 104:b9ad9a133dc7 1600 }
Kojto 104:b9ad9a133dc7 1601
Kojto 104:b9ad9a133dc7 1602
Kojto 104:b9ad9a133dc7 1603 /** \brief ITM Check Character
Kojto 104:b9ad9a133dc7 1604
Kojto 104:b9ad9a133dc7 1605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto 104:b9ad9a133dc7 1606
Kojto 104:b9ad9a133dc7 1607 \return 0 No character available.
Kojto 104:b9ad9a133dc7 1608 \return 1 Character available.
Kojto 104:b9ad9a133dc7 1609 */
Kojto 104:b9ad9a133dc7 1610 __STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto 104:b9ad9a133dc7 1611
Kojto 104:b9ad9a133dc7 1612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto 104:b9ad9a133dc7 1613 return (0); /* no character available */
Kojto 104:b9ad9a133dc7 1614 } else {
Kojto 104:b9ad9a133dc7 1615 return (1); /* character available */
Kojto 104:b9ad9a133dc7 1616 }
Kojto 104:b9ad9a133dc7 1617 }
Kojto 104:b9ad9a133dc7 1618
Kojto 104:b9ad9a133dc7 1619 /*@} end of CMSIS_core_DebugFunctions */
Kojto 104:b9ad9a133dc7 1620
Kojto 104:b9ad9a133dc7 1621 #endif /* __CORE_CM3_H_DEPENDANT */
Kojto 104:b9ad9a133dc7 1622
Kojto 104:b9ad9a133dc7 1623 #endif /* __CMSIS_GENERIC */
Kojto 104:b9ad9a133dc7 1624
Kojto 104:b9ad9a133dc7 1625 #ifdef __cplusplus
Kojto 104:b9ad9a133dc7 1626 }
Kojto 104:b9ad9a133dc7 1627 #endif