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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_smc.h@104:b9ad9a133dc7, 2015-08-05 (annotated)
- Committer:
- Kojto
- Date:
- Wed Aug 05 13:16:35 2015 +0100
- Revision:
- 104:b9ad9a133dc7
- Parent:
- 90:cb3d968589d8
Release 104 of the mbed library:
Changes:
- new platforms: nrf51 microbit
- MAXxxx - fix pwm array search
- LPC8xx - usart enable fix
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 90:cb3d968589d8 | 1 | /* |
Kojto | 90:cb3d968589d8 | 2 | ** ################################################################### |
Kojto | 90:cb3d968589d8 | 3 | ** Compilers: Keil ARM C/C++ Compiler |
Kojto | 90:cb3d968589d8 | 4 | ** Freescale C/C++ for Embedded ARM |
Kojto | 90:cb3d968589d8 | 5 | ** GNU C Compiler |
Kojto | 90:cb3d968589d8 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
Kojto | 90:cb3d968589d8 | 7 | ** |
Kojto | 90:cb3d968589d8 | 8 | ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 |
Kojto | 90:cb3d968589d8 | 9 | ** Version: rev. 2.5, 2014-02-10 |
Kojto | 90:cb3d968589d8 | 10 | ** Build: b140604 |
Kojto | 90:cb3d968589d8 | 11 | ** |
Kojto | 90:cb3d968589d8 | 12 | ** Abstract: |
Kojto | 90:cb3d968589d8 | 13 | ** Extension to the CMSIS register access layer header. |
Kojto | 90:cb3d968589d8 | 14 | ** |
Kojto | 90:cb3d968589d8 | 15 | ** Copyright (c) 2014 Freescale Semiconductor, Inc. |
Kojto | 90:cb3d968589d8 | 16 | ** All rights reserved. |
Kojto | 90:cb3d968589d8 | 17 | ** |
Kojto | 90:cb3d968589d8 | 18 | ** Redistribution and use in source and binary forms, with or without modification, |
Kojto | 90:cb3d968589d8 | 19 | ** are permitted provided that the following conditions are met: |
Kojto | 90:cb3d968589d8 | 20 | ** |
Kojto | 90:cb3d968589d8 | 21 | ** o Redistributions of source code must retain the above copyright notice, this list |
Kojto | 90:cb3d968589d8 | 22 | ** of conditions and the following disclaimer. |
Kojto | 90:cb3d968589d8 | 23 | ** |
Kojto | 90:cb3d968589d8 | 24 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
Kojto | 90:cb3d968589d8 | 25 | ** list of conditions and the following disclaimer in the documentation and/or |
Kojto | 90:cb3d968589d8 | 26 | ** other materials provided with the distribution. |
Kojto | 90:cb3d968589d8 | 27 | ** |
Kojto | 90:cb3d968589d8 | 28 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
Kojto | 90:cb3d968589d8 | 29 | ** contributors may be used to endorse or promote products derived from this |
Kojto | 90:cb3d968589d8 | 30 | ** software without specific prior written permission. |
Kojto | 90:cb3d968589d8 | 31 | ** |
Kojto | 90:cb3d968589d8 | 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
Kojto | 90:cb3d968589d8 | 33 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
Kojto | 90:cb3d968589d8 | 34 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Kojto | 90:cb3d968589d8 | 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
Kojto | 90:cb3d968589d8 | 36 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
Kojto | 90:cb3d968589d8 | 37 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
Kojto | 90:cb3d968589d8 | 38 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
Kojto | 90:cb3d968589d8 | 39 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
Kojto | 90:cb3d968589d8 | 40 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
Kojto | 90:cb3d968589d8 | 41 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Kojto | 90:cb3d968589d8 | 42 | ** |
Kojto | 90:cb3d968589d8 | 43 | ** http: www.freescale.com |
Kojto | 90:cb3d968589d8 | 44 | ** mail: support@freescale.com |
Kojto | 90:cb3d968589d8 | 45 | ** |
Kojto | 90:cb3d968589d8 | 46 | ** Revisions: |
Kojto | 90:cb3d968589d8 | 47 | ** - rev. 1.0 (2013-08-12) |
Kojto | 90:cb3d968589d8 | 48 | ** Initial version. |
Kojto | 90:cb3d968589d8 | 49 | ** - rev. 2.0 (2013-10-29) |
Kojto | 90:cb3d968589d8 | 50 | ** Register accessor macros added to the memory map. |
Kojto | 90:cb3d968589d8 | 51 | ** Symbols for Processor Expert memory map compatibility added to the memory map. |
Kojto | 90:cb3d968589d8 | 52 | ** Startup file for gcc has been updated according to CMSIS 3.2. |
Kojto | 90:cb3d968589d8 | 53 | ** System initialization updated. |
Kojto | 90:cb3d968589d8 | 54 | ** MCG - registers updated. |
Kojto | 90:cb3d968589d8 | 55 | ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. |
Kojto | 90:cb3d968589d8 | 56 | ** - rev. 2.1 (2013-10-30) |
Kojto | 90:cb3d968589d8 | 57 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. |
Kojto | 90:cb3d968589d8 | 58 | ** - rev. 2.2 (2013-12-09) |
Kojto | 90:cb3d968589d8 | 59 | ** DMA - EARS register removed. |
Kojto | 90:cb3d968589d8 | 60 | ** AIPS0, AIPS1 - MPRA register updated. |
Kojto | 90:cb3d968589d8 | 61 | ** - rev. 2.3 (2014-01-24) |
Kojto | 90:cb3d968589d8 | 62 | ** Update according to reference manual rev. 2 |
Kojto | 90:cb3d968589d8 | 63 | ** ENET, MCG, MCM, SIM, USB - registers updated |
Kojto | 90:cb3d968589d8 | 64 | ** - rev. 2.4 (2014-02-10) |
Kojto | 90:cb3d968589d8 | 65 | ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h |
Kojto | 90:cb3d968589d8 | 66 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. |
Kojto | 90:cb3d968589d8 | 67 | ** - rev. 2.5 (2014-02-10) |
Kojto | 90:cb3d968589d8 | 68 | ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h |
Kojto | 90:cb3d968589d8 | 69 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. |
Kojto | 90:cb3d968589d8 | 70 | ** Module access macro module_BASES replaced by module_BASE_PTRS. |
Kojto | 90:cb3d968589d8 | 71 | ** |
Kojto | 90:cb3d968589d8 | 72 | ** ################################################################### |
Kojto | 90:cb3d968589d8 | 73 | */ |
Kojto | 90:cb3d968589d8 | 74 | |
Kojto | 90:cb3d968589d8 | 75 | /* |
Kojto | 90:cb3d968589d8 | 76 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
Kojto | 90:cb3d968589d8 | 77 | * |
Kojto | 90:cb3d968589d8 | 78 | * This file was generated automatically and any changes may be lost. |
Kojto | 90:cb3d968589d8 | 79 | */ |
Kojto | 90:cb3d968589d8 | 80 | #ifndef __HW_SMC_REGISTERS_H__ |
Kojto | 90:cb3d968589d8 | 81 | #define __HW_SMC_REGISTERS_H__ |
Kojto | 90:cb3d968589d8 | 82 | |
Kojto | 90:cb3d968589d8 | 83 | #include "MK64F12.h" |
Kojto | 90:cb3d968589d8 | 84 | #include "fsl_bitaccess.h" |
Kojto | 90:cb3d968589d8 | 85 | |
Kojto | 90:cb3d968589d8 | 86 | /* |
Kojto | 90:cb3d968589d8 | 87 | * MK64F12 SMC |
Kojto | 90:cb3d968589d8 | 88 | * |
Kojto | 90:cb3d968589d8 | 89 | * System Mode Controller |
Kojto | 90:cb3d968589d8 | 90 | * |
Kojto | 90:cb3d968589d8 | 91 | * Registers defined in this header file: |
Kojto | 90:cb3d968589d8 | 92 | * - HW_SMC_PMPROT - Power Mode Protection register |
Kojto | 90:cb3d968589d8 | 93 | * - HW_SMC_PMCTRL - Power Mode Control register |
Kojto | 90:cb3d968589d8 | 94 | * - HW_SMC_VLLSCTRL - VLLS Control register |
Kojto | 90:cb3d968589d8 | 95 | * - HW_SMC_PMSTAT - Power Mode Status register |
Kojto | 90:cb3d968589d8 | 96 | * |
Kojto | 90:cb3d968589d8 | 97 | * - hw_smc_t - Struct containing all module registers. |
Kojto | 90:cb3d968589d8 | 98 | */ |
Kojto | 90:cb3d968589d8 | 99 | |
Kojto | 90:cb3d968589d8 | 100 | #define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */ |
Kojto | 90:cb3d968589d8 | 101 | |
Kojto | 90:cb3d968589d8 | 102 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 103 | * HW_SMC_PMPROT - Power Mode Protection register |
Kojto | 90:cb3d968589d8 | 104 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 105 | |
Kojto | 90:cb3d968589d8 | 106 | /*! |
Kojto | 90:cb3d968589d8 | 107 | * @brief HW_SMC_PMPROT - Power Mode Protection register (RW) |
Kojto | 90:cb3d968589d8 | 108 | * |
Kojto | 90:cb3d968589d8 | 109 | * Reset value: 0x00U |
Kojto | 90:cb3d968589d8 | 110 | * |
Kojto | 90:cb3d968589d8 | 111 | * This register provides protection for entry into any low-power run or stop |
Kojto | 90:cb3d968589d8 | 112 | * mode. The enabling of the low-power run or stop mode occurs by configuring the |
Kojto | 90:cb3d968589d8 | 113 | * Power Mode Control register (PMCTRL). The PMPROT register can be written only |
Kojto | 90:cb3d968589d8 | 114 | * once after any system reset. If the MCU is configured for a disallowed or |
Kojto | 90:cb3d968589d8 | 115 | * reserved power mode, the MCU remains in its current power mode. For example, if the |
Kojto | 90:cb3d968589d8 | 116 | * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using |
Kojto | 90:cb3d968589d8 | 117 | * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is |
Kojto | 90:cb3d968589d8 | 118 | * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by |
Kojto | 90:cb3d968589d8 | 119 | * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types |
Kojto | 90:cb3d968589d8 | 120 | * that do not trigger Chip Reset not VLLS. See the Reset section details for more |
Kojto | 90:cb3d968589d8 | 121 | * information. |
Kojto | 90:cb3d968589d8 | 122 | */ |
Kojto | 90:cb3d968589d8 | 123 | typedef union _hw_smc_pmprot |
Kojto | 90:cb3d968589d8 | 124 | { |
Kojto | 90:cb3d968589d8 | 125 | uint8_t U; |
Kojto | 90:cb3d968589d8 | 126 | struct _hw_smc_pmprot_bitfields |
Kojto | 90:cb3d968589d8 | 127 | { |
Kojto | 90:cb3d968589d8 | 128 | uint8_t RESERVED0 : 1; /*!< [0] */ |
Kojto | 90:cb3d968589d8 | 129 | uint8_t AVLLS : 1; /*!< [1] Allow Very-Low-Leakage Stop Mode */ |
Kojto | 90:cb3d968589d8 | 130 | uint8_t RESERVED1 : 1; /*!< [2] */ |
Kojto | 90:cb3d968589d8 | 131 | uint8_t ALLS : 1; /*!< [3] Allow Low-Leakage Stop Mode */ |
Kojto | 90:cb3d968589d8 | 132 | uint8_t RESERVED2 : 1; /*!< [4] */ |
Kojto | 90:cb3d968589d8 | 133 | uint8_t AVLP : 1; /*!< [5] Allow Very-Low-Power Modes */ |
Kojto | 90:cb3d968589d8 | 134 | uint8_t RESERVED3 : 2; /*!< [7:6] */ |
Kojto | 90:cb3d968589d8 | 135 | } B; |
Kojto | 90:cb3d968589d8 | 136 | } hw_smc_pmprot_t; |
Kojto | 90:cb3d968589d8 | 137 | |
Kojto | 90:cb3d968589d8 | 138 | /*! |
Kojto | 90:cb3d968589d8 | 139 | * @name Constants and macros for entire SMC_PMPROT register |
Kojto | 90:cb3d968589d8 | 140 | */ |
Kojto | 90:cb3d968589d8 | 141 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 142 | #define HW_SMC_PMPROT_ADDR(x) ((x) + 0x0U) |
Kojto | 90:cb3d968589d8 | 143 | |
Kojto | 90:cb3d968589d8 | 144 | #define HW_SMC_PMPROT(x) (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 145 | #define HW_SMC_PMPROT_RD(x) (HW_SMC_PMPROT(x).U) |
Kojto | 90:cb3d968589d8 | 146 | #define HW_SMC_PMPROT_WR(x, v) (HW_SMC_PMPROT(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 147 | #define HW_SMC_PMPROT_SET(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 148 | #define HW_SMC_PMPROT_CLR(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 149 | #define HW_SMC_PMPROT_TOG(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 150 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 151 | |
Kojto | 90:cb3d968589d8 | 152 | /* |
Kojto | 90:cb3d968589d8 | 153 | * Constants & macros for individual SMC_PMPROT bitfields |
Kojto | 90:cb3d968589d8 | 154 | */ |
Kojto | 90:cb3d968589d8 | 155 | |
Kojto | 90:cb3d968589d8 | 156 | /*! |
Kojto | 90:cb3d968589d8 | 157 | * @name Register SMC_PMPROT, field AVLLS[1] (RW) |
Kojto | 90:cb3d968589d8 | 158 | * |
Kojto | 90:cb3d968589d8 | 159 | * Provided the appropriate control bits are set up in PMCTRL, this write once |
Kojto | 90:cb3d968589d8 | 160 | * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx). |
Kojto | 90:cb3d968589d8 | 161 | * |
Kojto | 90:cb3d968589d8 | 162 | * Values: |
Kojto | 90:cb3d968589d8 | 163 | * - 0 - Any VLLSx mode is not allowed |
Kojto | 90:cb3d968589d8 | 164 | * - 1 - Any VLLSx mode is allowed |
Kojto | 90:cb3d968589d8 | 165 | */ |
Kojto | 90:cb3d968589d8 | 166 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 167 | #define BP_SMC_PMPROT_AVLLS (1U) /*!< Bit position for SMC_PMPROT_AVLLS. */ |
Kojto | 90:cb3d968589d8 | 168 | #define BM_SMC_PMPROT_AVLLS (0x02U) /*!< Bit mask for SMC_PMPROT_AVLLS. */ |
Kojto | 90:cb3d968589d8 | 169 | #define BS_SMC_PMPROT_AVLLS (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */ |
Kojto | 90:cb3d968589d8 | 170 | |
Kojto | 90:cb3d968589d8 | 171 | /*! @brief Read current value of the SMC_PMPROT_AVLLS field. */ |
Kojto | 90:cb3d968589d8 | 172 | #define BR_SMC_PMPROT_AVLLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS)) |
Kojto | 90:cb3d968589d8 | 173 | |
Kojto | 90:cb3d968589d8 | 174 | /*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */ |
Kojto | 90:cb3d968589d8 | 175 | #define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS) |
Kojto | 90:cb3d968589d8 | 176 | |
Kojto | 90:cb3d968589d8 | 177 | /*! @brief Set the AVLLS field to a new value. */ |
Kojto | 90:cb3d968589d8 | 178 | #define BW_SMC_PMPROT_AVLLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS) = (v)) |
Kojto | 90:cb3d968589d8 | 179 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 180 | |
Kojto | 90:cb3d968589d8 | 181 | /*! |
Kojto | 90:cb3d968589d8 | 182 | * @name Register SMC_PMPROT, field ALLS[3] (RW) |
Kojto | 90:cb3d968589d8 | 183 | * |
Kojto | 90:cb3d968589d8 | 184 | * Provided the appropriate control bits are set up in PMCTRL, this write-once |
Kojto | 90:cb3d968589d8 | 185 | * field allows the MCU to enter any low-leakage stop mode (LLS). |
Kojto | 90:cb3d968589d8 | 186 | * |
Kojto | 90:cb3d968589d8 | 187 | * Values: |
Kojto | 90:cb3d968589d8 | 188 | * - 0 - LLS is not allowed |
Kojto | 90:cb3d968589d8 | 189 | * - 1 - LLS is allowed |
Kojto | 90:cb3d968589d8 | 190 | */ |
Kojto | 90:cb3d968589d8 | 191 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 192 | #define BP_SMC_PMPROT_ALLS (3U) /*!< Bit position for SMC_PMPROT_ALLS. */ |
Kojto | 90:cb3d968589d8 | 193 | #define BM_SMC_PMPROT_ALLS (0x08U) /*!< Bit mask for SMC_PMPROT_ALLS. */ |
Kojto | 90:cb3d968589d8 | 194 | #define BS_SMC_PMPROT_ALLS (1U) /*!< Bit field size in bits for SMC_PMPROT_ALLS. */ |
Kojto | 90:cb3d968589d8 | 195 | |
Kojto | 90:cb3d968589d8 | 196 | /*! @brief Read current value of the SMC_PMPROT_ALLS field. */ |
Kojto | 90:cb3d968589d8 | 197 | #define BR_SMC_PMPROT_ALLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS)) |
Kojto | 90:cb3d968589d8 | 198 | |
Kojto | 90:cb3d968589d8 | 199 | /*! @brief Format value for bitfield SMC_PMPROT_ALLS. */ |
Kojto | 90:cb3d968589d8 | 200 | #define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS) |
Kojto | 90:cb3d968589d8 | 201 | |
Kojto | 90:cb3d968589d8 | 202 | /*! @brief Set the ALLS field to a new value. */ |
Kojto | 90:cb3d968589d8 | 203 | #define BW_SMC_PMPROT_ALLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS) = (v)) |
Kojto | 90:cb3d968589d8 | 204 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 205 | |
Kojto | 90:cb3d968589d8 | 206 | /*! |
Kojto | 90:cb3d968589d8 | 207 | * @name Register SMC_PMPROT, field AVLP[5] (RW) |
Kojto | 90:cb3d968589d8 | 208 | * |
Kojto | 90:cb3d968589d8 | 209 | * Provided the appropriate control bits are set up in PMCTRL, this write-once |
Kojto | 90:cb3d968589d8 | 210 | * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS). |
Kojto | 90:cb3d968589d8 | 211 | * |
Kojto | 90:cb3d968589d8 | 212 | * Values: |
Kojto | 90:cb3d968589d8 | 213 | * - 0 - VLPR, VLPW, and VLPS are not allowed. |
Kojto | 90:cb3d968589d8 | 214 | * - 1 - VLPR, VLPW, and VLPS are allowed. |
Kojto | 90:cb3d968589d8 | 215 | */ |
Kojto | 90:cb3d968589d8 | 216 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 217 | #define BP_SMC_PMPROT_AVLP (5U) /*!< Bit position for SMC_PMPROT_AVLP. */ |
Kojto | 90:cb3d968589d8 | 218 | #define BM_SMC_PMPROT_AVLP (0x20U) /*!< Bit mask for SMC_PMPROT_AVLP. */ |
Kojto | 90:cb3d968589d8 | 219 | #define BS_SMC_PMPROT_AVLP (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLP. */ |
Kojto | 90:cb3d968589d8 | 220 | |
Kojto | 90:cb3d968589d8 | 221 | /*! @brief Read current value of the SMC_PMPROT_AVLP field. */ |
Kojto | 90:cb3d968589d8 | 222 | #define BR_SMC_PMPROT_AVLP(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP)) |
Kojto | 90:cb3d968589d8 | 223 | |
Kojto | 90:cb3d968589d8 | 224 | /*! @brief Format value for bitfield SMC_PMPROT_AVLP. */ |
Kojto | 90:cb3d968589d8 | 225 | #define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP) |
Kojto | 90:cb3d968589d8 | 226 | |
Kojto | 90:cb3d968589d8 | 227 | /*! @brief Set the AVLP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 228 | #define BW_SMC_PMPROT_AVLP(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP) = (v)) |
Kojto | 90:cb3d968589d8 | 229 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 230 | |
Kojto | 90:cb3d968589d8 | 231 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 232 | * HW_SMC_PMCTRL - Power Mode Control register |
Kojto | 90:cb3d968589d8 | 233 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 234 | |
Kojto | 90:cb3d968589d8 | 235 | /*! |
Kojto | 90:cb3d968589d8 | 236 | * @brief HW_SMC_PMCTRL - Power Mode Control register (RW) |
Kojto | 90:cb3d968589d8 | 237 | * |
Kojto | 90:cb3d968589d8 | 238 | * Reset value: 0x00U |
Kojto | 90:cb3d968589d8 | 239 | * |
Kojto | 90:cb3d968589d8 | 240 | * The PMCTRL register controls entry into low-power Run and Stop modes, |
Kojto | 90:cb3d968589d8 | 241 | * provided that the selected power mode is allowed via an appropriate setting of the |
Kojto | 90:cb3d968589d8 | 242 | * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by |
Kojto | 90:cb3d968589d8 | 243 | * reset types that trigger Chip POR not VLLS. It is unaffected by reset types |
Kojto | 90:cb3d968589d8 | 244 | * that do not trigger Chip POR not VLLS. See the Reset section details for more |
Kojto | 90:cb3d968589d8 | 245 | * information. |
Kojto | 90:cb3d968589d8 | 246 | */ |
Kojto | 90:cb3d968589d8 | 247 | typedef union _hw_smc_pmctrl |
Kojto | 90:cb3d968589d8 | 248 | { |
Kojto | 90:cb3d968589d8 | 249 | uint8_t U; |
Kojto | 90:cb3d968589d8 | 250 | struct _hw_smc_pmctrl_bitfields |
Kojto | 90:cb3d968589d8 | 251 | { |
Kojto | 90:cb3d968589d8 | 252 | uint8_t STOPM : 3; /*!< [2:0] Stop Mode Control */ |
Kojto | 90:cb3d968589d8 | 253 | uint8_t STOPA : 1; /*!< [3] Stop Aborted */ |
Kojto | 90:cb3d968589d8 | 254 | uint8_t RESERVED0 : 1; /*!< [4] */ |
Kojto | 90:cb3d968589d8 | 255 | uint8_t RUNM : 2; /*!< [6:5] Run Mode Control */ |
Kojto | 90:cb3d968589d8 | 256 | uint8_t LPWUI : 1; /*!< [7] Low-Power Wake Up On Interrupt */ |
Kojto | 90:cb3d968589d8 | 257 | } B; |
Kojto | 90:cb3d968589d8 | 258 | } hw_smc_pmctrl_t; |
Kojto | 90:cb3d968589d8 | 259 | |
Kojto | 90:cb3d968589d8 | 260 | /*! |
Kojto | 90:cb3d968589d8 | 261 | * @name Constants and macros for entire SMC_PMCTRL register |
Kojto | 90:cb3d968589d8 | 262 | */ |
Kojto | 90:cb3d968589d8 | 263 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 264 | #define HW_SMC_PMCTRL_ADDR(x) ((x) + 0x1U) |
Kojto | 90:cb3d968589d8 | 265 | |
Kojto | 90:cb3d968589d8 | 266 | #define HW_SMC_PMCTRL(x) (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 267 | #define HW_SMC_PMCTRL_RD(x) (HW_SMC_PMCTRL(x).U) |
Kojto | 90:cb3d968589d8 | 268 | #define HW_SMC_PMCTRL_WR(x, v) (HW_SMC_PMCTRL(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 269 | #define HW_SMC_PMCTRL_SET(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 270 | #define HW_SMC_PMCTRL_CLR(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 271 | #define HW_SMC_PMCTRL_TOG(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 272 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 273 | |
Kojto | 90:cb3d968589d8 | 274 | /* |
Kojto | 90:cb3d968589d8 | 275 | * Constants & macros for individual SMC_PMCTRL bitfields |
Kojto | 90:cb3d968589d8 | 276 | */ |
Kojto | 90:cb3d968589d8 | 277 | |
Kojto | 90:cb3d968589d8 | 278 | /*! |
Kojto | 90:cb3d968589d8 | 279 | * @name Register SMC_PMCTRL, field STOPM[2:0] (RW) |
Kojto | 90:cb3d968589d8 | 280 | * |
Kojto | 90:cb3d968589d8 | 281 | * When written, controls entry into the selected stop mode when Sleep-Now or |
Kojto | 90:cb3d968589d8 | 282 | * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are |
Kojto | 90:cb3d968589d8 | 283 | * blocked if the protection level has not been enabled using the PMPROT register. |
Kojto | 90:cb3d968589d8 | 284 | * After any system reset, this field is cleared by hardware on any successful write |
Kojto | 90:cb3d968589d8 | 285 | * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL |
Kojto | 90:cb3d968589d8 | 286 | * register is used to further select the particular VLLS submode which will be |
Kojto | 90:cb3d968589d8 | 287 | * entered. |
Kojto | 90:cb3d968589d8 | 288 | * |
Kojto | 90:cb3d968589d8 | 289 | * Values: |
Kojto | 90:cb3d968589d8 | 290 | * - 000 - Normal Stop (STOP) |
Kojto | 90:cb3d968589d8 | 291 | * - 001 - Reserved |
Kojto | 90:cb3d968589d8 | 292 | * - 010 - Very-Low-Power Stop (VLPS) |
Kojto | 90:cb3d968589d8 | 293 | * - 011 - Low-Leakage Stop (LLS) |
Kojto | 90:cb3d968589d8 | 294 | * - 100 - Very-Low-Leakage Stop (VLLSx) |
Kojto | 90:cb3d968589d8 | 295 | * - 101 - Reserved |
Kojto | 90:cb3d968589d8 | 296 | * - 110 - Reseved |
Kojto | 90:cb3d968589d8 | 297 | * - 111 - Reserved |
Kojto | 90:cb3d968589d8 | 298 | */ |
Kojto | 90:cb3d968589d8 | 299 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 300 | #define BP_SMC_PMCTRL_STOPM (0U) /*!< Bit position for SMC_PMCTRL_STOPM. */ |
Kojto | 90:cb3d968589d8 | 301 | #define BM_SMC_PMCTRL_STOPM (0x07U) /*!< Bit mask for SMC_PMCTRL_STOPM. */ |
Kojto | 90:cb3d968589d8 | 302 | #define BS_SMC_PMCTRL_STOPM (3U) /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */ |
Kojto | 90:cb3d968589d8 | 303 | |
Kojto | 90:cb3d968589d8 | 304 | /*! @brief Read current value of the SMC_PMCTRL_STOPM field. */ |
Kojto | 90:cb3d968589d8 | 305 | #define BR_SMC_PMCTRL_STOPM(x) (HW_SMC_PMCTRL(x).B.STOPM) |
Kojto | 90:cb3d968589d8 | 306 | |
Kojto | 90:cb3d968589d8 | 307 | /*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */ |
Kojto | 90:cb3d968589d8 | 308 | #define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM) |
Kojto | 90:cb3d968589d8 | 309 | |
Kojto | 90:cb3d968589d8 | 310 | /*! @brief Set the STOPM field to a new value. */ |
Kojto | 90:cb3d968589d8 | 311 | #define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v))) |
Kojto | 90:cb3d968589d8 | 312 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 313 | |
Kojto | 90:cb3d968589d8 | 314 | /*! |
Kojto | 90:cb3d968589d8 | 315 | * @name Register SMC_PMCTRL, field STOPA[3] (RO) |
Kojto | 90:cb3d968589d8 | 316 | * |
Kojto | 90:cb3d968589d8 | 317 | * When set, this read-only status bit indicates an interrupt or reset occured |
Kojto | 90:cb3d968589d8 | 318 | * during the previous stop mode entry sequence, preventing the system from |
Kojto | 90:cb3d968589d8 | 319 | * entering that mode. This field is cleared by hardware at the beginning of any stop |
Kojto | 90:cb3d968589d8 | 320 | * mode entry sequence and is set if the sequence was aborted. |
Kojto | 90:cb3d968589d8 | 321 | * |
Kojto | 90:cb3d968589d8 | 322 | * Values: |
Kojto | 90:cb3d968589d8 | 323 | * - 0 - The previous stop mode entry was successsful. |
Kojto | 90:cb3d968589d8 | 324 | * - 1 - The previous stop mode entry was aborted. |
Kojto | 90:cb3d968589d8 | 325 | */ |
Kojto | 90:cb3d968589d8 | 326 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 327 | #define BP_SMC_PMCTRL_STOPA (3U) /*!< Bit position for SMC_PMCTRL_STOPA. */ |
Kojto | 90:cb3d968589d8 | 328 | #define BM_SMC_PMCTRL_STOPA (0x08U) /*!< Bit mask for SMC_PMCTRL_STOPA. */ |
Kojto | 90:cb3d968589d8 | 329 | #define BS_SMC_PMCTRL_STOPA (1U) /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */ |
Kojto | 90:cb3d968589d8 | 330 | |
Kojto | 90:cb3d968589d8 | 331 | /*! @brief Read current value of the SMC_PMCTRL_STOPA field. */ |
Kojto | 90:cb3d968589d8 | 332 | #define BR_SMC_PMCTRL_STOPA(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA)) |
Kojto | 90:cb3d968589d8 | 333 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 334 | |
Kojto | 90:cb3d968589d8 | 335 | /*! |
Kojto | 90:cb3d968589d8 | 336 | * @name Register SMC_PMCTRL, field RUNM[6:5] (RW) |
Kojto | 90:cb3d968589d8 | 337 | * |
Kojto | 90:cb3d968589d8 | 338 | * When written, causes entry into the selected run mode. Writes to this field |
Kojto | 90:cb3d968589d8 | 339 | * are blocked if the protection level has not been enabled using the PMPROT |
Kojto | 90:cb3d968589d8 | 340 | * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to |
Kojto | 90:cb3d968589d8 | 341 | * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. |
Kojto | 90:cb3d968589d8 | 342 | * |
Kojto | 90:cb3d968589d8 | 343 | * Values: |
Kojto | 90:cb3d968589d8 | 344 | * - 00 - Normal Run mode (RUN) |
Kojto | 90:cb3d968589d8 | 345 | * - 01 - Reserved |
Kojto | 90:cb3d968589d8 | 346 | * - 10 - Very-Low-Power Run mode (VLPR) |
Kojto | 90:cb3d968589d8 | 347 | * - 11 - Reserved |
Kojto | 90:cb3d968589d8 | 348 | */ |
Kojto | 90:cb3d968589d8 | 349 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 350 | #define BP_SMC_PMCTRL_RUNM (5U) /*!< Bit position for SMC_PMCTRL_RUNM. */ |
Kojto | 90:cb3d968589d8 | 351 | #define BM_SMC_PMCTRL_RUNM (0x60U) /*!< Bit mask for SMC_PMCTRL_RUNM. */ |
Kojto | 90:cb3d968589d8 | 352 | #define BS_SMC_PMCTRL_RUNM (2U) /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */ |
Kojto | 90:cb3d968589d8 | 353 | |
Kojto | 90:cb3d968589d8 | 354 | /*! @brief Read current value of the SMC_PMCTRL_RUNM field. */ |
Kojto | 90:cb3d968589d8 | 355 | #define BR_SMC_PMCTRL_RUNM(x) (HW_SMC_PMCTRL(x).B.RUNM) |
Kojto | 90:cb3d968589d8 | 356 | |
Kojto | 90:cb3d968589d8 | 357 | /*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */ |
Kojto | 90:cb3d968589d8 | 358 | #define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM) |
Kojto | 90:cb3d968589d8 | 359 | |
Kojto | 90:cb3d968589d8 | 360 | /*! @brief Set the RUNM field to a new value. */ |
Kojto | 90:cb3d968589d8 | 361 | #define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v))) |
Kojto | 90:cb3d968589d8 | 362 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 363 | |
Kojto | 90:cb3d968589d8 | 364 | /*! |
Kojto | 90:cb3d968589d8 | 365 | * @name Register SMC_PMCTRL, field LPWUI[7] (RW) |
Kojto | 90:cb3d968589d8 | 366 | * |
Kojto | 90:cb3d968589d8 | 367 | * Causes the SMC to exit to normal RUN mode when any active MCU interrupt |
Kojto | 90:cb3d968589d8 | 368 | * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly |
Kojto | 90:cb3d968589d8 | 369 | * from RUN mode, the SMC will always exit back to normal RUN mode regardless of |
Kojto | 90:cb3d968589d8 | 370 | * the LPWUI setting. LPWUI must be modified only while the system is in RUN |
Kojto | 90:cb3d968589d8 | 371 | * mode, that is, when PMSTAT=RUN. |
Kojto | 90:cb3d968589d8 | 372 | * |
Kojto | 90:cb3d968589d8 | 373 | * Values: |
Kojto | 90:cb3d968589d8 | 374 | * - 0 - The system remains in a VLP mode on an interrupt |
Kojto | 90:cb3d968589d8 | 375 | * - 1 - The system exits to Normal RUN mode on an interrupt |
Kojto | 90:cb3d968589d8 | 376 | */ |
Kojto | 90:cb3d968589d8 | 377 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 378 | #define BP_SMC_PMCTRL_LPWUI (7U) /*!< Bit position for SMC_PMCTRL_LPWUI. */ |
Kojto | 90:cb3d968589d8 | 379 | #define BM_SMC_PMCTRL_LPWUI (0x80U) /*!< Bit mask for SMC_PMCTRL_LPWUI. */ |
Kojto | 90:cb3d968589d8 | 380 | #define BS_SMC_PMCTRL_LPWUI (1U) /*!< Bit field size in bits for SMC_PMCTRL_LPWUI. */ |
Kojto | 90:cb3d968589d8 | 381 | |
Kojto | 90:cb3d968589d8 | 382 | /*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */ |
Kojto | 90:cb3d968589d8 | 383 | #define BR_SMC_PMCTRL_LPWUI(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_LPWUI)) |
Kojto | 90:cb3d968589d8 | 384 | |
Kojto | 90:cb3d968589d8 | 385 | /*! @brief Format value for bitfield SMC_PMCTRL_LPWUI. */ |
Kojto | 90:cb3d968589d8 | 386 | #define BF_SMC_PMCTRL_LPWUI(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_LPWUI) & BM_SMC_PMCTRL_LPWUI) |
Kojto | 90:cb3d968589d8 | 387 | |
Kojto | 90:cb3d968589d8 | 388 | /*! @brief Set the LPWUI field to a new value. */ |
Kojto | 90:cb3d968589d8 | 389 | #define BW_SMC_PMCTRL_LPWUI(x, v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_LPWUI) = (v)) |
Kojto | 90:cb3d968589d8 | 390 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 391 | |
Kojto | 90:cb3d968589d8 | 392 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 393 | * HW_SMC_VLLSCTRL - VLLS Control register |
Kojto | 90:cb3d968589d8 | 394 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 395 | |
Kojto | 90:cb3d968589d8 | 396 | /*! |
Kojto | 90:cb3d968589d8 | 397 | * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW) |
Kojto | 90:cb3d968589d8 | 398 | * |
Kojto | 90:cb3d968589d8 | 399 | * Reset value: 0x03U |
Kojto | 90:cb3d968589d8 | 400 | * |
Kojto | 90:cb3d968589d8 | 401 | * The VLLSCTRL register controls features related to VLLS modes. This register |
Kojto | 90:cb3d968589d8 | 402 | * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not |
Kojto | 90:cb3d968589d8 | 403 | * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See |
Kojto | 90:cb3d968589d8 | 404 | * the Reset section details for more information. |
Kojto | 90:cb3d968589d8 | 405 | */ |
Kojto | 90:cb3d968589d8 | 406 | typedef union _hw_smc_vllsctrl |
Kojto | 90:cb3d968589d8 | 407 | { |
Kojto | 90:cb3d968589d8 | 408 | uint8_t U; |
Kojto | 90:cb3d968589d8 | 409 | struct _hw_smc_vllsctrl_bitfields |
Kojto | 90:cb3d968589d8 | 410 | { |
Kojto | 90:cb3d968589d8 | 411 | uint8_t VLLSM : 3; /*!< [2:0] VLLS Mode Control */ |
Kojto | 90:cb3d968589d8 | 412 | uint8_t RESERVED0 : 2; /*!< [4:3] */ |
Kojto | 90:cb3d968589d8 | 413 | uint8_t PORPO : 1; /*!< [5] POR Power Option */ |
Kojto | 90:cb3d968589d8 | 414 | uint8_t RESERVED1 : 2; /*!< [7:6] */ |
Kojto | 90:cb3d968589d8 | 415 | } B; |
Kojto | 90:cb3d968589d8 | 416 | } hw_smc_vllsctrl_t; |
Kojto | 90:cb3d968589d8 | 417 | |
Kojto | 90:cb3d968589d8 | 418 | /*! |
Kojto | 90:cb3d968589d8 | 419 | * @name Constants and macros for entire SMC_VLLSCTRL register |
Kojto | 90:cb3d968589d8 | 420 | */ |
Kojto | 90:cb3d968589d8 | 421 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 422 | #define HW_SMC_VLLSCTRL_ADDR(x) ((x) + 0x2U) |
Kojto | 90:cb3d968589d8 | 423 | |
Kojto | 90:cb3d968589d8 | 424 | #define HW_SMC_VLLSCTRL(x) (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 425 | #define HW_SMC_VLLSCTRL_RD(x) (HW_SMC_VLLSCTRL(x).U) |
Kojto | 90:cb3d968589d8 | 426 | #define HW_SMC_VLLSCTRL_WR(x, v) (HW_SMC_VLLSCTRL(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 427 | #define HW_SMC_VLLSCTRL_SET(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 428 | #define HW_SMC_VLLSCTRL_CLR(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 429 | #define HW_SMC_VLLSCTRL_TOG(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 430 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 431 | |
Kojto | 90:cb3d968589d8 | 432 | /* |
Kojto | 90:cb3d968589d8 | 433 | * Constants & macros for individual SMC_VLLSCTRL bitfields |
Kojto | 90:cb3d968589d8 | 434 | */ |
Kojto | 90:cb3d968589d8 | 435 | |
Kojto | 90:cb3d968589d8 | 436 | /*! |
Kojto | 90:cb3d968589d8 | 437 | * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW) |
Kojto | 90:cb3d968589d8 | 438 | * |
Kojto | 90:cb3d968589d8 | 439 | * Controls which VLLS sub-mode to enter if STOPM=VLLS. |
Kojto | 90:cb3d968589d8 | 440 | * |
Kojto | 90:cb3d968589d8 | 441 | * Values: |
Kojto | 90:cb3d968589d8 | 442 | * - 000 - VLLS0 |
Kojto | 90:cb3d968589d8 | 443 | * - 001 - VLLS1 |
Kojto | 90:cb3d968589d8 | 444 | * - 010 - VLLS2 |
Kojto | 90:cb3d968589d8 | 445 | * - 011 - VLLS3 |
Kojto | 90:cb3d968589d8 | 446 | * - 100 - Reserved |
Kojto | 90:cb3d968589d8 | 447 | * - 101 - Reserved |
Kojto | 90:cb3d968589d8 | 448 | * - 110 - Reserved |
Kojto | 90:cb3d968589d8 | 449 | * - 111 - Reserved |
Kojto | 90:cb3d968589d8 | 450 | */ |
Kojto | 90:cb3d968589d8 | 451 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 452 | #define BP_SMC_VLLSCTRL_VLLSM (0U) /*!< Bit position for SMC_VLLSCTRL_VLLSM. */ |
Kojto | 90:cb3d968589d8 | 453 | #define BM_SMC_VLLSCTRL_VLLSM (0x07U) /*!< Bit mask for SMC_VLLSCTRL_VLLSM. */ |
Kojto | 90:cb3d968589d8 | 454 | #define BS_SMC_VLLSCTRL_VLLSM (3U) /*!< Bit field size in bits for SMC_VLLSCTRL_VLLSM. */ |
Kojto | 90:cb3d968589d8 | 455 | |
Kojto | 90:cb3d968589d8 | 456 | /*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */ |
Kojto | 90:cb3d968589d8 | 457 | #define BR_SMC_VLLSCTRL_VLLSM(x) (HW_SMC_VLLSCTRL(x).B.VLLSM) |
Kojto | 90:cb3d968589d8 | 458 | |
Kojto | 90:cb3d968589d8 | 459 | /*! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM. */ |
Kojto | 90:cb3d968589d8 | 460 | #define BF_SMC_VLLSCTRL_VLLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_VLLSCTRL_VLLSM) & BM_SMC_VLLSCTRL_VLLSM) |
Kojto | 90:cb3d968589d8 | 461 | |
Kojto | 90:cb3d968589d8 | 462 | /*! @brief Set the VLLSM field to a new value. */ |
Kojto | 90:cb3d968589d8 | 463 | #define BW_SMC_VLLSCTRL_VLLSM(x, v) (HW_SMC_VLLSCTRL_WR(x, (HW_SMC_VLLSCTRL_RD(x) & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v))) |
Kojto | 90:cb3d968589d8 | 464 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 465 | |
Kojto | 90:cb3d968589d8 | 466 | /*! |
Kojto | 90:cb3d968589d8 | 467 | * @name Register SMC_VLLSCTRL, field PORPO[5] (RW) |
Kojto | 90:cb3d968589d8 | 468 | * |
Kojto | 90:cb3d968589d8 | 469 | * Controls whether the POR detect circuit (for brown-out detection) is enabled |
Kojto | 90:cb3d968589d8 | 470 | * in VLLS0 mode. |
Kojto | 90:cb3d968589d8 | 471 | * |
Kojto | 90:cb3d968589d8 | 472 | * Values: |
Kojto | 90:cb3d968589d8 | 473 | * - 0 - POR detect circuit is enabled in VLLS0. |
Kojto | 90:cb3d968589d8 | 474 | * - 1 - POR detect circuit is disabled in VLLS0. |
Kojto | 90:cb3d968589d8 | 475 | */ |
Kojto | 90:cb3d968589d8 | 476 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 477 | #define BP_SMC_VLLSCTRL_PORPO (5U) /*!< Bit position for SMC_VLLSCTRL_PORPO. */ |
Kojto | 90:cb3d968589d8 | 478 | #define BM_SMC_VLLSCTRL_PORPO (0x20U) /*!< Bit mask for SMC_VLLSCTRL_PORPO. */ |
Kojto | 90:cb3d968589d8 | 479 | #define BS_SMC_VLLSCTRL_PORPO (1U) /*!< Bit field size in bits for SMC_VLLSCTRL_PORPO. */ |
Kojto | 90:cb3d968589d8 | 480 | |
Kojto | 90:cb3d968589d8 | 481 | /*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */ |
Kojto | 90:cb3d968589d8 | 482 | #define BR_SMC_VLLSCTRL_PORPO(x) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR(x), BP_SMC_VLLSCTRL_PORPO)) |
Kojto | 90:cb3d968589d8 | 483 | |
Kojto | 90:cb3d968589d8 | 484 | /*! @brief Format value for bitfield SMC_VLLSCTRL_PORPO. */ |
Kojto | 90:cb3d968589d8 | 485 | #define BF_SMC_VLLSCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_VLLSCTRL_PORPO) & BM_SMC_VLLSCTRL_PORPO) |
Kojto | 90:cb3d968589d8 | 486 | |
Kojto | 90:cb3d968589d8 | 487 | /*! @brief Set the PORPO field to a new value. */ |
Kojto | 90:cb3d968589d8 | 488 | #define BW_SMC_VLLSCTRL_PORPO(x, v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR(x), BP_SMC_VLLSCTRL_PORPO) = (v)) |
Kojto | 90:cb3d968589d8 | 489 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 490 | |
Kojto | 90:cb3d968589d8 | 491 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 492 | * HW_SMC_PMSTAT - Power Mode Status register |
Kojto | 90:cb3d968589d8 | 493 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 494 | |
Kojto | 90:cb3d968589d8 | 495 | /*! |
Kojto | 90:cb3d968589d8 | 496 | * @brief HW_SMC_PMSTAT - Power Mode Status register (RO) |
Kojto | 90:cb3d968589d8 | 497 | * |
Kojto | 90:cb3d968589d8 | 498 | * Reset value: 0x01U |
Kojto | 90:cb3d968589d8 | 499 | * |
Kojto | 90:cb3d968589d8 | 500 | * PMSTAT is a read-only, one-hot register which indicates the current power |
Kojto | 90:cb3d968589d8 | 501 | * mode of the system. This register is reset on Chip POR not VLLS and by reset |
Kojto | 90:cb3d968589d8 | 502 | * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not |
Kojto | 90:cb3d968589d8 | 503 | * trigger Chip POR not VLLS. See the Reset section details for more information. |
Kojto | 90:cb3d968589d8 | 504 | */ |
Kojto | 90:cb3d968589d8 | 505 | typedef union _hw_smc_pmstat |
Kojto | 90:cb3d968589d8 | 506 | { |
Kojto | 90:cb3d968589d8 | 507 | uint8_t U; |
Kojto | 90:cb3d968589d8 | 508 | struct _hw_smc_pmstat_bitfields |
Kojto | 90:cb3d968589d8 | 509 | { |
Kojto | 90:cb3d968589d8 | 510 | uint8_t PMSTAT : 7; /*!< [6:0] */ |
Kojto | 90:cb3d968589d8 | 511 | uint8_t RESERVED0 : 1; /*!< [7] */ |
Kojto | 90:cb3d968589d8 | 512 | } B; |
Kojto | 90:cb3d968589d8 | 513 | } hw_smc_pmstat_t; |
Kojto | 90:cb3d968589d8 | 514 | |
Kojto | 90:cb3d968589d8 | 515 | /*! |
Kojto | 90:cb3d968589d8 | 516 | * @name Constants and macros for entire SMC_PMSTAT register |
Kojto | 90:cb3d968589d8 | 517 | */ |
Kojto | 90:cb3d968589d8 | 518 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 519 | #define HW_SMC_PMSTAT_ADDR(x) ((x) + 0x3U) |
Kojto | 90:cb3d968589d8 | 520 | |
Kojto | 90:cb3d968589d8 | 521 | #define HW_SMC_PMSTAT(x) (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 522 | #define HW_SMC_PMSTAT_RD(x) (HW_SMC_PMSTAT(x).U) |
Kojto | 90:cb3d968589d8 | 523 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 524 | |
Kojto | 90:cb3d968589d8 | 525 | /* |
Kojto | 90:cb3d968589d8 | 526 | * Constants & macros for individual SMC_PMSTAT bitfields |
Kojto | 90:cb3d968589d8 | 527 | */ |
Kojto | 90:cb3d968589d8 | 528 | |
Kojto | 90:cb3d968589d8 | 529 | /*! |
Kojto | 90:cb3d968589d8 | 530 | * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO) |
Kojto | 90:cb3d968589d8 | 531 | * |
Kojto | 90:cb3d968589d8 | 532 | * When debug is enabled, the PMSTAT will not update to STOP or VLPS |
Kojto | 90:cb3d968589d8 | 533 | */ |
Kojto | 90:cb3d968589d8 | 534 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 535 | #define BP_SMC_PMSTAT_PMSTAT (0U) /*!< Bit position for SMC_PMSTAT_PMSTAT. */ |
Kojto | 90:cb3d968589d8 | 536 | #define BM_SMC_PMSTAT_PMSTAT (0x7FU) /*!< Bit mask for SMC_PMSTAT_PMSTAT. */ |
Kojto | 90:cb3d968589d8 | 537 | #define BS_SMC_PMSTAT_PMSTAT (7U) /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */ |
Kojto | 90:cb3d968589d8 | 538 | |
Kojto | 90:cb3d968589d8 | 539 | /*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */ |
Kojto | 90:cb3d968589d8 | 540 | #define BR_SMC_PMSTAT_PMSTAT(x) (HW_SMC_PMSTAT(x).B.PMSTAT) |
Kojto | 90:cb3d968589d8 | 541 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 542 | |
Kojto | 90:cb3d968589d8 | 543 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 544 | * hw_smc_t - module struct |
Kojto | 90:cb3d968589d8 | 545 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 546 | /*! |
Kojto | 90:cb3d968589d8 | 547 | * @brief All SMC module registers. |
Kojto | 90:cb3d968589d8 | 548 | */ |
Kojto | 90:cb3d968589d8 | 549 | #pragma pack(1) |
Kojto | 90:cb3d968589d8 | 550 | typedef struct _hw_smc |
Kojto | 90:cb3d968589d8 | 551 | { |
Kojto | 90:cb3d968589d8 | 552 | __IO hw_smc_pmprot_t PMPROT; /*!< [0x0] Power Mode Protection register */ |
Kojto | 90:cb3d968589d8 | 553 | __IO hw_smc_pmctrl_t PMCTRL; /*!< [0x1] Power Mode Control register */ |
Kojto | 90:cb3d968589d8 | 554 | __IO hw_smc_vllsctrl_t VLLSCTRL; /*!< [0x2] VLLS Control register */ |
Kojto | 90:cb3d968589d8 | 555 | __I hw_smc_pmstat_t PMSTAT; /*!< [0x3] Power Mode Status register */ |
Kojto | 90:cb3d968589d8 | 556 | } hw_smc_t; |
Kojto | 90:cb3d968589d8 | 557 | #pragma pack() |
Kojto | 90:cb3d968589d8 | 558 | |
Kojto | 90:cb3d968589d8 | 559 | /*! @brief Macro to access all SMC registers. */ |
Kojto | 90:cb3d968589d8 | 560 | /*! @param x SMC module instance base address. */ |
Kojto | 90:cb3d968589d8 | 561 | /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
Kojto | 90:cb3d968589d8 | 562 | * use the '&' operator, like <code>&HW_SMC(SMC_BASE)</code>. */ |
Kojto | 90:cb3d968589d8 | 563 | #define HW_SMC(x) (*(hw_smc_t *)(x)) |
Kojto | 90:cb3d968589d8 | 564 | |
Kojto | 90:cb3d968589d8 | 565 | #endif /* __HW_SMC_REGISTERS_H__ */ |
Kojto | 90:cb3d968589d8 | 566 | /* EOF */ |