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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_pit.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_PIT_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_PIT_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 PIT
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * Periodic Interrupt Timer
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_PIT_MCR - PIT Module Control Register
Kojto 90:cb3d968589d8 93 * - HW_PIT_LDVALn - Timer Load Value Register
Kojto 90:cb3d968589d8 94 * - HW_PIT_CVALn - Current Timer Value Register
Kojto 90:cb3d968589d8 95 * - HW_PIT_TCTRLn - Timer Control Register
Kojto 90:cb3d968589d8 96 * - HW_PIT_TFLGn - Timer Flag Register
Kojto 90:cb3d968589d8 97 *
Kojto 90:cb3d968589d8 98 * - hw_pit_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 99 */
Kojto 90:cb3d968589d8 100
Kojto 90:cb3d968589d8 101 #define HW_PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
Kojto 90:cb3d968589d8 102
Kojto 90:cb3d968589d8 103 /*******************************************************************************
Kojto 90:cb3d968589d8 104 * HW_PIT_MCR - PIT Module Control Register
Kojto 90:cb3d968589d8 105 ******************************************************************************/
Kojto 90:cb3d968589d8 106
Kojto 90:cb3d968589d8 107 /*!
Kojto 90:cb3d968589d8 108 * @brief HW_PIT_MCR - PIT Module Control Register (RW)
Kojto 90:cb3d968589d8 109 *
Kojto 90:cb3d968589d8 110 * Reset value: 0x00000006U
Kojto 90:cb3d968589d8 111 *
Kojto 90:cb3d968589d8 112 * This register enables or disables the PIT timer clocks and controls the
Kojto 90:cb3d968589d8 113 * timers when the PIT enters the Debug mode.
Kojto 90:cb3d968589d8 114 */
Kojto 90:cb3d968589d8 115 typedef union _hw_pit_mcr
Kojto 90:cb3d968589d8 116 {
Kojto 90:cb3d968589d8 117 uint32_t U;
Kojto 90:cb3d968589d8 118 struct _hw_pit_mcr_bitfields
Kojto 90:cb3d968589d8 119 {
Kojto 90:cb3d968589d8 120 uint32_t FRZ : 1; /*!< [0] Freeze */
Kojto 90:cb3d968589d8 121 uint32_t MDIS : 1; /*!< [1] Module Disable - (PIT section) */
Kojto 90:cb3d968589d8 122 uint32_t RESERVED0 : 30; /*!< [31:2] */
Kojto 90:cb3d968589d8 123 } B;
Kojto 90:cb3d968589d8 124 } hw_pit_mcr_t;
Kojto 90:cb3d968589d8 125
Kojto 90:cb3d968589d8 126 /*!
Kojto 90:cb3d968589d8 127 * @name Constants and macros for entire PIT_MCR register
Kojto 90:cb3d968589d8 128 */
Kojto 90:cb3d968589d8 129 /*@{*/
Kojto 90:cb3d968589d8 130 #define HW_PIT_MCR_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 131
Kojto 90:cb3d968589d8 132 #define HW_PIT_MCR(x) (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR(x))
Kojto 90:cb3d968589d8 133 #define HW_PIT_MCR_RD(x) (HW_PIT_MCR(x).U)
Kojto 90:cb3d968589d8 134 #define HW_PIT_MCR_WR(x, v) (HW_PIT_MCR(x).U = (v))
Kojto 90:cb3d968589d8 135 #define HW_PIT_MCR_SET(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) | (v)))
Kojto 90:cb3d968589d8 136 #define HW_PIT_MCR_CLR(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 137 #define HW_PIT_MCR_TOG(x, v) (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 138 /*@}*/
Kojto 90:cb3d968589d8 139
Kojto 90:cb3d968589d8 140 /*
Kojto 90:cb3d968589d8 141 * Constants & macros for individual PIT_MCR bitfields
Kojto 90:cb3d968589d8 142 */
Kojto 90:cb3d968589d8 143
Kojto 90:cb3d968589d8 144 /*!
Kojto 90:cb3d968589d8 145 * @name Register PIT_MCR, field FRZ[0] (RW)
Kojto 90:cb3d968589d8 146 *
Kojto 90:cb3d968589d8 147 * Allows the timers to be stopped when the device enters the Debug mode.
Kojto 90:cb3d968589d8 148 *
Kojto 90:cb3d968589d8 149 * Values:
Kojto 90:cb3d968589d8 150 * - 0 - Timers continue to run in Debug mode.
Kojto 90:cb3d968589d8 151 * - 1 - Timers are stopped in Debug mode.
Kojto 90:cb3d968589d8 152 */
Kojto 90:cb3d968589d8 153 /*@{*/
Kojto 90:cb3d968589d8 154 #define BP_PIT_MCR_FRZ (0U) /*!< Bit position for PIT_MCR_FRZ. */
Kojto 90:cb3d968589d8 155 #define BM_PIT_MCR_FRZ (0x00000001U) /*!< Bit mask for PIT_MCR_FRZ. */
Kojto 90:cb3d968589d8 156 #define BS_PIT_MCR_FRZ (1U) /*!< Bit field size in bits for PIT_MCR_FRZ. */
Kojto 90:cb3d968589d8 157
Kojto 90:cb3d968589d8 158 /*! @brief Read current value of the PIT_MCR_FRZ field. */
Kojto 90:cb3d968589d8 159 #define BR_PIT_MCR_FRZ(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ))
Kojto 90:cb3d968589d8 160
Kojto 90:cb3d968589d8 161 /*! @brief Format value for bitfield PIT_MCR_FRZ. */
Kojto 90:cb3d968589d8 162 #define BF_PIT_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_FRZ) & BM_PIT_MCR_FRZ)
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 /*! @brief Set the FRZ field to a new value. */
Kojto 90:cb3d968589d8 165 #define BW_PIT_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ) = (v))
Kojto 90:cb3d968589d8 166 /*@}*/
Kojto 90:cb3d968589d8 167
Kojto 90:cb3d968589d8 168 /*!
Kojto 90:cb3d968589d8 169 * @name Register PIT_MCR, field MDIS[1] (RW)
Kojto 90:cb3d968589d8 170 *
Kojto 90:cb3d968589d8 171 * Disables the standard timers. This field must be enabled before any other
Kojto 90:cb3d968589d8 172 * setup is done.
Kojto 90:cb3d968589d8 173 *
Kojto 90:cb3d968589d8 174 * Values:
Kojto 90:cb3d968589d8 175 * - 0 - Clock for standard PIT timers is enabled.
Kojto 90:cb3d968589d8 176 * - 1 - Clock for standard PIT timers is disabled.
Kojto 90:cb3d968589d8 177 */
Kojto 90:cb3d968589d8 178 /*@{*/
Kojto 90:cb3d968589d8 179 #define BP_PIT_MCR_MDIS (1U) /*!< Bit position for PIT_MCR_MDIS. */
Kojto 90:cb3d968589d8 180 #define BM_PIT_MCR_MDIS (0x00000002U) /*!< Bit mask for PIT_MCR_MDIS. */
Kojto 90:cb3d968589d8 181 #define BS_PIT_MCR_MDIS (1U) /*!< Bit field size in bits for PIT_MCR_MDIS. */
Kojto 90:cb3d968589d8 182
Kojto 90:cb3d968589d8 183 /*! @brief Read current value of the PIT_MCR_MDIS field. */
Kojto 90:cb3d968589d8 184 #define BR_PIT_MCR_MDIS(x) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS))
Kojto 90:cb3d968589d8 185
Kojto 90:cb3d968589d8 186 /*! @brief Format value for bitfield PIT_MCR_MDIS. */
Kojto 90:cb3d968589d8 187 #define BF_PIT_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_MDIS) & BM_PIT_MCR_MDIS)
Kojto 90:cb3d968589d8 188
Kojto 90:cb3d968589d8 189 /*! @brief Set the MDIS field to a new value. */
Kojto 90:cb3d968589d8 190 #define BW_PIT_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS) = (v))
Kojto 90:cb3d968589d8 191 /*@}*/
Kojto 90:cb3d968589d8 192
Kojto 90:cb3d968589d8 193 /*******************************************************************************
Kojto 90:cb3d968589d8 194 * HW_PIT_LDVALn - Timer Load Value Register
Kojto 90:cb3d968589d8 195 ******************************************************************************/
Kojto 90:cb3d968589d8 196
Kojto 90:cb3d968589d8 197 /*!
Kojto 90:cb3d968589d8 198 * @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
Kojto 90:cb3d968589d8 199 *
Kojto 90:cb3d968589d8 200 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 201 *
Kojto 90:cb3d968589d8 202 * These registers select the timeout period for the timer interrupts.
Kojto 90:cb3d968589d8 203 */
Kojto 90:cb3d968589d8 204 typedef union _hw_pit_ldvaln
Kojto 90:cb3d968589d8 205 {
Kojto 90:cb3d968589d8 206 uint32_t U;
Kojto 90:cb3d968589d8 207 struct _hw_pit_ldvaln_bitfields
Kojto 90:cb3d968589d8 208 {
Kojto 90:cb3d968589d8 209 uint32_t TSV : 32; /*!< [31:0] Timer Start Value */
Kojto 90:cb3d968589d8 210 } B;
Kojto 90:cb3d968589d8 211 } hw_pit_ldvaln_t;
Kojto 90:cb3d968589d8 212
Kojto 90:cb3d968589d8 213 /*!
Kojto 90:cb3d968589d8 214 * @name Constants and macros for entire PIT_LDVALn register
Kojto 90:cb3d968589d8 215 */
Kojto 90:cb3d968589d8 216 /*@{*/
Kojto 90:cb3d968589d8 217 #define HW_PIT_LDVALn_COUNT (4U)
Kojto 90:cb3d968589d8 218
Kojto 90:cb3d968589d8 219 #define HW_PIT_LDVALn_ADDR(x, n) ((x) + 0x100U + (0x10U * (n)))
Kojto 90:cb3d968589d8 220
Kojto 90:cb3d968589d8 221 #define HW_PIT_LDVALn(x, n) (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(x, n))
Kojto 90:cb3d968589d8 222 #define HW_PIT_LDVALn_RD(x, n) (HW_PIT_LDVALn(x, n).U)
Kojto 90:cb3d968589d8 223 #define HW_PIT_LDVALn_WR(x, n, v) (HW_PIT_LDVALn(x, n).U = (v))
Kojto 90:cb3d968589d8 224 #define HW_PIT_LDVALn_SET(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 225 #define HW_PIT_LDVALn_CLR(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 226 #define HW_PIT_LDVALn_TOG(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 227 /*@}*/
Kojto 90:cb3d968589d8 228
Kojto 90:cb3d968589d8 229 /*
Kojto 90:cb3d968589d8 230 * Constants & macros for individual PIT_LDVALn bitfields
Kojto 90:cb3d968589d8 231 */
Kojto 90:cb3d968589d8 232
Kojto 90:cb3d968589d8 233 /*!
Kojto 90:cb3d968589d8 234 * @name Register PIT_LDVALn, field TSV[31:0] (RW)
Kojto 90:cb3d968589d8 235 *
Kojto 90:cb3d968589d8 236 * Sets the timer start value. The timer will count down until it reaches 0,
Kojto 90:cb3d968589d8 237 * then it will generate an interrupt and load this register value again. Writing a
Kojto 90:cb3d968589d8 238 * new value to this register will not restart the timer; instead the value will
Kojto 90:cb3d968589d8 239 * be loaded after the timer expires. To abort the current cycle and start a
Kojto 90:cb3d968589d8 240 * timer period with the new value, the timer must be disabled and enabled again.
Kojto 90:cb3d968589d8 241 */
Kojto 90:cb3d968589d8 242 /*@{*/
Kojto 90:cb3d968589d8 243 #define BP_PIT_LDVALn_TSV (0U) /*!< Bit position for PIT_LDVALn_TSV. */
Kojto 90:cb3d968589d8 244 #define BM_PIT_LDVALn_TSV (0xFFFFFFFFU) /*!< Bit mask for PIT_LDVALn_TSV. */
Kojto 90:cb3d968589d8 245 #define BS_PIT_LDVALn_TSV (32U) /*!< Bit field size in bits for PIT_LDVALn_TSV. */
Kojto 90:cb3d968589d8 246
Kojto 90:cb3d968589d8 247 /*! @brief Read current value of the PIT_LDVALn_TSV field. */
Kojto 90:cb3d968589d8 248 #define BR_PIT_LDVALn_TSV(x, n) (HW_PIT_LDVALn(x, n).U)
Kojto 90:cb3d968589d8 249
Kojto 90:cb3d968589d8 250 /*! @brief Format value for bitfield PIT_LDVALn_TSV. */
Kojto 90:cb3d968589d8 251 #define BF_PIT_LDVALn_TSV(v) ((uint32_t)((uint32_t)(v) << BP_PIT_LDVALn_TSV) & BM_PIT_LDVALn_TSV)
Kojto 90:cb3d968589d8 252
Kojto 90:cb3d968589d8 253 /*! @brief Set the TSV field to a new value. */
Kojto 90:cb3d968589d8 254 #define BW_PIT_LDVALn_TSV(x, n, v) (HW_PIT_LDVALn_WR(x, n, v))
Kojto 90:cb3d968589d8 255 /*@}*/
Kojto 90:cb3d968589d8 256 /*******************************************************************************
Kojto 90:cb3d968589d8 257 * HW_PIT_CVALn - Current Timer Value Register
Kojto 90:cb3d968589d8 258 ******************************************************************************/
Kojto 90:cb3d968589d8 259
Kojto 90:cb3d968589d8 260 /*!
Kojto 90:cb3d968589d8 261 * @brief HW_PIT_CVALn - Current Timer Value Register (RO)
Kojto 90:cb3d968589d8 262 *
Kojto 90:cb3d968589d8 263 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 264 *
Kojto 90:cb3d968589d8 265 * These registers indicate the current timer position.
Kojto 90:cb3d968589d8 266 */
Kojto 90:cb3d968589d8 267 typedef union _hw_pit_cvaln
Kojto 90:cb3d968589d8 268 {
Kojto 90:cb3d968589d8 269 uint32_t U;
Kojto 90:cb3d968589d8 270 struct _hw_pit_cvaln_bitfields
Kojto 90:cb3d968589d8 271 {
Kojto 90:cb3d968589d8 272 uint32_t TVL : 32; /*!< [31:0] Current Timer Value */
Kojto 90:cb3d968589d8 273 } B;
Kojto 90:cb3d968589d8 274 } hw_pit_cvaln_t;
Kojto 90:cb3d968589d8 275
Kojto 90:cb3d968589d8 276 /*!
Kojto 90:cb3d968589d8 277 * @name Constants and macros for entire PIT_CVALn register
Kojto 90:cb3d968589d8 278 */
Kojto 90:cb3d968589d8 279 /*@{*/
Kojto 90:cb3d968589d8 280 #define HW_PIT_CVALn_COUNT (4U)
Kojto 90:cb3d968589d8 281
Kojto 90:cb3d968589d8 282 #define HW_PIT_CVALn_ADDR(x, n) ((x) + 0x104U + (0x10U * (n)))
Kojto 90:cb3d968589d8 283
Kojto 90:cb3d968589d8 284 #define HW_PIT_CVALn(x, n) (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(x, n))
Kojto 90:cb3d968589d8 285 #define HW_PIT_CVALn_RD(x, n) (HW_PIT_CVALn(x, n).U)
Kojto 90:cb3d968589d8 286 /*@}*/
Kojto 90:cb3d968589d8 287
Kojto 90:cb3d968589d8 288 /*
Kojto 90:cb3d968589d8 289 * Constants & macros for individual PIT_CVALn bitfields
Kojto 90:cb3d968589d8 290 */
Kojto 90:cb3d968589d8 291
Kojto 90:cb3d968589d8 292 /*!
Kojto 90:cb3d968589d8 293 * @name Register PIT_CVALn, field TVL[31:0] (RO)
Kojto 90:cb3d968589d8 294 *
Kojto 90:cb3d968589d8 295 * Represents the current timer value, if the timer is enabled. If the timer is
Kojto 90:cb3d968589d8 296 * disabled, do not use this field as its value is unreliable. The timer uses a
Kojto 90:cb3d968589d8 297 * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
Kojto 90:cb3d968589d8 298 */
Kojto 90:cb3d968589d8 299 /*@{*/
Kojto 90:cb3d968589d8 300 #define BP_PIT_CVALn_TVL (0U) /*!< Bit position for PIT_CVALn_TVL. */
Kojto 90:cb3d968589d8 301 #define BM_PIT_CVALn_TVL (0xFFFFFFFFU) /*!< Bit mask for PIT_CVALn_TVL. */
Kojto 90:cb3d968589d8 302 #define BS_PIT_CVALn_TVL (32U) /*!< Bit field size in bits for PIT_CVALn_TVL. */
Kojto 90:cb3d968589d8 303
Kojto 90:cb3d968589d8 304 /*! @brief Read current value of the PIT_CVALn_TVL field. */
Kojto 90:cb3d968589d8 305 #define BR_PIT_CVALn_TVL(x, n) (HW_PIT_CVALn(x, n).U)
Kojto 90:cb3d968589d8 306 /*@}*/
Kojto 90:cb3d968589d8 307 /*******************************************************************************
Kojto 90:cb3d968589d8 308 * HW_PIT_TCTRLn - Timer Control Register
Kojto 90:cb3d968589d8 309 ******************************************************************************/
Kojto 90:cb3d968589d8 310
Kojto 90:cb3d968589d8 311 /*!
Kojto 90:cb3d968589d8 312 * @brief HW_PIT_TCTRLn - Timer Control Register (RW)
Kojto 90:cb3d968589d8 313 *
Kojto 90:cb3d968589d8 314 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 315 *
Kojto 90:cb3d968589d8 316 * These registers contain the control bits for each timer.
Kojto 90:cb3d968589d8 317 */
Kojto 90:cb3d968589d8 318 typedef union _hw_pit_tctrln
Kojto 90:cb3d968589d8 319 {
Kojto 90:cb3d968589d8 320 uint32_t U;
Kojto 90:cb3d968589d8 321 struct _hw_pit_tctrln_bitfields
Kojto 90:cb3d968589d8 322 {
Kojto 90:cb3d968589d8 323 uint32_t TEN : 1; /*!< [0] Timer Enable */
Kojto 90:cb3d968589d8 324 uint32_t TIE : 1; /*!< [1] Timer Interrupt Enable */
Kojto 90:cb3d968589d8 325 uint32_t CHN : 1; /*!< [2] Chain Mode */
Kojto 90:cb3d968589d8 326 uint32_t RESERVED0 : 29; /*!< [31:3] */
Kojto 90:cb3d968589d8 327 } B;
Kojto 90:cb3d968589d8 328 } hw_pit_tctrln_t;
Kojto 90:cb3d968589d8 329
Kojto 90:cb3d968589d8 330 /*!
Kojto 90:cb3d968589d8 331 * @name Constants and macros for entire PIT_TCTRLn register
Kojto 90:cb3d968589d8 332 */
Kojto 90:cb3d968589d8 333 /*@{*/
Kojto 90:cb3d968589d8 334 #define HW_PIT_TCTRLn_COUNT (4U)
Kojto 90:cb3d968589d8 335
Kojto 90:cb3d968589d8 336 #define HW_PIT_TCTRLn_ADDR(x, n) ((x) + 0x108U + (0x10U * (n)))
Kojto 90:cb3d968589d8 337
Kojto 90:cb3d968589d8 338 #define HW_PIT_TCTRLn(x, n) (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(x, n))
Kojto 90:cb3d968589d8 339 #define HW_PIT_TCTRLn_RD(x, n) (HW_PIT_TCTRLn(x, n).U)
Kojto 90:cb3d968589d8 340 #define HW_PIT_TCTRLn_WR(x, n, v) (HW_PIT_TCTRLn(x, n).U = (v))
Kojto 90:cb3d968589d8 341 #define HW_PIT_TCTRLn_SET(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 342 #define HW_PIT_TCTRLn_CLR(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 343 #define HW_PIT_TCTRLn_TOG(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 344 /*@}*/
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 /*
Kojto 90:cb3d968589d8 347 * Constants & macros for individual PIT_TCTRLn bitfields
Kojto 90:cb3d968589d8 348 */
Kojto 90:cb3d968589d8 349
Kojto 90:cb3d968589d8 350 /*!
Kojto 90:cb3d968589d8 351 * @name Register PIT_TCTRLn, field TEN[0] (RW)
Kojto 90:cb3d968589d8 352 *
Kojto 90:cb3d968589d8 353 * Enables or disables the timer.
Kojto 90:cb3d968589d8 354 *
Kojto 90:cb3d968589d8 355 * Values:
Kojto 90:cb3d968589d8 356 * - 0 - Timer n is disabled.
Kojto 90:cb3d968589d8 357 * - 1 - Timer n is enabled.
Kojto 90:cb3d968589d8 358 */
Kojto 90:cb3d968589d8 359 /*@{*/
Kojto 90:cb3d968589d8 360 #define BP_PIT_TCTRLn_TEN (0U) /*!< Bit position for PIT_TCTRLn_TEN. */
Kojto 90:cb3d968589d8 361 #define BM_PIT_TCTRLn_TEN (0x00000001U) /*!< Bit mask for PIT_TCTRLn_TEN. */
Kojto 90:cb3d968589d8 362 #define BS_PIT_TCTRLn_TEN (1U) /*!< Bit field size in bits for PIT_TCTRLn_TEN. */
Kojto 90:cb3d968589d8 363
Kojto 90:cb3d968589d8 364 /*! @brief Read current value of the PIT_TCTRLn_TEN field. */
Kojto 90:cb3d968589d8 365 #define BR_PIT_TCTRLn_TEN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN))
Kojto 90:cb3d968589d8 366
Kojto 90:cb3d968589d8 367 /*! @brief Format value for bitfield PIT_TCTRLn_TEN. */
Kojto 90:cb3d968589d8 368 #define BF_PIT_TCTRLn_TEN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TEN) & BM_PIT_TCTRLn_TEN)
Kojto 90:cb3d968589d8 369
Kojto 90:cb3d968589d8 370 /*! @brief Set the TEN field to a new value. */
Kojto 90:cb3d968589d8 371 #define BW_PIT_TCTRLn_TEN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN) = (v))
Kojto 90:cb3d968589d8 372 /*@}*/
Kojto 90:cb3d968589d8 373
Kojto 90:cb3d968589d8 374 /*!
Kojto 90:cb3d968589d8 375 * @name Register PIT_TCTRLn, field TIE[1] (RW)
Kojto 90:cb3d968589d8 376 *
Kojto 90:cb3d968589d8 377 * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
Kojto 90:cb3d968589d8 378 * will immediately cause an interrupt event. To avoid this, the associated
Kojto 90:cb3d968589d8 379 * TFLGn[TIF] must be cleared first.
Kojto 90:cb3d968589d8 380 *
Kojto 90:cb3d968589d8 381 * Values:
Kojto 90:cb3d968589d8 382 * - 0 - Interrupt requests from Timer n are disabled.
Kojto 90:cb3d968589d8 383 * - 1 - Interrupt will be requested whenever TIF is set.
Kojto 90:cb3d968589d8 384 */
Kojto 90:cb3d968589d8 385 /*@{*/
Kojto 90:cb3d968589d8 386 #define BP_PIT_TCTRLn_TIE (1U) /*!< Bit position for PIT_TCTRLn_TIE. */
Kojto 90:cb3d968589d8 387 #define BM_PIT_TCTRLn_TIE (0x00000002U) /*!< Bit mask for PIT_TCTRLn_TIE. */
Kojto 90:cb3d968589d8 388 #define BS_PIT_TCTRLn_TIE (1U) /*!< Bit field size in bits for PIT_TCTRLn_TIE. */
Kojto 90:cb3d968589d8 389
Kojto 90:cb3d968589d8 390 /*! @brief Read current value of the PIT_TCTRLn_TIE field. */
Kojto 90:cb3d968589d8 391 #define BR_PIT_TCTRLn_TIE(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE))
Kojto 90:cb3d968589d8 392
Kojto 90:cb3d968589d8 393 /*! @brief Format value for bitfield PIT_TCTRLn_TIE. */
Kojto 90:cb3d968589d8 394 #define BF_PIT_TCTRLn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TIE) & BM_PIT_TCTRLn_TIE)
Kojto 90:cb3d968589d8 395
Kojto 90:cb3d968589d8 396 /*! @brief Set the TIE field to a new value. */
Kojto 90:cb3d968589d8 397 #define BW_PIT_TCTRLn_TIE(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE) = (v))
Kojto 90:cb3d968589d8 398 /*@}*/
Kojto 90:cb3d968589d8 399
Kojto 90:cb3d968589d8 400 /*!
Kojto 90:cb3d968589d8 401 * @name Register PIT_TCTRLn, field CHN[2] (RW)
Kojto 90:cb3d968589d8 402 *
Kojto 90:cb3d968589d8 403 * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
Kojto 90:cb3d968589d8 404 * Timer 0 cannot be chained.
Kojto 90:cb3d968589d8 405 *
Kojto 90:cb3d968589d8 406 * Values:
Kojto 90:cb3d968589d8 407 * - 0 - Timer is not chained.
Kojto 90:cb3d968589d8 408 * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
Kojto 90:cb3d968589d8 409 * field is set, Timer 2 is chained to Timer 1.
Kojto 90:cb3d968589d8 410 */
Kojto 90:cb3d968589d8 411 /*@{*/
Kojto 90:cb3d968589d8 412 #define BP_PIT_TCTRLn_CHN (2U) /*!< Bit position for PIT_TCTRLn_CHN. */
Kojto 90:cb3d968589d8 413 #define BM_PIT_TCTRLn_CHN (0x00000004U) /*!< Bit mask for PIT_TCTRLn_CHN. */
Kojto 90:cb3d968589d8 414 #define BS_PIT_TCTRLn_CHN (1U) /*!< Bit field size in bits for PIT_TCTRLn_CHN. */
Kojto 90:cb3d968589d8 415
Kojto 90:cb3d968589d8 416 /*! @brief Read current value of the PIT_TCTRLn_CHN field. */
Kojto 90:cb3d968589d8 417 #define BR_PIT_TCTRLn_CHN(x, n) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN))
Kojto 90:cb3d968589d8 418
Kojto 90:cb3d968589d8 419 /*! @brief Format value for bitfield PIT_TCTRLn_CHN. */
Kojto 90:cb3d968589d8 420 #define BF_PIT_TCTRLn_CHN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_CHN) & BM_PIT_TCTRLn_CHN)
Kojto 90:cb3d968589d8 421
Kojto 90:cb3d968589d8 422 /*! @brief Set the CHN field to a new value. */
Kojto 90:cb3d968589d8 423 #define BW_PIT_TCTRLn_CHN(x, n, v) (BITBAND_ACCESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN) = (v))
Kojto 90:cb3d968589d8 424 /*@}*/
Kojto 90:cb3d968589d8 425 /*******************************************************************************
Kojto 90:cb3d968589d8 426 * HW_PIT_TFLGn - Timer Flag Register
Kojto 90:cb3d968589d8 427 ******************************************************************************/
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 /*!
Kojto 90:cb3d968589d8 430 * @brief HW_PIT_TFLGn - Timer Flag Register (RW)
Kojto 90:cb3d968589d8 431 *
Kojto 90:cb3d968589d8 432 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 433 *
Kojto 90:cb3d968589d8 434 * These registers hold the PIT interrupt flags.
Kojto 90:cb3d968589d8 435 */
Kojto 90:cb3d968589d8 436 typedef union _hw_pit_tflgn
Kojto 90:cb3d968589d8 437 {
Kojto 90:cb3d968589d8 438 uint32_t U;
Kojto 90:cb3d968589d8 439 struct _hw_pit_tflgn_bitfields
Kojto 90:cb3d968589d8 440 {
Kojto 90:cb3d968589d8 441 uint32_t TIF : 1; /*!< [0] Timer Interrupt Flag */
Kojto 90:cb3d968589d8 442 uint32_t RESERVED0 : 31; /*!< [31:1] */
Kojto 90:cb3d968589d8 443 } B;
Kojto 90:cb3d968589d8 444 } hw_pit_tflgn_t;
Kojto 90:cb3d968589d8 445
Kojto 90:cb3d968589d8 446 /*!
Kojto 90:cb3d968589d8 447 * @name Constants and macros for entire PIT_TFLGn register
Kojto 90:cb3d968589d8 448 */
Kojto 90:cb3d968589d8 449 /*@{*/
Kojto 90:cb3d968589d8 450 #define HW_PIT_TFLGn_COUNT (4U)
Kojto 90:cb3d968589d8 451
Kojto 90:cb3d968589d8 452 #define HW_PIT_TFLGn_ADDR(x, n) ((x) + 0x10CU + (0x10U * (n)))
Kojto 90:cb3d968589d8 453
Kojto 90:cb3d968589d8 454 #define HW_PIT_TFLGn(x, n) (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(x, n))
Kojto 90:cb3d968589d8 455 #define HW_PIT_TFLGn_RD(x, n) (HW_PIT_TFLGn(x, n).U)
Kojto 90:cb3d968589d8 456 #define HW_PIT_TFLGn_WR(x, n, v) (HW_PIT_TFLGn(x, n).U = (v))
Kojto 90:cb3d968589d8 457 #define HW_PIT_TFLGn_SET(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 458 #define HW_PIT_TFLGn_CLR(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 459 #define HW_PIT_TFLGn_TOG(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 460 /*@}*/
Kojto 90:cb3d968589d8 461
Kojto 90:cb3d968589d8 462 /*
Kojto 90:cb3d968589d8 463 * Constants & macros for individual PIT_TFLGn bitfields
Kojto 90:cb3d968589d8 464 */
Kojto 90:cb3d968589d8 465
Kojto 90:cb3d968589d8 466 /*!
Kojto 90:cb3d968589d8 467 * @name Register PIT_TFLGn, field TIF[0] (W1C)
Kojto 90:cb3d968589d8 468 *
Kojto 90:cb3d968589d8 469 * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
Kojto 90:cb3d968589d8 470 * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
Kojto 90:cb3d968589d8 471 * interrupt request.
Kojto 90:cb3d968589d8 472 *
Kojto 90:cb3d968589d8 473 * Values:
Kojto 90:cb3d968589d8 474 * - 0 - Timeout has not yet occurred.
Kojto 90:cb3d968589d8 475 * - 1 - Timeout has occurred.
Kojto 90:cb3d968589d8 476 */
Kojto 90:cb3d968589d8 477 /*@{*/
Kojto 90:cb3d968589d8 478 #define BP_PIT_TFLGn_TIF (0U) /*!< Bit position for PIT_TFLGn_TIF. */
Kojto 90:cb3d968589d8 479 #define BM_PIT_TFLGn_TIF (0x00000001U) /*!< Bit mask for PIT_TFLGn_TIF. */
Kojto 90:cb3d968589d8 480 #define BS_PIT_TFLGn_TIF (1U) /*!< Bit field size in bits for PIT_TFLGn_TIF. */
Kojto 90:cb3d968589d8 481
Kojto 90:cb3d968589d8 482 /*! @brief Read current value of the PIT_TFLGn_TIF field. */
Kojto 90:cb3d968589d8 483 #define BR_PIT_TFLGn_TIF(x, n) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF))
Kojto 90:cb3d968589d8 484
Kojto 90:cb3d968589d8 485 /*! @brief Format value for bitfield PIT_TFLGn_TIF. */
Kojto 90:cb3d968589d8 486 #define BF_PIT_TFLGn_TIF(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TFLGn_TIF) & BM_PIT_TFLGn_TIF)
Kojto 90:cb3d968589d8 487
Kojto 90:cb3d968589d8 488 /*! @brief Set the TIF field to a new value. */
Kojto 90:cb3d968589d8 489 #define BW_PIT_TFLGn_TIF(x, n, v) (BITBAND_ACCESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF) = (v))
Kojto 90:cb3d968589d8 490 /*@}*/
Kojto 90:cb3d968589d8 491
Kojto 90:cb3d968589d8 492 /*******************************************************************************
Kojto 90:cb3d968589d8 493 * hw_pit_t - module struct
Kojto 90:cb3d968589d8 494 ******************************************************************************/
Kojto 90:cb3d968589d8 495 /*!
Kojto 90:cb3d968589d8 496 * @brief All PIT module registers.
Kojto 90:cb3d968589d8 497 */
Kojto 90:cb3d968589d8 498 #pragma pack(1)
Kojto 90:cb3d968589d8 499 typedef struct _hw_pit
Kojto 90:cb3d968589d8 500 {
Kojto 90:cb3d968589d8 501 __IO hw_pit_mcr_t MCR; /*!< [0x0] PIT Module Control Register */
Kojto 90:cb3d968589d8 502 uint8_t _reserved0[252];
Kojto 90:cb3d968589d8 503 struct {
Kojto 90:cb3d968589d8 504 __IO hw_pit_ldvaln_t LDVALn; /*!< [0x100] Timer Load Value Register */
Kojto 90:cb3d968589d8 505 __I hw_pit_cvaln_t CVALn; /*!< [0x104] Current Timer Value Register */
Kojto 90:cb3d968589d8 506 __IO hw_pit_tctrln_t TCTRLn; /*!< [0x108] Timer Control Register */
Kojto 90:cb3d968589d8 507 __IO hw_pit_tflgn_t TFLGn; /*!< [0x10C] Timer Flag Register */
Kojto 90:cb3d968589d8 508 } CHANNEL[4];
Kojto 90:cb3d968589d8 509 } hw_pit_t;
Kojto 90:cb3d968589d8 510 #pragma pack()
Kojto 90:cb3d968589d8 511
Kojto 90:cb3d968589d8 512 /*! @brief Macro to access all PIT registers. */
Kojto 90:cb3d968589d8 513 /*! @param x PIT module instance base address. */
Kojto 90:cb3d968589d8 514 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 515 * use the '&' operator, like <code>&HW_PIT(PIT_BASE)</code>. */
Kojto 90:cb3d968589d8 516 #define HW_PIT(x) (*(hw_pit_t *)(x))
Kojto 90:cb3d968589d8 517
Kojto 90:cb3d968589d8 518 #endif /* __HW_PIT_REGISTERS_H__ */
Kojto 90:cb3d968589d8 519 /* EOF */