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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_i2s.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:: Kojto
Date:: Wed Aug 05 13:16:35 2015 +0100
Revision:: 104:b9ad9a133dc7
Parent:: 90:cb3d968589d8

Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/*
Kojto	90:cb3d968589d8	2	** ###################################################################
Kojto	90:cb3d968589d8	3	** Compilers: Keil ARM C/C++ Compiler
Kojto	90:cb3d968589d8	4	** Freescale C/C++ for Embedded ARM
Kojto	90:cb3d968589d8	5	** GNU C Compiler
Kojto	90:cb3d968589d8	6	** IAR ANSI C/C++ Compiler for ARM
Kojto	90:cb3d968589d8	7	**
Kojto	90:cb3d968589d8	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto	90:cb3d968589d8	9	** Version: rev. 2.5, 2014-02-10
Kojto	90:cb3d968589d8	10	** Build: b140604
Kojto	90:cb3d968589d8	11	**
Kojto	90:cb3d968589d8	12	** Abstract:
Kojto	90:cb3d968589d8	13	** Extension to the CMSIS register access layer header.
Kojto	90:cb3d968589d8	14	**
Kojto	90:cb3d968589d8	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto	90:cb3d968589d8	16	** All rights reserved.
Kojto	90:cb3d968589d8	17	**
Kojto	90:cb3d968589d8	18	** Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	19	** are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	20	**
Kojto	90:cb3d968589d8	21	** o Redistributions of source code must retain the above copyright notice, this list
Kojto	90:cb3d968589d8	22	** of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	23	**
Kojto	90:cb3d968589d8	24	** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto	90:cb3d968589d8	25	** list of conditions and the following disclaimer in the documentation and/or
Kojto	90:cb3d968589d8	26	** other materials provided with the distribution.
Kojto	90:cb3d968589d8	27	**
Kojto	90:cb3d968589d8	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto	90:cb3d968589d8	29	** contributors may be used to endorse or promote products derived from this
Kojto	90:cb3d968589d8	30	** software without specific prior written permission.
Kojto	90:cb3d968589d8	31	**
Kojto	90:cb3d968589d8	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	90:cb3d968589d8	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	90:cb3d968589d8	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	90:cb3d968589d8	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	90:cb3d968589d8	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	90:cb3d968589d8	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	90:cb3d968589d8	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	90:cb3d968589d8	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	90:cb3d968589d8	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	42	**
Kojto	90:cb3d968589d8	43	** http: www.freescale.com
Kojto	90:cb3d968589d8	44	** mail: support@freescale.com
Kojto	90:cb3d968589d8	45	**
Kojto	90:cb3d968589d8	46	** Revisions:
Kojto	90:cb3d968589d8	47	** - rev. 1.0 (2013-08-12)
Kojto	90:cb3d968589d8	48	** Initial version.
Kojto	90:cb3d968589d8	49	** - rev. 2.0 (2013-10-29)
Kojto	90:cb3d968589d8	50	** Register accessor macros added to the memory map.
Kojto	90:cb3d968589d8	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto	90:cb3d968589d8	52	** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto	90:cb3d968589d8	53	** System initialization updated.
Kojto	90:cb3d968589d8	54	** MCG - registers updated.
Kojto	90:cb3d968589d8	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto	90:cb3d968589d8	56	** - rev. 2.1 (2013-10-30)
Kojto	90:cb3d968589d8	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto	90:cb3d968589d8	58	** - rev. 2.2 (2013-12-09)
Kojto	90:cb3d968589d8	59	** DMA - EARS register removed.
Kojto	90:cb3d968589d8	60	** AIPS0, AIPS1 - MPRA register updated.
Kojto	90:cb3d968589d8	61	** - rev. 2.3 (2014-01-24)
Kojto	90:cb3d968589d8	62	** Update according to reference manual rev. 2
Kojto	90:cb3d968589d8	63	** ENET, MCG, MCM, SIM, USB - registers updated
Kojto	90:cb3d968589d8	64	** - rev. 2.4 (2014-02-10)
Kojto	90:cb3d968589d8	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	67	** - rev. 2.5 (2014-02-10)
Kojto	90:cb3d968589d8	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto	90:cb3d968589d8	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto	90:cb3d968589d8	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto	90:cb3d968589d8	71	**
Kojto	90:cb3d968589d8	72	** ###################################################################
Kojto	90:cb3d968589d8	73	*/
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	/*
Kojto	90:cb3d968589d8	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto	90:cb3d968589d8	77	*
Kojto	90:cb3d968589d8	78	* This file was generated automatically and any changes may be lost.
Kojto	90:cb3d968589d8	79	*/
Kojto	90:cb3d968589d8	80	#ifndef __HW_I2S_REGISTERS_H__
Kojto	90:cb3d968589d8	81	#define __HW_I2S_REGISTERS_H__
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	#include "MK64F12.h"
Kojto	90:cb3d968589d8	84	#include "fsl_bitaccess.h"
Kojto	90:cb3d968589d8	85
Kojto	90:cb3d968589d8	86	/*
Kojto	90:cb3d968589d8	87	* MK64F12 I2S
Kojto	90:cb3d968589d8	88	*
Kojto	90:cb3d968589d8	89	* Inter-IC Sound / Synchronous Audio Interface
Kojto	90:cb3d968589d8	90	*
Kojto	90:cb3d968589d8	91	* Registers defined in this header file:
Kojto	90:cb3d968589d8	92	* - HW_I2S_TCSR - SAI Transmit Control Register
Kojto	90:cb3d968589d8	93	* - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
Kojto	90:cb3d968589d8	94	* - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
Kojto	90:cb3d968589d8	95	* - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
Kojto	90:cb3d968589d8	96	* - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
Kojto	90:cb3d968589d8	97	* - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
Kojto	90:cb3d968589d8	98	* - HW_I2S_TDRn - SAI Transmit Data Register
Kojto	90:cb3d968589d8	99	* - HW_I2S_TFRn - SAI Transmit FIFO Register
Kojto	90:cb3d968589d8	100	* - HW_I2S_TMR - SAI Transmit Mask Register
Kojto	90:cb3d968589d8	101	* - HW_I2S_RCSR - SAI Receive Control Register
Kojto	90:cb3d968589d8	102	* - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
Kojto	90:cb3d968589d8	103	* - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
Kojto	90:cb3d968589d8	104	* - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
Kojto	90:cb3d968589d8	105	* - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
Kojto	90:cb3d968589d8	106	* - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
Kojto	90:cb3d968589d8	107	* - HW_I2S_RDRn - SAI Receive Data Register
Kojto	90:cb3d968589d8	108	* - HW_I2S_RFRn - SAI Receive FIFO Register
Kojto	90:cb3d968589d8	109	* - HW_I2S_RMR - SAI Receive Mask Register
Kojto	90:cb3d968589d8	110	* - HW_I2S_MCR - SAI MCLK Control Register
Kojto	90:cb3d968589d8	111	* - HW_I2S_MDR - SAI MCLK Divide Register
Kojto	90:cb3d968589d8	112	*
Kojto	90:cb3d968589d8	113	* - hw_i2s_t - Struct containing all module registers.
Kojto	90:cb3d968589d8	114	*/
Kojto	90:cb3d968589d8	115
Kojto	90:cb3d968589d8	116	#define HW_I2S_INSTANCE_COUNT (1U) /!< Number of instances of the I2S module. /
Kojto	90:cb3d968589d8	117
Kojto	90:cb3d968589d8	118	/*******************************************************************************
Kojto	90:cb3d968589d8	119	* HW_I2S_TCSR - SAI Transmit Control Register
Kojto	90:cb3d968589d8	120	******************************************************************************/
Kojto	90:cb3d968589d8	121
Kojto	90:cb3d968589d8	122	/*!
Kojto	90:cb3d968589d8	123	* @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
Kojto	90:cb3d968589d8	124	*
Kojto	90:cb3d968589d8	125	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	126	*/
Kojto	90:cb3d968589d8	127	typedef union _hw_i2s_tcsr
Kojto	90:cb3d968589d8	128	{
Kojto	90:cb3d968589d8	129	uint32_t U;
Kojto	90:cb3d968589d8	130	struct _hw_i2s_tcsr_bitfields
Kojto	90:cb3d968589d8	131	{
Kojto	90:cb3d968589d8	132	uint32_t FRDE : 1; /!< [0] FIFO Request DMA Enable /
Kojto	90:cb3d968589d8	133	uint32_t FWDE : 1; /!< [1] FIFO Warning DMA Enable /
Kojto	90:cb3d968589d8	134	uint32_t RESERVED0 : 6; /!< [7:2] /
Kojto	90:cb3d968589d8	135	uint32_t FRIE : 1; /!< [8] FIFO Request Interrupt Enable /
Kojto	90:cb3d968589d8	136	uint32_t FWIE : 1; /!< [9] FIFO Warning Interrupt Enable /
Kojto	90:cb3d968589d8	137	uint32_t FEIE : 1; /!< [10] FIFO Error Interrupt Enable /
Kojto	90:cb3d968589d8	138	uint32_t SEIE : 1; /!< [11] Sync Error Interrupt Enable /
Kojto	90:cb3d968589d8	139	uint32_t WSIE : 1; /!< [12] Word Start Interrupt Enable /
Kojto	90:cb3d968589d8	140	uint32_t RESERVED1 : 3; /!< [15:13] /
Kojto	90:cb3d968589d8	141	uint32_t FRF : 1; /!< [16] FIFO Request Flag /
Kojto	90:cb3d968589d8	142	uint32_t FWF : 1; /!< [17] FIFO Warning Flag /
Kojto	90:cb3d968589d8	143	uint32_t FEF : 1; /!< [18] FIFO Error Flag /
Kojto	90:cb3d968589d8	144	uint32_t SEF : 1; /!< [19] Sync Error Flag /
Kojto	90:cb3d968589d8	145	uint32_t WSF : 1; /!< [20] Word Start Flag /
Kojto	90:cb3d968589d8	146	uint32_t RESERVED2 : 3; /!< [23:21] /
Kojto	90:cb3d968589d8	147	uint32_t SR : 1; /!< [24] Software Reset /
Kojto	90:cb3d968589d8	148	uint32_t FR : 1; /!< [25] FIFO Reset /
Kojto	90:cb3d968589d8	149	uint32_t RESERVED3 : 2; /!< [27:26] /
Kojto	90:cb3d968589d8	150	uint32_t BCE : 1; /!< [28] Bit Clock Enable /
Kojto	90:cb3d968589d8	151	uint32_t DBGE : 1; /!< [29] Debug Enable /
Kojto	90:cb3d968589d8	152	uint32_t STOPE : 1; /!< [30] Stop Enable /
Kojto	90:cb3d968589d8	153	uint32_t TE : 1; /!< [31] Transmitter Enable /
Kojto	90:cb3d968589d8	154	} B;
Kojto	90:cb3d968589d8	155	} hw_i2s_tcsr_t;
Kojto	90:cb3d968589d8	156
Kojto	90:cb3d968589d8	157	/*!
Kojto	90:cb3d968589d8	158	* @name Constants and macros for entire I2S_TCSR register
Kojto	90:cb3d968589d8	159	*/
Kojto	90:cb3d968589d8	160	/@{/
Kojto	90:cb3d968589d8	161	#define HW_I2S_TCSR_ADDR(x) ((x) + 0x0U)
Kojto	90:cb3d968589d8	162
Kojto	90:cb3d968589d8	163	#define HW_I2S_TCSR(x) ((__IO hw_i2s_tcsr_t ) HW_I2S_TCSR_ADDR(x))
Kojto	90:cb3d968589d8	164	#define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U)
Kojto	90:cb3d968589d8	165	#define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v))
Kojto	90:cb3d968589d8	166	#define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	167	#define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	168	#define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	169	/@}/
Kojto	90:cb3d968589d8	170
Kojto	90:cb3d968589d8	171	/*
Kojto	90:cb3d968589d8	172	* Constants & macros for individual I2S_TCSR bitfields
Kojto	90:cb3d968589d8	173	*/
Kojto	90:cb3d968589d8	174
Kojto	90:cb3d968589d8	175	/*!
Kojto	90:cb3d968589d8	176	* @name Register I2S_TCSR, field FRDE[0] (RW)
Kojto	90:cb3d968589d8	177	*
Kojto	90:cb3d968589d8	178	* Enables/disables DMA requests.
Kojto	90:cb3d968589d8	179	*
Kojto	90:cb3d968589d8	180	* Values:
Kojto	90:cb3d968589d8	181	* - 0 - Disables the DMA request.
Kojto	90:cb3d968589d8	182	* - 1 - Enables the DMA request.
Kojto	90:cb3d968589d8	183	*/
Kojto	90:cb3d968589d8	184	/@{/
Kojto	90:cb3d968589d8	185	#define BP_I2S_TCSR_FRDE (0U) /!< Bit position for I2S_TCSR_FRDE. /
Kojto	90:cb3d968589d8	186	#define BM_I2S_TCSR_FRDE (0x00000001U) /!< Bit mask for I2S_TCSR_FRDE. /
Kojto	90:cb3d968589d8	187	#define BS_I2S_TCSR_FRDE (1U) /!< Bit field size in bits for I2S_TCSR_FRDE. /
Kojto	90:cb3d968589d8	188
Kojto	90:cb3d968589d8	189	/! @brief Read current value of the I2S_TCSR_FRDE field. /
Kojto	90:cb3d968589d8	190	#define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
Kojto	90:cb3d968589d8	191
Kojto	90:cb3d968589d8	192	/! @brief Format value for bitfield I2S_TCSR_FRDE. /
Kojto	90:cb3d968589d8	193	#define BF_I2S_TCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRDE) & BM_I2S_TCSR_FRDE)
Kojto	90:cb3d968589d8	194
Kojto	90:cb3d968589d8	195	/! @brief Set the FRDE field to a new value. /
Kojto	90:cb3d968589d8	196	#define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
Kojto	90:cb3d968589d8	197	/@}/
Kojto	90:cb3d968589d8	198
Kojto	90:cb3d968589d8	199	/*!
Kojto	90:cb3d968589d8	200	* @name Register I2S_TCSR, field FWDE[1] (RW)
Kojto	90:cb3d968589d8	201	*
Kojto	90:cb3d968589d8	202	* Enables/disables DMA requests.
Kojto	90:cb3d968589d8	203	*
Kojto	90:cb3d968589d8	204	* Values:
Kojto	90:cb3d968589d8	205	* - 0 - Disables the DMA request.
Kojto	90:cb3d968589d8	206	* - 1 - Enables the DMA request.
Kojto	90:cb3d968589d8	207	*/
Kojto	90:cb3d968589d8	208	/@{/
Kojto	90:cb3d968589d8	209	#define BP_I2S_TCSR_FWDE (1U) /!< Bit position for I2S_TCSR_FWDE. /
Kojto	90:cb3d968589d8	210	#define BM_I2S_TCSR_FWDE (0x00000002U) /!< Bit mask for I2S_TCSR_FWDE. /
Kojto	90:cb3d968589d8	211	#define BS_I2S_TCSR_FWDE (1U) /!< Bit field size in bits for I2S_TCSR_FWDE. /
Kojto	90:cb3d968589d8	212
Kojto	90:cb3d968589d8	213	/! @brief Read current value of the I2S_TCSR_FWDE field. /
Kojto	90:cb3d968589d8	214	#define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
Kojto	90:cb3d968589d8	215
Kojto	90:cb3d968589d8	216	/! @brief Format value for bitfield I2S_TCSR_FWDE. /
Kojto	90:cb3d968589d8	217	#define BF_I2S_TCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWDE) & BM_I2S_TCSR_FWDE)
Kojto	90:cb3d968589d8	218
Kojto	90:cb3d968589d8	219	/! @brief Set the FWDE field to a new value. /
Kojto	90:cb3d968589d8	220	#define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
Kojto	90:cb3d968589d8	221	/@}/
Kojto	90:cb3d968589d8	222
Kojto	90:cb3d968589d8	223	/*!
Kojto	90:cb3d968589d8	224	* @name Register I2S_TCSR, field FRIE[8] (RW)
Kojto	90:cb3d968589d8	225	*
Kojto	90:cb3d968589d8	226	* Enables/disables FIFO request interrupts.
Kojto	90:cb3d968589d8	227	*
Kojto	90:cb3d968589d8	228	* Values:
Kojto	90:cb3d968589d8	229	* - 0 - Disables the interrupt.
Kojto	90:cb3d968589d8	230	* - 1 - Enables the interrupt.
Kojto	90:cb3d968589d8	231	*/
Kojto	90:cb3d968589d8	232	/@{/
Kojto	90:cb3d968589d8	233	#define BP_I2S_TCSR_FRIE (8U) /!< Bit position for I2S_TCSR_FRIE. /
Kojto	90:cb3d968589d8	234	#define BM_I2S_TCSR_FRIE (0x00000100U) /!< Bit mask for I2S_TCSR_FRIE. /
Kojto	90:cb3d968589d8	235	#define BS_I2S_TCSR_FRIE (1U) /!< Bit field size in bits for I2S_TCSR_FRIE. /
Kojto	90:cb3d968589d8	236
Kojto	90:cb3d968589d8	237	/! @brief Read current value of the I2S_TCSR_FRIE field. /
Kojto	90:cb3d968589d8	238	#define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
Kojto	90:cb3d968589d8	239
Kojto	90:cb3d968589d8	240	/! @brief Format value for bitfield I2S_TCSR_FRIE. /
Kojto	90:cb3d968589d8	241	#define BF_I2S_TCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRIE) & BM_I2S_TCSR_FRIE)
Kojto	90:cb3d968589d8	242
Kojto	90:cb3d968589d8	243	/! @brief Set the FRIE field to a new value. /
Kojto	90:cb3d968589d8	244	#define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
Kojto	90:cb3d968589d8	245	/@}/
Kojto	90:cb3d968589d8	246
Kojto	90:cb3d968589d8	247	/*!
Kojto	90:cb3d968589d8	248	* @name Register I2S_TCSR, field FWIE[9] (RW)
Kojto	90:cb3d968589d8	249	*
Kojto	90:cb3d968589d8	250	* Enables/disables FIFO warning interrupts.
Kojto	90:cb3d968589d8	251	*
Kojto	90:cb3d968589d8	252	* Values:
Kojto	90:cb3d968589d8	253	* - 0 - Disables the interrupt.
Kojto	90:cb3d968589d8	254	* - 1 - Enables the interrupt.
Kojto	90:cb3d968589d8	255	*/
Kojto	90:cb3d968589d8	256	/@{/
Kojto	90:cb3d968589d8	257	#define BP_I2S_TCSR_FWIE (9U) /!< Bit position for I2S_TCSR_FWIE. /
Kojto	90:cb3d968589d8	258	#define BM_I2S_TCSR_FWIE (0x00000200U) /!< Bit mask for I2S_TCSR_FWIE. /
Kojto	90:cb3d968589d8	259	#define BS_I2S_TCSR_FWIE (1U) /!< Bit field size in bits for I2S_TCSR_FWIE. /
Kojto	90:cb3d968589d8	260
Kojto	90:cb3d968589d8	261	/! @brief Read current value of the I2S_TCSR_FWIE field. /
Kojto	90:cb3d968589d8	262	#define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
Kojto	90:cb3d968589d8	263
Kojto	90:cb3d968589d8	264	/! @brief Format value for bitfield I2S_TCSR_FWIE. /
Kojto	90:cb3d968589d8	265	#define BF_I2S_TCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWIE) & BM_I2S_TCSR_FWIE)
Kojto	90:cb3d968589d8	266
Kojto	90:cb3d968589d8	267	/! @brief Set the FWIE field to a new value. /
Kojto	90:cb3d968589d8	268	#define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
Kojto	90:cb3d968589d8	269	/@}/
Kojto	90:cb3d968589d8	270
Kojto	90:cb3d968589d8	271	/*!
Kojto	90:cb3d968589d8	272	* @name Register I2S_TCSR, field FEIE[10] (RW)
Kojto	90:cb3d968589d8	273	*
Kojto	90:cb3d968589d8	274	* Enables/disables FIFO error interrupts.
Kojto	90:cb3d968589d8	275	*
Kojto	90:cb3d968589d8	276	* Values:
Kojto	90:cb3d968589d8	277	* - 0 - Disables the interrupt.
Kojto	90:cb3d968589d8	278	* - 1 - Enables the interrupt.
Kojto	90:cb3d968589d8	279	*/
Kojto	90:cb3d968589d8	280	/@{/
Kojto	90:cb3d968589d8	281	#define BP_I2S_TCSR_FEIE (10U) /!< Bit position for I2S_TCSR_FEIE. /
Kojto	90:cb3d968589d8	282	#define BM_I2S_TCSR_FEIE (0x00000400U) /!< Bit mask for I2S_TCSR_FEIE. /
Kojto	90:cb3d968589d8	283	#define BS_I2S_TCSR_FEIE (1U) /!< Bit field size in bits for I2S_TCSR_FEIE. /
Kojto	90:cb3d968589d8	284
Kojto	90:cb3d968589d8	285	/! @brief Read current value of the I2S_TCSR_FEIE field. /
Kojto	90:cb3d968589d8	286	#define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
Kojto	90:cb3d968589d8	287
Kojto	90:cb3d968589d8	288	/! @brief Format value for bitfield I2S_TCSR_FEIE. /
Kojto	90:cb3d968589d8	289	#define BF_I2S_TCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEIE) & BM_I2S_TCSR_FEIE)
Kojto	90:cb3d968589d8	290
Kojto	90:cb3d968589d8	291	/! @brief Set the FEIE field to a new value. /
Kojto	90:cb3d968589d8	292	#define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
Kojto	90:cb3d968589d8	293	/@}/
Kojto	90:cb3d968589d8	294
Kojto	90:cb3d968589d8	295	/*!
Kojto	90:cb3d968589d8	296	* @name Register I2S_TCSR, field SEIE[11] (RW)
Kojto	90:cb3d968589d8	297	*
Kojto	90:cb3d968589d8	298	* Enables/disables sync error interrupts.
Kojto	90:cb3d968589d8	299	*
Kojto	90:cb3d968589d8	300	* Values:
Kojto	90:cb3d968589d8	301	* - 0 - Disables interrupt.
Kojto	90:cb3d968589d8	302	* - 1 - Enables interrupt.
Kojto	90:cb3d968589d8	303	*/
Kojto	90:cb3d968589d8	304	/@{/
Kojto	90:cb3d968589d8	305	#define BP_I2S_TCSR_SEIE (11U) /!< Bit position for I2S_TCSR_SEIE. /
Kojto	90:cb3d968589d8	306	#define BM_I2S_TCSR_SEIE (0x00000800U) /!< Bit mask for I2S_TCSR_SEIE. /
Kojto	90:cb3d968589d8	307	#define BS_I2S_TCSR_SEIE (1U) /!< Bit field size in bits for I2S_TCSR_SEIE. /
Kojto	90:cb3d968589d8	308
Kojto	90:cb3d968589d8	309	/! @brief Read current value of the I2S_TCSR_SEIE field. /
Kojto	90:cb3d968589d8	310	#define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
Kojto	90:cb3d968589d8	311
Kojto	90:cb3d968589d8	312	/! @brief Format value for bitfield I2S_TCSR_SEIE. /
Kojto	90:cb3d968589d8	313	#define BF_I2S_TCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEIE) & BM_I2S_TCSR_SEIE)
Kojto	90:cb3d968589d8	314
Kojto	90:cb3d968589d8	315	/! @brief Set the SEIE field to a new value. /
Kojto	90:cb3d968589d8	316	#define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
Kojto	90:cb3d968589d8	317	/@}/
Kojto	90:cb3d968589d8	318
Kojto	90:cb3d968589d8	319	/*!
Kojto	90:cb3d968589d8	320	* @name Register I2S_TCSR, field WSIE[12] (RW)
Kojto	90:cb3d968589d8	321	*
Kojto	90:cb3d968589d8	322	* Enables/disables word start interrupts.
Kojto	90:cb3d968589d8	323	*
Kojto	90:cb3d968589d8	324	* Values:
Kojto	90:cb3d968589d8	325	* - 0 - Disables interrupt.
Kojto	90:cb3d968589d8	326	* - 1 - Enables interrupt.
Kojto	90:cb3d968589d8	327	*/
Kojto	90:cb3d968589d8	328	/@{/
Kojto	90:cb3d968589d8	329	#define BP_I2S_TCSR_WSIE (12U) /!< Bit position for I2S_TCSR_WSIE. /
Kojto	90:cb3d968589d8	330	#define BM_I2S_TCSR_WSIE (0x00001000U) /!< Bit mask for I2S_TCSR_WSIE. /
Kojto	90:cb3d968589d8	331	#define BS_I2S_TCSR_WSIE (1U) /!< Bit field size in bits for I2S_TCSR_WSIE. /
Kojto	90:cb3d968589d8	332
Kojto	90:cb3d968589d8	333	/! @brief Read current value of the I2S_TCSR_WSIE field. /
Kojto	90:cb3d968589d8	334	#define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
Kojto	90:cb3d968589d8	335
Kojto	90:cb3d968589d8	336	/! @brief Format value for bitfield I2S_TCSR_WSIE. /
Kojto	90:cb3d968589d8	337	#define BF_I2S_TCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSIE) & BM_I2S_TCSR_WSIE)
Kojto	90:cb3d968589d8	338
Kojto	90:cb3d968589d8	339	/! @brief Set the WSIE field to a new value. /
Kojto	90:cb3d968589d8	340	#define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
Kojto	90:cb3d968589d8	341	/@}/
Kojto	90:cb3d968589d8	342
Kojto	90:cb3d968589d8	343	/*!
Kojto	90:cb3d968589d8	344	* @name Register I2S_TCSR, field FRF[16] (RO)
Kojto	90:cb3d968589d8	345	*
Kojto	90:cb3d968589d8	346	* Indicates that the number of words in an enabled transmit channel FIFO is
Kojto	90:cb3d968589d8	347	* less than or equal to the transmit FIFO watermark.
Kojto	90:cb3d968589d8	348	*
Kojto	90:cb3d968589d8	349	* Values:
Kojto	90:cb3d968589d8	350	* - 0 - Transmit FIFO watermark has not been reached.
Kojto	90:cb3d968589d8	351	* - 1 - Transmit FIFO watermark has been reached.
Kojto	90:cb3d968589d8	352	*/
Kojto	90:cb3d968589d8	353	/@{/
Kojto	90:cb3d968589d8	354	#define BP_I2S_TCSR_FRF (16U) /!< Bit position for I2S_TCSR_FRF. /
Kojto	90:cb3d968589d8	355	#define BM_I2S_TCSR_FRF (0x00010000U) /!< Bit mask for I2S_TCSR_FRF. /
Kojto	90:cb3d968589d8	356	#define BS_I2S_TCSR_FRF (1U) /!< Bit field size in bits for I2S_TCSR_FRF. /
Kojto	90:cb3d968589d8	357
Kojto	90:cb3d968589d8	358	/! @brief Read current value of the I2S_TCSR_FRF field. /
Kojto	90:cb3d968589d8	359	#define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
Kojto	90:cb3d968589d8	360	/@}/
Kojto	90:cb3d968589d8	361
Kojto	90:cb3d968589d8	362	/*!
Kojto	90:cb3d968589d8	363	* @name Register I2S_TCSR, field FWF[17] (RO)
Kojto	90:cb3d968589d8	364	*
Kojto	90:cb3d968589d8	365	* Indicates that an enabled transmit FIFO is empty.
Kojto	90:cb3d968589d8	366	*
Kojto	90:cb3d968589d8	367	* Values:
Kojto	90:cb3d968589d8	368	* - 0 - No enabled transmit FIFO is empty.
Kojto	90:cb3d968589d8	369	* - 1 - Enabled transmit FIFO is empty.
Kojto	90:cb3d968589d8	370	*/
Kojto	90:cb3d968589d8	371	/@{/
Kojto	90:cb3d968589d8	372	#define BP_I2S_TCSR_FWF (17U) /!< Bit position for I2S_TCSR_FWF. /
Kojto	90:cb3d968589d8	373	#define BM_I2S_TCSR_FWF (0x00020000U) /!< Bit mask for I2S_TCSR_FWF. /
Kojto	90:cb3d968589d8	374	#define BS_I2S_TCSR_FWF (1U) /!< Bit field size in bits for I2S_TCSR_FWF. /
Kojto	90:cb3d968589d8	375
Kojto	90:cb3d968589d8	376	/! @brief Read current value of the I2S_TCSR_FWF field. /
Kojto	90:cb3d968589d8	377	#define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
Kojto	90:cb3d968589d8	378	/@}/
Kojto	90:cb3d968589d8	379
Kojto	90:cb3d968589d8	380	/*!
Kojto	90:cb3d968589d8	381	* @name Register I2S_TCSR, field FEF[18] (W1C)
Kojto	90:cb3d968589d8	382	*
Kojto	90:cb3d968589d8	383	* Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
Kojto	90:cb3d968589d8	384	* field to clear this flag.
Kojto	90:cb3d968589d8	385	*
Kojto	90:cb3d968589d8	386	* Values:
Kojto	90:cb3d968589d8	387	* - 0 - Transmit underrun not detected.
Kojto	90:cb3d968589d8	388	* - 1 - Transmit underrun detected.
Kojto	90:cb3d968589d8	389	*/
Kojto	90:cb3d968589d8	390	/@{/
Kojto	90:cb3d968589d8	391	#define BP_I2S_TCSR_FEF (18U) /!< Bit position for I2S_TCSR_FEF. /
Kojto	90:cb3d968589d8	392	#define BM_I2S_TCSR_FEF (0x00040000U) /!< Bit mask for I2S_TCSR_FEF. /
Kojto	90:cb3d968589d8	393	#define BS_I2S_TCSR_FEF (1U) /!< Bit field size in bits for I2S_TCSR_FEF. /
Kojto	90:cb3d968589d8	394
Kojto	90:cb3d968589d8	395	/! @brief Read current value of the I2S_TCSR_FEF field. /
Kojto	90:cb3d968589d8	396	#define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
Kojto	90:cb3d968589d8	397
Kojto	90:cb3d968589d8	398	/! @brief Format value for bitfield I2S_TCSR_FEF. /
Kojto	90:cb3d968589d8	399	#define BF_I2S_TCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEF) & BM_I2S_TCSR_FEF)
Kojto	90:cb3d968589d8	400
Kojto	90:cb3d968589d8	401	/! @brief Set the FEF field to a new value. /
Kojto	90:cb3d968589d8	402	#define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
Kojto	90:cb3d968589d8	403	/@}/
Kojto	90:cb3d968589d8	404
Kojto	90:cb3d968589d8	405	/*!
Kojto	90:cb3d968589d8	406	* @name Register I2S_TCSR, field SEF[19] (W1C)
Kojto	90:cb3d968589d8	407	*
Kojto	90:cb3d968589d8	408	* Indicates that an error in the externally-generated frame sync has been
Kojto	90:cb3d968589d8	409	* detected. Write a logic 1 to this field to clear this flag.
Kojto	90:cb3d968589d8	410	*
Kojto	90:cb3d968589d8	411	* Values:
Kojto	90:cb3d968589d8	412	* - 0 - Sync error not detected.
Kojto	90:cb3d968589d8	413	* - 1 - Frame sync error detected.
Kojto	90:cb3d968589d8	414	*/
Kojto	90:cb3d968589d8	415	/@{/
Kojto	90:cb3d968589d8	416	#define BP_I2S_TCSR_SEF (19U) /!< Bit position for I2S_TCSR_SEF. /
Kojto	90:cb3d968589d8	417	#define BM_I2S_TCSR_SEF (0x00080000U) /!< Bit mask for I2S_TCSR_SEF. /
Kojto	90:cb3d968589d8	418	#define BS_I2S_TCSR_SEF (1U) /!< Bit field size in bits for I2S_TCSR_SEF. /
Kojto	90:cb3d968589d8	419
Kojto	90:cb3d968589d8	420	/! @brief Read current value of the I2S_TCSR_SEF field. /
Kojto	90:cb3d968589d8	421	#define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
Kojto	90:cb3d968589d8	422
Kojto	90:cb3d968589d8	423	/! @brief Format value for bitfield I2S_TCSR_SEF. /
Kojto	90:cb3d968589d8	424	#define BF_I2S_TCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEF) & BM_I2S_TCSR_SEF)
Kojto	90:cb3d968589d8	425
Kojto	90:cb3d968589d8	426	/! @brief Set the SEF field to a new value. /
Kojto	90:cb3d968589d8	427	#define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
Kojto	90:cb3d968589d8	428	/@}/
Kojto	90:cb3d968589d8	429
Kojto	90:cb3d968589d8	430	/*!
Kojto	90:cb3d968589d8	431	* @name Register I2S_TCSR, field WSF[20] (W1C)
Kojto	90:cb3d968589d8	432	*
Kojto	90:cb3d968589d8	433	* Indicates that the start of the configured word has been detected. Write a
Kojto	90:cb3d968589d8	434	* logic 1 to this field to clear this flag.
Kojto	90:cb3d968589d8	435	*
Kojto	90:cb3d968589d8	436	* Values:
Kojto	90:cb3d968589d8	437	* - 0 - Start of word not detected.
Kojto	90:cb3d968589d8	438	* - 1 - Start of word detected.
Kojto	90:cb3d968589d8	439	*/
Kojto	90:cb3d968589d8	440	/@{/
Kojto	90:cb3d968589d8	441	#define BP_I2S_TCSR_WSF (20U) /!< Bit position for I2S_TCSR_WSF. /
Kojto	90:cb3d968589d8	442	#define BM_I2S_TCSR_WSF (0x00100000U) /!< Bit mask for I2S_TCSR_WSF. /
Kojto	90:cb3d968589d8	443	#define BS_I2S_TCSR_WSF (1U) /!< Bit field size in bits for I2S_TCSR_WSF. /
Kojto	90:cb3d968589d8	444
Kojto	90:cb3d968589d8	445	/! @brief Read current value of the I2S_TCSR_WSF field. /
Kojto	90:cb3d968589d8	446	#define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
Kojto	90:cb3d968589d8	447
Kojto	90:cb3d968589d8	448	/! @brief Format value for bitfield I2S_TCSR_WSF. /
Kojto	90:cb3d968589d8	449	#define BF_I2S_TCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSF) & BM_I2S_TCSR_WSF)
Kojto	90:cb3d968589d8	450
Kojto	90:cb3d968589d8	451	/! @brief Set the WSF field to a new value. /
Kojto	90:cb3d968589d8	452	#define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
Kojto	90:cb3d968589d8	453	/@}/
Kojto	90:cb3d968589d8	454
Kojto	90:cb3d968589d8	455	/*!
Kojto	90:cb3d968589d8	456	* @name Register I2S_TCSR, field SR[24] (RW)
Kojto	90:cb3d968589d8	457	*
Kojto	90:cb3d968589d8	458	* When set, resets the internal transmitter logic including the FIFO pointers.
Kojto	90:cb3d968589d8	459	* Software-visible registers are not affected, except for the status registers.
Kojto	90:cb3d968589d8	460	*
Kojto	90:cb3d968589d8	461	* Values:
Kojto	90:cb3d968589d8	462	* - 0 - No effect.
Kojto	90:cb3d968589d8	463	* - 1 - Software reset.
Kojto	90:cb3d968589d8	464	*/
Kojto	90:cb3d968589d8	465	/@{/
Kojto	90:cb3d968589d8	466	#define BP_I2S_TCSR_SR (24U) /!< Bit position for I2S_TCSR_SR. /
Kojto	90:cb3d968589d8	467	#define BM_I2S_TCSR_SR (0x01000000U) /!< Bit mask for I2S_TCSR_SR. /
Kojto	90:cb3d968589d8	468	#define BS_I2S_TCSR_SR (1U) /!< Bit field size in bits for I2S_TCSR_SR. /
Kojto	90:cb3d968589d8	469
Kojto	90:cb3d968589d8	470	/! @brief Read current value of the I2S_TCSR_SR field. /
Kojto	90:cb3d968589d8	471	#define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
Kojto	90:cb3d968589d8	472
Kojto	90:cb3d968589d8	473	/! @brief Format value for bitfield I2S_TCSR_SR. /
Kojto	90:cb3d968589d8	474	#define BF_I2S_TCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SR) & BM_I2S_TCSR_SR)
Kojto	90:cb3d968589d8	475
Kojto	90:cb3d968589d8	476	/! @brief Set the SR field to a new value. /
Kojto	90:cb3d968589d8	477	#define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
Kojto	90:cb3d968589d8	478	/@}/
Kojto	90:cb3d968589d8	479
Kojto	90:cb3d968589d8	480	/*!
Kojto	90:cb3d968589d8	481	* @name Register I2S_TCSR, field FR[25] (WORZ)
Kojto	90:cb3d968589d8	482	*
Kojto	90:cb3d968589d8	483	* Resets the FIFO pointers. Reading this field will always return zero. FIFO
Kojto	90:cb3d968589d8	484	* pointers should only be reset when the transmitter is disabled or the FIFO error
Kojto	90:cb3d968589d8	485	* flag is set.
Kojto	90:cb3d968589d8	486	*
Kojto	90:cb3d968589d8	487	* Values:
Kojto	90:cb3d968589d8	488	* - 0 - No effect.
Kojto	90:cb3d968589d8	489	* - 1 - FIFO reset.
Kojto	90:cb3d968589d8	490	*/
Kojto	90:cb3d968589d8	491	/@{/
Kojto	90:cb3d968589d8	492	#define BP_I2S_TCSR_FR (25U) /!< Bit position for I2S_TCSR_FR. /
Kojto	90:cb3d968589d8	493	#define BM_I2S_TCSR_FR (0x02000000U) /!< Bit mask for I2S_TCSR_FR. /
Kojto	90:cb3d968589d8	494	#define BS_I2S_TCSR_FR (1U) /!< Bit field size in bits for I2S_TCSR_FR. /
Kojto	90:cb3d968589d8	495
Kojto	90:cb3d968589d8	496	/! @brief Format value for bitfield I2S_TCSR_FR. /
Kojto	90:cb3d968589d8	497	#define BF_I2S_TCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FR) & BM_I2S_TCSR_FR)
Kojto	90:cb3d968589d8	498
Kojto	90:cb3d968589d8	499	/! @brief Set the FR field to a new value. /
Kojto	90:cb3d968589d8	500	#define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
Kojto	90:cb3d968589d8	501	/@}/
Kojto	90:cb3d968589d8	502
Kojto	90:cb3d968589d8	503	/*!
Kojto	90:cb3d968589d8	504	* @name Register I2S_TCSR, field BCE[28] (RW)
Kojto	90:cb3d968589d8	505	*
Kojto	90:cb3d968589d8	506	* Enables the transmit bit clock, separately from the TE. This field is
Kojto	90:cb3d968589d8	507	* automatically set whenever TE is set. When software clears this field, the transmit
Kojto	90:cb3d968589d8	508	* bit clock remains enabled, and this bit remains set, until the end of the
Kojto	90:cb3d968589d8	509	* current frame.
Kojto	90:cb3d968589d8	510	*
Kojto	90:cb3d968589d8	511	* Values:
Kojto	90:cb3d968589d8	512	* - 0 - Transmit bit clock is disabled.
Kojto	90:cb3d968589d8	513	* - 1 - Transmit bit clock is enabled.
Kojto	90:cb3d968589d8	514	*/
Kojto	90:cb3d968589d8	515	/@{/
Kojto	90:cb3d968589d8	516	#define BP_I2S_TCSR_BCE (28U) /!< Bit position for I2S_TCSR_BCE. /
Kojto	90:cb3d968589d8	517	#define BM_I2S_TCSR_BCE (0x10000000U) /!< Bit mask for I2S_TCSR_BCE. /
Kojto	90:cb3d968589d8	518	#define BS_I2S_TCSR_BCE (1U) /!< Bit field size in bits for I2S_TCSR_BCE. /
Kojto	90:cb3d968589d8	519
Kojto	90:cb3d968589d8	520	/! @brief Read current value of the I2S_TCSR_BCE field. /
Kojto	90:cb3d968589d8	521	#define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
Kojto	90:cb3d968589d8	522
Kojto	90:cb3d968589d8	523	/! @brief Format value for bitfield I2S_TCSR_BCE. /
Kojto	90:cb3d968589d8	524	#define BF_I2S_TCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_BCE) & BM_I2S_TCSR_BCE)
Kojto	90:cb3d968589d8	525
Kojto	90:cb3d968589d8	526	/! @brief Set the BCE field to a new value. /
Kojto	90:cb3d968589d8	527	#define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
Kojto	90:cb3d968589d8	528	/@}/
Kojto	90:cb3d968589d8	529
Kojto	90:cb3d968589d8	530	/*!
Kojto	90:cb3d968589d8	531	* @name Register I2S_TCSR, field DBGE[29] (RW)
Kojto	90:cb3d968589d8	532	*
Kojto	90:cb3d968589d8	533	* Enables/disables transmitter operation in Debug mode. The transmit bit clock
Kojto	90:cb3d968589d8	534	* is not affected by debug mode.
Kojto	90:cb3d968589d8	535	*
Kojto	90:cb3d968589d8	536	* Values:
Kojto	90:cb3d968589d8	537	* - 0 - Transmitter is disabled in Debug mode, after completing the current
Kojto	90:cb3d968589d8	538	* frame.
Kojto	90:cb3d968589d8	539	* - 1 - Transmitter is enabled in Debug mode.
Kojto	90:cb3d968589d8	540	*/
Kojto	90:cb3d968589d8	541	/@{/
Kojto	90:cb3d968589d8	542	#define BP_I2S_TCSR_DBGE (29U) /!< Bit position for I2S_TCSR_DBGE. /
Kojto	90:cb3d968589d8	543	#define BM_I2S_TCSR_DBGE (0x20000000U) /!< Bit mask for I2S_TCSR_DBGE. /
Kojto	90:cb3d968589d8	544	#define BS_I2S_TCSR_DBGE (1U) /!< Bit field size in bits for I2S_TCSR_DBGE. /
Kojto	90:cb3d968589d8	545
Kojto	90:cb3d968589d8	546	/! @brief Read current value of the I2S_TCSR_DBGE field. /
Kojto	90:cb3d968589d8	547	#define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
Kojto	90:cb3d968589d8	548
Kojto	90:cb3d968589d8	549	/! @brief Format value for bitfield I2S_TCSR_DBGE. /
Kojto	90:cb3d968589d8	550	#define BF_I2S_TCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_DBGE) & BM_I2S_TCSR_DBGE)
Kojto	90:cb3d968589d8	551
Kojto	90:cb3d968589d8	552	/! @brief Set the DBGE field to a new value. /
Kojto	90:cb3d968589d8	553	#define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
Kojto	90:cb3d968589d8	554	/@}/
Kojto	90:cb3d968589d8	555
Kojto	90:cb3d968589d8	556	/*!
Kojto	90:cb3d968589d8	557	* @name Register I2S_TCSR, field STOPE[30] (RW)
Kojto	90:cb3d968589d8	558	*
Kojto	90:cb3d968589d8	559	* Configures transmitter operation in Stop mode. This field is ignored and the
Kojto	90:cb3d968589d8	560	* transmitter is disabled in all low-leakage stop modes.
Kojto	90:cb3d968589d8	561	*
Kojto	90:cb3d968589d8	562	* Values:
Kojto	90:cb3d968589d8	563	* - 0 - Transmitter disabled in Stop mode.
Kojto	90:cb3d968589d8	564	* - 1 - Transmitter enabled in Stop mode.
Kojto	90:cb3d968589d8	565	*/
Kojto	90:cb3d968589d8	566	/@{/
Kojto	90:cb3d968589d8	567	#define BP_I2S_TCSR_STOPE (30U) /!< Bit position for I2S_TCSR_STOPE. /
Kojto	90:cb3d968589d8	568	#define BM_I2S_TCSR_STOPE (0x40000000U) /!< Bit mask for I2S_TCSR_STOPE. /
Kojto	90:cb3d968589d8	569	#define BS_I2S_TCSR_STOPE (1U) /!< Bit field size in bits for I2S_TCSR_STOPE. /
Kojto	90:cb3d968589d8	570
Kojto	90:cb3d968589d8	571	/! @brief Read current value of the I2S_TCSR_STOPE field. /
Kojto	90:cb3d968589d8	572	#define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
Kojto	90:cb3d968589d8	573
Kojto	90:cb3d968589d8	574	/! @brief Format value for bitfield I2S_TCSR_STOPE. /
Kojto	90:cb3d968589d8	575	#define BF_I2S_TCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_STOPE) & BM_I2S_TCSR_STOPE)
Kojto	90:cb3d968589d8	576
Kojto	90:cb3d968589d8	577	/! @brief Set the STOPE field to a new value. /
Kojto	90:cb3d968589d8	578	#define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
Kojto	90:cb3d968589d8	579	/@}/
Kojto	90:cb3d968589d8	580
Kojto	90:cb3d968589d8	581	/*!
Kojto	90:cb3d968589d8	582	* @name Register I2S_TCSR, field TE[31] (RW)
Kojto	90:cb3d968589d8	583	*
Kojto	90:cb3d968589d8	584	* Enables/disables the transmitter. When software clears this field, the
Kojto	90:cb3d968589d8	585	* transmitter remains enabled, and this bit remains set, until the end of the current
Kojto	90:cb3d968589d8	586	* frame.
Kojto	90:cb3d968589d8	587	*
Kojto	90:cb3d968589d8	588	* Values:
Kojto	90:cb3d968589d8	589	* - 0 - Transmitter is disabled.
Kojto	90:cb3d968589d8	590	* - 1 - Transmitter is enabled, or transmitter has been disabled and has not
Kojto	90:cb3d968589d8	591	* yet reached end of frame.
Kojto	90:cb3d968589d8	592	*/
Kojto	90:cb3d968589d8	593	/@{/
Kojto	90:cb3d968589d8	594	#define BP_I2S_TCSR_TE (31U) /!< Bit position for I2S_TCSR_TE. /
Kojto	90:cb3d968589d8	595	#define BM_I2S_TCSR_TE (0x80000000U) /!< Bit mask for I2S_TCSR_TE. /
Kojto	90:cb3d968589d8	596	#define BS_I2S_TCSR_TE (1U) /!< Bit field size in bits for I2S_TCSR_TE. /
Kojto	90:cb3d968589d8	597
Kojto	90:cb3d968589d8	598	/! @brief Read current value of the I2S_TCSR_TE field. /
Kojto	90:cb3d968589d8	599	#define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
Kojto	90:cb3d968589d8	600
Kojto	90:cb3d968589d8	601	/! @brief Format value for bitfield I2S_TCSR_TE. /
Kojto	90:cb3d968589d8	602	#define BF_I2S_TCSR_TE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_TE) & BM_I2S_TCSR_TE)
Kojto	90:cb3d968589d8	603
Kojto	90:cb3d968589d8	604	/! @brief Set the TE field to a new value. /
Kojto	90:cb3d968589d8	605	#define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
Kojto	90:cb3d968589d8	606	/@}/
Kojto	90:cb3d968589d8	607
Kojto	90:cb3d968589d8	608	/*******************************************************************************
Kojto	90:cb3d968589d8	609	* HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
Kojto	90:cb3d968589d8	610	******************************************************************************/
Kojto	90:cb3d968589d8	611
Kojto	90:cb3d968589d8	612	/*!
Kojto	90:cb3d968589d8	613	* @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
Kojto	90:cb3d968589d8	614	*
Kojto	90:cb3d968589d8	615	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	616	*/
Kojto	90:cb3d968589d8	617	typedef union _hw_i2s_tcr1
Kojto	90:cb3d968589d8	618	{
Kojto	90:cb3d968589d8	619	uint32_t U;
Kojto	90:cb3d968589d8	620	struct _hw_i2s_tcr1_bitfields
Kojto	90:cb3d968589d8	621	{
Kojto	90:cb3d968589d8	622	uint32_t TFW : 3; /!< [2:0] Transmit FIFO Watermark /
Kojto	90:cb3d968589d8	623	uint32_t RESERVED0 : 29; /!< [31:3] /
Kojto	90:cb3d968589d8	624	} B;
Kojto	90:cb3d968589d8	625	} hw_i2s_tcr1_t;
Kojto	90:cb3d968589d8	626
Kojto	90:cb3d968589d8	627	/*!
Kojto	90:cb3d968589d8	628	* @name Constants and macros for entire I2S_TCR1 register
Kojto	90:cb3d968589d8	629	*/
Kojto	90:cb3d968589d8	630	/@{/
Kojto	90:cb3d968589d8	631	#define HW_I2S_TCR1_ADDR(x) ((x) + 0x4U)
Kojto	90:cb3d968589d8	632
Kojto	90:cb3d968589d8	633	#define HW_I2S_TCR1(x) ((__IO hw_i2s_tcr1_t ) HW_I2S_TCR1_ADDR(x))
Kojto	90:cb3d968589d8	634	#define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U)
Kojto	90:cb3d968589d8	635	#define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v))
Kojto	90:cb3d968589d8	636	#define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	637	#define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	638	#define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	639	/@}/
Kojto	90:cb3d968589d8	640
Kojto	90:cb3d968589d8	641	/*
Kojto	90:cb3d968589d8	642	* Constants & macros for individual I2S_TCR1 bitfields
Kojto	90:cb3d968589d8	643	*/
Kojto	90:cb3d968589d8	644
Kojto	90:cb3d968589d8	645	/*!
Kojto	90:cb3d968589d8	646	* @name Register I2S_TCR1, field TFW[2:0] (RW)
Kojto	90:cb3d968589d8	647	*
Kojto	90:cb3d968589d8	648	* Configures the watermark level for all enabled transmit channels.
Kojto	90:cb3d968589d8	649	*/
Kojto	90:cb3d968589d8	650	/@{/
Kojto	90:cb3d968589d8	651	#define BP_I2S_TCR1_TFW (0U) /!< Bit position for I2S_TCR1_TFW. /
Kojto	90:cb3d968589d8	652	#define BM_I2S_TCR1_TFW (0x00000007U) /!< Bit mask for I2S_TCR1_TFW. /
Kojto	90:cb3d968589d8	653	#define BS_I2S_TCR1_TFW (3U) /!< Bit field size in bits for I2S_TCR1_TFW. /
Kojto	90:cb3d968589d8	654
Kojto	90:cb3d968589d8	655	/! @brief Read current value of the I2S_TCR1_TFW field. /
Kojto	90:cb3d968589d8	656	#define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW)
Kojto	90:cb3d968589d8	657
Kojto	90:cb3d968589d8	658	/! @brief Format value for bitfield I2S_TCR1_TFW. /
Kojto	90:cb3d968589d8	659	#define BF_I2S_TCR1_TFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR1_TFW) & BM_I2S_TCR1_TFW)
Kojto	90:cb3d968589d8	660
Kojto	90:cb3d968589d8	661	/! @brief Set the TFW field to a new value. /
Kojto	90:cb3d968589d8	662	#define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) \| BF_I2S_TCR1_TFW(v)))
Kojto	90:cb3d968589d8	663	/@}/
Kojto	90:cb3d968589d8	664
Kojto	90:cb3d968589d8	665	/*******************************************************************************
Kojto	90:cb3d968589d8	666	* HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
Kojto	90:cb3d968589d8	667	******************************************************************************/
Kojto	90:cb3d968589d8	668
Kojto	90:cb3d968589d8	669	/*!
Kojto	90:cb3d968589d8	670	* @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
Kojto	90:cb3d968589d8	671	*
Kojto	90:cb3d968589d8	672	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	673	*
Kojto	90:cb3d968589d8	674	* This register must not be altered when TCSR[TE] is set.
Kojto	90:cb3d968589d8	675	*/
Kojto	90:cb3d968589d8	676	typedef union _hw_i2s_tcr2
Kojto	90:cb3d968589d8	677	{
Kojto	90:cb3d968589d8	678	uint32_t U;
Kojto	90:cb3d968589d8	679	struct _hw_i2s_tcr2_bitfields
Kojto	90:cb3d968589d8	680	{
Kojto	90:cb3d968589d8	681	uint32_t DIV : 8; /!< [7:0] Bit Clock Divide /
Kojto	90:cb3d968589d8	682	uint32_t RESERVED0 : 16; /!< [23:8] /
Kojto	90:cb3d968589d8	683	uint32_t BCD : 1; /!< [24] Bit Clock Direction /
Kojto	90:cb3d968589d8	684	uint32_t BCP : 1; /!< [25] Bit Clock Polarity /
Kojto	90:cb3d968589d8	685	uint32_t MSEL : 2; /!< [27:26] MCLK Select /
Kojto	90:cb3d968589d8	686	uint32_t BCI : 1; /!< [28] Bit Clock Input /
Kojto	90:cb3d968589d8	687	uint32_t BCS : 1; /!< [29] Bit Clock Swap /
Kojto	90:cb3d968589d8	688	uint32_t SYNC : 2; /!< [31:30] Synchronous Mode /
Kojto	90:cb3d968589d8	689	} B;
Kojto	90:cb3d968589d8	690	} hw_i2s_tcr2_t;
Kojto	90:cb3d968589d8	691
Kojto	90:cb3d968589d8	692	/*!
Kojto	90:cb3d968589d8	693	* @name Constants and macros for entire I2S_TCR2 register
Kojto	90:cb3d968589d8	694	*/
Kojto	90:cb3d968589d8	695	/@{/
Kojto	90:cb3d968589d8	696	#define HW_I2S_TCR2_ADDR(x) ((x) + 0x8U)
Kojto	90:cb3d968589d8	697
Kojto	90:cb3d968589d8	698	#define HW_I2S_TCR2(x) ((__IO hw_i2s_tcr2_t ) HW_I2S_TCR2_ADDR(x))
Kojto	90:cb3d968589d8	699	#define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U)
Kojto	90:cb3d968589d8	700	#define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v))
Kojto	90:cb3d968589d8	701	#define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	702	#define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	703	#define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	704	/@}/
Kojto	90:cb3d968589d8	705
Kojto	90:cb3d968589d8	706	/*
Kojto	90:cb3d968589d8	707	* Constants & macros for individual I2S_TCR2 bitfields
Kojto	90:cb3d968589d8	708	*/
Kojto	90:cb3d968589d8	709
Kojto	90:cb3d968589d8	710	/*!
Kojto	90:cb3d968589d8	711	* @name Register I2S_TCR2, field DIV[7:0] (RW)
Kojto	90:cb3d968589d8	712	*
Kojto	90:cb3d968589d8	713	* Divides down the audio master clock to generate the bit clock when configured
Kojto	90:cb3d968589d8	714	* for an internal bit clock. The division value is (DIV + 1) * 2.
Kojto	90:cb3d968589d8	715	*/
Kojto	90:cb3d968589d8	716	/@{/
Kojto	90:cb3d968589d8	717	#define BP_I2S_TCR2_DIV (0U) /!< Bit position for I2S_TCR2_DIV. /
Kojto	90:cb3d968589d8	718	#define BM_I2S_TCR2_DIV (0x000000FFU) /!< Bit mask for I2S_TCR2_DIV. /
Kojto	90:cb3d968589d8	719	#define BS_I2S_TCR2_DIV (8U) /!< Bit field size in bits for I2S_TCR2_DIV. /
Kojto	90:cb3d968589d8	720
Kojto	90:cb3d968589d8	721	/! @brief Read current value of the I2S_TCR2_DIV field. /
Kojto	90:cb3d968589d8	722	#define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV)
Kojto	90:cb3d968589d8	723
Kojto	90:cb3d968589d8	724	/! @brief Format value for bitfield I2S_TCR2_DIV. /
Kojto	90:cb3d968589d8	725	#define BF_I2S_TCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_DIV) & BM_I2S_TCR2_DIV)
Kojto	90:cb3d968589d8	726
Kojto	90:cb3d968589d8	727	/! @brief Set the DIV field to a new value. /
Kojto	90:cb3d968589d8	728	#define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) \| BF_I2S_TCR2_DIV(v)))
Kojto	90:cb3d968589d8	729	/@}/
Kojto	90:cb3d968589d8	730
Kojto	90:cb3d968589d8	731	/*!
Kojto	90:cb3d968589d8	732	* @name Register I2S_TCR2, field BCD[24] (RW)
Kojto	90:cb3d968589d8	733	*
Kojto	90:cb3d968589d8	734	* Configures the direction of the bit clock.
Kojto	90:cb3d968589d8	735	*
Kojto	90:cb3d968589d8	736	* Values:
Kojto	90:cb3d968589d8	737	* - 0 - Bit clock is generated externally in Slave mode.
Kojto	90:cb3d968589d8	738	* - 1 - Bit clock is generated internally in Master mode.
Kojto	90:cb3d968589d8	739	*/
Kojto	90:cb3d968589d8	740	/@{/
Kojto	90:cb3d968589d8	741	#define BP_I2S_TCR2_BCD (24U) /!< Bit position for I2S_TCR2_BCD. /
Kojto	90:cb3d968589d8	742	#define BM_I2S_TCR2_BCD (0x01000000U) /!< Bit mask for I2S_TCR2_BCD. /
Kojto	90:cb3d968589d8	743	#define BS_I2S_TCR2_BCD (1U) /!< Bit field size in bits for I2S_TCR2_BCD. /
Kojto	90:cb3d968589d8	744
Kojto	90:cb3d968589d8	745	/! @brief Read current value of the I2S_TCR2_BCD field. /
Kojto	90:cb3d968589d8	746	#define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
Kojto	90:cb3d968589d8	747
Kojto	90:cb3d968589d8	748	/! @brief Format value for bitfield I2S_TCR2_BCD. /
Kojto	90:cb3d968589d8	749	#define BF_I2S_TCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCD) & BM_I2S_TCR2_BCD)
Kojto	90:cb3d968589d8	750
Kojto	90:cb3d968589d8	751	/! @brief Set the BCD field to a new value. /
Kojto	90:cb3d968589d8	752	#define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
Kojto	90:cb3d968589d8	753	/@}/
Kojto	90:cb3d968589d8	754
Kojto	90:cb3d968589d8	755	/*!
Kojto	90:cb3d968589d8	756	* @name Register I2S_TCR2, field BCP[25] (RW)
Kojto	90:cb3d968589d8	757	*
Kojto	90:cb3d968589d8	758	* Configures the polarity of the bit clock.
Kojto	90:cb3d968589d8	759	*
Kojto	90:cb3d968589d8	760	* Values:
Kojto	90:cb3d968589d8	761	* - 0 - Bit clock is active high with drive outputs on rising edge and sample
Kojto	90:cb3d968589d8	762	* inputs on falling edge.
Kojto	90:cb3d968589d8	763	* - 1 - Bit clock is active low with drive outputs on falling edge and sample
Kojto	90:cb3d968589d8	764	* inputs on rising edge.
Kojto	90:cb3d968589d8	765	*/
Kojto	90:cb3d968589d8	766	/@{/
Kojto	90:cb3d968589d8	767	#define BP_I2S_TCR2_BCP (25U) /!< Bit position for I2S_TCR2_BCP. /
Kojto	90:cb3d968589d8	768	#define BM_I2S_TCR2_BCP (0x02000000U) /!< Bit mask for I2S_TCR2_BCP. /
Kojto	90:cb3d968589d8	769	#define BS_I2S_TCR2_BCP (1U) /!< Bit field size in bits for I2S_TCR2_BCP. /
Kojto	90:cb3d968589d8	770
Kojto	90:cb3d968589d8	771	/! @brief Read current value of the I2S_TCR2_BCP field. /
Kojto	90:cb3d968589d8	772	#define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
Kojto	90:cb3d968589d8	773
Kojto	90:cb3d968589d8	774	/! @brief Format value for bitfield I2S_TCR2_BCP. /
Kojto	90:cb3d968589d8	775	#define BF_I2S_TCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCP) & BM_I2S_TCR2_BCP)
Kojto	90:cb3d968589d8	776
Kojto	90:cb3d968589d8	777	/! @brief Set the BCP field to a new value. /
Kojto	90:cb3d968589d8	778	#define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
Kojto	90:cb3d968589d8	779	/@}/
Kojto	90:cb3d968589d8	780
Kojto	90:cb3d968589d8	781	/*!
Kojto	90:cb3d968589d8	782	* @name Register I2S_TCR2, field MSEL[27:26] (RW)
Kojto	90:cb3d968589d8	783	*
Kojto	90:cb3d968589d8	784	* Selects the audio Master Clock option used to generate an internally
Kojto	90:cb3d968589d8	785	* generated bit clock. This field has no effect when configured for an externally
Kojto	90:cb3d968589d8	786	* generated bit clock. Depending on the device, some Master Clock options might not be
Kojto	90:cb3d968589d8	787	* available. See the chip configuration details for the availability and
Kojto	90:cb3d968589d8	788	* chip-specific meaning of each option.
Kojto	90:cb3d968589d8	789	*
Kojto	90:cb3d968589d8	790	* Values:
Kojto	90:cb3d968589d8	791	* - 00 - Bus Clock selected.
Kojto	90:cb3d968589d8	792	* - 01 - Master Clock (MCLK) 1 option selected.
Kojto	90:cb3d968589d8	793	* - 10 - Master Clock (MCLK) 2 option selected.
Kojto	90:cb3d968589d8	794	* - 11 - Master Clock (MCLK) 3 option selected.
Kojto	90:cb3d968589d8	795	*/
Kojto	90:cb3d968589d8	796	/@{/
Kojto	90:cb3d968589d8	797	#define BP_I2S_TCR2_MSEL (26U) /!< Bit position for I2S_TCR2_MSEL. /
Kojto	90:cb3d968589d8	798	#define BM_I2S_TCR2_MSEL (0x0C000000U) /!< Bit mask for I2S_TCR2_MSEL. /
Kojto	90:cb3d968589d8	799	#define BS_I2S_TCR2_MSEL (2U) /!< Bit field size in bits for I2S_TCR2_MSEL. /
Kojto	90:cb3d968589d8	800
Kojto	90:cb3d968589d8	801	/! @brief Read current value of the I2S_TCR2_MSEL field. /
Kojto	90:cb3d968589d8	802	#define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL)
Kojto	90:cb3d968589d8	803
Kojto	90:cb3d968589d8	804	/! @brief Format value for bitfield I2S_TCR2_MSEL. /
Kojto	90:cb3d968589d8	805	#define BF_I2S_TCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_MSEL) & BM_I2S_TCR2_MSEL)
Kojto	90:cb3d968589d8	806
Kojto	90:cb3d968589d8	807	/! @brief Set the MSEL field to a new value. /
Kojto	90:cb3d968589d8	808	#define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) \| BF_I2S_TCR2_MSEL(v)))
Kojto	90:cb3d968589d8	809	/@}/
Kojto	90:cb3d968589d8	810
Kojto	90:cb3d968589d8	811	/*!
Kojto	90:cb3d968589d8	812	* @name Register I2S_TCR2, field BCI[28] (RW)
Kojto	90:cb3d968589d8	813	*
Kojto	90:cb3d968589d8	814	* When this field is set and using an internally generated bit clock in either
Kojto	90:cb3d968589d8	815	* synchronous or asynchronous mode, the bit clock actually used by the
Kojto	90:cb3d968589d8	816	* transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
Kojto	90:cb3d968589d8	817	* input as if the clock was externally generated). This has the effect of
Kojto	90:cb3d968589d8	818	* decreasing the data input setup time, but increasing the data output valid time. The
Kojto	90:cb3d968589d8	819	* slave mode timing from the datasheet should be used for the transmitter when
Kojto	90:cb3d968589d8	820	* this bit is set. In synchronous mode, this bit allows the transmitter to use
Kojto	90:cb3d968589d8	821	* the slave mode timing from the datasheet, while the receiver uses the master
Kojto	90:cb3d968589d8	822	* mode timing. This field has no effect when configured for an externally generated
Kojto	90:cb3d968589d8	823	* bit clock or when synchronous to another SAI peripheral .
Kojto	90:cb3d968589d8	824	*
Kojto	90:cb3d968589d8	825	* Values:
Kojto	90:cb3d968589d8	826	* - 0 - No effect.
Kojto	90:cb3d968589d8	827	* - 1 - Internal logic is clocked as if bit clock was externally generated.
Kojto	90:cb3d968589d8	828	*/
Kojto	90:cb3d968589d8	829	/@{/
Kojto	90:cb3d968589d8	830	#define BP_I2S_TCR2_BCI (28U) /!< Bit position for I2S_TCR2_BCI. /
Kojto	90:cb3d968589d8	831	#define BM_I2S_TCR2_BCI (0x10000000U) /!< Bit mask for I2S_TCR2_BCI. /
Kojto	90:cb3d968589d8	832	#define BS_I2S_TCR2_BCI (1U) /!< Bit field size in bits for I2S_TCR2_BCI. /
Kojto	90:cb3d968589d8	833
Kojto	90:cb3d968589d8	834	/! @brief Read current value of the I2S_TCR2_BCI field. /
Kojto	90:cb3d968589d8	835	#define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
Kojto	90:cb3d968589d8	836
Kojto	90:cb3d968589d8	837	/! @brief Format value for bitfield I2S_TCR2_BCI. /
Kojto	90:cb3d968589d8	838	#define BF_I2S_TCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCI) & BM_I2S_TCR2_BCI)
Kojto	90:cb3d968589d8	839
Kojto	90:cb3d968589d8	840	/! @brief Set the BCI field to a new value. /
Kojto	90:cb3d968589d8	841	#define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
Kojto	90:cb3d968589d8	842	/@}/
Kojto	90:cb3d968589d8	843
Kojto	90:cb3d968589d8	844	/*!
Kojto	90:cb3d968589d8	845	* @name Register I2S_TCR2, field BCS[29] (RW)
Kojto	90:cb3d968589d8	846	*
Kojto	90:cb3d968589d8	847	* This field swaps the bit clock used by the transmitter. When the transmitter
Kojto	90:cb3d968589d8	848	* is configured in asynchronous mode and this bit is set, the transmitter is
Kojto	90:cb3d968589d8	849	* clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
Kojto	90:cb3d968589d8	850	* receiver to share the same bit clock, but the transmitter continues to use the
Kojto	90:cb3d968589d8	851	* transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
Kojto	90:cb3d968589d8	852	* synchronous mode, the transmitter BCS field and receiver BCS field must be set to
Kojto	90:cb3d968589d8	853	* the same value. When both are set, the transmitter and receiver are both
Kojto	90:cb3d968589d8	854	* clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
Kojto	90:cb3d968589d8	855	* (SAI_RX_SYNC). This field has no effect when synchronous to another SAI
Kojto	90:cb3d968589d8	856	* peripheral.
Kojto	90:cb3d968589d8	857	*
Kojto	90:cb3d968589d8	858	* Values:
Kojto	90:cb3d968589d8	859	* - 0 - Use the normal bit clock source.
Kojto	90:cb3d968589d8	860	* - 1 - Swap the bit clock source.
Kojto	90:cb3d968589d8	861	*/
Kojto	90:cb3d968589d8	862	/@{/
Kojto	90:cb3d968589d8	863	#define BP_I2S_TCR2_BCS (29U) /!< Bit position for I2S_TCR2_BCS. /
Kojto	90:cb3d968589d8	864	#define BM_I2S_TCR2_BCS (0x20000000U) /!< Bit mask for I2S_TCR2_BCS. /
Kojto	90:cb3d968589d8	865	#define BS_I2S_TCR2_BCS (1U) /!< Bit field size in bits for I2S_TCR2_BCS. /
Kojto	90:cb3d968589d8	866
Kojto	90:cb3d968589d8	867	/! @brief Read current value of the I2S_TCR2_BCS field. /
Kojto	90:cb3d968589d8	868	#define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
Kojto	90:cb3d968589d8	869
Kojto	90:cb3d968589d8	870	/! @brief Format value for bitfield I2S_TCR2_BCS. /
Kojto	90:cb3d968589d8	871	#define BF_I2S_TCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCS) & BM_I2S_TCR2_BCS)
Kojto	90:cb3d968589d8	872
Kojto	90:cb3d968589d8	873	/! @brief Set the BCS field to a new value. /
Kojto	90:cb3d968589d8	874	#define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
Kojto	90:cb3d968589d8	875	/@}/
Kojto	90:cb3d968589d8	876
Kojto	90:cb3d968589d8	877	/*!
Kojto	90:cb3d968589d8	878	* @name Register I2S_TCR2, field SYNC[31:30] (RW)
Kojto	90:cb3d968589d8	879	*
Kojto	90:cb3d968589d8	880	* Configures between asynchronous and synchronous modes of operation. When
Kojto	90:cb3d968589d8	881	* configured for a synchronous mode of operation, the receiver or other SAI
Kojto	90:cb3d968589d8	882	* peripheral must be configured for asynchronous operation.
Kojto	90:cb3d968589d8	883	*
Kojto	90:cb3d968589d8	884	* Values:
Kojto	90:cb3d968589d8	885	* - 00 - Asynchronous mode.
Kojto	90:cb3d968589d8	886	* - 01 - Synchronous with receiver.
Kojto	90:cb3d968589d8	887	* - 10 - Synchronous with another SAI transmitter.
Kojto	90:cb3d968589d8	888	* - 11 - Synchronous with another SAI receiver.
Kojto	90:cb3d968589d8	889	*/
Kojto	90:cb3d968589d8	890	/@{/
Kojto	90:cb3d968589d8	891	#define BP_I2S_TCR2_SYNC (30U) /!< Bit position for I2S_TCR2_SYNC. /
Kojto	90:cb3d968589d8	892	#define BM_I2S_TCR2_SYNC (0xC0000000U) /!< Bit mask for I2S_TCR2_SYNC. /
Kojto	90:cb3d968589d8	893	#define BS_I2S_TCR2_SYNC (2U) /!< Bit field size in bits for I2S_TCR2_SYNC. /
Kojto	90:cb3d968589d8	894
Kojto	90:cb3d968589d8	895	/! @brief Read current value of the I2S_TCR2_SYNC field. /
Kojto	90:cb3d968589d8	896	#define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC)
Kojto	90:cb3d968589d8	897
Kojto	90:cb3d968589d8	898	/! @brief Format value for bitfield I2S_TCR2_SYNC. /
Kojto	90:cb3d968589d8	899	#define BF_I2S_TCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_SYNC) & BM_I2S_TCR2_SYNC)
Kojto	90:cb3d968589d8	900
Kojto	90:cb3d968589d8	901	/! @brief Set the SYNC field to a new value. /
Kojto	90:cb3d968589d8	902	#define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) \| BF_I2S_TCR2_SYNC(v)))
Kojto	90:cb3d968589d8	903	/@}/
Kojto	90:cb3d968589d8	904
Kojto	90:cb3d968589d8	905	/*******************************************************************************
Kojto	90:cb3d968589d8	906	* HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
Kojto	90:cb3d968589d8	907	******************************************************************************/
Kojto	90:cb3d968589d8	908
Kojto	90:cb3d968589d8	909	/*!
Kojto	90:cb3d968589d8	910	* @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
Kojto	90:cb3d968589d8	911	*
Kojto	90:cb3d968589d8	912	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	913	*
Kojto	90:cb3d968589d8	914	* This register must not be altered when TCSR[TE] is set.
Kojto	90:cb3d968589d8	915	*/
Kojto	90:cb3d968589d8	916	typedef union _hw_i2s_tcr3
Kojto	90:cb3d968589d8	917	{
Kojto	90:cb3d968589d8	918	uint32_t U;
Kojto	90:cb3d968589d8	919	struct _hw_i2s_tcr3_bitfields
Kojto	90:cb3d968589d8	920	{
Kojto	90:cb3d968589d8	921	uint32_t WDFL : 5; /!< [4:0] Word Flag Configuration /
Kojto	90:cb3d968589d8	922	uint32_t RESERVED0 : 11; /!< [15:5] /
Kojto	90:cb3d968589d8	923	uint32_t TCE : 2; /!< [17:16] Transmit Channel Enable /
Kojto	90:cb3d968589d8	924	uint32_t RESERVED1 : 14; /!< [31:18] /
Kojto	90:cb3d968589d8	925	} B;
Kojto	90:cb3d968589d8	926	} hw_i2s_tcr3_t;
Kojto	90:cb3d968589d8	927
Kojto	90:cb3d968589d8	928	/*!
Kojto	90:cb3d968589d8	929	* @name Constants and macros for entire I2S_TCR3 register
Kojto	90:cb3d968589d8	930	*/
Kojto	90:cb3d968589d8	931	/@{/
Kojto	90:cb3d968589d8	932	#define HW_I2S_TCR3_ADDR(x) ((x) + 0xCU)
Kojto	90:cb3d968589d8	933
Kojto	90:cb3d968589d8	934	#define HW_I2S_TCR3(x) ((__IO hw_i2s_tcr3_t ) HW_I2S_TCR3_ADDR(x))
Kojto	90:cb3d968589d8	935	#define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U)
Kojto	90:cb3d968589d8	936	#define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v))
Kojto	90:cb3d968589d8	937	#define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) \| (v)))
Kojto	90:cb3d968589d8	938	#define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	939	#define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	940	/@}/
Kojto	90:cb3d968589d8	941
Kojto	90:cb3d968589d8	942	/*
Kojto	90:cb3d968589d8	943	* Constants & macros for individual I2S_TCR3 bitfields
Kojto	90:cb3d968589d8	944	*/
Kojto	90:cb3d968589d8	945
Kojto	90:cb3d968589d8	946	/*!
Kojto	90:cb3d968589d8	947	* @name Register I2S_TCR3, field WDFL[4:0] (RW)
Kojto	90:cb3d968589d8	948	*
Kojto	90:cb3d968589d8	949	* Configures which word sets the start of word flag. The value written must be
Kojto	90:cb3d968589d8	950	* one less than the word number. For example, writing 0 configures the first
Kojto	90:cb3d968589d8	951	* word in the frame. When configured to a value greater than TCR4[FRSZ], then the
Kojto	90:cb3d968589d8	952	* start of word flag is never set.
Kojto	90:cb3d968589d8	953	*/
Kojto	90:cb3d968589d8	954	/@{/
Kojto	90:cb3d968589d8	955	#define BP_I2S_TCR3_WDFL (0U) /!< Bit position for I2S_TCR3_WDFL. /
Kojto	90:cb3d968589d8	956	#define BM_I2S_TCR3_WDFL (0x0000001FU) /!< Bit mask for I2S_TCR3_WDFL. /
Kojto	90:cb3d968589d8	957	#define BS_I2S_TCR3_WDFL (5U) /!< Bit field size in bits for I2S_TCR3_WDFL. /
Kojto	90:cb3d968589d8	958
Kojto	90:cb3d968589d8	959	/! @brief Read current value of the I2S_TCR3_WDFL field. /
Kojto	90:cb3d968589d8	960	#define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL)
Kojto	90:cb3d968589d8	961
Kojto	90:cb3d968589d8	962	/! @brief Format value for bitfield I2S_TCR3_WDFL. /
Kojto	90:cb3d968589d8	963	#define BF_I2S_TCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_WDFL) & BM_I2S_TCR3_WDFL)
Kojto	90:cb3d968589d8	964
Kojto	90:cb3d968589d8	965	/! @brief Set the WDFL field to a new value. /
Kojto	90:cb3d968589d8	966	#define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) \| BF_I2S_TCR3_WDFL(v)))
Kojto	90:cb3d968589d8	967	/@}/
Kojto	90:cb3d968589d8	968
Kojto	90:cb3d968589d8	969	/*!
Kojto	90:cb3d968589d8	970	* @name Register I2S_TCR3, field TCE[17:16] (RW)
Kojto	90:cb3d968589d8	971	*
Kojto	90:cb3d968589d8	972	* Enables the corresponding data channel for transmit operation. A channel must
Kojto	90:cb3d968589d8	973	* be enabled before its FIFO is accessed.
Kojto	90:cb3d968589d8	974	*
Kojto	90:cb3d968589d8	975	* Values:
Kojto	90:cb3d968589d8	976	* - 0 - Transmit data channel N is disabled.
Kojto	90:cb3d968589d8	977	* - 1 - Transmit data channel N is enabled.
Kojto	90:cb3d968589d8	978	*/
Kojto	90:cb3d968589d8	979	/@{/
Kojto	90:cb3d968589d8	980	#define BP_I2S_TCR3_TCE (16U) /!< Bit position for I2S_TCR3_TCE. /
Kojto	90:cb3d968589d8	981	#define BM_I2S_TCR3_TCE (0x00030000U) /!< Bit mask for I2S_TCR3_TCE. /
Kojto	90:cb3d968589d8	982	#define BS_I2S_TCR3_TCE (2U) /!< Bit field size in bits for I2S_TCR3_TCE. /
Kojto	90:cb3d968589d8	983
Kojto	90:cb3d968589d8	984	/! @brief Read current value of the I2S_TCR3_TCE field. /
Kojto	90:cb3d968589d8	985	#define BR_I2S_TCR3_TCE(x) (HW_I2S_TCR3(x).B.TCE)
Kojto	90:cb3d968589d8	986
Kojto	90:cb3d968589d8	987	/! @brief Format value for bitfield I2S_TCR3_TCE. /
Kojto	90:cb3d968589d8	988	#define BF_I2S_TCR3_TCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_TCE) & BM_I2S_TCR3_TCE)
Kojto	90:cb3d968589d8	989
Kojto	90:cb3d968589d8	990	/! @brief Set the TCE field to a new value. /
Kojto	90:cb3d968589d8	991	#define BW_I2S_TCR3_TCE(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_TCE) \| BF_I2S_TCR3_TCE(v)))
Kojto	90:cb3d968589d8	992	/@}/
Kojto	90:cb3d968589d8	993
Kojto	90:cb3d968589d8	994	/*******************************************************************************
Kojto	90:cb3d968589d8	995	* HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
Kojto	90:cb3d968589d8	996	******************************************************************************/
Kojto	90:cb3d968589d8	997
Kojto	90:cb3d968589d8	998	/*!
Kojto	90:cb3d968589d8	999	* @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
Kojto	90:cb3d968589d8	1000	*
Kojto	90:cb3d968589d8	1001	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1002	*
Kojto	90:cb3d968589d8	1003	* This register must not be altered when TCSR[TE] is set.
Kojto	90:cb3d968589d8	1004	*/
Kojto	90:cb3d968589d8	1005	typedef union _hw_i2s_tcr4
Kojto	90:cb3d968589d8	1006	{
Kojto	90:cb3d968589d8	1007	uint32_t U;
Kojto	90:cb3d968589d8	1008	struct _hw_i2s_tcr4_bitfields
Kojto	90:cb3d968589d8	1009	{
Kojto	90:cb3d968589d8	1010	uint32_t FSD : 1; /!< [0] Frame Sync Direction /
Kojto	90:cb3d968589d8	1011	uint32_t FSP : 1; /!< [1] Frame Sync Polarity /
Kojto	90:cb3d968589d8	1012	uint32_t RESERVED0 : 1; /!< [2] /
Kojto	90:cb3d968589d8	1013	uint32_t FSE : 1; /!< [3] Frame Sync Early /
Kojto	90:cb3d968589d8	1014	uint32_t MF : 1; /!< [4] MSB First /
Kojto	90:cb3d968589d8	1015	uint32_t RESERVED1 : 3; /!< [7:5] /
Kojto	90:cb3d968589d8	1016	uint32_t SYWD : 5; /!< [12:8] Sync Width /
Kojto	90:cb3d968589d8	1017	uint32_t RESERVED2 : 3; /!< [15:13] /
Kojto	90:cb3d968589d8	1018	uint32_t FRSZ : 5; /!< [20:16] Frame size /
Kojto	90:cb3d968589d8	1019	uint32_t RESERVED3 : 11; /!< [31:21] /
Kojto	90:cb3d968589d8	1020	} B;
Kojto	90:cb3d968589d8	1021	} hw_i2s_tcr4_t;
Kojto	90:cb3d968589d8	1022
Kojto	90:cb3d968589d8	1023	/*!
Kojto	90:cb3d968589d8	1024	* @name Constants and macros for entire I2S_TCR4 register
Kojto	90:cb3d968589d8	1025	*/
Kojto	90:cb3d968589d8	1026	/@{/
Kojto	90:cb3d968589d8	1027	#define HW_I2S_TCR4_ADDR(x) ((x) + 0x10U)
Kojto	90:cb3d968589d8	1028
Kojto	90:cb3d968589d8	1029	#define HW_I2S_TCR4(x) ((__IO hw_i2s_tcr4_t ) HW_I2S_TCR4_ADDR(x))
Kojto	90:cb3d968589d8	1030	#define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U)
Kojto	90:cb3d968589d8	1031	#define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v))
Kojto	90:cb3d968589d8	1032	#define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1033	#define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1034	#define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1035	/@}/
Kojto	90:cb3d968589d8	1036
Kojto	90:cb3d968589d8	1037	/*
Kojto	90:cb3d968589d8	1038	* Constants & macros for individual I2S_TCR4 bitfields
Kojto	90:cb3d968589d8	1039	*/
Kojto	90:cb3d968589d8	1040
Kojto	90:cb3d968589d8	1041	/*!
Kojto	90:cb3d968589d8	1042	* @name Register I2S_TCR4, field FSD[0] (RW)
Kojto	90:cb3d968589d8	1043	*
Kojto	90:cb3d968589d8	1044	* Configures the direction of the frame sync.
Kojto	90:cb3d968589d8	1045	*
Kojto	90:cb3d968589d8	1046	* Values:
Kojto	90:cb3d968589d8	1047	* - 0 - Frame sync is generated externally in Slave mode.
Kojto	90:cb3d968589d8	1048	* - 1 - Frame sync is generated internally in Master mode.
Kojto	90:cb3d968589d8	1049	*/
Kojto	90:cb3d968589d8	1050	/@{/
Kojto	90:cb3d968589d8	1051	#define BP_I2S_TCR4_FSD (0U) /!< Bit position for I2S_TCR4_FSD. /
Kojto	90:cb3d968589d8	1052	#define BM_I2S_TCR4_FSD (0x00000001U) /!< Bit mask for I2S_TCR4_FSD. /
Kojto	90:cb3d968589d8	1053	#define BS_I2S_TCR4_FSD (1U) /!< Bit field size in bits for I2S_TCR4_FSD. /
Kojto	90:cb3d968589d8	1054
Kojto	90:cb3d968589d8	1055	/! @brief Read current value of the I2S_TCR4_FSD field. /
Kojto	90:cb3d968589d8	1056	#define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
Kojto	90:cb3d968589d8	1057
Kojto	90:cb3d968589d8	1058	/! @brief Format value for bitfield I2S_TCR4_FSD. /
Kojto	90:cb3d968589d8	1059	#define BF_I2S_TCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSD) & BM_I2S_TCR4_FSD)
Kojto	90:cb3d968589d8	1060
Kojto	90:cb3d968589d8	1061	/! @brief Set the FSD field to a new value. /
Kojto	90:cb3d968589d8	1062	#define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
Kojto	90:cb3d968589d8	1063	/@}/
Kojto	90:cb3d968589d8	1064
Kojto	90:cb3d968589d8	1065	/*!
Kojto	90:cb3d968589d8	1066	* @name Register I2S_TCR4, field FSP[1] (RW)
Kojto	90:cb3d968589d8	1067	*
Kojto	90:cb3d968589d8	1068	* Configures the polarity of the frame sync.
Kojto	90:cb3d968589d8	1069	*
Kojto	90:cb3d968589d8	1070	* Values:
Kojto	90:cb3d968589d8	1071	* - 0 - Frame sync is active high.
Kojto	90:cb3d968589d8	1072	* - 1 - Frame sync is active low.
Kojto	90:cb3d968589d8	1073	*/
Kojto	90:cb3d968589d8	1074	/@{/
Kojto	90:cb3d968589d8	1075	#define BP_I2S_TCR4_FSP (1U) /!< Bit position for I2S_TCR4_FSP. /
Kojto	90:cb3d968589d8	1076	#define BM_I2S_TCR4_FSP (0x00000002U) /!< Bit mask for I2S_TCR4_FSP. /
Kojto	90:cb3d968589d8	1077	#define BS_I2S_TCR4_FSP (1U) /!< Bit field size in bits for I2S_TCR4_FSP. /
Kojto	90:cb3d968589d8	1078
Kojto	90:cb3d968589d8	1079	/! @brief Read current value of the I2S_TCR4_FSP field. /
Kojto	90:cb3d968589d8	1080	#define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
Kojto	90:cb3d968589d8	1081
Kojto	90:cb3d968589d8	1082	/! @brief Format value for bitfield I2S_TCR4_FSP. /
Kojto	90:cb3d968589d8	1083	#define BF_I2S_TCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSP) & BM_I2S_TCR4_FSP)
Kojto	90:cb3d968589d8	1084
Kojto	90:cb3d968589d8	1085	/! @brief Set the FSP field to a new value. /
Kojto	90:cb3d968589d8	1086	#define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
Kojto	90:cb3d968589d8	1087	/@}/
Kojto	90:cb3d968589d8	1088
Kojto	90:cb3d968589d8	1089	/*!
Kojto	90:cb3d968589d8	1090	* @name Register I2S_TCR4, field FSE[3] (RW)
Kojto	90:cb3d968589d8	1091	*
Kojto	90:cb3d968589d8	1092	* Values:
Kojto	90:cb3d968589d8	1093	* - 0 - Frame sync asserts with the first bit of the frame.
Kojto	90:cb3d968589d8	1094	* - 1 - Frame sync asserts one bit before the first bit of the frame.
Kojto	90:cb3d968589d8	1095	*/
Kojto	90:cb3d968589d8	1096	/@{/
Kojto	90:cb3d968589d8	1097	#define BP_I2S_TCR4_FSE (3U) /!< Bit position for I2S_TCR4_FSE. /
Kojto	90:cb3d968589d8	1098	#define BM_I2S_TCR4_FSE (0x00000008U) /!< Bit mask for I2S_TCR4_FSE. /
Kojto	90:cb3d968589d8	1099	#define BS_I2S_TCR4_FSE (1U) /!< Bit field size in bits for I2S_TCR4_FSE. /
Kojto	90:cb3d968589d8	1100
Kojto	90:cb3d968589d8	1101	/! @brief Read current value of the I2S_TCR4_FSE field. /
Kojto	90:cb3d968589d8	1102	#define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
Kojto	90:cb3d968589d8	1103
Kojto	90:cb3d968589d8	1104	/! @brief Format value for bitfield I2S_TCR4_FSE. /
Kojto	90:cb3d968589d8	1105	#define BF_I2S_TCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSE) & BM_I2S_TCR4_FSE)
Kojto	90:cb3d968589d8	1106
Kojto	90:cb3d968589d8	1107	/! @brief Set the FSE field to a new value. /
Kojto	90:cb3d968589d8	1108	#define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
Kojto	90:cb3d968589d8	1109	/@}/
Kojto	90:cb3d968589d8	1110
Kojto	90:cb3d968589d8	1111	/*!
Kojto	90:cb3d968589d8	1112	* @name Register I2S_TCR4, field MF[4] (RW)
Kojto	90:cb3d968589d8	1113	*
Kojto	90:cb3d968589d8	1114	* Configures whether the LSB or the MSB is transmitted first.
Kojto	90:cb3d968589d8	1115	*
Kojto	90:cb3d968589d8	1116	* Values:
Kojto	90:cb3d968589d8	1117	* - 0 - LSB is transmitted first.
Kojto	90:cb3d968589d8	1118	* - 1 - MSB is transmitted first.
Kojto	90:cb3d968589d8	1119	*/
Kojto	90:cb3d968589d8	1120	/@{/
Kojto	90:cb3d968589d8	1121	#define BP_I2S_TCR4_MF (4U) /!< Bit position for I2S_TCR4_MF. /
Kojto	90:cb3d968589d8	1122	#define BM_I2S_TCR4_MF (0x00000010U) /!< Bit mask for I2S_TCR4_MF. /
Kojto	90:cb3d968589d8	1123	#define BS_I2S_TCR4_MF (1U) /!< Bit field size in bits for I2S_TCR4_MF. /
Kojto	90:cb3d968589d8	1124
Kojto	90:cb3d968589d8	1125	/! @brief Read current value of the I2S_TCR4_MF field. /
Kojto	90:cb3d968589d8	1126	#define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
Kojto	90:cb3d968589d8	1127
Kojto	90:cb3d968589d8	1128	/! @brief Format value for bitfield I2S_TCR4_MF. /
Kojto	90:cb3d968589d8	1129	#define BF_I2S_TCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_MF) & BM_I2S_TCR4_MF)
Kojto	90:cb3d968589d8	1130
Kojto	90:cb3d968589d8	1131	/! @brief Set the MF field to a new value. /
Kojto	90:cb3d968589d8	1132	#define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
Kojto	90:cb3d968589d8	1133	/@}/
Kojto	90:cb3d968589d8	1134
Kojto	90:cb3d968589d8	1135	/*!
Kojto	90:cb3d968589d8	1136	* @name Register I2S_TCR4, field SYWD[12:8] (RW)
Kojto	90:cb3d968589d8	1137	*
Kojto	90:cb3d968589d8	1138	* Configures the length of the frame sync in number of bit clocks. The value
Kojto	90:cb3d968589d8	1139	* written must be one less than the number of bit clocks. For example, write 0 for
Kojto	90:cb3d968589d8	1140	* the frame sync to assert for one bit clock only. The sync width cannot be
Kojto	90:cb3d968589d8	1141	* configured longer than the first word of the frame.
Kojto	90:cb3d968589d8	1142	*/
Kojto	90:cb3d968589d8	1143	/@{/
Kojto	90:cb3d968589d8	1144	#define BP_I2S_TCR4_SYWD (8U) /!< Bit position for I2S_TCR4_SYWD. /
Kojto	90:cb3d968589d8	1145	#define BM_I2S_TCR4_SYWD (0x00001F00U) /!< Bit mask for I2S_TCR4_SYWD. /
Kojto	90:cb3d968589d8	1146	#define BS_I2S_TCR4_SYWD (5U) /!< Bit field size in bits for I2S_TCR4_SYWD. /
Kojto	90:cb3d968589d8	1147
Kojto	90:cb3d968589d8	1148	/! @brief Read current value of the I2S_TCR4_SYWD field. /
Kojto	90:cb3d968589d8	1149	#define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD)
Kojto	90:cb3d968589d8	1150
Kojto	90:cb3d968589d8	1151	/! @brief Format value for bitfield I2S_TCR4_SYWD. /
Kojto	90:cb3d968589d8	1152	#define BF_I2S_TCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_SYWD) & BM_I2S_TCR4_SYWD)
Kojto	90:cb3d968589d8	1153
Kojto	90:cb3d968589d8	1154	/! @brief Set the SYWD field to a new value. /
Kojto	90:cb3d968589d8	1155	#define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) \| BF_I2S_TCR4_SYWD(v)))
Kojto	90:cb3d968589d8	1156	/@}/
Kojto	90:cb3d968589d8	1157
Kojto	90:cb3d968589d8	1158	/*!
Kojto	90:cb3d968589d8	1159	* @name Register I2S_TCR4, field FRSZ[20:16] (RW)
Kojto	90:cb3d968589d8	1160	*
Kojto	90:cb3d968589d8	1161	* Configures the number of words in each frame. The value written must be one
Kojto	90:cb3d968589d8	1162	* less than the number of words in the frame. For example, write 0 for one word
Kojto	90:cb3d968589d8	1163	* per frame. The maximum supported frame size is 32 words.
Kojto	90:cb3d968589d8	1164	*/
Kojto	90:cb3d968589d8	1165	/@{/
Kojto	90:cb3d968589d8	1166	#define BP_I2S_TCR4_FRSZ (16U) /!< Bit position for I2S_TCR4_FRSZ. /
Kojto	90:cb3d968589d8	1167	#define BM_I2S_TCR4_FRSZ (0x001F0000U) /!< Bit mask for I2S_TCR4_FRSZ. /
Kojto	90:cb3d968589d8	1168	#define BS_I2S_TCR4_FRSZ (5U) /!< Bit field size in bits for I2S_TCR4_FRSZ. /
Kojto	90:cb3d968589d8	1169
Kojto	90:cb3d968589d8	1170	/! @brief Read current value of the I2S_TCR4_FRSZ field. /
Kojto	90:cb3d968589d8	1171	#define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ)
Kojto	90:cb3d968589d8	1172
Kojto	90:cb3d968589d8	1173	/! @brief Format value for bitfield I2S_TCR4_FRSZ. /
Kojto	90:cb3d968589d8	1174	#define BF_I2S_TCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FRSZ) & BM_I2S_TCR4_FRSZ)
Kojto	90:cb3d968589d8	1175
Kojto	90:cb3d968589d8	1176	/! @brief Set the FRSZ field to a new value. /
Kojto	90:cb3d968589d8	1177	#define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) \| BF_I2S_TCR4_FRSZ(v)))
Kojto	90:cb3d968589d8	1178	/@}/
Kojto	90:cb3d968589d8	1179
Kojto	90:cb3d968589d8	1180	/*******************************************************************************
Kojto	90:cb3d968589d8	1181	* HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
Kojto	90:cb3d968589d8	1182	******************************************************************************/
Kojto	90:cb3d968589d8	1183
Kojto	90:cb3d968589d8	1184	/*!
Kojto	90:cb3d968589d8	1185	* @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
Kojto	90:cb3d968589d8	1186	*
Kojto	90:cb3d968589d8	1187	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1188	*
Kojto	90:cb3d968589d8	1189	* This register must not be altered when TCSR[TE] is set.
Kojto	90:cb3d968589d8	1190	*/
Kojto	90:cb3d968589d8	1191	typedef union _hw_i2s_tcr5
Kojto	90:cb3d968589d8	1192	{
Kojto	90:cb3d968589d8	1193	uint32_t U;
Kojto	90:cb3d968589d8	1194	struct _hw_i2s_tcr5_bitfields
Kojto	90:cb3d968589d8	1195	{
Kojto	90:cb3d968589d8	1196	uint32_t RESERVED0 : 8; /!< [7:0] /
Kojto	90:cb3d968589d8	1197	uint32_t FBT : 5; /!< [12:8] First Bit Shifted /
Kojto	90:cb3d968589d8	1198	uint32_t RESERVED1 : 3; /!< [15:13] /
Kojto	90:cb3d968589d8	1199	uint32_t W0W : 5; /!< [20:16] Word 0 Width /
Kojto	90:cb3d968589d8	1200	uint32_t RESERVED2 : 3; /!< [23:21] /
Kojto	90:cb3d968589d8	1201	uint32_t WNW : 5; /!< [28:24] Word N Width /
Kojto	90:cb3d968589d8	1202	uint32_t RESERVED3 : 3; /!< [31:29] /
Kojto	90:cb3d968589d8	1203	} B;
Kojto	90:cb3d968589d8	1204	} hw_i2s_tcr5_t;
Kojto	90:cb3d968589d8	1205
Kojto	90:cb3d968589d8	1206	/*!
Kojto	90:cb3d968589d8	1207	* @name Constants and macros for entire I2S_TCR5 register
Kojto	90:cb3d968589d8	1208	*/
Kojto	90:cb3d968589d8	1209	/@{/
Kojto	90:cb3d968589d8	1210	#define HW_I2S_TCR5_ADDR(x) ((x) + 0x14U)
Kojto	90:cb3d968589d8	1211
Kojto	90:cb3d968589d8	1212	#define HW_I2S_TCR5(x) ((__IO hw_i2s_tcr5_t ) HW_I2S_TCR5_ADDR(x))
Kojto	90:cb3d968589d8	1213	#define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U)
Kojto	90:cb3d968589d8	1214	#define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v))
Kojto	90:cb3d968589d8	1215	#define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1216	#define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1217	#define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1218	/@}/
Kojto	90:cb3d968589d8	1219
Kojto	90:cb3d968589d8	1220	/*
Kojto	90:cb3d968589d8	1221	* Constants & macros for individual I2S_TCR5 bitfields
Kojto	90:cb3d968589d8	1222	*/
Kojto	90:cb3d968589d8	1223
Kojto	90:cb3d968589d8	1224	/*!
Kojto	90:cb3d968589d8	1225	* @name Register I2S_TCR5, field FBT[12:8] (RW)
Kojto	90:cb3d968589d8	1226	*
Kojto	90:cb3d968589d8	1227	* Configures the bit index for the first bit transmitted for each word in the
Kojto	90:cb3d968589d8	1228	* frame. If configured for MSB First, the index of the next bit transmitted is
Kojto	90:cb3d968589d8	1229	* one less than the current bit transmitted. If configured for LSB First, the
Kojto	90:cb3d968589d8	1230	* index of the next bit transmitted is one more than the current bit transmitted.
Kojto	90:cb3d968589d8	1231	* The value written must be greater than or equal to the word width when
Kojto	90:cb3d968589d8	1232	* configured for MSB First. The value written must be less than or equal to 31-word width
Kojto	90:cb3d968589d8	1233	* when configured for LSB First.
Kojto	90:cb3d968589d8	1234	*/
Kojto	90:cb3d968589d8	1235	/@{/
Kojto	90:cb3d968589d8	1236	#define BP_I2S_TCR5_FBT (8U) /!< Bit position for I2S_TCR5_FBT. /
Kojto	90:cb3d968589d8	1237	#define BM_I2S_TCR5_FBT (0x00001F00U) /!< Bit mask for I2S_TCR5_FBT. /
Kojto	90:cb3d968589d8	1238	#define BS_I2S_TCR5_FBT (5U) /!< Bit field size in bits for I2S_TCR5_FBT. /
Kojto	90:cb3d968589d8	1239
Kojto	90:cb3d968589d8	1240	/! @brief Read current value of the I2S_TCR5_FBT field. /
Kojto	90:cb3d968589d8	1241	#define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT)
Kojto	90:cb3d968589d8	1242
Kojto	90:cb3d968589d8	1243	/! @brief Format value for bitfield I2S_TCR5_FBT. /
Kojto	90:cb3d968589d8	1244	#define BF_I2S_TCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_FBT) & BM_I2S_TCR5_FBT)
Kojto	90:cb3d968589d8	1245
Kojto	90:cb3d968589d8	1246	/! @brief Set the FBT field to a new value. /
Kojto	90:cb3d968589d8	1247	#define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) \| BF_I2S_TCR5_FBT(v)))
Kojto	90:cb3d968589d8	1248	/@}/
Kojto	90:cb3d968589d8	1249
Kojto	90:cb3d968589d8	1250	/*!
Kojto	90:cb3d968589d8	1251	* @name Register I2S_TCR5, field W0W[20:16] (RW)
Kojto	90:cb3d968589d8	1252	*
Kojto	90:cb3d968589d8	1253	* Configures the number of bits in the first word in each frame. The value
Kojto	90:cb3d968589d8	1254	* written must be one less than the number of bits in the first word. Word width of
Kojto	90:cb3d968589d8	1255	* less than 8 bits is not supported if there is only one word per frame.
Kojto	90:cb3d968589d8	1256	*/
Kojto	90:cb3d968589d8	1257	/@{/
Kojto	90:cb3d968589d8	1258	#define BP_I2S_TCR5_W0W (16U) /!< Bit position for I2S_TCR5_W0W. /
Kojto	90:cb3d968589d8	1259	#define BM_I2S_TCR5_W0W (0x001F0000U) /!< Bit mask for I2S_TCR5_W0W. /
Kojto	90:cb3d968589d8	1260	#define BS_I2S_TCR5_W0W (5U) /!< Bit field size in bits for I2S_TCR5_W0W. /
Kojto	90:cb3d968589d8	1261
Kojto	90:cb3d968589d8	1262	/! @brief Read current value of the I2S_TCR5_W0W field. /
Kojto	90:cb3d968589d8	1263	#define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W)
Kojto	90:cb3d968589d8	1264
Kojto	90:cb3d968589d8	1265	/! @brief Format value for bitfield I2S_TCR5_W0W. /
Kojto	90:cb3d968589d8	1266	#define BF_I2S_TCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_W0W) & BM_I2S_TCR5_W0W)
Kojto	90:cb3d968589d8	1267
Kojto	90:cb3d968589d8	1268	/! @brief Set the W0W field to a new value. /
Kojto	90:cb3d968589d8	1269	#define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) \| BF_I2S_TCR5_W0W(v)))
Kojto	90:cb3d968589d8	1270	/@}/
Kojto	90:cb3d968589d8	1271
Kojto	90:cb3d968589d8	1272	/*!
Kojto	90:cb3d968589d8	1273	* @name Register I2S_TCR5, field WNW[28:24] (RW)
Kojto	90:cb3d968589d8	1274	*
Kojto	90:cb3d968589d8	1275	* Configures the number of bits in each word, for each word except the first in
Kojto	90:cb3d968589d8	1276	* the frame. The value written must be one less than the number of bits per
Kojto	90:cb3d968589d8	1277	* word. Word width of less than 8 bits is not supported.
Kojto	90:cb3d968589d8	1278	*/
Kojto	90:cb3d968589d8	1279	/@{/
Kojto	90:cb3d968589d8	1280	#define BP_I2S_TCR5_WNW (24U) /!< Bit position for I2S_TCR5_WNW. /
Kojto	90:cb3d968589d8	1281	#define BM_I2S_TCR5_WNW (0x1F000000U) /!< Bit mask for I2S_TCR5_WNW. /
Kojto	90:cb3d968589d8	1282	#define BS_I2S_TCR5_WNW (5U) /!< Bit field size in bits for I2S_TCR5_WNW. /
Kojto	90:cb3d968589d8	1283
Kojto	90:cb3d968589d8	1284	/! @brief Read current value of the I2S_TCR5_WNW field. /
Kojto	90:cb3d968589d8	1285	#define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW)
Kojto	90:cb3d968589d8	1286
Kojto	90:cb3d968589d8	1287	/! @brief Format value for bitfield I2S_TCR5_WNW. /
Kojto	90:cb3d968589d8	1288	#define BF_I2S_TCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_WNW) & BM_I2S_TCR5_WNW)
Kojto	90:cb3d968589d8	1289
Kojto	90:cb3d968589d8	1290	/! @brief Set the WNW field to a new value. /
Kojto	90:cb3d968589d8	1291	#define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) \| BF_I2S_TCR5_WNW(v)))
Kojto	90:cb3d968589d8	1292	/@}/
Kojto	90:cb3d968589d8	1293
Kojto	90:cb3d968589d8	1294	/*******************************************************************************
Kojto	90:cb3d968589d8	1295	* HW_I2S_TDRn - SAI Transmit Data Register
Kojto	90:cb3d968589d8	1296	******************************************************************************/
Kojto	90:cb3d968589d8	1297
Kojto	90:cb3d968589d8	1298	/*!
Kojto	90:cb3d968589d8	1299	* @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
Kojto	90:cb3d968589d8	1300	*
Kojto	90:cb3d968589d8	1301	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1302	*/
Kojto	90:cb3d968589d8	1303	typedef union _hw_i2s_tdrn
Kojto	90:cb3d968589d8	1304	{
Kojto	90:cb3d968589d8	1305	uint32_t U;
Kojto	90:cb3d968589d8	1306	struct _hw_i2s_tdrn_bitfields
Kojto	90:cb3d968589d8	1307	{
Kojto	90:cb3d968589d8	1308	uint32_t TDR : 32; /!< [31:0] Transmit Data Register /
Kojto	90:cb3d968589d8	1309	} B;
Kojto	90:cb3d968589d8	1310	} hw_i2s_tdrn_t;
Kojto	90:cb3d968589d8	1311
Kojto	90:cb3d968589d8	1312	/*!
Kojto	90:cb3d968589d8	1313	* @name Constants and macros for entire I2S_TDRn register
Kojto	90:cb3d968589d8	1314	*/
Kojto	90:cb3d968589d8	1315	/@{/
Kojto	90:cb3d968589d8	1316	#define HW_I2S_TDRn_COUNT (2U)
Kojto	90:cb3d968589d8	1317
Kojto	90:cb3d968589d8	1318	#define HW_I2S_TDRn_ADDR(x, n) ((x) + 0x20U + (0x4U * (n)))
Kojto	90:cb3d968589d8	1319
Kojto	90:cb3d968589d8	1320	#define HW_I2S_TDRn(x, n) ((__O hw_i2s_tdrn_t ) HW_I2S_TDRn_ADDR(x, n))
Kojto	90:cb3d968589d8	1321	#define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U)
Kojto	90:cb3d968589d8	1322	#define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v))
Kojto	90:cb3d968589d8	1323	/@}/
Kojto	90:cb3d968589d8	1324
Kojto	90:cb3d968589d8	1325	/*
Kojto	90:cb3d968589d8	1326	* Constants & macros for individual I2S_TDRn bitfields
Kojto	90:cb3d968589d8	1327	*/
Kojto	90:cb3d968589d8	1328
Kojto	90:cb3d968589d8	1329	/*!
Kojto	90:cb3d968589d8	1330	* @name Register I2S_TDRn, field TDR[31:0] (WORZ)
Kojto	90:cb3d968589d8	1331	*
Kojto	90:cb3d968589d8	1332	* The corresponding TCR3[TCE] bit must be set before accessing the channel's
Kojto	90:cb3d968589d8	1333	* transmit data register. Writes to this register when the transmit FIFO is not
Kojto	90:cb3d968589d8	1334	* full will push the data written into the transmit data FIFO. Writes to this
Kojto	90:cb3d968589d8	1335	* register when the transmit FIFO is full are ignored.
Kojto	90:cb3d968589d8	1336	*/
Kojto	90:cb3d968589d8	1337	/@{/
Kojto	90:cb3d968589d8	1338	#define BP_I2S_TDRn_TDR (0U) /!< Bit position for I2S_TDRn_TDR. /
Kojto	90:cb3d968589d8	1339	#define BM_I2S_TDRn_TDR (0xFFFFFFFFU) /!< Bit mask for I2S_TDRn_TDR. /
Kojto	90:cb3d968589d8	1340	#define BS_I2S_TDRn_TDR (32U) /!< Bit field size in bits for I2S_TDRn_TDR. /
Kojto	90:cb3d968589d8	1341
Kojto	90:cb3d968589d8	1342	/! @brief Format value for bitfield I2S_TDRn_TDR. /
Kojto	90:cb3d968589d8	1343	#define BF_I2S_TDRn_TDR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TDRn_TDR) & BM_I2S_TDRn_TDR)
Kojto	90:cb3d968589d8	1344
Kojto	90:cb3d968589d8	1345	/! @brief Set the TDR field to a new value. /
Kojto	90:cb3d968589d8	1346	#define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
Kojto	90:cb3d968589d8	1347	/@}/
Kojto	90:cb3d968589d8	1348
Kojto	90:cb3d968589d8	1349	/*******************************************************************************
Kojto	90:cb3d968589d8	1350	* HW_I2S_TFRn - SAI Transmit FIFO Register
Kojto	90:cb3d968589d8	1351	******************************************************************************/
Kojto	90:cb3d968589d8	1352
Kojto	90:cb3d968589d8	1353	/*!
Kojto	90:cb3d968589d8	1354	* @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
Kojto	90:cb3d968589d8	1355	*
Kojto	90:cb3d968589d8	1356	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1357	*
Kojto	90:cb3d968589d8	1358	* The MSB of the read and write pointers is used to distinguish between FIFO
Kojto	90:cb3d968589d8	1359	* full and empty conditions. If the read and write pointers are identical, then
Kojto	90:cb3d968589d8	1360	* the FIFO is empty. If the read and write pointers are identical except for the
Kojto	90:cb3d968589d8	1361	* MSB, then the FIFO is full.
Kojto	90:cb3d968589d8	1362	*/
Kojto	90:cb3d968589d8	1363	typedef union _hw_i2s_tfrn
Kojto	90:cb3d968589d8	1364	{
Kojto	90:cb3d968589d8	1365	uint32_t U;
Kojto	90:cb3d968589d8	1366	struct _hw_i2s_tfrn_bitfields
Kojto	90:cb3d968589d8	1367	{
Kojto	90:cb3d968589d8	1368	uint32_t RFP : 4; /!< [3:0] Read FIFO Pointer /
Kojto	90:cb3d968589d8	1369	uint32_t RESERVED0 : 12; /!< [15:4] /
Kojto	90:cb3d968589d8	1370	uint32_t WFP : 4; /!< [19:16] Write FIFO Pointer /
Kojto	90:cb3d968589d8	1371	uint32_t RESERVED1 : 12; /!< [31:20] /
Kojto	90:cb3d968589d8	1372	} B;
Kojto	90:cb3d968589d8	1373	} hw_i2s_tfrn_t;
Kojto	90:cb3d968589d8	1374
Kojto	90:cb3d968589d8	1375	/*!
Kojto	90:cb3d968589d8	1376	* @name Constants and macros for entire I2S_TFRn register
Kojto	90:cb3d968589d8	1377	*/
Kojto	90:cb3d968589d8	1378	/@{/
Kojto	90:cb3d968589d8	1379	#define HW_I2S_TFRn_COUNT (2U)
Kojto	90:cb3d968589d8	1380
Kojto	90:cb3d968589d8	1381	#define HW_I2S_TFRn_ADDR(x, n) ((x) + 0x40U + (0x4U * (n)))
Kojto	90:cb3d968589d8	1382
Kojto	90:cb3d968589d8	1383	#define HW_I2S_TFRn(x, n) ((__I hw_i2s_tfrn_t ) HW_I2S_TFRn_ADDR(x, n))
Kojto	90:cb3d968589d8	1384	#define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U)
Kojto	90:cb3d968589d8	1385	/@}/
Kojto	90:cb3d968589d8	1386
Kojto	90:cb3d968589d8	1387	/*
Kojto	90:cb3d968589d8	1388	* Constants & macros for individual I2S_TFRn bitfields
Kojto	90:cb3d968589d8	1389	*/
Kojto	90:cb3d968589d8	1390
Kojto	90:cb3d968589d8	1391	/*!
Kojto	90:cb3d968589d8	1392	* @name Register I2S_TFRn, field RFP[3:0] (RO)
Kojto	90:cb3d968589d8	1393	*
Kojto	90:cb3d968589d8	1394	* FIFO read pointer for transmit data channel.
Kojto	90:cb3d968589d8	1395	*/
Kojto	90:cb3d968589d8	1396	/@{/
Kojto	90:cb3d968589d8	1397	#define BP_I2S_TFRn_RFP (0U) /!< Bit position for I2S_TFRn_RFP. /
Kojto	90:cb3d968589d8	1398	#define BM_I2S_TFRn_RFP (0x0000000FU) /!< Bit mask for I2S_TFRn_RFP. /
Kojto	90:cb3d968589d8	1399	#define BS_I2S_TFRn_RFP (4U) /!< Bit field size in bits for I2S_TFRn_RFP. /
Kojto	90:cb3d968589d8	1400
Kojto	90:cb3d968589d8	1401	/! @brief Read current value of the I2S_TFRn_RFP field. /
Kojto	90:cb3d968589d8	1402	#define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
Kojto	90:cb3d968589d8	1403	/@}/
Kojto	90:cb3d968589d8	1404
Kojto	90:cb3d968589d8	1405	/*!
Kojto	90:cb3d968589d8	1406	* @name Register I2S_TFRn, field WFP[19:16] (RO)
Kojto	90:cb3d968589d8	1407	*
Kojto	90:cb3d968589d8	1408	* FIFO write pointer for transmit data channel.
Kojto	90:cb3d968589d8	1409	*/
Kojto	90:cb3d968589d8	1410	/@{/
Kojto	90:cb3d968589d8	1411	#define BP_I2S_TFRn_WFP (16U) /!< Bit position for I2S_TFRn_WFP. /
Kojto	90:cb3d968589d8	1412	#define BM_I2S_TFRn_WFP (0x000F0000U) /!< Bit mask for I2S_TFRn_WFP. /
Kojto	90:cb3d968589d8	1413	#define BS_I2S_TFRn_WFP (4U) /!< Bit field size in bits for I2S_TFRn_WFP. /
Kojto	90:cb3d968589d8	1414
Kojto	90:cb3d968589d8	1415	/! @brief Read current value of the I2S_TFRn_WFP field. /
Kojto	90:cb3d968589d8	1416	#define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
Kojto	90:cb3d968589d8	1417	/@}/
Kojto	90:cb3d968589d8	1418
Kojto	90:cb3d968589d8	1419	/*******************************************************************************
Kojto	90:cb3d968589d8	1420	* HW_I2S_TMR - SAI Transmit Mask Register
Kojto	90:cb3d968589d8	1421	******************************************************************************/
Kojto	90:cb3d968589d8	1422
Kojto	90:cb3d968589d8	1423	/*!
Kojto	90:cb3d968589d8	1424	* @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
Kojto	90:cb3d968589d8	1425	*
Kojto	90:cb3d968589d8	1426	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1427	*
Kojto	90:cb3d968589d8	1428	* This register is double-buffered and updates: When TCSR[TE] is first set At
Kojto	90:cb3d968589d8	1429	* the end of each frame. This allows the masked words in each frame to change
Kojto	90:cb3d968589d8	1430	* from frame to frame.
Kojto	90:cb3d968589d8	1431	*/
Kojto	90:cb3d968589d8	1432	typedef union _hw_i2s_tmr
Kojto	90:cb3d968589d8	1433	{
Kojto	90:cb3d968589d8	1434	uint32_t U;
Kojto	90:cb3d968589d8	1435	struct _hw_i2s_tmr_bitfields
Kojto	90:cb3d968589d8	1436	{
Kojto	90:cb3d968589d8	1437	uint32_t TWM : 32; /!< [31:0] Transmit Word Mask /
Kojto	90:cb3d968589d8	1438	} B;
Kojto	90:cb3d968589d8	1439	} hw_i2s_tmr_t;
Kojto	90:cb3d968589d8	1440
Kojto	90:cb3d968589d8	1441	/*!
Kojto	90:cb3d968589d8	1442	* @name Constants and macros for entire I2S_TMR register
Kojto	90:cb3d968589d8	1443	*/
Kojto	90:cb3d968589d8	1444	/@{/
Kojto	90:cb3d968589d8	1445	#define HW_I2S_TMR_ADDR(x) ((x) + 0x60U)
Kojto	90:cb3d968589d8	1446
Kojto	90:cb3d968589d8	1447	#define HW_I2S_TMR(x) ((__IO hw_i2s_tmr_t ) HW_I2S_TMR_ADDR(x))
Kojto	90:cb3d968589d8	1448	#define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U)
Kojto	90:cb3d968589d8	1449	#define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v))
Kojto	90:cb3d968589d8	1450	#define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1451	#define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1452	#define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1453	/@}/
Kojto	90:cb3d968589d8	1454
Kojto	90:cb3d968589d8	1455	/*
Kojto	90:cb3d968589d8	1456	* Constants & macros for individual I2S_TMR bitfields
Kojto	90:cb3d968589d8	1457	*/
Kojto	90:cb3d968589d8	1458
Kojto	90:cb3d968589d8	1459	/*!
Kojto	90:cb3d968589d8	1460	* @name Register I2S_TMR, field TWM[31:0] (RW)
Kojto	90:cb3d968589d8	1461	*
Kojto	90:cb3d968589d8	1462	* Configures whether the transmit word is masked (transmit data pin tristated
Kojto	90:cb3d968589d8	1463	* and transmit data not read from FIFO) for the corresponding word in the frame.
Kojto	90:cb3d968589d8	1464	*
Kojto	90:cb3d968589d8	1465	* Values:
Kojto	90:cb3d968589d8	1466	* - 0 - Word N is enabled.
Kojto	90:cb3d968589d8	1467	* - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
Kojto	90:cb3d968589d8	1468	*/
Kojto	90:cb3d968589d8	1469	/@{/
Kojto	90:cb3d968589d8	1470	#define BP_I2S_TMR_TWM (0U) /!< Bit position for I2S_TMR_TWM. /
Kojto	90:cb3d968589d8	1471	#define BM_I2S_TMR_TWM (0xFFFFFFFFU) /!< Bit mask for I2S_TMR_TWM. /
Kojto	90:cb3d968589d8	1472	#define BS_I2S_TMR_TWM (32U) /!< Bit field size in bits for I2S_TMR_TWM. /
Kojto	90:cb3d968589d8	1473
Kojto	90:cb3d968589d8	1474	/! @brief Read current value of the I2S_TMR_TWM field. /
Kojto	90:cb3d968589d8	1475	#define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).U)
Kojto	90:cb3d968589d8	1476
Kojto	90:cb3d968589d8	1477	/! @brief Format value for bitfield I2S_TMR_TWM. /
Kojto	90:cb3d968589d8	1478	#define BF_I2S_TMR_TWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TMR_TWM) & BM_I2S_TMR_TWM)
Kojto	90:cb3d968589d8	1479
Kojto	90:cb3d968589d8	1480	/! @brief Set the TWM field to a new value. /
Kojto	90:cb3d968589d8	1481	#define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, v))
Kojto	90:cb3d968589d8	1482	/@}/
Kojto	90:cb3d968589d8	1483
Kojto	90:cb3d968589d8	1484	/*******************************************************************************
Kojto	90:cb3d968589d8	1485	* HW_I2S_RCSR - SAI Receive Control Register
Kojto	90:cb3d968589d8	1486	******************************************************************************/
Kojto	90:cb3d968589d8	1487
Kojto	90:cb3d968589d8	1488	/*!
Kojto	90:cb3d968589d8	1489	* @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
Kojto	90:cb3d968589d8	1490	*
Kojto	90:cb3d968589d8	1491	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1492	*/
Kojto	90:cb3d968589d8	1493	typedef union _hw_i2s_rcsr
Kojto	90:cb3d968589d8	1494	{
Kojto	90:cb3d968589d8	1495	uint32_t U;
Kojto	90:cb3d968589d8	1496	struct _hw_i2s_rcsr_bitfields
Kojto	90:cb3d968589d8	1497	{
Kojto	90:cb3d968589d8	1498	uint32_t FRDE : 1; /!< [0] FIFO Request DMA Enable /
Kojto	90:cb3d968589d8	1499	uint32_t FWDE : 1; /!< [1] FIFO Warning DMA Enable /
Kojto	90:cb3d968589d8	1500	uint32_t RESERVED0 : 6; /!< [7:2] /
Kojto	90:cb3d968589d8	1501	uint32_t FRIE : 1; /!< [8] FIFO Request Interrupt Enable /
Kojto	90:cb3d968589d8	1502	uint32_t FWIE : 1; /!< [9] FIFO Warning Interrupt Enable /
Kojto	90:cb3d968589d8	1503	uint32_t FEIE : 1; /!< [10] FIFO Error Interrupt Enable /
Kojto	90:cb3d968589d8	1504	uint32_t SEIE : 1; /!< [11] Sync Error Interrupt Enable /
Kojto	90:cb3d968589d8	1505	uint32_t WSIE : 1; /!< [12] Word Start Interrupt Enable /
Kojto	90:cb3d968589d8	1506	uint32_t RESERVED1 : 3; /!< [15:13] /
Kojto	90:cb3d968589d8	1507	uint32_t FRF : 1; /!< [16] FIFO Request Flag /
Kojto	90:cb3d968589d8	1508	uint32_t FWF : 1; /!< [17] FIFO Warning Flag /
Kojto	90:cb3d968589d8	1509	uint32_t FEF : 1; /!< [18] FIFO Error Flag /
Kojto	90:cb3d968589d8	1510	uint32_t SEF : 1; /!< [19] Sync Error Flag /
Kojto	90:cb3d968589d8	1511	uint32_t WSF : 1; /!< [20] Word Start Flag /
Kojto	90:cb3d968589d8	1512	uint32_t RESERVED2 : 3; /!< [23:21] /
Kojto	90:cb3d968589d8	1513	uint32_t SR : 1; /!< [24] Software Reset /
Kojto	90:cb3d968589d8	1514	uint32_t FR : 1; /!< [25] FIFO Reset /
Kojto	90:cb3d968589d8	1515	uint32_t RESERVED3 : 2; /!< [27:26] /
Kojto	90:cb3d968589d8	1516	uint32_t BCE : 1; /!< [28] Bit Clock Enable /
Kojto	90:cb3d968589d8	1517	uint32_t DBGE : 1; /!< [29] Debug Enable /
Kojto	90:cb3d968589d8	1518	uint32_t STOPE : 1; /!< [30] Stop Enable /
Kojto	90:cb3d968589d8	1519	uint32_t RE : 1; /!< [31] Receiver Enable /
Kojto	90:cb3d968589d8	1520	} B;
Kojto	90:cb3d968589d8	1521	} hw_i2s_rcsr_t;
Kojto	90:cb3d968589d8	1522
Kojto	90:cb3d968589d8	1523	/*!
Kojto	90:cb3d968589d8	1524	* @name Constants and macros for entire I2S_RCSR register
Kojto	90:cb3d968589d8	1525	*/
Kojto	90:cb3d968589d8	1526	/@{/
Kojto	90:cb3d968589d8	1527	#define HW_I2S_RCSR_ADDR(x) ((x) + 0x80U)
Kojto	90:cb3d968589d8	1528
Kojto	90:cb3d968589d8	1529	#define HW_I2S_RCSR(x) ((__IO hw_i2s_rcsr_t ) HW_I2S_RCSR_ADDR(x))
Kojto	90:cb3d968589d8	1530	#define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U)
Kojto	90:cb3d968589d8	1531	#define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v))
Kojto	90:cb3d968589d8	1532	#define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	1533	#define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	1534	#define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	1535	/@}/
Kojto	90:cb3d968589d8	1536
Kojto	90:cb3d968589d8	1537	/*
Kojto	90:cb3d968589d8	1538	* Constants & macros for individual I2S_RCSR bitfields
Kojto	90:cb3d968589d8	1539	*/
Kojto	90:cb3d968589d8	1540
Kojto	90:cb3d968589d8	1541	/*!
Kojto	90:cb3d968589d8	1542	* @name Register I2S_RCSR, field FRDE[0] (RW)
Kojto	90:cb3d968589d8	1543	*
Kojto	90:cb3d968589d8	1544	* Enables/disables DMA requests.
Kojto	90:cb3d968589d8	1545	*
Kojto	90:cb3d968589d8	1546	* Values:
Kojto	90:cb3d968589d8	1547	* - 0 - Disables the DMA request.
Kojto	90:cb3d968589d8	1548	* - 1 - Enables the DMA request.
Kojto	90:cb3d968589d8	1549	*/
Kojto	90:cb3d968589d8	1550	/@{/
Kojto	90:cb3d968589d8	1551	#define BP_I2S_RCSR_FRDE (0U) /!< Bit position for I2S_RCSR_FRDE. /
Kojto	90:cb3d968589d8	1552	#define BM_I2S_RCSR_FRDE (0x00000001U) /!< Bit mask for I2S_RCSR_FRDE. /
Kojto	90:cb3d968589d8	1553	#define BS_I2S_RCSR_FRDE (1U) /!< Bit field size in bits for I2S_RCSR_FRDE. /
Kojto	90:cb3d968589d8	1554
Kojto	90:cb3d968589d8	1555	/! @brief Read current value of the I2S_RCSR_FRDE field. /
Kojto	90:cb3d968589d8	1556	#define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
Kojto	90:cb3d968589d8	1557
Kojto	90:cb3d968589d8	1558	/! @brief Format value for bitfield I2S_RCSR_FRDE. /
Kojto	90:cb3d968589d8	1559	#define BF_I2S_RCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRDE) & BM_I2S_RCSR_FRDE)
Kojto	90:cb3d968589d8	1560
Kojto	90:cb3d968589d8	1561	/! @brief Set the FRDE field to a new value. /
Kojto	90:cb3d968589d8	1562	#define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
Kojto	90:cb3d968589d8	1563	/@}/
Kojto	90:cb3d968589d8	1564
Kojto	90:cb3d968589d8	1565	/*!
Kojto	90:cb3d968589d8	1566	* @name Register I2S_RCSR, field FWDE[1] (RW)
Kojto	90:cb3d968589d8	1567	*
Kojto	90:cb3d968589d8	1568	* Enables/disables DMA requests.
Kojto	90:cb3d968589d8	1569	*
Kojto	90:cb3d968589d8	1570	* Values:
Kojto	90:cb3d968589d8	1571	* - 0 - Disables the DMA request.
Kojto	90:cb3d968589d8	1572	* - 1 - Enables the DMA request.
Kojto	90:cb3d968589d8	1573	*/
Kojto	90:cb3d968589d8	1574	/@{/
Kojto	90:cb3d968589d8	1575	#define BP_I2S_RCSR_FWDE (1U) /!< Bit position for I2S_RCSR_FWDE. /
Kojto	90:cb3d968589d8	1576	#define BM_I2S_RCSR_FWDE (0x00000002U) /!< Bit mask for I2S_RCSR_FWDE. /
Kojto	90:cb3d968589d8	1577	#define BS_I2S_RCSR_FWDE (1U) /!< Bit field size in bits for I2S_RCSR_FWDE. /
Kojto	90:cb3d968589d8	1578
Kojto	90:cb3d968589d8	1579	/! @brief Read current value of the I2S_RCSR_FWDE field. /
Kojto	90:cb3d968589d8	1580	#define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
Kojto	90:cb3d968589d8	1581
Kojto	90:cb3d968589d8	1582	/! @brief Format value for bitfield I2S_RCSR_FWDE. /
Kojto	90:cb3d968589d8	1583	#define BF_I2S_RCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWDE) & BM_I2S_RCSR_FWDE)
Kojto	90:cb3d968589d8	1584
Kojto	90:cb3d968589d8	1585	/! @brief Set the FWDE field to a new value. /
Kojto	90:cb3d968589d8	1586	#define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
Kojto	90:cb3d968589d8	1587	/@}/
Kojto	90:cb3d968589d8	1588
Kojto	90:cb3d968589d8	1589	/*!
Kojto	90:cb3d968589d8	1590	* @name Register I2S_RCSR, field FRIE[8] (RW)
Kojto	90:cb3d968589d8	1591	*
Kojto	90:cb3d968589d8	1592	* Enables/disables FIFO request interrupts.
Kojto	90:cb3d968589d8	1593	*
Kojto	90:cb3d968589d8	1594	* Values:
Kojto	90:cb3d968589d8	1595	* - 0 - Disables the interrupt.
Kojto	90:cb3d968589d8	1596	* - 1 - Enables the interrupt.
Kojto	90:cb3d968589d8	1597	*/
Kojto	90:cb3d968589d8	1598	/@{/
Kojto	90:cb3d968589d8	1599	#define BP_I2S_RCSR_FRIE (8U) /!< Bit position for I2S_RCSR_FRIE. /
Kojto	90:cb3d968589d8	1600	#define BM_I2S_RCSR_FRIE (0x00000100U) /!< Bit mask for I2S_RCSR_FRIE. /
Kojto	90:cb3d968589d8	1601	#define BS_I2S_RCSR_FRIE (1U) /!< Bit field size in bits for I2S_RCSR_FRIE. /
Kojto	90:cb3d968589d8	1602
Kojto	90:cb3d968589d8	1603	/! @brief Read current value of the I2S_RCSR_FRIE field. /
Kojto	90:cb3d968589d8	1604	#define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
Kojto	90:cb3d968589d8	1605
Kojto	90:cb3d968589d8	1606	/! @brief Format value for bitfield I2S_RCSR_FRIE. /
Kojto	90:cb3d968589d8	1607	#define BF_I2S_RCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRIE) & BM_I2S_RCSR_FRIE)
Kojto	90:cb3d968589d8	1608
Kojto	90:cb3d968589d8	1609	/! @brief Set the FRIE field to a new value. /
Kojto	90:cb3d968589d8	1610	#define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
Kojto	90:cb3d968589d8	1611	/@}/
Kojto	90:cb3d968589d8	1612
Kojto	90:cb3d968589d8	1613	/*!
Kojto	90:cb3d968589d8	1614	* @name Register I2S_RCSR, field FWIE[9] (RW)
Kojto	90:cb3d968589d8	1615	*
Kojto	90:cb3d968589d8	1616	* Enables/disables FIFO warning interrupts.
Kojto	90:cb3d968589d8	1617	*
Kojto	90:cb3d968589d8	1618	* Values:
Kojto	90:cb3d968589d8	1619	* - 0 - Disables the interrupt.
Kojto	90:cb3d968589d8	1620	* - 1 - Enables the interrupt.
Kojto	90:cb3d968589d8	1621	*/
Kojto	90:cb3d968589d8	1622	/@{/
Kojto	90:cb3d968589d8	1623	#define BP_I2S_RCSR_FWIE (9U) /!< Bit position for I2S_RCSR_FWIE. /
Kojto	90:cb3d968589d8	1624	#define BM_I2S_RCSR_FWIE (0x00000200U) /!< Bit mask for I2S_RCSR_FWIE. /
Kojto	90:cb3d968589d8	1625	#define BS_I2S_RCSR_FWIE (1U) /!< Bit field size in bits for I2S_RCSR_FWIE. /
Kojto	90:cb3d968589d8	1626
Kojto	90:cb3d968589d8	1627	/! @brief Read current value of the I2S_RCSR_FWIE field. /
Kojto	90:cb3d968589d8	1628	#define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
Kojto	90:cb3d968589d8	1629
Kojto	90:cb3d968589d8	1630	/! @brief Format value for bitfield I2S_RCSR_FWIE. /
Kojto	90:cb3d968589d8	1631	#define BF_I2S_RCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWIE) & BM_I2S_RCSR_FWIE)
Kojto	90:cb3d968589d8	1632
Kojto	90:cb3d968589d8	1633	/! @brief Set the FWIE field to a new value. /
Kojto	90:cb3d968589d8	1634	#define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
Kojto	90:cb3d968589d8	1635	/@}/
Kojto	90:cb3d968589d8	1636
Kojto	90:cb3d968589d8	1637	/*!
Kojto	90:cb3d968589d8	1638	* @name Register I2S_RCSR, field FEIE[10] (RW)
Kojto	90:cb3d968589d8	1639	*
Kojto	90:cb3d968589d8	1640	* Enables/disables FIFO error interrupts.
Kojto	90:cb3d968589d8	1641	*
Kojto	90:cb3d968589d8	1642	* Values:
Kojto	90:cb3d968589d8	1643	* - 0 - Disables the interrupt.
Kojto	90:cb3d968589d8	1644	* - 1 - Enables the interrupt.
Kojto	90:cb3d968589d8	1645	*/
Kojto	90:cb3d968589d8	1646	/@{/
Kojto	90:cb3d968589d8	1647	#define BP_I2S_RCSR_FEIE (10U) /!< Bit position for I2S_RCSR_FEIE. /
Kojto	90:cb3d968589d8	1648	#define BM_I2S_RCSR_FEIE (0x00000400U) /!< Bit mask for I2S_RCSR_FEIE. /
Kojto	90:cb3d968589d8	1649	#define BS_I2S_RCSR_FEIE (1U) /!< Bit field size in bits for I2S_RCSR_FEIE. /
Kojto	90:cb3d968589d8	1650
Kojto	90:cb3d968589d8	1651	/! @brief Read current value of the I2S_RCSR_FEIE field. /
Kojto	90:cb3d968589d8	1652	#define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
Kojto	90:cb3d968589d8	1653
Kojto	90:cb3d968589d8	1654	/! @brief Format value for bitfield I2S_RCSR_FEIE. /
Kojto	90:cb3d968589d8	1655	#define BF_I2S_RCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEIE) & BM_I2S_RCSR_FEIE)
Kojto	90:cb3d968589d8	1656
Kojto	90:cb3d968589d8	1657	/! @brief Set the FEIE field to a new value. /
Kojto	90:cb3d968589d8	1658	#define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
Kojto	90:cb3d968589d8	1659	/@}/
Kojto	90:cb3d968589d8	1660
Kojto	90:cb3d968589d8	1661	/*!
Kojto	90:cb3d968589d8	1662	* @name Register I2S_RCSR, field SEIE[11] (RW)
Kojto	90:cb3d968589d8	1663	*
Kojto	90:cb3d968589d8	1664	* Enables/disables sync error interrupts.
Kojto	90:cb3d968589d8	1665	*
Kojto	90:cb3d968589d8	1666	* Values:
Kojto	90:cb3d968589d8	1667	* - 0 - Disables interrupt.
Kojto	90:cb3d968589d8	1668	* - 1 - Enables interrupt.
Kojto	90:cb3d968589d8	1669	*/
Kojto	90:cb3d968589d8	1670	/@{/
Kojto	90:cb3d968589d8	1671	#define BP_I2S_RCSR_SEIE (11U) /!< Bit position for I2S_RCSR_SEIE. /
Kojto	90:cb3d968589d8	1672	#define BM_I2S_RCSR_SEIE (0x00000800U) /!< Bit mask for I2S_RCSR_SEIE. /
Kojto	90:cb3d968589d8	1673	#define BS_I2S_RCSR_SEIE (1U) /!< Bit field size in bits for I2S_RCSR_SEIE. /
Kojto	90:cb3d968589d8	1674
Kojto	90:cb3d968589d8	1675	/! @brief Read current value of the I2S_RCSR_SEIE field. /
Kojto	90:cb3d968589d8	1676	#define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
Kojto	90:cb3d968589d8	1677
Kojto	90:cb3d968589d8	1678	/! @brief Format value for bitfield I2S_RCSR_SEIE. /
Kojto	90:cb3d968589d8	1679	#define BF_I2S_RCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEIE) & BM_I2S_RCSR_SEIE)
Kojto	90:cb3d968589d8	1680
Kojto	90:cb3d968589d8	1681	/! @brief Set the SEIE field to a new value. /
Kojto	90:cb3d968589d8	1682	#define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
Kojto	90:cb3d968589d8	1683	/@}/
Kojto	90:cb3d968589d8	1684
Kojto	90:cb3d968589d8	1685	/*!
Kojto	90:cb3d968589d8	1686	* @name Register I2S_RCSR, field WSIE[12] (RW)
Kojto	90:cb3d968589d8	1687	*
Kojto	90:cb3d968589d8	1688	* Enables/disables word start interrupts.
Kojto	90:cb3d968589d8	1689	*
Kojto	90:cb3d968589d8	1690	* Values:
Kojto	90:cb3d968589d8	1691	* - 0 - Disables interrupt.
Kojto	90:cb3d968589d8	1692	* - 1 - Enables interrupt.
Kojto	90:cb3d968589d8	1693	*/
Kojto	90:cb3d968589d8	1694	/@{/
Kojto	90:cb3d968589d8	1695	#define BP_I2S_RCSR_WSIE (12U) /!< Bit position for I2S_RCSR_WSIE. /
Kojto	90:cb3d968589d8	1696	#define BM_I2S_RCSR_WSIE (0x00001000U) /!< Bit mask for I2S_RCSR_WSIE. /
Kojto	90:cb3d968589d8	1697	#define BS_I2S_RCSR_WSIE (1U) /!< Bit field size in bits for I2S_RCSR_WSIE. /
Kojto	90:cb3d968589d8	1698
Kojto	90:cb3d968589d8	1699	/! @brief Read current value of the I2S_RCSR_WSIE field. /
Kojto	90:cb3d968589d8	1700	#define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
Kojto	90:cb3d968589d8	1701
Kojto	90:cb3d968589d8	1702	/! @brief Format value for bitfield I2S_RCSR_WSIE. /
Kojto	90:cb3d968589d8	1703	#define BF_I2S_RCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSIE) & BM_I2S_RCSR_WSIE)
Kojto	90:cb3d968589d8	1704
Kojto	90:cb3d968589d8	1705	/! @brief Set the WSIE field to a new value. /
Kojto	90:cb3d968589d8	1706	#define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
Kojto	90:cb3d968589d8	1707	/@}/
Kojto	90:cb3d968589d8	1708
Kojto	90:cb3d968589d8	1709	/*!
Kojto	90:cb3d968589d8	1710	* @name Register I2S_RCSR, field FRF[16] (RO)
Kojto	90:cb3d968589d8	1711	*
Kojto	90:cb3d968589d8	1712	* Indicates that the number of words in an enabled receive channel FIFO is
Kojto	90:cb3d968589d8	1713	* greater than the receive FIFO watermark.
Kojto	90:cb3d968589d8	1714	*
Kojto	90:cb3d968589d8	1715	* Values:
Kojto	90:cb3d968589d8	1716	* - 0 - Receive FIFO watermark not reached.
Kojto	90:cb3d968589d8	1717	* - 1 - Receive FIFO watermark has been reached.
Kojto	90:cb3d968589d8	1718	*/
Kojto	90:cb3d968589d8	1719	/@{/
Kojto	90:cb3d968589d8	1720	#define BP_I2S_RCSR_FRF (16U) /!< Bit position for I2S_RCSR_FRF. /
Kojto	90:cb3d968589d8	1721	#define BM_I2S_RCSR_FRF (0x00010000U) /!< Bit mask for I2S_RCSR_FRF. /
Kojto	90:cb3d968589d8	1722	#define BS_I2S_RCSR_FRF (1U) /!< Bit field size in bits for I2S_RCSR_FRF. /
Kojto	90:cb3d968589d8	1723
Kojto	90:cb3d968589d8	1724	/! @brief Read current value of the I2S_RCSR_FRF field. /
Kojto	90:cb3d968589d8	1725	#define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
Kojto	90:cb3d968589d8	1726	/@}/
Kojto	90:cb3d968589d8	1727
Kojto	90:cb3d968589d8	1728	/*!
Kojto	90:cb3d968589d8	1729	* @name Register I2S_RCSR, field FWF[17] (RO)
Kojto	90:cb3d968589d8	1730	*
Kojto	90:cb3d968589d8	1731	* Indicates that an enabled receive FIFO is full.
Kojto	90:cb3d968589d8	1732	*
Kojto	90:cb3d968589d8	1733	* Values:
Kojto	90:cb3d968589d8	1734	* - 0 - No enabled receive FIFO is full.
Kojto	90:cb3d968589d8	1735	* - 1 - Enabled receive FIFO is full.
Kojto	90:cb3d968589d8	1736	*/
Kojto	90:cb3d968589d8	1737	/@{/
Kojto	90:cb3d968589d8	1738	#define BP_I2S_RCSR_FWF (17U) /!< Bit position for I2S_RCSR_FWF. /
Kojto	90:cb3d968589d8	1739	#define BM_I2S_RCSR_FWF (0x00020000U) /!< Bit mask for I2S_RCSR_FWF. /
Kojto	90:cb3d968589d8	1740	#define BS_I2S_RCSR_FWF (1U) /!< Bit field size in bits for I2S_RCSR_FWF. /
Kojto	90:cb3d968589d8	1741
Kojto	90:cb3d968589d8	1742	/! @brief Read current value of the I2S_RCSR_FWF field. /
Kojto	90:cb3d968589d8	1743	#define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
Kojto	90:cb3d968589d8	1744	/@}/
Kojto	90:cb3d968589d8	1745
Kojto	90:cb3d968589d8	1746	/*!
Kojto	90:cb3d968589d8	1747	* @name Register I2S_RCSR, field FEF[18] (W1C)
Kojto	90:cb3d968589d8	1748	*
Kojto	90:cb3d968589d8	1749	* Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
Kojto	90:cb3d968589d8	1750	* this field to clear this flag.
Kojto	90:cb3d968589d8	1751	*
Kojto	90:cb3d968589d8	1752	* Values:
Kojto	90:cb3d968589d8	1753	* - 0 - Receive overflow not detected.
Kojto	90:cb3d968589d8	1754	* - 1 - Receive overflow detected.
Kojto	90:cb3d968589d8	1755	*/
Kojto	90:cb3d968589d8	1756	/@{/
Kojto	90:cb3d968589d8	1757	#define BP_I2S_RCSR_FEF (18U) /!< Bit position for I2S_RCSR_FEF. /
Kojto	90:cb3d968589d8	1758	#define BM_I2S_RCSR_FEF (0x00040000U) /!< Bit mask for I2S_RCSR_FEF. /
Kojto	90:cb3d968589d8	1759	#define BS_I2S_RCSR_FEF (1U) /!< Bit field size in bits for I2S_RCSR_FEF. /
Kojto	90:cb3d968589d8	1760
Kojto	90:cb3d968589d8	1761	/! @brief Read current value of the I2S_RCSR_FEF field. /
Kojto	90:cb3d968589d8	1762	#define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
Kojto	90:cb3d968589d8	1763
Kojto	90:cb3d968589d8	1764	/! @brief Format value for bitfield I2S_RCSR_FEF. /
Kojto	90:cb3d968589d8	1765	#define BF_I2S_RCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEF) & BM_I2S_RCSR_FEF)
Kojto	90:cb3d968589d8	1766
Kojto	90:cb3d968589d8	1767	/! @brief Set the FEF field to a new value. /
Kojto	90:cb3d968589d8	1768	#define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
Kojto	90:cb3d968589d8	1769	/@}/
Kojto	90:cb3d968589d8	1770
Kojto	90:cb3d968589d8	1771	/*!
Kojto	90:cb3d968589d8	1772	* @name Register I2S_RCSR, field SEF[19] (W1C)
Kojto	90:cb3d968589d8	1773	*
Kojto	90:cb3d968589d8	1774	* Indicates that an error in the externally-generated frame sync has been
Kojto	90:cb3d968589d8	1775	* detected. Write a logic 1 to this field to clear this flag.
Kojto	90:cb3d968589d8	1776	*
Kojto	90:cb3d968589d8	1777	* Values:
Kojto	90:cb3d968589d8	1778	* - 0 - Sync error not detected.
Kojto	90:cb3d968589d8	1779	* - 1 - Frame sync error detected.
Kojto	90:cb3d968589d8	1780	*/
Kojto	90:cb3d968589d8	1781	/@{/
Kojto	90:cb3d968589d8	1782	#define BP_I2S_RCSR_SEF (19U) /!< Bit position for I2S_RCSR_SEF. /
Kojto	90:cb3d968589d8	1783	#define BM_I2S_RCSR_SEF (0x00080000U) /!< Bit mask for I2S_RCSR_SEF. /
Kojto	90:cb3d968589d8	1784	#define BS_I2S_RCSR_SEF (1U) /!< Bit field size in bits for I2S_RCSR_SEF. /
Kojto	90:cb3d968589d8	1785
Kojto	90:cb3d968589d8	1786	/! @brief Read current value of the I2S_RCSR_SEF field. /
Kojto	90:cb3d968589d8	1787	#define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
Kojto	90:cb3d968589d8	1788
Kojto	90:cb3d968589d8	1789	/! @brief Format value for bitfield I2S_RCSR_SEF. /
Kojto	90:cb3d968589d8	1790	#define BF_I2S_RCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEF) & BM_I2S_RCSR_SEF)
Kojto	90:cb3d968589d8	1791
Kojto	90:cb3d968589d8	1792	/! @brief Set the SEF field to a new value. /
Kojto	90:cb3d968589d8	1793	#define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
Kojto	90:cb3d968589d8	1794	/@}/
Kojto	90:cb3d968589d8	1795
Kojto	90:cb3d968589d8	1796	/*!
Kojto	90:cb3d968589d8	1797	* @name Register I2S_RCSR, field WSF[20] (W1C)
Kojto	90:cb3d968589d8	1798	*
Kojto	90:cb3d968589d8	1799	* Indicates that the start of the configured word has been detected. Write a
Kojto	90:cb3d968589d8	1800	* logic 1 to this field to clear this flag.
Kojto	90:cb3d968589d8	1801	*
Kojto	90:cb3d968589d8	1802	* Values:
Kojto	90:cb3d968589d8	1803	* - 0 - Start of word not detected.
Kojto	90:cb3d968589d8	1804	* - 1 - Start of word detected.
Kojto	90:cb3d968589d8	1805	*/
Kojto	90:cb3d968589d8	1806	/@{/
Kojto	90:cb3d968589d8	1807	#define BP_I2S_RCSR_WSF (20U) /!< Bit position for I2S_RCSR_WSF. /
Kojto	90:cb3d968589d8	1808	#define BM_I2S_RCSR_WSF (0x00100000U) /!< Bit mask for I2S_RCSR_WSF. /
Kojto	90:cb3d968589d8	1809	#define BS_I2S_RCSR_WSF (1U) /!< Bit field size in bits for I2S_RCSR_WSF. /
Kojto	90:cb3d968589d8	1810
Kojto	90:cb3d968589d8	1811	/! @brief Read current value of the I2S_RCSR_WSF field. /
Kojto	90:cb3d968589d8	1812	#define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
Kojto	90:cb3d968589d8	1813
Kojto	90:cb3d968589d8	1814	/! @brief Format value for bitfield I2S_RCSR_WSF. /
Kojto	90:cb3d968589d8	1815	#define BF_I2S_RCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSF) & BM_I2S_RCSR_WSF)
Kojto	90:cb3d968589d8	1816
Kojto	90:cb3d968589d8	1817	/! @brief Set the WSF field to a new value. /
Kojto	90:cb3d968589d8	1818	#define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
Kojto	90:cb3d968589d8	1819	/@}/
Kojto	90:cb3d968589d8	1820
Kojto	90:cb3d968589d8	1821	/*!
Kojto	90:cb3d968589d8	1822	* @name Register I2S_RCSR, field SR[24] (RW)
Kojto	90:cb3d968589d8	1823	*
Kojto	90:cb3d968589d8	1824	* Resets the internal receiver logic including the FIFO pointers.
Kojto	90:cb3d968589d8	1825	* Software-visible registers are not affected, except for the status registers.
Kojto	90:cb3d968589d8	1826	*
Kojto	90:cb3d968589d8	1827	* Values:
Kojto	90:cb3d968589d8	1828	* - 0 - No effect.
Kojto	90:cb3d968589d8	1829	* - 1 - Software reset.
Kojto	90:cb3d968589d8	1830	*/
Kojto	90:cb3d968589d8	1831	/@{/
Kojto	90:cb3d968589d8	1832	#define BP_I2S_RCSR_SR (24U) /!< Bit position for I2S_RCSR_SR. /
Kojto	90:cb3d968589d8	1833	#define BM_I2S_RCSR_SR (0x01000000U) /!< Bit mask for I2S_RCSR_SR. /
Kojto	90:cb3d968589d8	1834	#define BS_I2S_RCSR_SR (1U) /!< Bit field size in bits for I2S_RCSR_SR. /
Kojto	90:cb3d968589d8	1835
Kojto	90:cb3d968589d8	1836	/! @brief Read current value of the I2S_RCSR_SR field. /
Kojto	90:cb3d968589d8	1837	#define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
Kojto	90:cb3d968589d8	1838
Kojto	90:cb3d968589d8	1839	/! @brief Format value for bitfield I2S_RCSR_SR. /
Kojto	90:cb3d968589d8	1840	#define BF_I2S_RCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SR) & BM_I2S_RCSR_SR)
Kojto	90:cb3d968589d8	1841
Kojto	90:cb3d968589d8	1842	/! @brief Set the SR field to a new value. /
Kojto	90:cb3d968589d8	1843	#define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
Kojto	90:cb3d968589d8	1844	/@}/
Kojto	90:cb3d968589d8	1845
Kojto	90:cb3d968589d8	1846	/*!
Kojto	90:cb3d968589d8	1847	* @name Register I2S_RCSR, field FR[25] (WORZ)
Kojto	90:cb3d968589d8	1848	*
Kojto	90:cb3d968589d8	1849	* Resets the FIFO pointers. Reading this field will always return zero. FIFO
Kojto	90:cb3d968589d8	1850	* pointers should only be reset when the receiver is disabled or the FIFO error
Kojto	90:cb3d968589d8	1851	* flag is set.
Kojto	90:cb3d968589d8	1852	*
Kojto	90:cb3d968589d8	1853	* Values:
Kojto	90:cb3d968589d8	1854	* - 0 - No effect.
Kojto	90:cb3d968589d8	1855	* - 1 - FIFO reset.
Kojto	90:cb3d968589d8	1856	*/
Kojto	90:cb3d968589d8	1857	/@{/
Kojto	90:cb3d968589d8	1858	#define BP_I2S_RCSR_FR (25U) /!< Bit position for I2S_RCSR_FR. /
Kojto	90:cb3d968589d8	1859	#define BM_I2S_RCSR_FR (0x02000000U) /!< Bit mask for I2S_RCSR_FR. /
Kojto	90:cb3d968589d8	1860	#define BS_I2S_RCSR_FR (1U) /!< Bit field size in bits for I2S_RCSR_FR. /
Kojto	90:cb3d968589d8	1861
Kojto	90:cb3d968589d8	1862	/! @brief Format value for bitfield I2S_RCSR_FR. /
Kojto	90:cb3d968589d8	1863	#define BF_I2S_RCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FR) & BM_I2S_RCSR_FR)
Kojto	90:cb3d968589d8	1864
Kojto	90:cb3d968589d8	1865	/! @brief Set the FR field to a new value. /
Kojto	90:cb3d968589d8	1866	#define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
Kojto	90:cb3d968589d8	1867	/@}/
Kojto	90:cb3d968589d8	1868
Kojto	90:cb3d968589d8	1869	/*!
Kojto	90:cb3d968589d8	1870	* @name Register I2S_RCSR, field BCE[28] (RW)
Kojto	90:cb3d968589d8	1871	*
Kojto	90:cb3d968589d8	1872	* Enables the receive bit clock, separately from RE. This field is
Kojto	90:cb3d968589d8	1873	* automatically set whenever RE is set. When software clears this field, the receive bit
Kojto	90:cb3d968589d8	1874	* clock remains enabled, and this field remains set, until the end of the current
Kojto	90:cb3d968589d8	1875	* frame.
Kojto	90:cb3d968589d8	1876	*
Kojto	90:cb3d968589d8	1877	* Values:
Kojto	90:cb3d968589d8	1878	* - 0 - Receive bit clock is disabled.
Kojto	90:cb3d968589d8	1879	* - 1 - Receive bit clock is enabled.
Kojto	90:cb3d968589d8	1880	*/
Kojto	90:cb3d968589d8	1881	/@{/
Kojto	90:cb3d968589d8	1882	#define BP_I2S_RCSR_BCE (28U) /!< Bit position for I2S_RCSR_BCE. /
Kojto	90:cb3d968589d8	1883	#define BM_I2S_RCSR_BCE (0x10000000U) /!< Bit mask for I2S_RCSR_BCE. /
Kojto	90:cb3d968589d8	1884	#define BS_I2S_RCSR_BCE (1U) /!< Bit field size in bits for I2S_RCSR_BCE. /
Kojto	90:cb3d968589d8	1885
Kojto	90:cb3d968589d8	1886	/! @brief Read current value of the I2S_RCSR_BCE field. /
Kojto	90:cb3d968589d8	1887	#define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
Kojto	90:cb3d968589d8	1888
Kojto	90:cb3d968589d8	1889	/! @brief Format value for bitfield I2S_RCSR_BCE. /
Kojto	90:cb3d968589d8	1890	#define BF_I2S_RCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_BCE) & BM_I2S_RCSR_BCE)
Kojto	90:cb3d968589d8	1891
Kojto	90:cb3d968589d8	1892	/! @brief Set the BCE field to a new value. /
Kojto	90:cb3d968589d8	1893	#define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
Kojto	90:cb3d968589d8	1894	/@}/
Kojto	90:cb3d968589d8	1895
Kojto	90:cb3d968589d8	1896	/*!
Kojto	90:cb3d968589d8	1897	* @name Register I2S_RCSR, field DBGE[29] (RW)
Kojto	90:cb3d968589d8	1898	*
Kojto	90:cb3d968589d8	1899	* Enables/disables receiver operation in Debug mode. The receive bit clock is
Kojto	90:cb3d968589d8	1900	* not affected by Debug mode.
Kojto	90:cb3d968589d8	1901	*
Kojto	90:cb3d968589d8	1902	* Values:
Kojto	90:cb3d968589d8	1903	* - 0 - Receiver is disabled in Debug mode, after completing the current frame.
Kojto	90:cb3d968589d8	1904	* - 1 - Receiver is enabled in Debug mode.
Kojto	90:cb3d968589d8	1905	*/
Kojto	90:cb3d968589d8	1906	/@{/
Kojto	90:cb3d968589d8	1907	#define BP_I2S_RCSR_DBGE (29U) /!< Bit position for I2S_RCSR_DBGE. /
Kojto	90:cb3d968589d8	1908	#define BM_I2S_RCSR_DBGE (0x20000000U) /!< Bit mask for I2S_RCSR_DBGE. /
Kojto	90:cb3d968589d8	1909	#define BS_I2S_RCSR_DBGE (1U) /!< Bit field size in bits for I2S_RCSR_DBGE. /
Kojto	90:cb3d968589d8	1910
Kojto	90:cb3d968589d8	1911	/! @brief Read current value of the I2S_RCSR_DBGE field. /
Kojto	90:cb3d968589d8	1912	#define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
Kojto	90:cb3d968589d8	1913
Kojto	90:cb3d968589d8	1914	/! @brief Format value for bitfield I2S_RCSR_DBGE. /
Kojto	90:cb3d968589d8	1915	#define BF_I2S_RCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_DBGE) & BM_I2S_RCSR_DBGE)
Kojto	90:cb3d968589d8	1916
Kojto	90:cb3d968589d8	1917	/! @brief Set the DBGE field to a new value. /
Kojto	90:cb3d968589d8	1918	#define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
Kojto	90:cb3d968589d8	1919	/@}/
Kojto	90:cb3d968589d8	1920
Kojto	90:cb3d968589d8	1921	/*!
Kojto	90:cb3d968589d8	1922	* @name Register I2S_RCSR, field STOPE[30] (RW)
Kojto	90:cb3d968589d8	1923	*
Kojto	90:cb3d968589d8	1924	* Configures receiver operation in Stop mode. This bit is ignored and the
Kojto	90:cb3d968589d8	1925	* receiver is disabled in all low-leakage stop modes.
Kojto	90:cb3d968589d8	1926	*
Kojto	90:cb3d968589d8	1927	* Values:
Kojto	90:cb3d968589d8	1928	* - 0 - Receiver disabled in Stop mode.
Kojto	90:cb3d968589d8	1929	* - 1 - Receiver enabled in Stop mode.
Kojto	90:cb3d968589d8	1930	*/
Kojto	90:cb3d968589d8	1931	/@{/
Kojto	90:cb3d968589d8	1932	#define BP_I2S_RCSR_STOPE (30U) /!< Bit position for I2S_RCSR_STOPE. /
Kojto	90:cb3d968589d8	1933	#define BM_I2S_RCSR_STOPE (0x40000000U) /!< Bit mask for I2S_RCSR_STOPE. /
Kojto	90:cb3d968589d8	1934	#define BS_I2S_RCSR_STOPE (1U) /!< Bit field size in bits for I2S_RCSR_STOPE. /
Kojto	90:cb3d968589d8	1935
Kojto	90:cb3d968589d8	1936	/! @brief Read current value of the I2S_RCSR_STOPE field. /
Kojto	90:cb3d968589d8	1937	#define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
Kojto	90:cb3d968589d8	1938
Kojto	90:cb3d968589d8	1939	/! @brief Format value for bitfield I2S_RCSR_STOPE. /
Kojto	90:cb3d968589d8	1940	#define BF_I2S_RCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_STOPE) & BM_I2S_RCSR_STOPE)
Kojto	90:cb3d968589d8	1941
Kojto	90:cb3d968589d8	1942	/! @brief Set the STOPE field to a new value. /
Kojto	90:cb3d968589d8	1943	#define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
Kojto	90:cb3d968589d8	1944	/@}/
Kojto	90:cb3d968589d8	1945
Kojto	90:cb3d968589d8	1946	/*!
Kojto	90:cb3d968589d8	1947	* @name Register I2S_RCSR, field RE[31] (RW)
Kojto	90:cb3d968589d8	1948	*
Kojto	90:cb3d968589d8	1949	* Enables/disables the receiver. When software clears this field, the receiver
Kojto	90:cb3d968589d8	1950	* remains enabled, and this bit remains set, until the end of the current frame.
Kojto	90:cb3d968589d8	1951	*
Kojto	90:cb3d968589d8	1952	* Values:
Kojto	90:cb3d968589d8	1953	* - 0 - Receiver is disabled.
Kojto	90:cb3d968589d8	1954	* - 1 - Receiver is enabled, or receiver has been disabled and has not yet
Kojto	90:cb3d968589d8	1955	* reached end of frame.
Kojto	90:cb3d968589d8	1956	*/
Kojto	90:cb3d968589d8	1957	/@{/
Kojto	90:cb3d968589d8	1958	#define BP_I2S_RCSR_RE (31U) /!< Bit position for I2S_RCSR_RE. /
Kojto	90:cb3d968589d8	1959	#define BM_I2S_RCSR_RE (0x80000000U) /!< Bit mask for I2S_RCSR_RE. /
Kojto	90:cb3d968589d8	1960	#define BS_I2S_RCSR_RE (1U) /!< Bit field size in bits for I2S_RCSR_RE. /
Kojto	90:cb3d968589d8	1961
Kojto	90:cb3d968589d8	1962	/! @brief Read current value of the I2S_RCSR_RE field. /
Kojto	90:cb3d968589d8	1963	#define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
Kojto	90:cb3d968589d8	1964
Kojto	90:cb3d968589d8	1965	/! @brief Format value for bitfield I2S_RCSR_RE. /
Kojto	90:cb3d968589d8	1966	#define BF_I2S_RCSR_RE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_RE) & BM_I2S_RCSR_RE)
Kojto	90:cb3d968589d8	1967
Kojto	90:cb3d968589d8	1968	/! @brief Set the RE field to a new value. /
Kojto	90:cb3d968589d8	1969	#define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
Kojto	90:cb3d968589d8	1970	/@}/
Kojto	90:cb3d968589d8	1971
Kojto	90:cb3d968589d8	1972	/*******************************************************************************
Kojto	90:cb3d968589d8	1973	* HW_I2S_RCR1 - SAI Receive Configuration 1 Register
Kojto	90:cb3d968589d8	1974	******************************************************************************/
Kojto	90:cb3d968589d8	1975
Kojto	90:cb3d968589d8	1976	/*!
Kojto	90:cb3d968589d8	1977	* @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
Kojto	90:cb3d968589d8	1978	*
Kojto	90:cb3d968589d8	1979	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	1980	*/
Kojto	90:cb3d968589d8	1981	typedef union _hw_i2s_rcr1
Kojto	90:cb3d968589d8	1982	{
Kojto	90:cb3d968589d8	1983	uint32_t U;
Kojto	90:cb3d968589d8	1984	struct _hw_i2s_rcr1_bitfields
Kojto	90:cb3d968589d8	1985	{
Kojto	90:cb3d968589d8	1986	uint32_t RFW : 3; /!< [2:0] Receive FIFO Watermark /
Kojto	90:cb3d968589d8	1987	uint32_t RESERVED0 : 29; /!< [31:3] /
Kojto	90:cb3d968589d8	1988	} B;
Kojto	90:cb3d968589d8	1989	} hw_i2s_rcr1_t;
Kojto	90:cb3d968589d8	1990
Kojto	90:cb3d968589d8	1991	/*!
Kojto	90:cb3d968589d8	1992	* @name Constants and macros for entire I2S_RCR1 register
Kojto	90:cb3d968589d8	1993	*/
Kojto	90:cb3d968589d8	1994	/@{/
Kojto	90:cb3d968589d8	1995	#define HW_I2S_RCR1_ADDR(x) ((x) + 0x84U)
Kojto	90:cb3d968589d8	1996
Kojto	90:cb3d968589d8	1997	#define HW_I2S_RCR1(x) ((__IO hw_i2s_rcr1_t ) HW_I2S_RCR1_ADDR(x))
Kojto	90:cb3d968589d8	1998	#define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U)
Kojto	90:cb3d968589d8	1999	#define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v))
Kojto	90:cb3d968589d8	2000	#define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2001	#define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2002	#define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2003	/@}/
Kojto	90:cb3d968589d8	2004
Kojto	90:cb3d968589d8	2005	/*
Kojto	90:cb3d968589d8	2006	* Constants & macros for individual I2S_RCR1 bitfields
Kojto	90:cb3d968589d8	2007	*/
Kojto	90:cb3d968589d8	2008
Kojto	90:cb3d968589d8	2009	/*!
Kojto	90:cb3d968589d8	2010	* @name Register I2S_RCR1, field RFW[2:0] (RW)
Kojto	90:cb3d968589d8	2011	*
Kojto	90:cb3d968589d8	2012	* Configures the watermark level for all enabled receiver channels.
Kojto	90:cb3d968589d8	2013	*/
Kojto	90:cb3d968589d8	2014	/@{/
Kojto	90:cb3d968589d8	2015	#define BP_I2S_RCR1_RFW (0U) /!< Bit position for I2S_RCR1_RFW. /
Kojto	90:cb3d968589d8	2016	#define BM_I2S_RCR1_RFW (0x00000007U) /!< Bit mask for I2S_RCR1_RFW. /
Kojto	90:cb3d968589d8	2017	#define BS_I2S_RCR1_RFW (3U) /!< Bit field size in bits for I2S_RCR1_RFW. /
Kojto	90:cb3d968589d8	2018
Kojto	90:cb3d968589d8	2019	/! @brief Read current value of the I2S_RCR1_RFW field. /
Kojto	90:cb3d968589d8	2020	#define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW)
Kojto	90:cb3d968589d8	2021
Kojto	90:cb3d968589d8	2022	/! @brief Format value for bitfield I2S_RCR1_RFW. /
Kojto	90:cb3d968589d8	2023	#define BF_I2S_RCR1_RFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR1_RFW) & BM_I2S_RCR1_RFW)
Kojto	90:cb3d968589d8	2024
Kojto	90:cb3d968589d8	2025	/! @brief Set the RFW field to a new value. /
Kojto	90:cb3d968589d8	2026	#define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) \| BF_I2S_RCR1_RFW(v)))
Kojto	90:cb3d968589d8	2027	/@}/
Kojto	90:cb3d968589d8	2028
Kojto	90:cb3d968589d8	2029	/*******************************************************************************
Kojto	90:cb3d968589d8	2030	* HW_I2S_RCR2 - SAI Receive Configuration 2 Register
Kojto	90:cb3d968589d8	2031	******************************************************************************/
Kojto	90:cb3d968589d8	2032
Kojto	90:cb3d968589d8	2033	/*!
Kojto	90:cb3d968589d8	2034	* @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
Kojto	90:cb3d968589d8	2035	*
Kojto	90:cb3d968589d8	2036	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2037	*
Kojto	90:cb3d968589d8	2038	* This register must not be altered when RCSR[RE] is set.
Kojto	90:cb3d968589d8	2039	*/
Kojto	90:cb3d968589d8	2040	typedef union _hw_i2s_rcr2
Kojto	90:cb3d968589d8	2041	{
Kojto	90:cb3d968589d8	2042	uint32_t U;
Kojto	90:cb3d968589d8	2043	struct _hw_i2s_rcr2_bitfields
Kojto	90:cb3d968589d8	2044	{
Kojto	90:cb3d968589d8	2045	uint32_t DIV : 8; /!< [7:0] Bit Clock Divide /
Kojto	90:cb3d968589d8	2046	uint32_t RESERVED0 : 16; /!< [23:8] /
Kojto	90:cb3d968589d8	2047	uint32_t BCD : 1; /!< [24] Bit Clock Direction /
Kojto	90:cb3d968589d8	2048	uint32_t BCP : 1; /!< [25] Bit Clock Polarity /
Kojto	90:cb3d968589d8	2049	uint32_t MSEL : 2; /!< [27:26] MCLK Select /
Kojto	90:cb3d968589d8	2050	uint32_t BCI : 1; /!< [28] Bit Clock Input /
Kojto	90:cb3d968589d8	2051	uint32_t BCS : 1; /!< [29] Bit Clock Swap /
Kojto	90:cb3d968589d8	2052	uint32_t SYNC : 2; /!< [31:30] Synchronous Mode /
Kojto	90:cb3d968589d8	2053	} B;
Kojto	90:cb3d968589d8	2054	} hw_i2s_rcr2_t;
Kojto	90:cb3d968589d8	2055
Kojto	90:cb3d968589d8	2056	/*!
Kojto	90:cb3d968589d8	2057	* @name Constants and macros for entire I2S_RCR2 register
Kojto	90:cb3d968589d8	2058	*/
Kojto	90:cb3d968589d8	2059	/@{/
Kojto	90:cb3d968589d8	2060	#define HW_I2S_RCR2_ADDR(x) ((x) + 0x88U)
Kojto	90:cb3d968589d8	2061
Kojto	90:cb3d968589d8	2062	#define HW_I2S_RCR2(x) ((__IO hw_i2s_rcr2_t ) HW_I2S_RCR2_ADDR(x))
Kojto	90:cb3d968589d8	2063	#define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U)
Kojto	90:cb3d968589d8	2064	#define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v))
Kojto	90:cb3d968589d8	2065	#define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2066	#define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2067	#define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2068	/@}/
Kojto	90:cb3d968589d8	2069
Kojto	90:cb3d968589d8	2070	/*
Kojto	90:cb3d968589d8	2071	* Constants & macros for individual I2S_RCR2 bitfields
Kojto	90:cb3d968589d8	2072	*/
Kojto	90:cb3d968589d8	2073
Kojto	90:cb3d968589d8	2074	/*!
Kojto	90:cb3d968589d8	2075	* @name Register I2S_RCR2, field DIV[7:0] (RW)
Kojto	90:cb3d968589d8	2076	*
Kojto	90:cb3d968589d8	2077	* Divides down the audio master clock to generate the bit clock when configured
Kojto	90:cb3d968589d8	2078	* for an internal bit clock. The division value is (DIV + 1) * 2.
Kojto	90:cb3d968589d8	2079	*/
Kojto	90:cb3d968589d8	2080	/@{/
Kojto	90:cb3d968589d8	2081	#define BP_I2S_RCR2_DIV (0U) /!< Bit position for I2S_RCR2_DIV. /
Kojto	90:cb3d968589d8	2082	#define BM_I2S_RCR2_DIV (0x000000FFU) /!< Bit mask for I2S_RCR2_DIV. /
Kojto	90:cb3d968589d8	2083	#define BS_I2S_RCR2_DIV (8U) /!< Bit field size in bits for I2S_RCR2_DIV. /
Kojto	90:cb3d968589d8	2084
Kojto	90:cb3d968589d8	2085	/! @brief Read current value of the I2S_RCR2_DIV field. /
Kojto	90:cb3d968589d8	2086	#define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV)
Kojto	90:cb3d968589d8	2087
Kojto	90:cb3d968589d8	2088	/! @brief Format value for bitfield I2S_RCR2_DIV. /
Kojto	90:cb3d968589d8	2089	#define BF_I2S_RCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_DIV) & BM_I2S_RCR2_DIV)
Kojto	90:cb3d968589d8	2090
Kojto	90:cb3d968589d8	2091	/! @brief Set the DIV field to a new value. /
Kojto	90:cb3d968589d8	2092	#define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) \| BF_I2S_RCR2_DIV(v)))
Kojto	90:cb3d968589d8	2093	/@}/
Kojto	90:cb3d968589d8	2094
Kojto	90:cb3d968589d8	2095	/*!
Kojto	90:cb3d968589d8	2096	* @name Register I2S_RCR2, field BCD[24] (RW)
Kojto	90:cb3d968589d8	2097	*
Kojto	90:cb3d968589d8	2098	* Configures the direction of the bit clock.
Kojto	90:cb3d968589d8	2099	*
Kojto	90:cb3d968589d8	2100	* Values:
Kojto	90:cb3d968589d8	2101	* - 0 - Bit clock is generated externally in Slave mode.
Kojto	90:cb3d968589d8	2102	* - 1 - Bit clock is generated internally in Master mode.
Kojto	90:cb3d968589d8	2103	*/
Kojto	90:cb3d968589d8	2104	/@{/
Kojto	90:cb3d968589d8	2105	#define BP_I2S_RCR2_BCD (24U) /!< Bit position for I2S_RCR2_BCD. /
Kojto	90:cb3d968589d8	2106	#define BM_I2S_RCR2_BCD (0x01000000U) /!< Bit mask for I2S_RCR2_BCD. /
Kojto	90:cb3d968589d8	2107	#define BS_I2S_RCR2_BCD (1U) /!< Bit field size in bits for I2S_RCR2_BCD. /
Kojto	90:cb3d968589d8	2108
Kojto	90:cb3d968589d8	2109	/! @brief Read current value of the I2S_RCR2_BCD field. /
Kojto	90:cb3d968589d8	2110	#define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
Kojto	90:cb3d968589d8	2111
Kojto	90:cb3d968589d8	2112	/! @brief Format value for bitfield I2S_RCR2_BCD. /
Kojto	90:cb3d968589d8	2113	#define BF_I2S_RCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCD) & BM_I2S_RCR2_BCD)
Kojto	90:cb3d968589d8	2114
Kojto	90:cb3d968589d8	2115	/! @brief Set the BCD field to a new value. /
Kojto	90:cb3d968589d8	2116	#define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
Kojto	90:cb3d968589d8	2117	/@}/
Kojto	90:cb3d968589d8	2118
Kojto	90:cb3d968589d8	2119	/*!
Kojto	90:cb3d968589d8	2120	* @name Register I2S_RCR2, field BCP[25] (RW)
Kojto	90:cb3d968589d8	2121	*
Kojto	90:cb3d968589d8	2122	* Configures the polarity of the bit clock.
Kojto	90:cb3d968589d8	2123	*
Kojto	90:cb3d968589d8	2124	* Values:
Kojto	90:cb3d968589d8	2125	* - 0 - Bit Clock is active high with drive outputs on rising edge and sample
Kojto	90:cb3d968589d8	2126	* inputs on falling edge.
Kojto	90:cb3d968589d8	2127	* - 1 - Bit Clock is active low with drive outputs on falling edge and sample
Kojto	90:cb3d968589d8	2128	* inputs on rising edge.
Kojto	90:cb3d968589d8	2129	*/
Kojto	90:cb3d968589d8	2130	/@{/
Kojto	90:cb3d968589d8	2131	#define BP_I2S_RCR2_BCP (25U) /!< Bit position for I2S_RCR2_BCP. /
Kojto	90:cb3d968589d8	2132	#define BM_I2S_RCR2_BCP (0x02000000U) /!< Bit mask for I2S_RCR2_BCP. /
Kojto	90:cb3d968589d8	2133	#define BS_I2S_RCR2_BCP (1U) /!< Bit field size in bits for I2S_RCR2_BCP. /
Kojto	90:cb3d968589d8	2134
Kojto	90:cb3d968589d8	2135	/! @brief Read current value of the I2S_RCR2_BCP field. /
Kojto	90:cb3d968589d8	2136	#define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
Kojto	90:cb3d968589d8	2137
Kojto	90:cb3d968589d8	2138	/! @brief Format value for bitfield I2S_RCR2_BCP. /
Kojto	90:cb3d968589d8	2139	#define BF_I2S_RCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCP) & BM_I2S_RCR2_BCP)
Kojto	90:cb3d968589d8	2140
Kojto	90:cb3d968589d8	2141	/! @brief Set the BCP field to a new value. /
Kojto	90:cb3d968589d8	2142	#define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
Kojto	90:cb3d968589d8	2143	/@}/
Kojto	90:cb3d968589d8	2144
Kojto	90:cb3d968589d8	2145	/*!
Kojto	90:cb3d968589d8	2146	* @name Register I2S_RCR2, field MSEL[27:26] (RW)
Kojto	90:cb3d968589d8	2147	*
Kojto	90:cb3d968589d8	2148	* Selects the audio Master Clock option used to generate an internally
Kojto	90:cb3d968589d8	2149	* generated bit clock. This field has no effect when configured for an externally
Kojto	90:cb3d968589d8	2150	* generated bit clock. Depending on the device, some Master Clock options might not be
Kojto	90:cb3d968589d8	2151	* available. See the chip configuration details for the availability and
Kojto	90:cb3d968589d8	2152	* chip-specific meaning of each option.
Kojto	90:cb3d968589d8	2153	*
Kojto	90:cb3d968589d8	2154	* Values:
Kojto	90:cb3d968589d8	2155	* - 00 - Bus Clock selected.
Kojto	90:cb3d968589d8	2156	* - 01 - Master Clock (MCLK) 1 option selected.
Kojto	90:cb3d968589d8	2157	* - 10 - Master Clock (MCLK) 2 option selected.
Kojto	90:cb3d968589d8	2158	* - 11 - Master Clock (MCLK) 3 option selected.
Kojto	90:cb3d968589d8	2159	*/
Kojto	90:cb3d968589d8	2160	/@{/
Kojto	90:cb3d968589d8	2161	#define BP_I2S_RCR2_MSEL (26U) /!< Bit position for I2S_RCR2_MSEL. /
Kojto	90:cb3d968589d8	2162	#define BM_I2S_RCR2_MSEL (0x0C000000U) /!< Bit mask for I2S_RCR2_MSEL. /
Kojto	90:cb3d968589d8	2163	#define BS_I2S_RCR2_MSEL (2U) /!< Bit field size in bits for I2S_RCR2_MSEL. /
Kojto	90:cb3d968589d8	2164
Kojto	90:cb3d968589d8	2165	/! @brief Read current value of the I2S_RCR2_MSEL field. /
Kojto	90:cb3d968589d8	2166	#define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL)
Kojto	90:cb3d968589d8	2167
Kojto	90:cb3d968589d8	2168	/! @brief Format value for bitfield I2S_RCR2_MSEL. /
Kojto	90:cb3d968589d8	2169	#define BF_I2S_RCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_MSEL) & BM_I2S_RCR2_MSEL)
Kojto	90:cb3d968589d8	2170
Kojto	90:cb3d968589d8	2171	/! @brief Set the MSEL field to a new value. /
Kojto	90:cb3d968589d8	2172	#define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) \| BF_I2S_RCR2_MSEL(v)))
Kojto	90:cb3d968589d8	2173	/@}/
Kojto	90:cb3d968589d8	2174
Kojto	90:cb3d968589d8	2175	/*!
Kojto	90:cb3d968589d8	2176	* @name Register I2S_RCR2, field BCI[28] (RW)
Kojto	90:cb3d968589d8	2177	*
Kojto	90:cb3d968589d8	2178	* When this field is set and using an internally generated bit clock in either
Kojto	90:cb3d968589d8	2179	* synchronous or asynchronous mode, the bit clock actually used by the receiver
Kojto	90:cb3d968589d8	2180	* is delayed by the pad output delay (the receiver is clocked by the pad input
Kojto	90:cb3d968589d8	2181	* as if the clock was externally generated). This has the effect of decreasing
Kojto	90:cb3d968589d8	2182	* the data input setup time, but increasing the data output valid time. The slave
Kojto	90:cb3d968589d8	2183	* mode timing from the datasheet should be used for the receiver when this bit
Kojto	90:cb3d968589d8	2184	* is set. In synchronous mode, this bit allows the receiver to use the slave mode
Kojto	90:cb3d968589d8	2185	* timing from the datasheet, while the transmitter uses the master mode timing.
Kojto	90:cb3d968589d8	2186	* This field has no effect when configured for an externally generated bit
Kojto	90:cb3d968589d8	2187	* clock or when synchronous to another SAI peripheral .
Kojto	90:cb3d968589d8	2188	*
Kojto	90:cb3d968589d8	2189	* Values:
Kojto	90:cb3d968589d8	2190	* - 0 - No effect.
Kojto	90:cb3d968589d8	2191	* - 1 - Internal logic is clocked as if bit clock was externally generated.
Kojto	90:cb3d968589d8	2192	*/
Kojto	90:cb3d968589d8	2193	/@{/
Kojto	90:cb3d968589d8	2194	#define BP_I2S_RCR2_BCI (28U) /!< Bit position for I2S_RCR2_BCI. /
Kojto	90:cb3d968589d8	2195	#define BM_I2S_RCR2_BCI (0x10000000U) /!< Bit mask for I2S_RCR2_BCI. /
Kojto	90:cb3d968589d8	2196	#define BS_I2S_RCR2_BCI (1U) /!< Bit field size in bits for I2S_RCR2_BCI. /
Kojto	90:cb3d968589d8	2197
Kojto	90:cb3d968589d8	2198	/! @brief Read current value of the I2S_RCR2_BCI field. /
Kojto	90:cb3d968589d8	2199	#define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
Kojto	90:cb3d968589d8	2200
Kojto	90:cb3d968589d8	2201	/! @brief Format value for bitfield I2S_RCR2_BCI. /
Kojto	90:cb3d968589d8	2202	#define BF_I2S_RCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCI) & BM_I2S_RCR2_BCI)
Kojto	90:cb3d968589d8	2203
Kojto	90:cb3d968589d8	2204	/! @brief Set the BCI field to a new value. /
Kojto	90:cb3d968589d8	2205	#define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
Kojto	90:cb3d968589d8	2206	/@}/
Kojto	90:cb3d968589d8	2207
Kojto	90:cb3d968589d8	2208	/*!
Kojto	90:cb3d968589d8	2209	* @name Register I2S_RCR2, field BCS[29] (RW)
Kojto	90:cb3d968589d8	2210	*
Kojto	90:cb3d968589d8	2211	* This field swaps the bit clock used by the receiver. When the receiver is
Kojto	90:cb3d968589d8	2212	* configured in asynchronous mode and this bit is set, the receiver is clocked by
Kojto	90:cb3d968589d8	2213	* the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
Kojto	90:cb3d968589d8	2214	* receiver to share the same bit clock, but the receiver continues to use the receiver
Kojto	90:cb3d968589d8	2215	* frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
Kojto	90:cb3d968589d8	2216	* mode, the transmitter BCS field and receiver BCS field must be set to the same
Kojto	90:cb3d968589d8	2217	* value. When both are set, the transmitter and receiver are both clocked by the
Kojto	90:cb3d968589d8	2218	* receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
Kojto	90:cb3d968589d8	2219	* (SAI_TX_SYNC). This field has no effect when synchronous to another SAI peripheral.
Kojto	90:cb3d968589d8	2220	*
Kojto	90:cb3d968589d8	2221	* Values:
Kojto	90:cb3d968589d8	2222	* - 0 - Use the normal bit clock source.
Kojto	90:cb3d968589d8	2223	* - 1 - Swap the bit clock source.
Kojto	90:cb3d968589d8	2224	*/
Kojto	90:cb3d968589d8	2225	/@{/
Kojto	90:cb3d968589d8	2226	#define BP_I2S_RCR2_BCS (29U) /!< Bit position for I2S_RCR2_BCS. /
Kojto	90:cb3d968589d8	2227	#define BM_I2S_RCR2_BCS (0x20000000U) /!< Bit mask for I2S_RCR2_BCS. /
Kojto	90:cb3d968589d8	2228	#define BS_I2S_RCR2_BCS (1U) /!< Bit field size in bits for I2S_RCR2_BCS. /
Kojto	90:cb3d968589d8	2229
Kojto	90:cb3d968589d8	2230	/! @brief Read current value of the I2S_RCR2_BCS field. /
Kojto	90:cb3d968589d8	2231	#define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
Kojto	90:cb3d968589d8	2232
Kojto	90:cb3d968589d8	2233	/! @brief Format value for bitfield I2S_RCR2_BCS. /
Kojto	90:cb3d968589d8	2234	#define BF_I2S_RCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCS) & BM_I2S_RCR2_BCS)
Kojto	90:cb3d968589d8	2235
Kojto	90:cb3d968589d8	2236	/! @brief Set the BCS field to a new value. /
Kojto	90:cb3d968589d8	2237	#define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
Kojto	90:cb3d968589d8	2238	/@}/
Kojto	90:cb3d968589d8	2239
Kojto	90:cb3d968589d8	2240	/*!
Kojto	90:cb3d968589d8	2241	* @name Register I2S_RCR2, field SYNC[31:30] (RW)
Kojto	90:cb3d968589d8	2242	*
Kojto	90:cb3d968589d8	2243	* Configures between asynchronous and synchronous modes of operation. When
Kojto	90:cb3d968589d8	2244	* configured for a synchronous mode of operation, the transmitter or other SAI
Kojto	90:cb3d968589d8	2245	* peripheral must be configured for asynchronous operation.
Kojto	90:cb3d968589d8	2246	*
Kojto	90:cb3d968589d8	2247	* Values:
Kojto	90:cb3d968589d8	2248	* - 00 - Asynchronous mode.
Kojto	90:cb3d968589d8	2249	* - 01 - Synchronous with transmitter.
Kojto	90:cb3d968589d8	2250	* - 10 - Synchronous with another SAI receiver.
Kojto	90:cb3d968589d8	2251	* - 11 - Synchronous with another SAI transmitter.
Kojto	90:cb3d968589d8	2252	*/
Kojto	90:cb3d968589d8	2253	/@{/
Kojto	90:cb3d968589d8	2254	#define BP_I2S_RCR2_SYNC (30U) /!< Bit position for I2S_RCR2_SYNC. /
Kojto	90:cb3d968589d8	2255	#define BM_I2S_RCR2_SYNC (0xC0000000U) /!< Bit mask for I2S_RCR2_SYNC. /
Kojto	90:cb3d968589d8	2256	#define BS_I2S_RCR2_SYNC (2U) /!< Bit field size in bits for I2S_RCR2_SYNC. /
Kojto	90:cb3d968589d8	2257
Kojto	90:cb3d968589d8	2258	/! @brief Read current value of the I2S_RCR2_SYNC field. /
Kojto	90:cb3d968589d8	2259	#define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC)
Kojto	90:cb3d968589d8	2260
Kojto	90:cb3d968589d8	2261	/! @brief Format value for bitfield I2S_RCR2_SYNC. /
Kojto	90:cb3d968589d8	2262	#define BF_I2S_RCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_SYNC) & BM_I2S_RCR2_SYNC)
Kojto	90:cb3d968589d8	2263
Kojto	90:cb3d968589d8	2264	/! @brief Set the SYNC field to a new value. /
Kojto	90:cb3d968589d8	2265	#define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) \| BF_I2S_RCR2_SYNC(v)))
Kojto	90:cb3d968589d8	2266	/@}/
Kojto	90:cb3d968589d8	2267
Kojto	90:cb3d968589d8	2268	/*******************************************************************************
Kojto	90:cb3d968589d8	2269	* HW_I2S_RCR3 - SAI Receive Configuration 3 Register
Kojto	90:cb3d968589d8	2270	******************************************************************************/
Kojto	90:cb3d968589d8	2271
Kojto	90:cb3d968589d8	2272	/*!
Kojto	90:cb3d968589d8	2273	* @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
Kojto	90:cb3d968589d8	2274	*
Kojto	90:cb3d968589d8	2275	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2276	*
Kojto	90:cb3d968589d8	2277	* This register must not be altered when RCSR[RE] is set.
Kojto	90:cb3d968589d8	2278	*/
Kojto	90:cb3d968589d8	2279	typedef union _hw_i2s_rcr3
Kojto	90:cb3d968589d8	2280	{
Kojto	90:cb3d968589d8	2281	uint32_t U;
Kojto	90:cb3d968589d8	2282	struct _hw_i2s_rcr3_bitfields
Kojto	90:cb3d968589d8	2283	{
Kojto	90:cb3d968589d8	2284	uint32_t WDFL : 5; /!< [4:0] Word Flag Configuration /
Kojto	90:cb3d968589d8	2285	uint32_t RESERVED0 : 11; /!< [15:5] /
Kojto	90:cb3d968589d8	2286	uint32_t RCE : 2; /!< [17:16] Receive Channel Enable /
Kojto	90:cb3d968589d8	2287	uint32_t RESERVED1 : 14; /!< [31:18] /
Kojto	90:cb3d968589d8	2288	} B;
Kojto	90:cb3d968589d8	2289	} hw_i2s_rcr3_t;
Kojto	90:cb3d968589d8	2290
Kojto	90:cb3d968589d8	2291	/*!
Kojto	90:cb3d968589d8	2292	* @name Constants and macros for entire I2S_RCR3 register
Kojto	90:cb3d968589d8	2293	*/
Kojto	90:cb3d968589d8	2294	/@{/
Kojto	90:cb3d968589d8	2295	#define HW_I2S_RCR3_ADDR(x) ((x) + 0x8CU)
Kojto	90:cb3d968589d8	2296
Kojto	90:cb3d968589d8	2297	#define HW_I2S_RCR3(x) ((__IO hw_i2s_rcr3_t ) HW_I2S_RCR3_ADDR(x))
Kojto	90:cb3d968589d8	2298	#define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U)
Kojto	90:cb3d968589d8	2299	#define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v))
Kojto	90:cb3d968589d8	2300	#define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2301	#define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2302	#define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2303	/@}/
Kojto	90:cb3d968589d8	2304
Kojto	90:cb3d968589d8	2305	/*
Kojto	90:cb3d968589d8	2306	* Constants & macros for individual I2S_RCR3 bitfields
Kojto	90:cb3d968589d8	2307	*/
Kojto	90:cb3d968589d8	2308
Kojto	90:cb3d968589d8	2309	/*!
Kojto	90:cb3d968589d8	2310	* @name Register I2S_RCR3, field WDFL[4:0] (RW)
Kojto	90:cb3d968589d8	2311	*
Kojto	90:cb3d968589d8	2312	* Configures which word the start of word flag is set. The value written should
Kojto	90:cb3d968589d8	2313	* be one less than the word number (for example, write zero to configure for
Kojto	90:cb3d968589d8	2314	* the first word in the frame). When configured to a value greater than the Frame
Kojto	90:cb3d968589d8	2315	* Size field, then the start of word flag is never set.
Kojto	90:cb3d968589d8	2316	*/
Kojto	90:cb3d968589d8	2317	/@{/
Kojto	90:cb3d968589d8	2318	#define BP_I2S_RCR3_WDFL (0U) /!< Bit position for I2S_RCR3_WDFL. /
Kojto	90:cb3d968589d8	2319	#define BM_I2S_RCR3_WDFL (0x0000001FU) /!< Bit mask for I2S_RCR3_WDFL. /
Kojto	90:cb3d968589d8	2320	#define BS_I2S_RCR3_WDFL (5U) /!< Bit field size in bits for I2S_RCR3_WDFL. /
Kojto	90:cb3d968589d8	2321
Kojto	90:cb3d968589d8	2322	/! @brief Read current value of the I2S_RCR3_WDFL field. /
Kojto	90:cb3d968589d8	2323	#define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL)
Kojto	90:cb3d968589d8	2324
Kojto	90:cb3d968589d8	2325	/! @brief Format value for bitfield I2S_RCR3_WDFL. /
Kojto	90:cb3d968589d8	2326	#define BF_I2S_RCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_WDFL) & BM_I2S_RCR3_WDFL)
Kojto	90:cb3d968589d8	2327
Kojto	90:cb3d968589d8	2328	/! @brief Set the WDFL field to a new value. /
Kojto	90:cb3d968589d8	2329	#define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) \| BF_I2S_RCR3_WDFL(v)))
Kojto	90:cb3d968589d8	2330	/@}/
Kojto	90:cb3d968589d8	2331
Kojto	90:cb3d968589d8	2332	/*!
Kojto	90:cb3d968589d8	2333	* @name Register I2S_RCR3, field RCE[17:16] (RW)
Kojto	90:cb3d968589d8	2334	*
Kojto	90:cb3d968589d8	2335	* Enables the corresponding data channel for receive operation. A channel must
Kojto	90:cb3d968589d8	2336	* be enabled before its FIFO is accessed.
Kojto	90:cb3d968589d8	2337	*
Kojto	90:cb3d968589d8	2338	* Values:
Kojto	90:cb3d968589d8	2339	* - 0 - Receive data channel N is disabled.
Kojto	90:cb3d968589d8	2340	* - 1 - Receive data channel N is enabled.
Kojto	90:cb3d968589d8	2341	*/
Kojto	90:cb3d968589d8	2342	/@{/
Kojto	90:cb3d968589d8	2343	#define BP_I2S_RCR3_RCE (16U) /!< Bit position for I2S_RCR3_RCE. /
Kojto	90:cb3d968589d8	2344	#define BM_I2S_RCR3_RCE (0x00030000U) /!< Bit mask for I2S_RCR3_RCE. /
Kojto	90:cb3d968589d8	2345	#define BS_I2S_RCR3_RCE (2U) /!< Bit field size in bits for I2S_RCR3_RCE. /
Kojto	90:cb3d968589d8	2346
Kojto	90:cb3d968589d8	2347	/! @brief Read current value of the I2S_RCR3_RCE field. /
Kojto	90:cb3d968589d8	2348	#define BR_I2S_RCR3_RCE(x) (HW_I2S_RCR3(x).B.RCE)
Kojto	90:cb3d968589d8	2349
Kojto	90:cb3d968589d8	2350	/! @brief Format value for bitfield I2S_RCR3_RCE. /
Kojto	90:cb3d968589d8	2351	#define BF_I2S_RCR3_RCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_RCE) & BM_I2S_RCR3_RCE)
Kojto	90:cb3d968589d8	2352
Kojto	90:cb3d968589d8	2353	/! @brief Set the RCE field to a new value. /
Kojto	90:cb3d968589d8	2354	#define BW_I2S_RCR3_RCE(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_RCE) \| BF_I2S_RCR3_RCE(v)))
Kojto	90:cb3d968589d8	2355	/@}/
Kojto	90:cb3d968589d8	2356
Kojto	90:cb3d968589d8	2357	/*******************************************************************************
Kojto	90:cb3d968589d8	2358	* HW_I2S_RCR4 - SAI Receive Configuration 4 Register
Kojto	90:cb3d968589d8	2359	******************************************************************************/
Kojto	90:cb3d968589d8	2360
Kojto	90:cb3d968589d8	2361	/*!
Kojto	90:cb3d968589d8	2362	* @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
Kojto	90:cb3d968589d8	2363	*
Kojto	90:cb3d968589d8	2364	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2365	*
Kojto	90:cb3d968589d8	2366	* This register must not be altered when RCSR[RE] is set.
Kojto	90:cb3d968589d8	2367	*/
Kojto	90:cb3d968589d8	2368	typedef union _hw_i2s_rcr4
Kojto	90:cb3d968589d8	2369	{
Kojto	90:cb3d968589d8	2370	uint32_t U;
Kojto	90:cb3d968589d8	2371	struct _hw_i2s_rcr4_bitfields
Kojto	90:cb3d968589d8	2372	{
Kojto	90:cb3d968589d8	2373	uint32_t FSD : 1; /!< [0] Frame Sync Direction /
Kojto	90:cb3d968589d8	2374	uint32_t FSP : 1; /!< [1] Frame Sync Polarity /
Kojto	90:cb3d968589d8	2375	uint32_t RESERVED0 : 1; /!< [2] /
Kojto	90:cb3d968589d8	2376	uint32_t FSE : 1; /!< [3] Frame Sync Early /
Kojto	90:cb3d968589d8	2377	uint32_t MF : 1; /!< [4] MSB First /
Kojto	90:cb3d968589d8	2378	uint32_t RESERVED1 : 3; /!< [7:5] /
Kojto	90:cb3d968589d8	2379	uint32_t SYWD : 5; /!< [12:8] Sync Width /
Kojto	90:cb3d968589d8	2380	uint32_t RESERVED2 : 3; /!< [15:13] /
Kojto	90:cb3d968589d8	2381	uint32_t FRSZ : 5; /!< [20:16] Frame Size /
Kojto	90:cb3d968589d8	2382	uint32_t RESERVED3 : 11; /!< [31:21] /
Kojto	90:cb3d968589d8	2383	} B;
Kojto	90:cb3d968589d8	2384	} hw_i2s_rcr4_t;
Kojto	90:cb3d968589d8	2385
Kojto	90:cb3d968589d8	2386	/*!
Kojto	90:cb3d968589d8	2387	* @name Constants and macros for entire I2S_RCR4 register
Kojto	90:cb3d968589d8	2388	*/
Kojto	90:cb3d968589d8	2389	/@{/
Kojto	90:cb3d968589d8	2390	#define HW_I2S_RCR4_ADDR(x) ((x) + 0x90U)
Kojto	90:cb3d968589d8	2391
Kojto	90:cb3d968589d8	2392	#define HW_I2S_RCR4(x) ((__IO hw_i2s_rcr4_t ) HW_I2S_RCR4_ADDR(x))
Kojto	90:cb3d968589d8	2393	#define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U)
Kojto	90:cb3d968589d8	2394	#define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v))
Kojto	90:cb3d968589d8	2395	#define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2396	#define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2397	#define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2398	/@}/
Kojto	90:cb3d968589d8	2399
Kojto	90:cb3d968589d8	2400	/*
Kojto	90:cb3d968589d8	2401	* Constants & macros for individual I2S_RCR4 bitfields
Kojto	90:cb3d968589d8	2402	*/
Kojto	90:cb3d968589d8	2403
Kojto	90:cb3d968589d8	2404	/*!
Kojto	90:cb3d968589d8	2405	* @name Register I2S_RCR4, field FSD[0] (RW)
Kojto	90:cb3d968589d8	2406	*
Kojto	90:cb3d968589d8	2407	* Configures the direction of the frame sync.
Kojto	90:cb3d968589d8	2408	*
Kojto	90:cb3d968589d8	2409	* Values:
Kojto	90:cb3d968589d8	2410	* - 0 - Frame Sync is generated externally in Slave mode.
Kojto	90:cb3d968589d8	2411	* - 1 - Frame Sync is generated internally in Master mode.
Kojto	90:cb3d968589d8	2412	*/
Kojto	90:cb3d968589d8	2413	/@{/
Kojto	90:cb3d968589d8	2414	#define BP_I2S_RCR4_FSD (0U) /!< Bit position for I2S_RCR4_FSD. /
Kojto	90:cb3d968589d8	2415	#define BM_I2S_RCR4_FSD (0x00000001U) /!< Bit mask for I2S_RCR4_FSD. /
Kojto	90:cb3d968589d8	2416	#define BS_I2S_RCR4_FSD (1U) /!< Bit field size in bits for I2S_RCR4_FSD. /
Kojto	90:cb3d968589d8	2417
Kojto	90:cb3d968589d8	2418	/! @brief Read current value of the I2S_RCR4_FSD field. /
Kojto	90:cb3d968589d8	2419	#define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
Kojto	90:cb3d968589d8	2420
Kojto	90:cb3d968589d8	2421	/! @brief Format value for bitfield I2S_RCR4_FSD. /
Kojto	90:cb3d968589d8	2422	#define BF_I2S_RCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSD) & BM_I2S_RCR4_FSD)
Kojto	90:cb3d968589d8	2423
Kojto	90:cb3d968589d8	2424	/! @brief Set the FSD field to a new value. /
Kojto	90:cb3d968589d8	2425	#define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
Kojto	90:cb3d968589d8	2426	/@}/
Kojto	90:cb3d968589d8	2427
Kojto	90:cb3d968589d8	2428	/*!
Kojto	90:cb3d968589d8	2429	* @name Register I2S_RCR4, field FSP[1] (RW)
Kojto	90:cb3d968589d8	2430	*
Kojto	90:cb3d968589d8	2431	* Configures the polarity of the frame sync.
Kojto	90:cb3d968589d8	2432	*
Kojto	90:cb3d968589d8	2433	* Values:
Kojto	90:cb3d968589d8	2434	* - 0 - Frame sync is active high.
Kojto	90:cb3d968589d8	2435	* - 1 - Frame sync is active low.
Kojto	90:cb3d968589d8	2436	*/
Kojto	90:cb3d968589d8	2437	/@{/
Kojto	90:cb3d968589d8	2438	#define BP_I2S_RCR4_FSP (1U) /!< Bit position for I2S_RCR4_FSP. /
Kojto	90:cb3d968589d8	2439	#define BM_I2S_RCR4_FSP (0x00000002U) /!< Bit mask for I2S_RCR4_FSP. /
Kojto	90:cb3d968589d8	2440	#define BS_I2S_RCR4_FSP (1U) /!< Bit field size in bits for I2S_RCR4_FSP. /
Kojto	90:cb3d968589d8	2441
Kojto	90:cb3d968589d8	2442	/! @brief Read current value of the I2S_RCR4_FSP field. /
Kojto	90:cb3d968589d8	2443	#define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
Kojto	90:cb3d968589d8	2444
Kojto	90:cb3d968589d8	2445	/! @brief Format value for bitfield I2S_RCR4_FSP. /
Kojto	90:cb3d968589d8	2446	#define BF_I2S_RCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSP) & BM_I2S_RCR4_FSP)
Kojto	90:cb3d968589d8	2447
Kojto	90:cb3d968589d8	2448	/! @brief Set the FSP field to a new value. /
Kojto	90:cb3d968589d8	2449	#define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
Kojto	90:cb3d968589d8	2450	/@}/
Kojto	90:cb3d968589d8	2451
Kojto	90:cb3d968589d8	2452	/*!
Kojto	90:cb3d968589d8	2453	* @name Register I2S_RCR4, field FSE[3] (RW)
Kojto	90:cb3d968589d8	2454	*
Kojto	90:cb3d968589d8	2455	* Values:
Kojto	90:cb3d968589d8	2456	* - 0 - Frame sync asserts with the first bit of the frame.
Kojto	90:cb3d968589d8	2457	* - 1 - Frame sync asserts one bit before the first bit of the frame.
Kojto	90:cb3d968589d8	2458	*/
Kojto	90:cb3d968589d8	2459	/@{/
Kojto	90:cb3d968589d8	2460	#define BP_I2S_RCR4_FSE (3U) /!< Bit position for I2S_RCR4_FSE. /
Kojto	90:cb3d968589d8	2461	#define BM_I2S_RCR4_FSE (0x00000008U) /!< Bit mask for I2S_RCR4_FSE. /
Kojto	90:cb3d968589d8	2462	#define BS_I2S_RCR4_FSE (1U) /!< Bit field size in bits for I2S_RCR4_FSE. /
Kojto	90:cb3d968589d8	2463
Kojto	90:cb3d968589d8	2464	/! @brief Read current value of the I2S_RCR4_FSE field. /
Kojto	90:cb3d968589d8	2465	#define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
Kojto	90:cb3d968589d8	2466
Kojto	90:cb3d968589d8	2467	/! @brief Format value for bitfield I2S_RCR4_FSE. /
Kojto	90:cb3d968589d8	2468	#define BF_I2S_RCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSE) & BM_I2S_RCR4_FSE)
Kojto	90:cb3d968589d8	2469
Kojto	90:cb3d968589d8	2470	/! @brief Set the FSE field to a new value. /
Kojto	90:cb3d968589d8	2471	#define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
Kojto	90:cb3d968589d8	2472	/@}/
Kojto	90:cb3d968589d8	2473
Kojto	90:cb3d968589d8	2474	/*!
Kojto	90:cb3d968589d8	2475	* @name Register I2S_RCR4, field MF[4] (RW)
Kojto	90:cb3d968589d8	2476	*
Kojto	90:cb3d968589d8	2477	* Configures whether the LSB or the MSB is received first.
Kojto	90:cb3d968589d8	2478	*
Kojto	90:cb3d968589d8	2479	* Values:
Kojto	90:cb3d968589d8	2480	* - 0 - LSB is received first.
Kojto	90:cb3d968589d8	2481	* - 1 - MSB is received first.
Kojto	90:cb3d968589d8	2482	*/
Kojto	90:cb3d968589d8	2483	/@{/
Kojto	90:cb3d968589d8	2484	#define BP_I2S_RCR4_MF (4U) /!< Bit position for I2S_RCR4_MF. /
Kojto	90:cb3d968589d8	2485	#define BM_I2S_RCR4_MF (0x00000010U) /!< Bit mask for I2S_RCR4_MF. /
Kojto	90:cb3d968589d8	2486	#define BS_I2S_RCR4_MF (1U) /!< Bit field size in bits for I2S_RCR4_MF. /
Kojto	90:cb3d968589d8	2487
Kojto	90:cb3d968589d8	2488	/! @brief Read current value of the I2S_RCR4_MF field. /
Kojto	90:cb3d968589d8	2489	#define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
Kojto	90:cb3d968589d8	2490
Kojto	90:cb3d968589d8	2491	/! @brief Format value for bitfield I2S_RCR4_MF. /
Kojto	90:cb3d968589d8	2492	#define BF_I2S_RCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_MF) & BM_I2S_RCR4_MF)
Kojto	90:cb3d968589d8	2493
Kojto	90:cb3d968589d8	2494	/! @brief Set the MF field to a new value. /
Kojto	90:cb3d968589d8	2495	#define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
Kojto	90:cb3d968589d8	2496	/@}/
Kojto	90:cb3d968589d8	2497
Kojto	90:cb3d968589d8	2498	/*!
Kojto	90:cb3d968589d8	2499	* @name Register I2S_RCR4, field SYWD[12:8] (RW)
Kojto	90:cb3d968589d8	2500	*
Kojto	90:cb3d968589d8	2501	* Configures the length of the frame sync in number of bit clocks. The value
Kojto	90:cb3d968589d8	2502	* written must be one less than the number of bit clocks. For example, write 0 for
Kojto	90:cb3d968589d8	2503	* the frame sync to assert for one bit clock only. The sync width cannot be
Kojto	90:cb3d968589d8	2504	* configured longer than the first word of the frame.
Kojto	90:cb3d968589d8	2505	*/
Kojto	90:cb3d968589d8	2506	/@{/
Kojto	90:cb3d968589d8	2507	#define BP_I2S_RCR4_SYWD (8U) /!< Bit position for I2S_RCR4_SYWD. /
Kojto	90:cb3d968589d8	2508	#define BM_I2S_RCR4_SYWD (0x00001F00U) /!< Bit mask for I2S_RCR4_SYWD. /
Kojto	90:cb3d968589d8	2509	#define BS_I2S_RCR4_SYWD (5U) /!< Bit field size in bits for I2S_RCR4_SYWD. /
Kojto	90:cb3d968589d8	2510
Kojto	90:cb3d968589d8	2511	/! @brief Read current value of the I2S_RCR4_SYWD field. /
Kojto	90:cb3d968589d8	2512	#define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD)
Kojto	90:cb3d968589d8	2513
Kojto	90:cb3d968589d8	2514	/! @brief Format value for bitfield I2S_RCR4_SYWD. /
Kojto	90:cb3d968589d8	2515	#define BF_I2S_RCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_SYWD) & BM_I2S_RCR4_SYWD)
Kojto	90:cb3d968589d8	2516
Kojto	90:cb3d968589d8	2517	/! @brief Set the SYWD field to a new value. /
Kojto	90:cb3d968589d8	2518	#define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) \| BF_I2S_RCR4_SYWD(v)))
Kojto	90:cb3d968589d8	2519	/@}/
Kojto	90:cb3d968589d8	2520
Kojto	90:cb3d968589d8	2521	/*!
Kojto	90:cb3d968589d8	2522	* @name Register I2S_RCR4, field FRSZ[20:16] (RW)
Kojto	90:cb3d968589d8	2523	*
Kojto	90:cb3d968589d8	2524	* Configures the number of words in each frame. The value written must be one
Kojto	90:cb3d968589d8	2525	* less than the number of words in the frame. For example, write 0 for one word
Kojto	90:cb3d968589d8	2526	* per frame. The maximum supported frame size is 32 words.
Kojto	90:cb3d968589d8	2527	*/
Kojto	90:cb3d968589d8	2528	/@{/
Kojto	90:cb3d968589d8	2529	#define BP_I2S_RCR4_FRSZ (16U) /!< Bit position for I2S_RCR4_FRSZ. /
Kojto	90:cb3d968589d8	2530	#define BM_I2S_RCR4_FRSZ (0x001F0000U) /!< Bit mask for I2S_RCR4_FRSZ. /
Kojto	90:cb3d968589d8	2531	#define BS_I2S_RCR4_FRSZ (5U) /!< Bit field size in bits for I2S_RCR4_FRSZ. /
Kojto	90:cb3d968589d8	2532
Kojto	90:cb3d968589d8	2533	/! @brief Read current value of the I2S_RCR4_FRSZ field. /
Kojto	90:cb3d968589d8	2534	#define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ)
Kojto	90:cb3d968589d8	2535
Kojto	90:cb3d968589d8	2536	/! @brief Format value for bitfield I2S_RCR4_FRSZ. /
Kojto	90:cb3d968589d8	2537	#define BF_I2S_RCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FRSZ) & BM_I2S_RCR4_FRSZ)
Kojto	90:cb3d968589d8	2538
Kojto	90:cb3d968589d8	2539	/! @brief Set the FRSZ field to a new value. /
Kojto	90:cb3d968589d8	2540	#define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) \| BF_I2S_RCR4_FRSZ(v)))
Kojto	90:cb3d968589d8	2541	/@}/
Kojto	90:cb3d968589d8	2542
Kojto	90:cb3d968589d8	2543	/*******************************************************************************
Kojto	90:cb3d968589d8	2544	* HW_I2S_RCR5 - SAI Receive Configuration 5 Register
Kojto	90:cb3d968589d8	2545	******************************************************************************/
Kojto	90:cb3d968589d8	2546
Kojto	90:cb3d968589d8	2547	/*!
Kojto	90:cb3d968589d8	2548	* @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
Kojto	90:cb3d968589d8	2549	*
Kojto	90:cb3d968589d8	2550	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2551	*
Kojto	90:cb3d968589d8	2552	* This register must not be altered when RCSR[RE] is set.
Kojto	90:cb3d968589d8	2553	*/
Kojto	90:cb3d968589d8	2554	typedef union _hw_i2s_rcr5
Kojto	90:cb3d968589d8	2555	{
Kojto	90:cb3d968589d8	2556	uint32_t U;
Kojto	90:cb3d968589d8	2557	struct _hw_i2s_rcr5_bitfields
Kojto	90:cb3d968589d8	2558	{
Kojto	90:cb3d968589d8	2559	uint32_t RESERVED0 : 8; /!< [7:0] /
Kojto	90:cb3d968589d8	2560	uint32_t FBT : 5; /!< [12:8] First Bit Shifted /
Kojto	90:cb3d968589d8	2561	uint32_t RESERVED1 : 3; /!< [15:13] /
Kojto	90:cb3d968589d8	2562	uint32_t W0W : 5; /!< [20:16] Word 0 Width /
Kojto	90:cb3d968589d8	2563	uint32_t RESERVED2 : 3; /!< [23:21] /
Kojto	90:cb3d968589d8	2564	uint32_t WNW : 5; /!< [28:24] Word N Width /
Kojto	90:cb3d968589d8	2565	uint32_t RESERVED3 : 3; /!< [31:29] /
Kojto	90:cb3d968589d8	2566	} B;
Kojto	90:cb3d968589d8	2567	} hw_i2s_rcr5_t;
Kojto	90:cb3d968589d8	2568
Kojto	90:cb3d968589d8	2569	/*!
Kojto	90:cb3d968589d8	2570	* @name Constants and macros for entire I2S_RCR5 register
Kojto	90:cb3d968589d8	2571	*/
Kojto	90:cb3d968589d8	2572	/@{/
Kojto	90:cb3d968589d8	2573	#define HW_I2S_RCR5_ADDR(x) ((x) + 0x94U)
Kojto	90:cb3d968589d8	2574
Kojto	90:cb3d968589d8	2575	#define HW_I2S_RCR5(x) ((__IO hw_i2s_rcr5_t ) HW_I2S_RCR5_ADDR(x))
Kojto	90:cb3d968589d8	2576	#define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U)
Kojto	90:cb3d968589d8	2577	#define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v))
Kojto	90:cb3d968589d8	2578	#define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2579	#define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2580	#define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2581	/@}/
Kojto	90:cb3d968589d8	2582
Kojto	90:cb3d968589d8	2583	/*
Kojto	90:cb3d968589d8	2584	* Constants & macros for individual I2S_RCR5 bitfields
Kojto	90:cb3d968589d8	2585	*/
Kojto	90:cb3d968589d8	2586
Kojto	90:cb3d968589d8	2587	/*!
Kojto	90:cb3d968589d8	2588	* @name Register I2S_RCR5, field FBT[12:8] (RW)
Kojto	90:cb3d968589d8	2589	*
Kojto	90:cb3d968589d8	2590	* Configures the bit index for the first bit received for each word in the
Kojto	90:cb3d968589d8	2591	* frame. If configured for MSB First, the index of the next bit received is one less
Kojto	90:cb3d968589d8	2592	* than the current bit received. If configured for LSB First, the index of the
Kojto	90:cb3d968589d8	2593	* next bit received is one more than the current bit received. The value written
Kojto	90:cb3d968589d8	2594	* must be greater than or equal to the word width when configured for MSB
Kojto	90:cb3d968589d8	2595	* First. The value written must be less than or equal to 31-word width when
Kojto	90:cb3d968589d8	2596	* configured for LSB First.
Kojto	90:cb3d968589d8	2597	*/
Kojto	90:cb3d968589d8	2598	/@{/
Kojto	90:cb3d968589d8	2599	#define BP_I2S_RCR5_FBT (8U) /!< Bit position for I2S_RCR5_FBT. /
Kojto	90:cb3d968589d8	2600	#define BM_I2S_RCR5_FBT (0x00001F00U) /!< Bit mask for I2S_RCR5_FBT. /
Kojto	90:cb3d968589d8	2601	#define BS_I2S_RCR5_FBT (5U) /!< Bit field size in bits for I2S_RCR5_FBT. /
Kojto	90:cb3d968589d8	2602
Kojto	90:cb3d968589d8	2603	/! @brief Read current value of the I2S_RCR5_FBT field. /
Kojto	90:cb3d968589d8	2604	#define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT)
Kojto	90:cb3d968589d8	2605
Kojto	90:cb3d968589d8	2606	/! @brief Format value for bitfield I2S_RCR5_FBT. /
Kojto	90:cb3d968589d8	2607	#define BF_I2S_RCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_FBT) & BM_I2S_RCR5_FBT)
Kojto	90:cb3d968589d8	2608
Kojto	90:cb3d968589d8	2609	/! @brief Set the FBT field to a new value. /
Kojto	90:cb3d968589d8	2610	#define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) \| BF_I2S_RCR5_FBT(v)))
Kojto	90:cb3d968589d8	2611	/@}/
Kojto	90:cb3d968589d8	2612
Kojto	90:cb3d968589d8	2613	/*!
Kojto	90:cb3d968589d8	2614	* @name Register I2S_RCR5, field W0W[20:16] (RW)
Kojto	90:cb3d968589d8	2615	*
Kojto	90:cb3d968589d8	2616	* Configures the number of bits in the first word in each frame. The value
Kojto	90:cb3d968589d8	2617	* written must be one less than the number of bits in the first word. Word width of
Kojto	90:cb3d968589d8	2618	* less than 8 bits is not supported if there is only one word per frame.
Kojto	90:cb3d968589d8	2619	*/
Kojto	90:cb3d968589d8	2620	/@{/
Kojto	90:cb3d968589d8	2621	#define BP_I2S_RCR5_W0W (16U) /!< Bit position for I2S_RCR5_W0W. /
Kojto	90:cb3d968589d8	2622	#define BM_I2S_RCR5_W0W (0x001F0000U) /!< Bit mask for I2S_RCR5_W0W. /
Kojto	90:cb3d968589d8	2623	#define BS_I2S_RCR5_W0W (5U) /!< Bit field size in bits for I2S_RCR5_W0W. /
Kojto	90:cb3d968589d8	2624
Kojto	90:cb3d968589d8	2625	/! @brief Read current value of the I2S_RCR5_W0W field. /
Kojto	90:cb3d968589d8	2626	#define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W)
Kojto	90:cb3d968589d8	2627
Kojto	90:cb3d968589d8	2628	/! @brief Format value for bitfield I2S_RCR5_W0W. /
Kojto	90:cb3d968589d8	2629	#define BF_I2S_RCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_W0W) & BM_I2S_RCR5_W0W)
Kojto	90:cb3d968589d8	2630
Kojto	90:cb3d968589d8	2631	/! @brief Set the W0W field to a new value. /
Kojto	90:cb3d968589d8	2632	#define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) \| BF_I2S_RCR5_W0W(v)))
Kojto	90:cb3d968589d8	2633	/@}/
Kojto	90:cb3d968589d8	2634
Kojto	90:cb3d968589d8	2635	/*!
Kojto	90:cb3d968589d8	2636	* @name Register I2S_RCR5, field WNW[28:24] (RW)
Kojto	90:cb3d968589d8	2637	*
Kojto	90:cb3d968589d8	2638	* Configures the number of bits in each word, for each word except the first in
Kojto	90:cb3d968589d8	2639	* the frame. The value written must be one less than the number of bits per
Kojto	90:cb3d968589d8	2640	* word. Word width of less than 8 bits is not supported.
Kojto	90:cb3d968589d8	2641	*/
Kojto	90:cb3d968589d8	2642	/@{/
Kojto	90:cb3d968589d8	2643	#define BP_I2S_RCR5_WNW (24U) /!< Bit position for I2S_RCR5_WNW. /
Kojto	90:cb3d968589d8	2644	#define BM_I2S_RCR5_WNW (0x1F000000U) /!< Bit mask for I2S_RCR5_WNW. /
Kojto	90:cb3d968589d8	2645	#define BS_I2S_RCR5_WNW (5U) /!< Bit field size in bits for I2S_RCR5_WNW. /
Kojto	90:cb3d968589d8	2646
Kojto	90:cb3d968589d8	2647	/! @brief Read current value of the I2S_RCR5_WNW field. /
Kojto	90:cb3d968589d8	2648	#define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW)
Kojto	90:cb3d968589d8	2649
Kojto	90:cb3d968589d8	2650	/! @brief Format value for bitfield I2S_RCR5_WNW. /
Kojto	90:cb3d968589d8	2651	#define BF_I2S_RCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_WNW) & BM_I2S_RCR5_WNW)
Kojto	90:cb3d968589d8	2652
Kojto	90:cb3d968589d8	2653	/! @brief Set the WNW field to a new value. /
Kojto	90:cb3d968589d8	2654	#define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) \| BF_I2S_RCR5_WNW(v)))
Kojto	90:cb3d968589d8	2655	/@}/
Kojto	90:cb3d968589d8	2656
Kojto	90:cb3d968589d8	2657	/*******************************************************************************
Kojto	90:cb3d968589d8	2658	* HW_I2S_RDRn - SAI Receive Data Register
Kojto	90:cb3d968589d8	2659	******************************************************************************/
Kojto	90:cb3d968589d8	2660
Kojto	90:cb3d968589d8	2661	/*!
Kojto	90:cb3d968589d8	2662	* @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
Kojto	90:cb3d968589d8	2663	*
Kojto	90:cb3d968589d8	2664	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2665	*
Kojto	90:cb3d968589d8	2666	* Reading this register introduces one additional peripheral clock wait state
Kojto	90:cb3d968589d8	2667	* on each read.
Kojto	90:cb3d968589d8	2668	*/
Kojto	90:cb3d968589d8	2669	typedef union _hw_i2s_rdrn
Kojto	90:cb3d968589d8	2670	{
Kojto	90:cb3d968589d8	2671	uint32_t U;
Kojto	90:cb3d968589d8	2672	struct _hw_i2s_rdrn_bitfields
Kojto	90:cb3d968589d8	2673	{
Kojto	90:cb3d968589d8	2674	uint32_t RDR : 32; /!< [31:0] Receive Data Register /
Kojto	90:cb3d968589d8	2675	} B;
Kojto	90:cb3d968589d8	2676	} hw_i2s_rdrn_t;
Kojto	90:cb3d968589d8	2677
Kojto	90:cb3d968589d8	2678	/*!
Kojto	90:cb3d968589d8	2679	* @name Constants and macros for entire I2S_RDRn register
Kojto	90:cb3d968589d8	2680	*/
Kojto	90:cb3d968589d8	2681	/@{/
Kojto	90:cb3d968589d8	2682	#define HW_I2S_RDRn_COUNT (2U)
Kojto	90:cb3d968589d8	2683
Kojto	90:cb3d968589d8	2684	#define HW_I2S_RDRn_ADDR(x, n) ((x) + 0xA0U + (0x4U * (n)))
Kojto	90:cb3d968589d8	2685
Kojto	90:cb3d968589d8	2686	#define HW_I2S_RDRn(x, n) ((__I hw_i2s_rdrn_t ) HW_I2S_RDRn_ADDR(x, n))
Kojto	90:cb3d968589d8	2687	#define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U)
Kojto	90:cb3d968589d8	2688	/@}/
Kojto	90:cb3d968589d8	2689
Kojto	90:cb3d968589d8	2690	/*
Kojto	90:cb3d968589d8	2691	* Constants & macros for individual I2S_RDRn bitfields
Kojto	90:cb3d968589d8	2692	*/
Kojto	90:cb3d968589d8	2693
Kojto	90:cb3d968589d8	2694	/*!
Kojto	90:cb3d968589d8	2695	* @name Register I2S_RDRn, field RDR[31:0] (RO)
Kojto	90:cb3d968589d8	2696	*
Kojto	90:cb3d968589d8	2697	* The corresponding RCR3[RCE] bit must be set before accessing the channel's
Kojto	90:cb3d968589d8	2698	* receive data register. Reads from this register when the receive FIFO is not
Kojto	90:cb3d968589d8	2699	* empty will return the data from the top of the receive FIFO. Reads from this
Kojto	90:cb3d968589d8	2700	* register when the receive FIFO is empty are ignored.
Kojto	90:cb3d968589d8	2701	*/
Kojto	90:cb3d968589d8	2702	/@{/
Kojto	90:cb3d968589d8	2703	#define BP_I2S_RDRn_RDR (0U) /!< Bit position for I2S_RDRn_RDR. /
Kojto	90:cb3d968589d8	2704	#define BM_I2S_RDRn_RDR (0xFFFFFFFFU) /!< Bit mask for I2S_RDRn_RDR. /
Kojto	90:cb3d968589d8	2705	#define BS_I2S_RDRn_RDR (32U) /!< Bit field size in bits for I2S_RDRn_RDR. /
Kojto	90:cb3d968589d8	2706
Kojto	90:cb3d968589d8	2707	/! @brief Read current value of the I2S_RDRn_RDR field. /
Kojto	90:cb3d968589d8	2708	#define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
Kojto	90:cb3d968589d8	2709	/@}/
Kojto	90:cb3d968589d8	2710
Kojto	90:cb3d968589d8	2711	/*******************************************************************************
Kojto	90:cb3d968589d8	2712	* HW_I2S_RFRn - SAI Receive FIFO Register
Kojto	90:cb3d968589d8	2713	******************************************************************************/
Kojto	90:cb3d968589d8	2714
Kojto	90:cb3d968589d8	2715	/*!
Kojto	90:cb3d968589d8	2716	* @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
Kojto	90:cb3d968589d8	2717	*
Kojto	90:cb3d968589d8	2718	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2719	*
Kojto	90:cb3d968589d8	2720	* The MSB of the read and write pointers is used to distinguish between FIFO
Kojto	90:cb3d968589d8	2721	* full and empty conditions. If the read and write pointers are identical, then
Kojto	90:cb3d968589d8	2722	* the FIFO is empty. If the read and write pointers are identical except for the
Kojto	90:cb3d968589d8	2723	* MSB, then the FIFO is full.
Kojto	90:cb3d968589d8	2724	*/
Kojto	90:cb3d968589d8	2725	typedef union _hw_i2s_rfrn
Kojto	90:cb3d968589d8	2726	{
Kojto	90:cb3d968589d8	2727	uint32_t U;
Kojto	90:cb3d968589d8	2728	struct _hw_i2s_rfrn_bitfields
Kojto	90:cb3d968589d8	2729	{
Kojto	90:cb3d968589d8	2730	uint32_t RFP : 4; /!< [3:0] Read FIFO Pointer /
Kojto	90:cb3d968589d8	2731	uint32_t RESERVED0 : 12; /!< [15:4] /
Kojto	90:cb3d968589d8	2732	uint32_t WFP : 4; /!< [19:16] Write FIFO Pointer /
Kojto	90:cb3d968589d8	2733	uint32_t RESERVED1 : 12; /!< [31:20] /
Kojto	90:cb3d968589d8	2734	} B;
Kojto	90:cb3d968589d8	2735	} hw_i2s_rfrn_t;
Kojto	90:cb3d968589d8	2736
Kojto	90:cb3d968589d8	2737	/*!
Kojto	90:cb3d968589d8	2738	* @name Constants and macros for entire I2S_RFRn register
Kojto	90:cb3d968589d8	2739	*/
Kojto	90:cb3d968589d8	2740	/@{/
Kojto	90:cb3d968589d8	2741	#define HW_I2S_RFRn_COUNT (2U)
Kojto	90:cb3d968589d8	2742
Kojto	90:cb3d968589d8	2743	#define HW_I2S_RFRn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n)))
Kojto	90:cb3d968589d8	2744
Kojto	90:cb3d968589d8	2745	#define HW_I2S_RFRn(x, n) ((__I hw_i2s_rfrn_t ) HW_I2S_RFRn_ADDR(x, n))
Kojto	90:cb3d968589d8	2746	#define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U)
Kojto	90:cb3d968589d8	2747	/@}/
Kojto	90:cb3d968589d8	2748
Kojto	90:cb3d968589d8	2749	/*
Kojto	90:cb3d968589d8	2750	* Constants & macros for individual I2S_RFRn bitfields
Kojto	90:cb3d968589d8	2751	*/
Kojto	90:cb3d968589d8	2752
Kojto	90:cb3d968589d8	2753	/*!
Kojto	90:cb3d968589d8	2754	* @name Register I2S_RFRn, field RFP[3:0] (RO)
Kojto	90:cb3d968589d8	2755	*
Kojto	90:cb3d968589d8	2756	* FIFO read pointer for receive data channel.
Kojto	90:cb3d968589d8	2757	*/
Kojto	90:cb3d968589d8	2758	/@{/
Kojto	90:cb3d968589d8	2759	#define BP_I2S_RFRn_RFP (0U) /!< Bit position for I2S_RFRn_RFP. /
Kojto	90:cb3d968589d8	2760	#define BM_I2S_RFRn_RFP (0x0000000FU) /!< Bit mask for I2S_RFRn_RFP. /
Kojto	90:cb3d968589d8	2761	#define BS_I2S_RFRn_RFP (4U) /!< Bit field size in bits for I2S_RFRn_RFP. /
Kojto	90:cb3d968589d8	2762
Kojto	90:cb3d968589d8	2763	/! @brief Read current value of the I2S_RFRn_RFP field. /
Kojto	90:cb3d968589d8	2764	#define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
Kojto	90:cb3d968589d8	2765	/@}/
Kojto	90:cb3d968589d8	2766
Kojto	90:cb3d968589d8	2767	/*!
Kojto	90:cb3d968589d8	2768	* @name Register I2S_RFRn, field WFP[19:16] (RO)
Kojto	90:cb3d968589d8	2769	*
Kojto	90:cb3d968589d8	2770	* FIFO write pointer for receive data channel.
Kojto	90:cb3d968589d8	2771	*/
Kojto	90:cb3d968589d8	2772	/@{/
Kojto	90:cb3d968589d8	2773	#define BP_I2S_RFRn_WFP (16U) /!< Bit position for I2S_RFRn_WFP. /
Kojto	90:cb3d968589d8	2774	#define BM_I2S_RFRn_WFP (0x000F0000U) /!< Bit mask for I2S_RFRn_WFP. /
Kojto	90:cb3d968589d8	2775	#define BS_I2S_RFRn_WFP (4U) /!< Bit field size in bits for I2S_RFRn_WFP. /
Kojto	90:cb3d968589d8	2776
Kojto	90:cb3d968589d8	2777	/! @brief Read current value of the I2S_RFRn_WFP field. /
Kojto	90:cb3d968589d8	2778	#define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
Kojto	90:cb3d968589d8	2779	/@}/
Kojto	90:cb3d968589d8	2780
Kojto	90:cb3d968589d8	2781	/*******************************************************************************
Kojto	90:cb3d968589d8	2782	* HW_I2S_RMR - SAI Receive Mask Register
Kojto	90:cb3d968589d8	2783	******************************************************************************/
Kojto	90:cb3d968589d8	2784
Kojto	90:cb3d968589d8	2785	/*!
Kojto	90:cb3d968589d8	2786	* @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
Kojto	90:cb3d968589d8	2787	*
Kojto	90:cb3d968589d8	2788	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2789	*
Kojto	90:cb3d968589d8	2790	* This register is double-buffered and updates: When RCSR[RE] is first set At
Kojto	90:cb3d968589d8	2791	* the end of each frame This allows the masked words in each frame to change from
Kojto	90:cb3d968589d8	2792	* frame to frame.
Kojto	90:cb3d968589d8	2793	*/
Kojto	90:cb3d968589d8	2794	typedef union _hw_i2s_rmr
Kojto	90:cb3d968589d8	2795	{
Kojto	90:cb3d968589d8	2796	uint32_t U;
Kojto	90:cb3d968589d8	2797	struct _hw_i2s_rmr_bitfields
Kojto	90:cb3d968589d8	2798	{
Kojto	90:cb3d968589d8	2799	uint32_t RWM : 32; /!< [31:0] Receive Word Mask /
Kojto	90:cb3d968589d8	2800	} B;
Kojto	90:cb3d968589d8	2801	} hw_i2s_rmr_t;
Kojto	90:cb3d968589d8	2802
Kojto	90:cb3d968589d8	2803	/*!
Kojto	90:cb3d968589d8	2804	* @name Constants and macros for entire I2S_RMR register
Kojto	90:cb3d968589d8	2805	*/
Kojto	90:cb3d968589d8	2806	/@{/
Kojto	90:cb3d968589d8	2807	#define HW_I2S_RMR_ADDR(x) ((x) + 0xE0U)
Kojto	90:cb3d968589d8	2808
Kojto	90:cb3d968589d8	2809	#define HW_I2S_RMR(x) ((__IO hw_i2s_rmr_t ) HW_I2S_RMR_ADDR(x))
Kojto	90:cb3d968589d8	2810	#define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U)
Kojto	90:cb3d968589d8	2811	#define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v))
Kojto	90:cb3d968589d8	2812	#define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2813	#define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2814	#define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2815	/@}/
Kojto	90:cb3d968589d8	2816
Kojto	90:cb3d968589d8	2817	/*
Kojto	90:cb3d968589d8	2818	* Constants & macros for individual I2S_RMR bitfields
Kojto	90:cb3d968589d8	2819	*/
Kojto	90:cb3d968589d8	2820
Kojto	90:cb3d968589d8	2821	/*!
Kojto	90:cb3d968589d8	2822	* @name Register I2S_RMR, field RWM[31:0] (RW)
Kojto	90:cb3d968589d8	2823	*
Kojto	90:cb3d968589d8	2824	* Configures whether the receive word is masked (received data ignored and not
Kojto	90:cb3d968589d8	2825	* written to receive FIFO) for the corresponding word in the frame.
Kojto	90:cb3d968589d8	2826	*
Kojto	90:cb3d968589d8	2827	* Values:
Kojto	90:cb3d968589d8	2828	* - 0 - Word N is enabled.
Kojto	90:cb3d968589d8	2829	* - 1 - Word N is masked.
Kojto	90:cb3d968589d8	2830	*/
Kojto	90:cb3d968589d8	2831	/@{/
Kojto	90:cb3d968589d8	2832	#define BP_I2S_RMR_RWM (0U) /!< Bit position for I2S_RMR_RWM. /
Kojto	90:cb3d968589d8	2833	#define BM_I2S_RMR_RWM (0xFFFFFFFFU) /!< Bit mask for I2S_RMR_RWM. /
Kojto	90:cb3d968589d8	2834	#define BS_I2S_RMR_RWM (32U) /!< Bit field size in bits for I2S_RMR_RWM. /
Kojto	90:cb3d968589d8	2835
Kojto	90:cb3d968589d8	2836	/! @brief Read current value of the I2S_RMR_RWM field. /
Kojto	90:cb3d968589d8	2837	#define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).U)
Kojto	90:cb3d968589d8	2838
Kojto	90:cb3d968589d8	2839	/! @brief Format value for bitfield I2S_RMR_RWM. /
Kojto	90:cb3d968589d8	2840	#define BF_I2S_RMR_RWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RMR_RWM) & BM_I2S_RMR_RWM)
Kojto	90:cb3d968589d8	2841
Kojto	90:cb3d968589d8	2842	/! @brief Set the RWM field to a new value. /
Kojto	90:cb3d968589d8	2843	#define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, v))
Kojto	90:cb3d968589d8	2844	/@}/
Kojto	90:cb3d968589d8	2845
Kojto	90:cb3d968589d8	2846	/*******************************************************************************
Kojto	90:cb3d968589d8	2847	* HW_I2S_MCR - SAI MCLK Control Register
Kojto	90:cb3d968589d8	2848	******************************************************************************/
Kojto	90:cb3d968589d8	2849
Kojto	90:cb3d968589d8	2850	/*!
Kojto	90:cb3d968589d8	2851	* @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
Kojto	90:cb3d968589d8	2852	*
Kojto	90:cb3d968589d8	2853	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2854	*
Kojto	90:cb3d968589d8	2855	* The MCLK Control Register (MCR) controls the clock source and direction of
Kojto	90:cb3d968589d8	2856	* the audio master clock.
Kojto	90:cb3d968589d8	2857	*/
Kojto	90:cb3d968589d8	2858	typedef union _hw_i2s_mcr
Kojto	90:cb3d968589d8	2859	{
Kojto	90:cb3d968589d8	2860	uint32_t U;
Kojto	90:cb3d968589d8	2861	struct _hw_i2s_mcr_bitfields
Kojto	90:cb3d968589d8	2862	{
Kojto	90:cb3d968589d8	2863	uint32_t RESERVED0 : 24; /!< [23:0] /
Kojto	90:cb3d968589d8	2864	uint32_t MICS : 2; /!< [25:24] MCLK Input Clock Select /
Kojto	90:cb3d968589d8	2865	uint32_t RESERVED1 : 4; /!< [29:26] /
Kojto	90:cb3d968589d8	2866	uint32_t MOE : 1; /!< [30] MCLK Output Enable /
Kojto	90:cb3d968589d8	2867	uint32_t DUF : 1; /!< [31] Divider Update Flag /
Kojto	90:cb3d968589d8	2868	} B;
Kojto	90:cb3d968589d8	2869	} hw_i2s_mcr_t;
Kojto	90:cb3d968589d8	2870
Kojto	90:cb3d968589d8	2871	/*!
Kojto	90:cb3d968589d8	2872	* @name Constants and macros for entire I2S_MCR register
Kojto	90:cb3d968589d8	2873	*/
Kojto	90:cb3d968589d8	2874	/@{/
Kojto	90:cb3d968589d8	2875	#define HW_I2S_MCR_ADDR(x) ((x) + 0x100U)
Kojto	90:cb3d968589d8	2876
Kojto	90:cb3d968589d8	2877	#define HW_I2S_MCR(x) ((__IO hw_i2s_mcr_t ) HW_I2S_MCR_ADDR(x))
Kojto	90:cb3d968589d8	2878	#define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U)
Kojto	90:cb3d968589d8	2879	#define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v))
Kojto	90:cb3d968589d8	2880	#define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2881	#define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	2882	#define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	2883	/@}/
Kojto	90:cb3d968589d8	2884
Kojto	90:cb3d968589d8	2885	/*
Kojto	90:cb3d968589d8	2886	* Constants & macros for individual I2S_MCR bitfields
Kojto	90:cb3d968589d8	2887	*/
Kojto	90:cb3d968589d8	2888
Kojto	90:cb3d968589d8	2889	/*!
Kojto	90:cb3d968589d8	2890	* @name Register I2S_MCR, field MICS[25:24] (RW)
Kojto	90:cb3d968589d8	2891	*
Kojto	90:cb3d968589d8	2892	* Selects the clock input to the MCLK divider. This field cannot be changed
Kojto	90:cb3d968589d8	2893	* while the MCLK divider is enabled. See the chip configuration details for
Kojto	90:cb3d968589d8	2894	* information about the connections to these inputs.
Kojto	90:cb3d968589d8	2895	*
Kojto	90:cb3d968589d8	2896	* Values:
Kojto	90:cb3d968589d8	2897	* - 00 - MCLK divider input clock 0 selected.
Kojto	90:cb3d968589d8	2898	* - 01 - MCLK divider input clock 1 selected.
Kojto	90:cb3d968589d8	2899	* - 10 - MCLK divider input clock 2 selected.
Kojto	90:cb3d968589d8	2900	* - 11 - MCLK divider input clock 3 selected.
Kojto	90:cb3d968589d8	2901	*/
Kojto	90:cb3d968589d8	2902	/@{/
Kojto	90:cb3d968589d8	2903	#define BP_I2S_MCR_MICS (24U) /!< Bit position for I2S_MCR_MICS. /
Kojto	90:cb3d968589d8	2904	#define BM_I2S_MCR_MICS (0x03000000U) /!< Bit mask for I2S_MCR_MICS. /
Kojto	90:cb3d968589d8	2905	#define BS_I2S_MCR_MICS (2U) /!< Bit field size in bits for I2S_MCR_MICS. /
Kojto	90:cb3d968589d8	2906
Kojto	90:cb3d968589d8	2907	/! @brief Read current value of the I2S_MCR_MICS field. /
Kojto	90:cb3d968589d8	2908	#define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS)
Kojto	90:cb3d968589d8	2909
Kojto	90:cb3d968589d8	2910	/! @brief Format value for bitfield I2S_MCR_MICS. /
Kojto	90:cb3d968589d8	2911	#define BF_I2S_MCR_MICS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MICS) & BM_I2S_MCR_MICS)
Kojto	90:cb3d968589d8	2912
Kojto	90:cb3d968589d8	2913	/! @brief Set the MICS field to a new value. /
Kojto	90:cb3d968589d8	2914	#define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) \| BF_I2S_MCR_MICS(v)))
Kojto	90:cb3d968589d8	2915	/@}/
Kojto	90:cb3d968589d8	2916
Kojto	90:cb3d968589d8	2917	/*!
Kojto	90:cb3d968589d8	2918	* @name Register I2S_MCR, field MOE[30] (RW)
Kojto	90:cb3d968589d8	2919	*
Kojto	90:cb3d968589d8	2920	* Enables the MCLK divider and configures the MCLK signal pin as an output.
Kojto	90:cb3d968589d8	2921	* When software clears this field, it remains set until the MCLK divider is fully
Kojto	90:cb3d968589d8	2922	* disabled.
Kojto	90:cb3d968589d8	2923	*
Kojto	90:cb3d968589d8	2924	* Values:
Kojto	90:cb3d968589d8	2925	* - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
Kojto	90:cb3d968589d8	2926	* divider.
Kojto	90:cb3d968589d8	2927	* - 1 - MCLK signal pin is configured as an output from the MCLK divider and
Kojto	90:cb3d968589d8	2928	* the MCLK divider is enabled.
Kojto	90:cb3d968589d8	2929	*/
Kojto	90:cb3d968589d8	2930	/@{/
Kojto	90:cb3d968589d8	2931	#define BP_I2S_MCR_MOE (30U) /!< Bit position for I2S_MCR_MOE. /
Kojto	90:cb3d968589d8	2932	#define BM_I2S_MCR_MOE (0x40000000U) /!< Bit mask for I2S_MCR_MOE. /
Kojto	90:cb3d968589d8	2933	#define BS_I2S_MCR_MOE (1U) /!< Bit field size in bits for I2S_MCR_MOE. /
Kojto	90:cb3d968589d8	2934
Kojto	90:cb3d968589d8	2935	/! @brief Read current value of the I2S_MCR_MOE field. /
Kojto	90:cb3d968589d8	2936	#define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
Kojto	90:cb3d968589d8	2937
Kojto	90:cb3d968589d8	2938	/! @brief Format value for bitfield I2S_MCR_MOE. /
Kojto	90:cb3d968589d8	2939	#define BF_I2S_MCR_MOE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MOE) & BM_I2S_MCR_MOE)
Kojto	90:cb3d968589d8	2940
Kojto	90:cb3d968589d8	2941	/! @brief Set the MOE field to a new value. /
Kojto	90:cb3d968589d8	2942	#define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
Kojto	90:cb3d968589d8	2943	/@}/
Kojto	90:cb3d968589d8	2944
Kojto	90:cb3d968589d8	2945	/*!
Kojto	90:cb3d968589d8	2946	* @name Register I2S_MCR, field DUF[31] (RO)
Kojto	90:cb3d968589d8	2947	*
Kojto	90:cb3d968589d8	2948	* Provides the status of on-the-fly updates to the MCLK divider ratio.
Kojto	90:cb3d968589d8	2949	*
Kojto	90:cb3d968589d8	2950	* Values:
Kojto	90:cb3d968589d8	2951	* - 0 - MCLK divider ratio is not being updated currently.
Kojto	90:cb3d968589d8	2952	* - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
Kojto	90:cb3d968589d8	2953	* divider ratio are blocked while this flag remains set.
Kojto	90:cb3d968589d8	2954	*/
Kojto	90:cb3d968589d8	2955	/@{/
Kojto	90:cb3d968589d8	2956	#define BP_I2S_MCR_DUF (31U) /!< Bit position for I2S_MCR_DUF. /
Kojto	90:cb3d968589d8	2957	#define BM_I2S_MCR_DUF (0x80000000U) /!< Bit mask for I2S_MCR_DUF. /
Kojto	90:cb3d968589d8	2958	#define BS_I2S_MCR_DUF (1U) /!< Bit field size in bits for I2S_MCR_DUF. /
Kojto	90:cb3d968589d8	2959
Kojto	90:cb3d968589d8	2960	/! @brief Read current value of the I2S_MCR_DUF field. /
Kojto	90:cb3d968589d8	2961	#define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
Kojto	90:cb3d968589d8	2962	/@}/
Kojto	90:cb3d968589d8	2963
Kojto	90:cb3d968589d8	2964	/*******************************************************************************
Kojto	90:cb3d968589d8	2965	* HW_I2S_MDR - SAI MCLK Divide Register
Kojto	90:cb3d968589d8	2966	******************************************************************************/
Kojto	90:cb3d968589d8	2967
Kojto	90:cb3d968589d8	2968	/*!
Kojto	90:cb3d968589d8	2969	* @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
Kojto	90:cb3d968589d8	2970	*
Kojto	90:cb3d968589d8	2971	* Reset value: 0x00000000U
Kojto	90:cb3d968589d8	2972	*
Kojto	90:cb3d968589d8	2973	* The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
Kojto	90:cb3d968589d8	2974	* MDR can be changed when the MCLK divider clock is enabled, additional writes
Kojto	90:cb3d968589d8	2975	* to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
Kojto	90:cb3d968589d8	2976	* divided clock is disabled do not set MCR[DUF].
Kojto	90:cb3d968589d8	2977	*/
Kojto	90:cb3d968589d8	2978	typedef union _hw_i2s_mdr
Kojto	90:cb3d968589d8	2979	{
Kojto	90:cb3d968589d8	2980	uint32_t U;
Kojto	90:cb3d968589d8	2981	struct _hw_i2s_mdr_bitfields
Kojto	90:cb3d968589d8	2982	{
Kojto	90:cb3d968589d8	2983	uint32_t DIVIDE : 12; /!< [11:0] MCLK Divide /
Kojto	90:cb3d968589d8	2984	uint32_t FRACT : 8; /!< [19:12] MCLK Fraction /
Kojto	90:cb3d968589d8	2985	uint32_t RESERVED0 : 12; /!< [31:20] /
Kojto	90:cb3d968589d8	2986	} B;
Kojto	90:cb3d968589d8	2987	} hw_i2s_mdr_t;
Kojto	90:cb3d968589d8	2988
Kojto	90:cb3d968589d8	2989	/*!
Kojto	90:cb3d968589d8	2990	* @name Constants and macros for entire I2S_MDR register
Kojto	90:cb3d968589d8	2991	*/
Kojto	90:cb3d968589d8	2992	/@{/
Kojto	90:cb3d968589d8	2993	#define HW_I2S_MDR_ADDR(x) ((x) + 0x104U)
Kojto	90:cb3d968589d8	2994
Kojto	90:cb3d968589d8	2995	#define HW_I2S_MDR(x) ((__IO hw_i2s_mdr_t ) HW_I2S_MDR_ADDR(x))
Kojto	90:cb3d968589d8	2996	#define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U)
Kojto	90:cb3d968589d8	2997	#define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v))
Kojto	90:cb3d968589d8	2998	#define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) \| (v)))
Kojto	90:cb3d968589d8	2999	#define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
Kojto	90:cb3d968589d8	3000	#define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v)))
Kojto	90:cb3d968589d8	3001	/@}/
Kojto	90:cb3d968589d8	3002
Kojto	90:cb3d968589d8	3003	/*
Kojto	90:cb3d968589d8	3004	* Constants & macros for individual I2S_MDR bitfields
Kojto	90:cb3d968589d8	3005	*/
Kojto	90:cb3d968589d8	3006
Kojto	90:cb3d968589d8	3007	/*!
Kojto	90:cb3d968589d8	3008	* @name Register I2S_MDR, field DIVIDE[11:0] (RW)
Kojto	90:cb3d968589d8	3009	*
Kojto	90:cb3d968589d8	3010	* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
Kojto	90:cb3d968589d8	3011	* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
Kojto	90:cb3d968589d8	3012	* DIVIDE field.
Kojto	90:cb3d968589d8	3013	*/
Kojto	90:cb3d968589d8	3014	/@{/
Kojto	90:cb3d968589d8	3015	#define BP_I2S_MDR_DIVIDE (0U) /!< Bit position for I2S_MDR_DIVIDE. /
Kojto	90:cb3d968589d8	3016	#define BM_I2S_MDR_DIVIDE (0x00000FFFU) /!< Bit mask for I2S_MDR_DIVIDE. /
Kojto	90:cb3d968589d8	3017	#define BS_I2S_MDR_DIVIDE (12U) /!< Bit field size in bits for I2S_MDR_DIVIDE. /
Kojto	90:cb3d968589d8	3018
Kojto	90:cb3d968589d8	3019	/! @brief Read current value of the I2S_MDR_DIVIDE field. /
Kojto	90:cb3d968589d8	3020	#define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
Kojto	90:cb3d968589d8	3021
Kojto	90:cb3d968589d8	3022	/! @brief Format value for bitfield I2S_MDR_DIVIDE. /
Kojto	90:cb3d968589d8	3023	#define BF_I2S_MDR_DIVIDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_DIVIDE) & BM_I2S_MDR_DIVIDE)
Kojto	90:cb3d968589d8	3024
Kojto	90:cb3d968589d8	3025	/! @brief Set the DIVIDE field to a new value. /
Kojto	90:cb3d968589d8	3026	#define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) \| BF_I2S_MDR_DIVIDE(v)))
Kojto	90:cb3d968589d8	3027	/@}/
Kojto	90:cb3d968589d8	3028
Kojto	90:cb3d968589d8	3029	/*!
Kojto	90:cb3d968589d8	3030	* @name Register I2S_MDR, field FRACT[19:12] (RW)
Kojto	90:cb3d968589d8	3031	*
Kojto	90:cb3d968589d8	3032	* Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
Kojto	90:cb3d968589d8	3033	* 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
Kojto	90:cb3d968589d8	3034	* DIVIDE field.
Kojto	90:cb3d968589d8	3035	*/
Kojto	90:cb3d968589d8	3036	/@{/
Kojto	90:cb3d968589d8	3037	#define BP_I2S_MDR_FRACT (12U) /!< Bit position for I2S_MDR_FRACT. /
Kojto	90:cb3d968589d8	3038	#define BM_I2S_MDR_FRACT (0x000FF000U) /!< Bit mask for I2S_MDR_FRACT. /
Kojto	90:cb3d968589d8	3039	#define BS_I2S_MDR_FRACT (8U) /!< Bit field size in bits for I2S_MDR_FRACT. /
Kojto	90:cb3d968589d8	3040
Kojto	90:cb3d968589d8	3041	/! @brief Read current value of the I2S_MDR_FRACT field. /
Kojto	90:cb3d968589d8	3042	#define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT)
Kojto	90:cb3d968589d8	3043
Kojto	90:cb3d968589d8	3044	/! @brief Format value for bitfield I2S_MDR_FRACT. /
Kojto	90:cb3d968589d8	3045	#define BF_I2S_MDR_FRACT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_FRACT) & BM_I2S_MDR_FRACT)
Kojto	90:cb3d968589d8	3046
Kojto	90:cb3d968589d8	3047	/! @brief Set the FRACT field to a new value. /
Kojto	90:cb3d968589d8	3048	#define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) \| BF_I2S_MDR_FRACT(v)))
Kojto	90:cb3d968589d8	3049	/@}/
Kojto	90:cb3d968589d8	3050
Kojto	90:cb3d968589d8	3051	/*******************************************************************************
Kojto	90:cb3d968589d8	3052	* hw_i2s_t - module struct
Kojto	90:cb3d968589d8	3053	******************************************************************************/
Kojto	90:cb3d968589d8	3054	/*!
Kojto	90:cb3d968589d8	3055	* @brief All I2S module registers.
Kojto	90:cb3d968589d8	3056	*/
Kojto	90:cb3d968589d8	3057	#pragma pack(1)
Kojto	90:cb3d968589d8	3058	typedef struct _hw_i2s
Kojto	90:cb3d968589d8	3059	{
Kojto	90:cb3d968589d8	3060	__IO hw_i2s_tcsr_t TCSR; /!< [0x0] SAI Transmit Control Register /
Kojto	90:cb3d968589d8	3061	__IO hw_i2s_tcr1_t TCR1; /!< [0x4] SAI Transmit Configuration 1 Register /
Kojto	90:cb3d968589d8	3062	__IO hw_i2s_tcr2_t TCR2; /!< [0x8] SAI Transmit Configuration 2 Register /
Kojto	90:cb3d968589d8	3063	__IO hw_i2s_tcr3_t TCR3; /!< [0xC] SAI Transmit Configuration 3 Register /
Kojto	90:cb3d968589d8	3064	__IO hw_i2s_tcr4_t TCR4; /!< [0x10] SAI Transmit Configuration 4 Register /
Kojto	90:cb3d968589d8	3065	__IO hw_i2s_tcr5_t TCR5; /!< [0x14] SAI Transmit Configuration 5 Register /
Kojto	90:cb3d968589d8	3066	uint8_t _reserved0[8];
Kojto	90:cb3d968589d8	3067	__O hw_i2s_tdrn_t TDRn[2]; /!< [0x20] SAI Transmit Data Register /
Kojto	90:cb3d968589d8	3068	uint8_t _reserved1[24];
Kojto	90:cb3d968589d8	3069	__I hw_i2s_tfrn_t TFRn[2]; /!< [0x40] SAI Transmit FIFO Register /
Kojto	90:cb3d968589d8	3070	uint8_t _reserved2[24];
Kojto	90:cb3d968589d8	3071	__IO hw_i2s_tmr_t TMR; /!< [0x60] SAI Transmit Mask Register /
Kojto	90:cb3d968589d8	3072	uint8_t _reserved3[28];
Kojto	90:cb3d968589d8	3073	__IO hw_i2s_rcsr_t RCSR; /!< [0x80] SAI Receive Control Register /
Kojto	90:cb3d968589d8	3074	__IO hw_i2s_rcr1_t RCR1; /!< [0x84] SAI Receive Configuration 1 Register /
Kojto	90:cb3d968589d8	3075	__IO hw_i2s_rcr2_t RCR2; /!< [0x88] SAI Receive Configuration 2 Register /
Kojto	90:cb3d968589d8	3076	__IO hw_i2s_rcr3_t RCR3; /!< [0x8C] SAI Receive Configuration 3 Register /
Kojto	90:cb3d968589d8	3077	__IO hw_i2s_rcr4_t RCR4; /!< [0x90] SAI Receive Configuration 4 Register /
Kojto	90:cb3d968589d8	3078	__IO hw_i2s_rcr5_t RCR5; /!< [0x94] SAI Receive Configuration 5 Register /
Kojto	90:cb3d968589d8	3079	uint8_t _reserved4[8];
Kojto	90:cb3d968589d8	3080	__I hw_i2s_rdrn_t RDRn[2]; /!< [0xA0] SAI Receive Data Register /
Kojto	90:cb3d968589d8	3081	uint8_t _reserved5[24];
Kojto	90:cb3d968589d8	3082	__I hw_i2s_rfrn_t RFRn[2]; /!< [0xC0] SAI Receive FIFO Register /
Kojto	90:cb3d968589d8	3083	uint8_t _reserved6[24];
Kojto	90:cb3d968589d8	3084	__IO hw_i2s_rmr_t RMR; /!< [0xE0] SAI Receive Mask Register /
Kojto	90:cb3d968589d8	3085	uint8_t _reserved7[28];
Kojto	90:cb3d968589d8	3086	__IO hw_i2s_mcr_t MCR; /!< [0x100] SAI MCLK Control Register /
Kojto	90:cb3d968589d8	3087	__IO hw_i2s_mdr_t MDR; /!< [0x104] SAI MCLK Divide Register /
Kojto	90:cb3d968589d8	3088	} hw_i2s_t;
Kojto	90:cb3d968589d8	3089	#pragma pack()
Kojto	90:cb3d968589d8	3090
Kojto	90:cb3d968589d8	3091	/! @brief Macro to access all I2S registers. /
Kojto	90:cb3d968589d8	3092	/! @param x I2S module instance base address. /
Kojto	90:cb3d968589d8	3093	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto	90:cb3d968589d8	3094	* use the '&' operator, like <code>&HW_I2S(I2S0_BASE)</code>. */
Kojto	90:cb3d968589d8	3095	#define HW_I2S(x) ((hw_i2s_t )(x))
Kojto	90:cb3d968589d8	3096
Kojto	90:cb3d968589d8	3097	#endif /* __HW_I2S_REGISTERS_H__ */
Kojto	90:cb3d968589d8	3098	/* EOF */