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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ftm.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_FTM_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_FTM_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 FTM
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * FlexTimer Module
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_FTM_SC - Status And Control
Kojto 90:cb3d968589d8 93 * - HW_FTM_CNT - Counter
Kojto 90:cb3d968589d8 94 * - HW_FTM_MOD - Modulo
Kojto 90:cb3d968589d8 95 * - HW_FTM_CnSC - Channel (n) Status And Control
Kojto 90:cb3d968589d8 96 * - HW_FTM_CnV - Channel (n) Value
Kojto 90:cb3d968589d8 97 * - HW_FTM_CNTIN - Counter Initial Value
Kojto 90:cb3d968589d8 98 * - HW_FTM_STATUS - Capture And Compare Status
Kojto 90:cb3d968589d8 99 * - HW_FTM_MODE - Features Mode Selection
Kojto 90:cb3d968589d8 100 * - HW_FTM_SYNC - Synchronization
Kojto 90:cb3d968589d8 101 * - HW_FTM_OUTINIT - Initial State For Channels Output
Kojto 90:cb3d968589d8 102 * - HW_FTM_OUTMASK - Output Mask
Kojto 90:cb3d968589d8 103 * - HW_FTM_COMBINE - Function For Linked Channels
Kojto 90:cb3d968589d8 104 * - HW_FTM_DEADTIME - Deadtime Insertion Control
Kojto 90:cb3d968589d8 105 * - HW_FTM_EXTTRIG - FTM External Trigger
Kojto 90:cb3d968589d8 106 * - HW_FTM_POL - Channels Polarity
Kojto 90:cb3d968589d8 107 * - HW_FTM_FMS - Fault Mode Status
Kojto 90:cb3d968589d8 108 * - HW_FTM_FILTER - Input Capture Filter Control
Kojto 90:cb3d968589d8 109 * - HW_FTM_FLTCTRL - Fault Control
Kojto 90:cb3d968589d8 110 * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
Kojto 90:cb3d968589d8 111 * - HW_FTM_CONF - Configuration
Kojto 90:cb3d968589d8 112 * - HW_FTM_FLTPOL - FTM Fault Input Polarity
Kojto 90:cb3d968589d8 113 * - HW_FTM_SYNCONF - Synchronization Configuration
Kojto 90:cb3d968589d8 114 * - HW_FTM_INVCTRL - FTM Inverting Control
Kojto 90:cb3d968589d8 115 * - HW_FTM_SWOCTRL - FTM Software Output Control
Kojto 90:cb3d968589d8 116 * - HW_FTM_PWMLOAD - FTM PWM Load
Kojto 90:cb3d968589d8 117 *
Kojto 90:cb3d968589d8 118 * - hw_ftm_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 119 */
Kojto 90:cb3d968589d8 120
Kojto 90:cb3d968589d8 121 #define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
Kojto 90:cb3d968589d8 122 #define HW_FTM0 (0U) /*!< Instance number for FTM0. */
Kojto 90:cb3d968589d8 123 #define HW_FTM1 (1U) /*!< Instance number for FTM1. */
Kojto 90:cb3d968589d8 124 #define HW_FTM2 (2U) /*!< Instance number for FTM2. */
Kojto 90:cb3d968589d8 125 #define HW_FTM3 (3U) /*!< Instance number for FTM3. */
Kojto 90:cb3d968589d8 126
Kojto 90:cb3d968589d8 127 /*******************************************************************************
Kojto 90:cb3d968589d8 128 * HW_FTM_SC - Status And Control
Kojto 90:cb3d968589d8 129 ******************************************************************************/
Kojto 90:cb3d968589d8 130
Kojto 90:cb3d968589d8 131 /*!
Kojto 90:cb3d968589d8 132 * @brief HW_FTM_SC - Status And Control (RW)
Kojto 90:cb3d968589d8 133 *
Kojto 90:cb3d968589d8 134 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 135 *
Kojto 90:cb3d968589d8 136 * SC contains the overflow status flag and control bits used to configure the
Kojto 90:cb3d968589d8 137 * interrupt enable, FTM configuration, clock source, and prescaler factor. These
Kojto 90:cb3d968589d8 138 * controls relate to all channels within this module.
Kojto 90:cb3d968589d8 139 */
Kojto 90:cb3d968589d8 140 typedef union _hw_ftm_sc
Kojto 90:cb3d968589d8 141 {
Kojto 90:cb3d968589d8 142 uint32_t U;
Kojto 90:cb3d968589d8 143 struct _hw_ftm_sc_bitfields
Kojto 90:cb3d968589d8 144 {
Kojto 90:cb3d968589d8 145 uint32_t PS : 3; /*!< [2:0] Prescale Factor Selection */
Kojto 90:cb3d968589d8 146 uint32_t CLKS : 2; /*!< [4:3] Clock Source Selection */
Kojto 90:cb3d968589d8 147 uint32_t CPWMS : 1; /*!< [5] Center-Aligned PWM Select */
Kojto 90:cb3d968589d8 148 uint32_t TOIE : 1; /*!< [6] Timer Overflow Interrupt Enable */
Kojto 90:cb3d968589d8 149 uint32_t TOF : 1; /*!< [7] Timer Overflow Flag */
Kojto 90:cb3d968589d8 150 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 151 } B;
Kojto 90:cb3d968589d8 152 } hw_ftm_sc_t;
Kojto 90:cb3d968589d8 153
Kojto 90:cb3d968589d8 154 /*!
Kojto 90:cb3d968589d8 155 * @name Constants and macros for entire FTM_SC register
Kojto 90:cb3d968589d8 156 */
Kojto 90:cb3d968589d8 157 /*@{*/
Kojto 90:cb3d968589d8 158 #define HW_FTM_SC_ADDR(x) ((x) + 0x0U)
Kojto 90:cb3d968589d8 159
Kojto 90:cb3d968589d8 160 #define HW_FTM_SC(x) (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
Kojto 90:cb3d968589d8 161 #define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
Kojto 90:cb3d968589d8 162 #define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
Kojto 90:cb3d968589d8 163 #define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) | (v)))
Kojto 90:cb3d968589d8 164 #define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 165 #define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 166 /*@}*/
Kojto 90:cb3d968589d8 167
Kojto 90:cb3d968589d8 168 /*
Kojto 90:cb3d968589d8 169 * Constants & macros for individual FTM_SC bitfields
Kojto 90:cb3d968589d8 170 */
Kojto 90:cb3d968589d8 171
Kojto 90:cb3d968589d8 172 /*!
Kojto 90:cb3d968589d8 173 * @name Register FTM_SC, field PS[2:0] (RW)
Kojto 90:cb3d968589d8 174 *
Kojto 90:cb3d968589d8 175 * Selects one of 8 division factors for the clock source selected by CLKS. The
Kojto 90:cb3d968589d8 176 * new prescaler factor affects the clock source on the next system clock cycle
Kojto 90:cb3d968589d8 177 * after the new value is updated into the register bits. This field is write
Kojto 90:cb3d968589d8 178 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 179 *
Kojto 90:cb3d968589d8 180 * Values:
Kojto 90:cb3d968589d8 181 * - 000 - Divide by 1
Kojto 90:cb3d968589d8 182 * - 001 - Divide by 2
Kojto 90:cb3d968589d8 183 * - 010 - Divide by 4
Kojto 90:cb3d968589d8 184 * - 011 - Divide by 8
Kojto 90:cb3d968589d8 185 * - 100 - Divide by 16
Kojto 90:cb3d968589d8 186 * - 101 - Divide by 32
Kojto 90:cb3d968589d8 187 * - 110 - Divide by 64
Kojto 90:cb3d968589d8 188 * - 111 - Divide by 128
Kojto 90:cb3d968589d8 189 */
Kojto 90:cb3d968589d8 190 /*@{*/
Kojto 90:cb3d968589d8 191 #define BP_FTM_SC_PS (0U) /*!< Bit position for FTM_SC_PS. */
Kojto 90:cb3d968589d8 192 #define BM_FTM_SC_PS (0x00000007U) /*!< Bit mask for FTM_SC_PS. */
Kojto 90:cb3d968589d8 193 #define BS_FTM_SC_PS (3U) /*!< Bit field size in bits for FTM_SC_PS. */
Kojto 90:cb3d968589d8 194
Kojto 90:cb3d968589d8 195 /*! @brief Read current value of the FTM_SC_PS field. */
Kojto 90:cb3d968589d8 196 #define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
Kojto 90:cb3d968589d8 197
Kojto 90:cb3d968589d8 198 /*! @brief Format value for bitfield FTM_SC_PS. */
Kojto 90:cb3d968589d8 199 #define BF_FTM_SC_PS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS)
Kojto 90:cb3d968589d8 200
Kojto 90:cb3d968589d8 201 /*! @brief Set the PS field to a new value. */
Kojto 90:cb3d968589d8 202 #define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
Kojto 90:cb3d968589d8 203 /*@}*/
Kojto 90:cb3d968589d8 204
Kojto 90:cb3d968589d8 205 /*!
Kojto 90:cb3d968589d8 206 * @name Register FTM_SC, field CLKS[4:3] (RW)
Kojto 90:cb3d968589d8 207 *
Kojto 90:cb3d968589d8 208 * Selects one of the three FTM counter clock sources. This field is write
Kojto 90:cb3d968589d8 209 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 210 *
Kojto 90:cb3d968589d8 211 * Values:
Kojto 90:cb3d968589d8 212 * - 00 - No clock selected. This in effect disables the FTM counter.
Kojto 90:cb3d968589d8 213 * - 01 - System clock
Kojto 90:cb3d968589d8 214 * - 10 - Fixed frequency clock
Kojto 90:cb3d968589d8 215 * - 11 - External clock
Kojto 90:cb3d968589d8 216 */
Kojto 90:cb3d968589d8 217 /*@{*/
Kojto 90:cb3d968589d8 218 #define BP_FTM_SC_CLKS (3U) /*!< Bit position for FTM_SC_CLKS. */
Kojto 90:cb3d968589d8 219 #define BM_FTM_SC_CLKS (0x00000018U) /*!< Bit mask for FTM_SC_CLKS. */
Kojto 90:cb3d968589d8 220 #define BS_FTM_SC_CLKS (2U) /*!< Bit field size in bits for FTM_SC_CLKS. */
Kojto 90:cb3d968589d8 221
Kojto 90:cb3d968589d8 222 /*! @brief Read current value of the FTM_SC_CLKS field. */
Kojto 90:cb3d968589d8 223 #define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
Kojto 90:cb3d968589d8 224
Kojto 90:cb3d968589d8 225 /*! @brief Format value for bitfield FTM_SC_CLKS. */
Kojto 90:cb3d968589d8 226 #define BF_FTM_SC_CLKS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS)
Kojto 90:cb3d968589d8 227
Kojto 90:cb3d968589d8 228 /*! @brief Set the CLKS field to a new value. */
Kojto 90:cb3d968589d8 229 #define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
Kojto 90:cb3d968589d8 230 /*@}*/
Kojto 90:cb3d968589d8 231
Kojto 90:cb3d968589d8 232 /*!
Kojto 90:cb3d968589d8 233 * @name Register FTM_SC, field CPWMS[5] (RW)
Kojto 90:cb3d968589d8 234 *
Kojto 90:cb3d968589d8 235 * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
Kojto 90:cb3d968589d8 236 * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
Kojto 90:cb3d968589d8 237 * = 1.
Kojto 90:cb3d968589d8 238 *
Kojto 90:cb3d968589d8 239 * Values:
Kojto 90:cb3d968589d8 240 * - 0 - FTM counter operates in Up Counting mode.
Kojto 90:cb3d968589d8 241 * - 1 - FTM counter operates in Up-Down Counting mode.
Kojto 90:cb3d968589d8 242 */
Kojto 90:cb3d968589d8 243 /*@{*/
Kojto 90:cb3d968589d8 244 #define BP_FTM_SC_CPWMS (5U) /*!< Bit position for FTM_SC_CPWMS. */
Kojto 90:cb3d968589d8 245 #define BM_FTM_SC_CPWMS (0x00000020U) /*!< Bit mask for FTM_SC_CPWMS. */
Kojto 90:cb3d968589d8 246 #define BS_FTM_SC_CPWMS (1U) /*!< Bit field size in bits for FTM_SC_CPWMS. */
Kojto 90:cb3d968589d8 247
Kojto 90:cb3d968589d8 248 /*! @brief Read current value of the FTM_SC_CPWMS field. */
Kojto 90:cb3d968589d8 249 #define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
Kojto 90:cb3d968589d8 250
Kojto 90:cb3d968589d8 251 /*! @brief Format value for bitfield FTM_SC_CPWMS. */
Kojto 90:cb3d968589d8 252 #define BF_FTM_SC_CPWMS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS)
Kojto 90:cb3d968589d8 253
Kojto 90:cb3d968589d8 254 /*! @brief Set the CPWMS field to a new value. */
Kojto 90:cb3d968589d8 255 #define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
Kojto 90:cb3d968589d8 256 /*@}*/
Kojto 90:cb3d968589d8 257
Kojto 90:cb3d968589d8 258 /*!
Kojto 90:cb3d968589d8 259 * @name Register FTM_SC, field TOIE[6] (RW)
Kojto 90:cb3d968589d8 260 *
Kojto 90:cb3d968589d8 261 * Enables FTM overflow interrupts.
Kojto 90:cb3d968589d8 262 *
Kojto 90:cb3d968589d8 263 * Values:
Kojto 90:cb3d968589d8 264 * - 0 - Disable TOF interrupts. Use software polling.
Kojto 90:cb3d968589d8 265 * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
Kojto 90:cb3d968589d8 266 */
Kojto 90:cb3d968589d8 267 /*@{*/
Kojto 90:cb3d968589d8 268 #define BP_FTM_SC_TOIE (6U) /*!< Bit position for FTM_SC_TOIE. */
Kojto 90:cb3d968589d8 269 #define BM_FTM_SC_TOIE (0x00000040U) /*!< Bit mask for FTM_SC_TOIE. */
Kojto 90:cb3d968589d8 270 #define BS_FTM_SC_TOIE (1U) /*!< Bit field size in bits for FTM_SC_TOIE. */
Kojto 90:cb3d968589d8 271
Kojto 90:cb3d968589d8 272 /*! @brief Read current value of the FTM_SC_TOIE field. */
Kojto 90:cb3d968589d8 273 #define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
Kojto 90:cb3d968589d8 274
Kojto 90:cb3d968589d8 275 /*! @brief Format value for bitfield FTM_SC_TOIE. */
Kojto 90:cb3d968589d8 276 #define BF_FTM_SC_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE)
Kojto 90:cb3d968589d8 277
Kojto 90:cb3d968589d8 278 /*! @brief Set the TOIE field to a new value. */
Kojto 90:cb3d968589d8 279 #define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
Kojto 90:cb3d968589d8 280 /*@}*/
Kojto 90:cb3d968589d8 281
Kojto 90:cb3d968589d8 282 /*!
Kojto 90:cb3d968589d8 283 * @name Register FTM_SC, field TOF[7] (ROWZ)
Kojto 90:cb3d968589d8 284 *
Kojto 90:cb3d968589d8 285 * Set by hardware when the FTM counter passes the value in the MOD register.
Kojto 90:cb3d968589d8 286 * The TOF bit is cleared by reading the SC register while TOF is set and then
Kojto 90:cb3d968589d8 287 * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
Kojto 90:cb3d968589d8 288 * occurs between the read and write operations, the write operation has no
Kojto 90:cb3d968589d8 289 * effect; therefore, TOF remains set indicating an overflow has occurred. In this
Kojto 90:cb3d968589d8 290 * case, a TOF interrupt request is not lost due to the clearing sequence for a
Kojto 90:cb3d968589d8 291 * previous TOF.
Kojto 90:cb3d968589d8 292 *
Kojto 90:cb3d968589d8 293 * Values:
Kojto 90:cb3d968589d8 294 * - 0 - FTM counter has not overflowed.
Kojto 90:cb3d968589d8 295 * - 1 - FTM counter has overflowed.
Kojto 90:cb3d968589d8 296 */
Kojto 90:cb3d968589d8 297 /*@{*/
Kojto 90:cb3d968589d8 298 #define BP_FTM_SC_TOF (7U) /*!< Bit position for FTM_SC_TOF. */
Kojto 90:cb3d968589d8 299 #define BM_FTM_SC_TOF (0x00000080U) /*!< Bit mask for FTM_SC_TOF. */
Kojto 90:cb3d968589d8 300 #define BS_FTM_SC_TOF (1U) /*!< Bit field size in bits for FTM_SC_TOF. */
Kojto 90:cb3d968589d8 301
Kojto 90:cb3d968589d8 302 /*! @brief Read current value of the FTM_SC_TOF field. */
Kojto 90:cb3d968589d8 303 #define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
Kojto 90:cb3d968589d8 304
Kojto 90:cb3d968589d8 305 /*! @brief Format value for bitfield FTM_SC_TOF. */
Kojto 90:cb3d968589d8 306 #define BF_FTM_SC_TOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF)
Kojto 90:cb3d968589d8 307
Kojto 90:cb3d968589d8 308 /*! @brief Set the TOF field to a new value. */
Kojto 90:cb3d968589d8 309 #define BW_FTM_SC_TOF(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF) = (v))
Kojto 90:cb3d968589d8 310 /*@}*/
Kojto 90:cb3d968589d8 311
Kojto 90:cb3d968589d8 312 /*******************************************************************************
Kojto 90:cb3d968589d8 313 * HW_FTM_CNT - Counter
Kojto 90:cb3d968589d8 314 ******************************************************************************/
Kojto 90:cb3d968589d8 315
Kojto 90:cb3d968589d8 316 /*!
Kojto 90:cb3d968589d8 317 * @brief HW_FTM_CNT - Counter (RW)
Kojto 90:cb3d968589d8 318 *
Kojto 90:cb3d968589d8 319 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 320 *
Kojto 90:cb3d968589d8 321 * The CNT register contains the FTM counter value. Reset clears the CNT
Kojto 90:cb3d968589d8 322 * register. Writing any value to COUNT updates the counter with its initial value,
Kojto 90:cb3d968589d8 323 * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
Kojto 90:cb3d968589d8 324 * may read.
Kojto 90:cb3d968589d8 325 */
Kojto 90:cb3d968589d8 326 typedef union _hw_ftm_cnt
Kojto 90:cb3d968589d8 327 {
Kojto 90:cb3d968589d8 328 uint32_t U;
Kojto 90:cb3d968589d8 329 struct _hw_ftm_cnt_bitfields
Kojto 90:cb3d968589d8 330 {
Kojto 90:cb3d968589d8 331 uint32_t COUNT : 16; /*!< [15:0] Counter Value */
Kojto 90:cb3d968589d8 332 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 333 } B;
Kojto 90:cb3d968589d8 334 } hw_ftm_cnt_t;
Kojto 90:cb3d968589d8 335
Kojto 90:cb3d968589d8 336 /*!
Kojto 90:cb3d968589d8 337 * @name Constants and macros for entire FTM_CNT register
Kojto 90:cb3d968589d8 338 */
Kojto 90:cb3d968589d8 339 /*@{*/
Kojto 90:cb3d968589d8 340 #define HW_FTM_CNT_ADDR(x) ((x) + 0x4U)
Kojto 90:cb3d968589d8 341
Kojto 90:cb3d968589d8 342 #define HW_FTM_CNT(x) (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
Kojto 90:cb3d968589d8 343 #define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
Kojto 90:cb3d968589d8 344 #define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
Kojto 90:cb3d968589d8 345 #define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) | (v)))
Kojto 90:cb3d968589d8 346 #define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 347 #define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 348 /*@}*/
Kojto 90:cb3d968589d8 349
Kojto 90:cb3d968589d8 350 /*
Kojto 90:cb3d968589d8 351 * Constants & macros for individual FTM_CNT bitfields
Kojto 90:cb3d968589d8 352 */
Kojto 90:cb3d968589d8 353
Kojto 90:cb3d968589d8 354 /*!
Kojto 90:cb3d968589d8 355 * @name Register FTM_CNT, field COUNT[15:0] (RW)
Kojto 90:cb3d968589d8 356 */
Kojto 90:cb3d968589d8 357 /*@{*/
Kojto 90:cb3d968589d8 358 #define BP_FTM_CNT_COUNT (0U) /*!< Bit position for FTM_CNT_COUNT. */
Kojto 90:cb3d968589d8 359 #define BM_FTM_CNT_COUNT (0x0000FFFFU) /*!< Bit mask for FTM_CNT_COUNT. */
Kojto 90:cb3d968589d8 360 #define BS_FTM_CNT_COUNT (16U) /*!< Bit field size in bits for FTM_CNT_COUNT. */
Kojto 90:cb3d968589d8 361
Kojto 90:cb3d968589d8 362 /*! @brief Read current value of the FTM_CNT_COUNT field. */
Kojto 90:cb3d968589d8 363 #define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
Kojto 90:cb3d968589d8 364
Kojto 90:cb3d968589d8 365 /*! @brief Format value for bitfield FTM_CNT_COUNT. */
Kojto 90:cb3d968589d8 366 #define BF_FTM_CNT_COUNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT)
Kojto 90:cb3d968589d8 367
Kojto 90:cb3d968589d8 368 /*! @brief Set the COUNT field to a new value. */
Kojto 90:cb3d968589d8 369 #define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
Kojto 90:cb3d968589d8 370 /*@}*/
Kojto 90:cb3d968589d8 371
Kojto 90:cb3d968589d8 372 /*******************************************************************************
Kojto 90:cb3d968589d8 373 * HW_FTM_MOD - Modulo
Kojto 90:cb3d968589d8 374 ******************************************************************************/
Kojto 90:cb3d968589d8 375
Kojto 90:cb3d968589d8 376 /*!
Kojto 90:cb3d968589d8 377 * @brief HW_FTM_MOD - Modulo (RW)
Kojto 90:cb3d968589d8 378 *
Kojto 90:cb3d968589d8 379 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 380 *
Kojto 90:cb3d968589d8 381 * The Modulo register contains the modulo value for the FTM counter. After the
Kojto 90:cb3d968589d8 382 * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
Kojto 90:cb3d968589d8 383 * the next clock, and the next value of FTM counter depends on the selected
Kojto 90:cb3d968589d8 384 * counting method; see Counter. Writing to the MOD register latches the value into a
Kojto 90:cb3d968589d8 385 * buffer. The MOD register is updated with the value of its write buffer
Kojto 90:cb3d968589d8 386 * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
Kojto 90:cb3d968589d8 387 * mechanism may be manually reset by writing to the SC register whether BDM is
Kojto 90:cb3d968589d8 388 * active or not. Initialize the FTM counter, by writing to CNT, before writing
Kojto 90:cb3d968589d8 389 * to the MOD register to avoid confusion about when the first counter overflow
Kojto 90:cb3d968589d8 390 * will occur.
Kojto 90:cb3d968589d8 391 */
Kojto 90:cb3d968589d8 392 typedef union _hw_ftm_mod
Kojto 90:cb3d968589d8 393 {
Kojto 90:cb3d968589d8 394 uint32_t U;
Kojto 90:cb3d968589d8 395 struct _hw_ftm_mod_bitfields
Kojto 90:cb3d968589d8 396 {
Kojto 90:cb3d968589d8 397 uint32_t MOD : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 398 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 399 } B;
Kojto 90:cb3d968589d8 400 } hw_ftm_mod_t;
Kojto 90:cb3d968589d8 401
Kojto 90:cb3d968589d8 402 /*!
Kojto 90:cb3d968589d8 403 * @name Constants and macros for entire FTM_MOD register
Kojto 90:cb3d968589d8 404 */
Kojto 90:cb3d968589d8 405 /*@{*/
Kojto 90:cb3d968589d8 406 #define HW_FTM_MOD_ADDR(x) ((x) + 0x8U)
Kojto 90:cb3d968589d8 407
Kojto 90:cb3d968589d8 408 #define HW_FTM_MOD(x) (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
Kojto 90:cb3d968589d8 409 #define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
Kojto 90:cb3d968589d8 410 #define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
Kojto 90:cb3d968589d8 411 #define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) | (v)))
Kojto 90:cb3d968589d8 412 #define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 413 #define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 414 /*@}*/
Kojto 90:cb3d968589d8 415
Kojto 90:cb3d968589d8 416 /*
Kojto 90:cb3d968589d8 417 * Constants & macros for individual FTM_MOD bitfields
Kojto 90:cb3d968589d8 418 */
Kojto 90:cb3d968589d8 419
Kojto 90:cb3d968589d8 420 /*!
Kojto 90:cb3d968589d8 421 * @name Register FTM_MOD, field MOD[15:0] (RW)
Kojto 90:cb3d968589d8 422 *
Kojto 90:cb3d968589d8 423 * Modulo Value
Kojto 90:cb3d968589d8 424 */
Kojto 90:cb3d968589d8 425 /*@{*/
Kojto 90:cb3d968589d8 426 #define BP_FTM_MOD_MOD (0U) /*!< Bit position for FTM_MOD_MOD. */
Kojto 90:cb3d968589d8 427 #define BM_FTM_MOD_MOD (0x0000FFFFU) /*!< Bit mask for FTM_MOD_MOD. */
Kojto 90:cb3d968589d8 428 #define BS_FTM_MOD_MOD (16U) /*!< Bit field size in bits for FTM_MOD_MOD. */
Kojto 90:cb3d968589d8 429
Kojto 90:cb3d968589d8 430 /*! @brief Read current value of the FTM_MOD_MOD field. */
Kojto 90:cb3d968589d8 431 #define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
Kojto 90:cb3d968589d8 432
Kojto 90:cb3d968589d8 433 /*! @brief Format value for bitfield FTM_MOD_MOD. */
Kojto 90:cb3d968589d8 434 #define BF_FTM_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD)
Kojto 90:cb3d968589d8 435
Kojto 90:cb3d968589d8 436 /*! @brief Set the MOD field to a new value. */
Kojto 90:cb3d968589d8 437 #define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
Kojto 90:cb3d968589d8 438 /*@}*/
Kojto 90:cb3d968589d8 439
Kojto 90:cb3d968589d8 440 /*******************************************************************************
Kojto 90:cb3d968589d8 441 * HW_FTM_CnSC - Channel (n) Status And Control
Kojto 90:cb3d968589d8 442 ******************************************************************************/
Kojto 90:cb3d968589d8 443
Kojto 90:cb3d968589d8 444 /*!
Kojto 90:cb3d968589d8 445 * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
Kojto 90:cb3d968589d8 446 *
Kojto 90:cb3d968589d8 447 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 448 *
Kojto 90:cb3d968589d8 449 * CnSC contains the channel-interrupt-status flag and control bits used to
Kojto 90:cb3d968589d8 450 * configure the interrupt enable, channel configuration, and pin function. Mode,
Kojto 90:cb3d968589d8 451 * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
Kojto 90:cb3d968589d8 452 * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
Kojto 90:cb3d968589d8 453 * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
Kojto 90:cb3d968589d8 454 * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
Kojto 90:cb3d968589d8 455 * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
Kojto 90:cb3d968589d8 456 * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
Kojto 90:cb3d968589d8 457 * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
Kojto 90:cb3d968589d8 458 * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
Kojto 90:cb3d968589d8 459 * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
Kojto 90:cb3d968589d8 460 * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
Kojto 90:cb3d968589d8 461 * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
Kojto 90:cb3d968589d8 462 * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
Kojto 90:cb3d968589d8 463 * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
Kojto 90:cb3d968589d8 464 * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
Kojto 90:cb3d968589d8 465 * Enabled Rising and falling edges
Kojto 90:cb3d968589d8 466 */
Kojto 90:cb3d968589d8 467 typedef union _hw_ftm_cnsc
Kojto 90:cb3d968589d8 468 {
Kojto 90:cb3d968589d8 469 uint32_t U;
Kojto 90:cb3d968589d8 470 struct _hw_ftm_cnsc_bitfields
Kojto 90:cb3d968589d8 471 {
Kojto 90:cb3d968589d8 472 uint32_t DMA : 1; /*!< [0] DMA Enable */
Kojto 90:cb3d968589d8 473 uint32_t RESERVED0 : 1; /*!< [1] */
Kojto 90:cb3d968589d8 474 uint32_t ELSA : 1; /*!< [2] Edge or Level Select */
Kojto 90:cb3d968589d8 475 uint32_t ELSB : 1; /*!< [3] Edge or Level Select */
Kojto 90:cb3d968589d8 476 uint32_t MSA : 1; /*!< [4] Channel Mode Select */
Kojto 90:cb3d968589d8 477 uint32_t MSB : 1; /*!< [5] Channel Mode Select */
Kojto 90:cb3d968589d8 478 uint32_t CHIE : 1; /*!< [6] Channel Interrupt Enable */
Kojto 90:cb3d968589d8 479 uint32_t CHF : 1; /*!< [7] Channel Flag */
Kojto 90:cb3d968589d8 480 uint32_t RESERVED1 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 481 } B;
Kojto 90:cb3d968589d8 482 } hw_ftm_cnsc_t;
Kojto 90:cb3d968589d8 483
Kojto 90:cb3d968589d8 484 /*!
Kojto 90:cb3d968589d8 485 * @name Constants and macros for entire FTM_CnSC register
Kojto 90:cb3d968589d8 486 */
Kojto 90:cb3d968589d8 487 /*@{*/
Kojto 90:cb3d968589d8 488 #define HW_FTM_CnSC_COUNT (8U)
Kojto 90:cb3d968589d8 489
Kojto 90:cb3d968589d8 490 #define HW_FTM_CnSC_ADDR(x, n) ((x) + 0xCU + (0x8U * (n)))
Kojto 90:cb3d968589d8 491
Kojto 90:cb3d968589d8 492 #define HW_FTM_CnSC(x, n) (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
Kojto 90:cb3d968589d8 493 #define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
Kojto 90:cb3d968589d8 494 #define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
Kojto 90:cb3d968589d8 495 #define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 496 #define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 497 #define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 498 /*@}*/
Kojto 90:cb3d968589d8 499
Kojto 90:cb3d968589d8 500 /*
Kojto 90:cb3d968589d8 501 * Constants & macros for individual FTM_CnSC bitfields
Kojto 90:cb3d968589d8 502 */
Kojto 90:cb3d968589d8 503
Kojto 90:cb3d968589d8 504 /*!
Kojto 90:cb3d968589d8 505 * @name Register FTM_CnSC, field DMA[0] (RW)
Kojto 90:cb3d968589d8 506 *
Kojto 90:cb3d968589d8 507 * Enables DMA transfers for the channel.
Kojto 90:cb3d968589d8 508 *
Kojto 90:cb3d968589d8 509 * Values:
Kojto 90:cb3d968589d8 510 * - 0 - Disable DMA transfers.
Kojto 90:cb3d968589d8 511 * - 1 - Enable DMA transfers.
Kojto 90:cb3d968589d8 512 */
Kojto 90:cb3d968589d8 513 /*@{*/
Kojto 90:cb3d968589d8 514 #define BP_FTM_CnSC_DMA (0U) /*!< Bit position for FTM_CnSC_DMA. */
Kojto 90:cb3d968589d8 515 #define BM_FTM_CnSC_DMA (0x00000001U) /*!< Bit mask for FTM_CnSC_DMA. */
Kojto 90:cb3d968589d8 516 #define BS_FTM_CnSC_DMA (1U) /*!< Bit field size in bits for FTM_CnSC_DMA. */
Kojto 90:cb3d968589d8 517
Kojto 90:cb3d968589d8 518 /*! @brief Read current value of the FTM_CnSC_DMA field. */
Kojto 90:cb3d968589d8 519 #define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
Kojto 90:cb3d968589d8 520
Kojto 90:cb3d968589d8 521 /*! @brief Format value for bitfield FTM_CnSC_DMA. */
Kojto 90:cb3d968589d8 522 #define BF_FTM_CnSC_DMA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA)
Kojto 90:cb3d968589d8 523
Kojto 90:cb3d968589d8 524 /*! @brief Set the DMA field to a new value. */
Kojto 90:cb3d968589d8 525 #define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
Kojto 90:cb3d968589d8 526 /*@}*/
Kojto 90:cb3d968589d8 527
Kojto 90:cb3d968589d8 528 /*!
Kojto 90:cb3d968589d8 529 * @name Register FTM_CnSC, field ELSA[2] (RW)
Kojto 90:cb3d968589d8 530 *
Kojto 90:cb3d968589d8 531 * The functionality of ELSB and ELSA depends on the channel mode. See
Kojto 90:cb3d968589d8 532 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
Kojto 90:cb3d968589d8 533 * = 1.
Kojto 90:cb3d968589d8 534 */
Kojto 90:cb3d968589d8 535 /*@{*/
Kojto 90:cb3d968589d8 536 #define BP_FTM_CnSC_ELSA (2U) /*!< Bit position for FTM_CnSC_ELSA. */
Kojto 90:cb3d968589d8 537 #define BM_FTM_CnSC_ELSA (0x00000004U) /*!< Bit mask for FTM_CnSC_ELSA. */
Kojto 90:cb3d968589d8 538 #define BS_FTM_CnSC_ELSA (1U) /*!< Bit field size in bits for FTM_CnSC_ELSA. */
Kojto 90:cb3d968589d8 539
Kojto 90:cb3d968589d8 540 /*! @brief Read current value of the FTM_CnSC_ELSA field. */
Kojto 90:cb3d968589d8 541 #define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
Kojto 90:cb3d968589d8 542
Kojto 90:cb3d968589d8 543 /*! @brief Format value for bitfield FTM_CnSC_ELSA. */
Kojto 90:cb3d968589d8 544 #define BF_FTM_CnSC_ELSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA)
Kojto 90:cb3d968589d8 545
Kojto 90:cb3d968589d8 546 /*! @brief Set the ELSA field to a new value. */
Kojto 90:cb3d968589d8 547 #define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
Kojto 90:cb3d968589d8 548 /*@}*/
Kojto 90:cb3d968589d8 549
Kojto 90:cb3d968589d8 550 /*!
Kojto 90:cb3d968589d8 551 * @name Register FTM_CnSC, field ELSB[3] (RW)
Kojto 90:cb3d968589d8 552 *
Kojto 90:cb3d968589d8 553 * The functionality of ELSB and ELSA depends on the channel mode. See
Kojto 90:cb3d968589d8 554 * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
Kojto 90:cb3d968589d8 555 * = 1.
Kojto 90:cb3d968589d8 556 */
Kojto 90:cb3d968589d8 557 /*@{*/
Kojto 90:cb3d968589d8 558 #define BP_FTM_CnSC_ELSB (3U) /*!< Bit position for FTM_CnSC_ELSB. */
Kojto 90:cb3d968589d8 559 #define BM_FTM_CnSC_ELSB (0x00000008U) /*!< Bit mask for FTM_CnSC_ELSB. */
Kojto 90:cb3d968589d8 560 #define BS_FTM_CnSC_ELSB (1U) /*!< Bit field size in bits for FTM_CnSC_ELSB. */
Kojto 90:cb3d968589d8 561
Kojto 90:cb3d968589d8 562 /*! @brief Read current value of the FTM_CnSC_ELSB field. */
Kojto 90:cb3d968589d8 563 #define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
Kojto 90:cb3d968589d8 564
Kojto 90:cb3d968589d8 565 /*! @brief Format value for bitfield FTM_CnSC_ELSB. */
Kojto 90:cb3d968589d8 566 #define BF_FTM_CnSC_ELSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB)
Kojto 90:cb3d968589d8 567
Kojto 90:cb3d968589d8 568 /*! @brief Set the ELSB field to a new value. */
Kojto 90:cb3d968589d8 569 #define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
Kojto 90:cb3d968589d8 570 /*@}*/
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572 /*!
Kojto 90:cb3d968589d8 573 * @name Register FTM_CnSC, field MSA[4] (RW)
Kojto 90:cb3d968589d8 574 *
Kojto 90:cb3d968589d8 575 * Used for further selections in the channel logic. Its functionality is
Kojto 90:cb3d968589d8 576 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
Kojto 90:cb3d968589d8 577 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 578 */
Kojto 90:cb3d968589d8 579 /*@{*/
Kojto 90:cb3d968589d8 580 #define BP_FTM_CnSC_MSA (4U) /*!< Bit position for FTM_CnSC_MSA. */
Kojto 90:cb3d968589d8 581 #define BM_FTM_CnSC_MSA (0x00000010U) /*!< Bit mask for FTM_CnSC_MSA. */
Kojto 90:cb3d968589d8 582 #define BS_FTM_CnSC_MSA (1U) /*!< Bit field size in bits for FTM_CnSC_MSA. */
Kojto 90:cb3d968589d8 583
Kojto 90:cb3d968589d8 584 /*! @brief Read current value of the FTM_CnSC_MSA field. */
Kojto 90:cb3d968589d8 585 #define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
Kojto 90:cb3d968589d8 586
Kojto 90:cb3d968589d8 587 /*! @brief Format value for bitfield FTM_CnSC_MSA. */
Kojto 90:cb3d968589d8 588 #define BF_FTM_CnSC_MSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA)
Kojto 90:cb3d968589d8 589
Kojto 90:cb3d968589d8 590 /*! @brief Set the MSA field to a new value. */
Kojto 90:cb3d968589d8 591 #define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
Kojto 90:cb3d968589d8 592 /*@}*/
Kojto 90:cb3d968589d8 593
Kojto 90:cb3d968589d8 594 /*!
Kojto 90:cb3d968589d8 595 * @name Register FTM_CnSC, field MSB[5] (RW)
Kojto 90:cb3d968589d8 596 *
Kojto 90:cb3d968589d8 597 * Used for further selections in the channel logic. Its functionality is
Kojto 90:cb3d968589d8 598 * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
Kojto 90:cb3d968589d8 599 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 600 */
Kojto 90:cb3d968589d8 601 /*@{*/
Kojto 90:cb3d968589d8 602 #define BP_FTM_CnSC_MSB (5U) /*!< Bit position for FTM_CnSC_MSB. */
Kojto 90:cb3d968589d8 603 #define BM_FTM_CnSC_MSB (0x00000020U) /*!< Bit mask for FTM_CnSC_MSB. */
Kojto 90:cb3d968589d8 604 #define BS_FTM_CnSC_MSB (1U) /*!< Bit field size in bits for FTM_CnSC_MSB. */
Kojto 90:cb3d968589d8 605
Kojto 90:cb3d968589d8 606 /*! @brief Read current value of the FTM_CnSC_MSB field. */
Kojto 90:cb3d968589d8 607 #define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
Kojto 90:cb3d968589d8 608
Kojto 90:cb3d968589d8 609 /*! @brief Format value for bitfield FTM_CnSC_MSB. */
Kojto 90:cb3d968589d8 610 #define BF_FTM_CnSC_MSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB)
Kojto 90:cb3d968589d8 611
Kojto 90:cb3d968589d8 612 /*! @brief Set the MSB field to a new value. */
Kojto 90:cb3d968589d8 613 #define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
Kojto 90:cb3d968589d8 614 /*@}*/
Kojto 90:cb3d968589d8 615
Kojto 90:cb3d968589d8 616 /*!
Kojto 90:cb3d968589d8 617 * @name Register FTM_CnSC, field CHIE[6] (RW)
Kojto 90:cb3d968589d8 618 *
Kojto 90:cb3d968589d8 619 * Enables channel interrupts.
Kojto 90:cb3d968589d8 620 *
Kojto 90:cb3d968589d8 621 * Values:
Kojto 90:cb3d968589d8 622 * - 0 - Disable channel interrupts. Use software polling.
Kojto 90:cb3d968589d8 623 * - 1 - Enable channel interrupts.
Kojto 90:cb3d968589d8 624 */
Kojto 90:cb3d968589d8 625 /*@{*/
Kojto 90:cb3d968589d8 626 #define BP_FTM_CnSC_CHIE (6U) /*!< Bit position for FTM_CnSC_CHIE. */
Kojto 90:cb3d968589d8 627 #define BM_FTM_CnSC_CHIE (0x00000040U) /*!< Bit mask for FTM_CnSC_CHIE. */
Kojto 90:cb3d968589d8 628 #define BS_FTM_CnSC_CHIE (1U) /*!< Bit field size in bits for FTM_CnSC_CHIE. */
Kojto 90:cb3d968589d8 629
Kojto 90:cb3d968589d8 630 /*! @brief Read current value of the FTM_CnSC_CHIE field. */
Kojto 90:cb3d968589d8 631 #define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
Kojto 90:cb3d968589d8 632
Kojto 90:cb3d968589d8 633 /*! @brief Format value for bitfield FTM_CnSC_CHIE. */
Kojto 90:cb3d968589d8 634 #define BF_FTM_CnSC_CHIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE)
Kojto 90:cb3d968589d8 635
Kojto 90:cb3d968589d8 636 /*! @brief Set the CHIE field to a new value. */
Kojto 90:cb3d968589d8 637 #define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
Kojto 90:cb3d968589d8 638 /*@}*/
Kojto 90:cb3d968589d8 639
Kojto 90:cb3d968589d8 640 /*!
Kojto 90:cb3d968589d8 641 * @name Register FTM_CnSC, field CHF[7] (ROWZ)
Kojto 90:cb3d968589d8 642 *
Kojto 90:cb3d968589d8 643 * Set by hardware when an event occurs on the channel. CHF is cleared by
Kojto 90:cb3d968589d8 644 * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
Kojto 90:cb3d968589d8 645 * Writing a 1 to CHF has no effect. If another event occurs between the read and
Kojto 90:cb3d968589d8 646 * write operations, the write operation has no effect; therefore, CHF remains set
Kojto 90:cb3d968589d8 647 * indicating an event has occurred. In this case a CHF interrupt request is not
Kojto 90:cb3d968589d8 648 * lost due to the clearing sequence for a previous CHF.
Kojto 90:cb3d968589d8 649 *
Kojto 90:cb3d968589d8 650 * Values:
Kojto 90:cb3d968589d8 651 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 652 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 653 */
Kojto 90:cb3d968589d8 654 /*@{*/
Kojto 90:cb3d968589d8 655 #define BP_FTM_CnSC_CHF (7U) /*!< Bit position for FTM_CnSC_CHF. */
Kojto 90:cb3d968589d8 656 #define BM_FTM_CnSC_CHF (0x00000080U) /*!< Bit mask for FTM_CnSC_CHF. */
Kojto 90:cb3d968589d8 657 #define BS_FTM_CnSC_CHF (1U) /*!< Bit field size in bits for FTM_CnSC_CHF. */
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659 /*! @brief Read current value of the FTM_CnSC_CHF field. */
Kojto 90:cb3d968589d8 660 #define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
Kojto 90:cb3d968589d8 661
Kojto 90:cb3d968589d8 662 /*! @brief Format value for bitfield FTM_CnSC_CHF. */
Kojto 90:cb3d968589d8 663 #define BF_FTM_CnSC_CHF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF)
Kojto 90:cb3d968589d8 664
Kojto 90:cb3d968589d8 665 /*! @brief Set the CHF field to a new value. */
Kojto 90:cb3d968589d8 666 #define BW_FTM_CnSC_CHF(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF) = (v))
Kojto 90:cb3d968589d8 667 /*@}*/
Kojto 90:cb3d968589d8 668 /*******************************************************************************
Kojto 90:cb3d968589d8 669 * HW_FTM_CnV - Channel (n) Value
Kojto 90:cb3d968589d8 670 ******************************************************************************/
Kojto 90:cb3d968589d8 671
Kojto 90:cb3d968589d8 672 /*!
Kojto 90:cb3d968589d8 673 * @brief HW_FTM_CnV - Channel (n) Value (RW)
Kojto 90:cb3d968589d8 674 *
Kojto 90:cb3d968589d8 675 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 676 *
Kojto 90:cb3d968589d8 677 * These registers contain the captured FTM counter value for the input modes or
Kojto 90:cb3d968589d8 678 * the match value for the output modes. In Input Capture, Capture Test, and
Kojto 90:cb3d968589d8 679 * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
Kojto 90:cb3d968589d8 680 * writing to a CnV register latches the value into a buffer. A CnV register is
Kojto 90:cb3d968589d8 681 * updated with the value of its write buffer according to Registers updated from
Kojto 90:cb3d968589d8 682 * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
Kojto 90:cb3d968589d8 683 * reset by writing to the CnSC register whether BDM mode is active or not.
Kojto 90:cb3d968589d8 684 */
Kojto 90:cb3d968589d8 685 typedef union _hw_ftm_cnv
Kojto 90:cb3d968589d8 686 {
Kojto 90:cb3d968589d8 687 uint32_t U;
Kojto 90:cb3d968589d8 688 struct _hw_ftm_cnv_bitfields
Kojto 90:cb3d968589d8 689 {
Kojto 90:cb3d968589d8 690 uint32_t VAL : 16; /*!< [15:0] Channel Value */
Kojto 90:cb3d968589d8 691 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 692 } B;
Kojto 90:cb3d968589d8 693 } hw_ftm_cnv_t;
Kojto 90:cb3d968589d8 694
Kojto 90:cb3d968589d8 695 /*!
Kojto 90:cb3d968589d8 696 * @name Constants and macros for entire FTM_CnV register
Kojto 90:cb3d968589d8 697 */
Kojto 90:cb3d968589d8 698 /*@{*/
Kojto 90:cb3d968589d8 699 #define HW_FTM_CnV_COUNT (8U)
Kojto 90:cb3d968589d8 700
Kojto 90:cb3d968589d8 701 #define HW_FTM_CnV_ADDR(x, n) ((x) + 0x10U + (0x8U * (n)))
Kojto 90:cb3d968589d8 702
Kojto 90:cb3d968589d8 703 #define HW_FTM_CnV(x, n) (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
Kojto 90:cb3d968589d8 704 #define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
Kojto 90:cb3d968589d8 705 #define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
Kojto 90:cb3d968589d8 706 #define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 707 #define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 708 #define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 709 /*@}*/
Kojto 90:cb3d968589d8 710
Kojto 90:cb3d968589d8 711 /*
Kojto 90:cb3d968589d8 712 * Constants & macros for individual FTM_CnV bitfields
Kojto 90:cb3d968589d8 713 */
Kojto 90:cb3d968589d8 714
Kojto 90:cb3d968589d8 715 /*!
Kojto 90:cb3d968589d8 716 * @name Register FTM_CnV, field VAL[15:0] (RW)
Kojto 90:cb3d968589d8 717 *
Kojto 90:cb3d968589d8 718 * Captured FTM counter value of the input modes or the match value for the
Kojto 90:cb3d968589d8 719 * output modes
Kojto 90:cb3d968589d8 720 */
Kojto 90:cb3d968589d8 721 /*@{*/
Kojto 90:cb3d968589d8 722 #define BP_FTM_CnV_VAL (0U) /*!< Bit position for FTM_CnV_VAL. */
Kojto 90:cb3d968589d8 723 #define BM_FTM_CnV_VAL (0x0000FFFFU) /*!< Bit mask for FTM_CnV_VAL. */
Kojto 90:cb3d968589d8 724 #define BS_FTM_CnV_VAL (16U) /*!< Bit field size in bits for FTM_CnV_VAL. */
Kojto 90:cb3d968589d8 725
Kojto 90:cb3d968589d8 726 /*! @brief Read current value of the FTM_CnV_VAL field. */
Kojto 90:cb3d968589d8 727 #define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
Kojto 90:cb3d968589d8 728
Kojto 90:cb3d968589d8 729 /*! @brief Format value for bitfield FTM_CnV_VAL. */
Kojto 90:cb3d968589d8 730 #define BF_FTM_CnV_VAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL)
Kojto 90:cb3d968589d8 731
Kojto 90:cb3d968589d8 732 /*! @brief Set the VAL field to a new value. */
Kojto 90:cb3d968589d8 733 #define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
Kojto 90:cb3d968589d8 734 /*@}*/
Kojto 90:cb3d968589d8 735
Kojto 90:cb3d968589d8 736 /*******************************************************************************
Kojto 90:cb3d968589d8 737 * HW_FTM_CNTIN - Counter Initial Value
Kojto 90:cb3d968589d8 738 ******************************************************************************/
Kojto 90:cb3d968589d8 739
Kojto 90:cb3d968589d8 740 /*!
Kojto 90:cb3d968589d8 741 * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
Kojto 90:cb3d968589d8 742 *
Kojto 90:cb3d968589d8 743 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 744 *
Kojto 90:cb3d968589d8 745 * The Counter Initial Value register contains the initial value for the FTM
Kojto 90:cb3d968589d8 746 * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
Kojto 90:cb3d968589d8 747 * register is updated with the value of its write buffer according to Registers
Kojto 90:cb3d968589d8 748 * updated from write buffers. When the FTM clock is initially selected, by
Kojto 90:cb3d968589d8 749 * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
Kojto 90:cb3d968589d8 750 * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
Kojto 90:cb3d968589d8 751 * write the new value to the the CNTIN register and then initialize the FTM
Kojto 90:cb3d968589d8 752 * counter by writing any value to the CNT register.
Kojto 90:cb3d968589d8 753 */
Kojto 90:cb3d968589d8 754 typedef union _hw_ftm_cntin
Kojto 90:cb3d968589d8 755 {
Kojto 90:cb3d968589d8 756 uint32_t U;
Kojto 90:cb3d968589d8 757 struct _hw_ftm_cntin_bitfields
Kojto 90:cb3d968589d8 758 {
Kojto 90:cb3d968589d8 759 uint32_t INIT : 16; /*!< [15:0] */
Kojto 90:cb3d968589d8 760 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 761 } B;
Kojto 90:cb3d968589d8 762 } hw_ftm_cntin_t;
Kojto 90:cb3d968589d8 763
Kojto 90:cb3d968589d8 764 /*!
Kojto 90:cb3d968589d8 765 * @name Constants and macros for entire FTM_CNTIN register
Kojto 90:cb3d968589d8 766 */
Kojto 90:cb3d968589d8 767 /*@{*/
Kojto 90:cb3d968589d8 768 #define HW_FTM_CNTIN_ADDR(x) ((x) + 0x4CU)
Kojto 90:cb3d968589d8 769
Kojto 90:cb3d968589d8 770 #define HW_FTM_CNTIN(x) (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
Kojto 90:cb3d968589d8 771 #define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
Kojto 90:cb3d968589d8 772 #define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
Kojto 90:cb3d968589d8 773 #define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) | (v)))
Kojto 90:cb3d968589d8 774 #define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 775 #define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 776 /*@}*/
Kojto 90:cb3d968589d8 777
Kojto 90:cb3d968589d8 778 /*
Kojto 90:cb3d968589d8 779 * Constants & macros for individual FTM_CNTIN bitfields
Kojto 90:cb3d968589d8 780 */
Kojto 90:cb3d968589d8 781
Kojto 90:cb3d968589d8 782 /*!
Kojto 90:cb3d968589d8 783 * @name Register FTM_CNTIN, field INIT[15:0] (RW)
Kojto 90:cb3d968589d8 784 *
Kojto 90:cb3d968589d8 785 * Initial Value Of The FTM Counter
Kojto 90:cb3d968589d8 786 */
Kojto 90:cb3d968589d8 787 /*@{*/
Kojto 90:cb3d968589d8 788 #define BP_FTM_CNTIN_INIT (0U) /*!< Bit position for FTM_CNTIN_INIT. */
Kojto 90:cb3d968589d8 789 #define BM_FTM_CNTIN_INIT (0x0000FFFFU) /*!< Bit mask for FTM_CNTIN_INIT. */
Kojto 90:cb3d968589d8 790 #define BS_FTM_CNTIN_INIT (16U) /*!< Bit field size in bits for FTM_CNTIN_INIT. */
Kojto 90:cb3d968589d8 791
Kojto 90:cb3d968589d8 792 /*! @brief Read current value of the FTM_CNTIN_INIT field. */
Kojto 90:cb3d968589d8 793 #define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
Kojto 90:cb3d968589d8 794
Kojto 90:cb3d968589d8 795 /*! @brief Format value for bitfield FTM_CNTIN_INIT. */
Kojto 90:cb3d968589d8 796 #define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT)
Kojto 90:cb3d968589d8 797
Kojto 90:cb3d968589d8 798 /*! @brief Set the INIT field to a new value. */
Kojto 90:cb3d968589d8 799 #define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
Kojto 90:cb3d968589d8 800 /*@}*/
Kojto 90:cb3d968589d8 801
Kojto 90:cb3d968589d8 802 /*******************************************************************************
Kojto 90:cb3d968589d8 803 * HW_FTM_STATUS - Capture And Compare Status
Kojto 90:cb3d968589d8 804 ******************************************************************************/
Kojto 90:cb3d968589d8 805
Kojto 90:cb3d968589d8 806 /*!
Kojto 90:cb3d968589d8 807 * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
Kojto 90:cb3d968589d8 808 *
Kojto 90:cb3d968589d8 809 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 810 *
Kojto 90:cb3d968589d8 811 * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
Kojto 90:cb3d968589d8 812 * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
Kojto 90:cb3d968589d8 813 * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
Kojto 90:cb3d968589d8 814 * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
Kojto 90:cb3d968589d8 815 * STATUS. Hardware sets the individual channel flags when an event occurs on the
Kojto 90:cb3d968589d8 816 * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
Kojto 90:cb3d968589d8 817 * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
Kojto 90:cb3d968589d8 818 * occurs between the read and write operations, the write operation has no effect;
Kojto 90:cb3d968589d8 819 * therefore, CHnF remains set indicating an event has occurred. In this case, a
Kojto 90:cb3d968589d8 820 * CHnF interrupt request is not lost due to the clearing sequence for a previous
Kojto 90:cb3d968589d8 821 * CHnF. The STATUS register should be used only in Combine mode.
Kojto 90:cb3d968589d8 822 */
Kojto 90:cb3d968589d8 823 typedef union _hw_ftm_status
Kojto 90:cb3d968589d8 824 {
Kojto 90:cb3d968589d8 825 uint32_t U;
Kojto 90:cb3d968589d8 826 struct _hw_ftm_status_bitfields
Kojto 90:cb3d968589d8 827 {
Kojto 90:cb3d968589d8 828 uint32_t CH0F : 1; /*!< [0] Channel 0 Flag */
Kojto 90:cb3d968589d8 829 uint32_t CH1F : 1; /*!< [1] Channel 1 Flag */
Kojto 90:cb3d968589d8 830 uint32_t CH2F : 1; /*!< [2] Channel 2 Flag */
Kojto 90:cb3d968589d8 831 uint32_t CH3F : 1; /*!< [3] Channel 3 Flag */
Kojto 90:cb3d968589d8 832 uint32_t CH4F : 1; /*!< [4] Channel 4 Flag */
Kojto 90:cb3d968589d8 833 uint32_t CH5F : 1; /*!< [5] Channel 5 Flag */
Kojto 90:cb3d968589d8 834 uint32_t CH6F : 1; /*!< [6] Channel 6 Flag */
Kojto 90:cb3d968589d8 835 uint32_t CH7F : 1; /*!< [7] Channel 7 Flag */
Kojto 90:cb3d968589d8 836 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 837 } B;
Kojto 90:cb3d968589d8 838 } hw_ftm_status_t;
Kojto 90:cb3d968589d8 839
Kojto 90:cb3d968589d8 840 /*!
Kojto 90:cb3d968589d8 841 * @name Constants and macros for entire FTM_STATUS register
Kojto 90:cb3d968589d8 842 */
Kojto 90:cb3d968589d8 843 /*@{*/
Kojto 90:cb3d968589d8 844 #define HW_FTM_STATUS_ADDR(x) ((x) + 0x50U)
Kojto 90:cb3d968589d8 845
Kojto 90:cb3d968589d8 846 #define HW_FTM_STATUS(x) (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
Kojto 90:cb3d968589d8 847 #define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
Kojto 90:cb3d968589d8 848 #define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
Kojto 90:cb3d968589d8 849 #define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) | (v)))
Kojto 90:cb3d968589d8 850 #define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 851 #define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 852 /*@}*/
Kojto 90:cb3d968589d8 853
Kojto 90:cb3d968589d8 854 /*
Kojto 90:cb3d968589d8 855 * Constants & macros for individual FTM_STATUS bitfields
Kojto 90:cb3d968589d8 856 */
Kojto 90:cb3d968589d8 857
Kojto 90:cb3d968589d8 858 /*!
Kojto 90:cb3d968589d8 859 * @name Register FTM_STATUS, field CH0F[0] (W1C)
Kojto 90:cb3d968589d8 860 *
Kojto 90:cb3d968589d8 861 * See the register description.
Kojto 90:cb3d968589d8 862 *
Kojto 90:cb3d968589d8 863 * Values:
Kojto 90:cb3d968589d8 864 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 865 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 866 */
Kojto 90:cb3d968589d8 867 /*@{*/
Kojto 90:cb3d968589d8 868 #define BP_FTM_STATUS_CH0F (0U) /*!< Bit position for FTM_STATUS_CH0F. */
Kojto 90:cb3d968589d8 869 #define BM_FTM_STATUS_CH0F (0x00000001U) /*!< Bit mask for FTM_STATUS_CH0F. */
Kojto 90:cb3d968589d8 870 #define BS_FTM_STATUS_CH0F (1U) /*!< Bit field size in bits for FTM_STATUS_CH0F. */
Kojto 90:cb3d968589d8 871
Kojto 90:cb3d968589d8 872 /*! @brief Read current value of the FTM_STATUS_CH0F field. */
Kojto 90:cb3d968589d8 873 #define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
Kojto 90:cb3d968589d8 874
Kojto 90:cb3d968589d8 875 /*! @brief Format value for bitfield FTM_STATUS_CH0F. */
Kojto 90:cb3d968589d8 876 #define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F)
Kojto 90:cb3d968589d8 877
Kojto 90:cb3d968589d8 878 /*! @brief Set the CH0F field to a new value. */
Kojto 90:cb3d968589d8 879 #define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
Kojto 90:cb3d968589d8 880 /*@}*/
Kojto 90:cb3d968589d8 881
Kojto 90:cb3d968589d8 882 /*!
Kojto 90:cb3d968589d8 883 * @name Register FTM_STATUS, field CH1F[1] (W1C)
Kojto 90:cb3d968589d8 884 *
Kojto 90:cb3d968589d8 885 * See the register description.
Kojto 90:cb3d968589d8 886 *
Kojto 90:cb3d968589d8 887 * Values:
Kojto 90:cb3d968589d8 888 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 889 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 890 */
Kojto 90:cb3d968589d8 891 /*@{*/
Kojto 90:cb3d968589d8 892 #define BP_FTM_STATUS_CH1F (1U) /*!< Bit position for FTM_STATUS_CH1F. */
Kojto 90:cb3d968589d8 893 #define BM_FTM_STATUS_CH1F (0x00000002U) /*!< Bit mask for FTM_STATUS_CH1F. */
Kojto 90:cb3d968589d8 894 #define BS_FTM_STATUS_CH1F (1U) /*!< Bit field size in bits for FTM_STATUS_CH1F. */
Kojto 90:cb3d968589d8 895
Kojto 90:cb3d968589d8 896 /*! @brief Read current value of the FTM_STATUS_CH1F field. */
Kojto 90:cb3d968589d8 897 #define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
Kojto 90:cb3d968589d8 898
Kojto 90:cb3d968589d8 899 /*! @brief Format value for bitfield FTM_STATUS_CH1F. */
Kojto 90:cb3d968589d8 900 #define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F)
Kojto 90:cb3d968589d8 901
Kojto 90:cb3d968589d8 902 /*! @brief Set the CH1F field to a new value. */
Kojto 90:cb3d968589d8 903 #define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
Kojto 90:cb3d968589d8 904 /*@}*/
Kojto 90:cb3d968589d8 905
Kojto 90:cb3d968589d8 906 /*!
Kojto 90:cb3d968589d8 907 * @name Register FTM_STATUS, field CH2F[2] (W1C)
Kojto 90:cb3d968589d8 908 *
Kojto 90:cb3d968589d8 909 * See the register description.
Kojto 90:cb3d968589d8 910 *
Kojto 90:cb3d968589d8 911 * Values:
Kojto 90:cb3d968589d8 912 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 913 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 914 */
Kojto 90:cb3d968589d8 915 /*@{*/
Kojto 90:cb3d968589d8 916 #define BP_FTM_STATUS_CH2F (2U) /*!< Bit position for FTM_STATUS_CH2F. */
Kojto 90:cb3d968589d8 917 #define BM_FTM_STATUS_CH2F (0x00000004U) /*!< Bit mask for FTM_STATUS_CH2F. */
Kojto 90:cb3d968589d8 918 #define BS_FTM_STATUS_CH2F (1U) /*!< Bit field size in bits for FTM_STATUS_CH2F. */
Kojto 90:cb3d968589d8 919
Kojto 90:cb3d968589d8 920 /*! @brief Read current value of the FTM_STATUS_CH2F field. */
Kojto 90:cb3d968589d8 921 #define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
Kojto 90:cb3d968589d8 922
Kojto 90:cb3d968589d8 923 /*! @brief Format value for bitfield FTM_STATUS_CH2F. */
Kojto 90:cb3d968589d8 924 #define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F)
Kojto 90:cb3d968589d8 925
Kojto 90:cb3d968589d8 926 /*! @brief Set the CH2F field to a new value. */
Kojto 90:cb3d968589d8 927 #define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
Kojto 90:cb3d968589d8 928 /*@}*/
Kojto 90:cb3d968589d8 929
Kojto 90:cb3d968589d8 930 /*!
Kojto 90:cb3d968589d8 931 * @name Register FTM_STATUS, field CH3F[3] (W1C)
Kojto 90:cb3d968589d8 932 *
Kojto 90:cb3d968589d8 933 * See the register description.
Kojto 90:cb3d968589d8 934 *
Kojto 90:cb3d968589d8 935 * Values:
Kojto 90:cb3d968589d8 936 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 937 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 938 */
Kojto 90:cb3d968589d8 939 /*@{*/
Kojto 90:cb3d968589d8 940 #define BP_FTM_STATUS_CH3F (3U) /*!< Bit position for FTM_STATUS_CH3F. */
Kojto 90:cb3d968589d8 941 #define BM_FTM_STATUS_CH3F (0x00000008U) /*!< Bit mask for FTM_STATUS_CH3F. */
Kojto 90:cb3d968589d8 942 #define BS_FTM_STATUS_CH3F (1U) /*!< Bit field size in bits for FTM_STATUS_CH3F. */
Kojto 90:cb3d968589d8 943
Kojto 90:cb3d968589d8 944 /*! @brief Read current value of the FTM_STATUS_CH3F field. */
Kojto 90:cb3d968589d8 945 #define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
Kojto 90:cb3d968589d8 946
Kojto 90:cb3d968589d8 947 /*! @brief Format value for bitfield FTM_STATUS_CH3F. */
Kojto 90:cb3d968589d8 948 #define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F)
Kojto 90:cb3d968589d8 949
Kojto 90:cb3d968589d8 950 /*! @brief Set the CH3F field to a new value. */
Kojto 90:cb3d968589d8 951 #define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
Kojto 90:cb3d968589d8 952 /*@}*/
Kojto 90:cb3d968589d8 953
Kojto 90:cb3d968589d8 954 /*!
Kojto 90:cb3d968589d8 955 * @name Register FTM_STATUS, field CH4F[4] (W1C)
Kojto 90:cb3d968589d8 956 *
Kojto 90:cb3d968589d8 957 * See the register description.
Kojto 90:cb3d968589d8 958 *
Kojto 90:cb3d968589d8 959 * Values:
Kojto 90:cb3d968589d8 960 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 961 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 962 */
Kojto 90:cb3d968589d8 963 /*@{*/
Kojto 90:cb3d968589d8 964 #define BP_FTM_STATUS_CH4F (4U) /*!< Bit position for FTM_STATUS_CH4F. */
Kojto 90:cb3d968589d8 965 #define BM_FTM_STATUS_CH4F (0x00000010U) /*!< Bit mask for FTM_STATUS_CH4F. */
Kojto 90:cb3d968589d8 966 #define BS_FTM_STATUS_CH4F (1U) /*!< Bit field size in bits for FTM_STATUS_CH4F. */
Kojto 90:cb3d968589d8 967
Kojto 90:cb3d968589d8 968 /*! @brief Read current value of the FTM_STATUS_CH4F field. */
Kojto 90:cb3d968589d8 969 #define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
Kojto 90:cb3d968589d8 970
Kojto 90:cb3d968589d8 971 /*! @brief Format value for bitfield FTM_STATUS_CH4F. */
Kojto 90:cb3d968589d8 972 #define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F)
Kojto 90:cb3d968589d8 973
Kojto 90:cb3d968589d8 974 /*! @brief Set the CH4F field to a new value. */
Kojto 90:cb3d968589d8 975 #define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
Kojto 90:cb3d968589d8 976 /*@}*/
Kojto 90:cb3d968589d8 977
Kojto 90:cb3d968589d8 978 /*!
Kojto 90:cb3d968589d8 979 * @name Register FTM_STATUS, field CH5F[5] (W1C)
Kojto 90:cb3d968589d8 980 *
Kojto 90:cb3d968589d8 981 * See the register description.
Kojto 90:cb3d968589d8 982 *
Kojto 90:cb3d968589d8 983 * Values:
Kojto 90:cb3d968589d8 984 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 985 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 986 */
Kojto 90:cb3d968589d8 987 /*@{*/
Kojto 90:cb3d968589d8 988 #define BP_FTM_STATUS_CH5F (5U) /*!< Bit position for FTM_STATUS_CH5F. */
Kojto 90:cb3d968589d8 989 #define BM_FTM_STATUS_CH5F (0x00000020U) /*!< Bit mask for FTM_STATUS_CH5F. */
Kojto 90:cb3d968589d8 990 #define BS_FTM_STATUS_CH5F (1U) /*!< Bit field size in bits for FTM_STATUS_CH5F. */
Kojto 90:cb3d968589d8 991
Kojto 90:cb3d968589d8 992 /*! @brief Read current value of the FTM_STATUS_CH5F field. */
Kojto 90:cb3d968589d8 993 #define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
Kojto 90:cb3d968589d8 994
Kojto 90:cb3d968589d8 995 /*! @brief Format value for bitfield FTM_STATUS_CH5F. */
Kojto 90:cb3d968589d8 996 #define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F)
Kojto 90:cb3d968589d8 997
Kojto 90:cb3d968589d8 998 /*! @brief Set the CH5F field to a new value. */
Kojto 90:cb3d968589d8 999 #define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
Kojto 90:cb3d968589d8 1000 /*@}*/
Kojto 90:cb3d968589d8 1001
Kojto 90:cb3d968589d8 1002 /*!
Kojto 90:cb3d968589d8 1003 * @name Register FTM_STATUS, field CH6F[6] (W1C)
Kojto 90:cb3d968589d8 1004 *
Kojto 90:cb3d968589d8 1005 * See the register description.
Kojto 90:cb3d968589d8 1006 *
Kojto 90:cb3d968589d8 1007 * Values:
Kojto 90:cb3d968589d8 1008 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 1009 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 1010 */
Kojto 90:cb3d968589d8 1011 /*@{*/
Kojto 90:cb3d968589d8 1012 #define BP_FTM_STATUS_CH6F (6U) /*!< Bit position for FTM_STATUS_CH6F. */
Kojto 90:cb3d968589d8 1013 #define BM_FTM_STATUS_CH6F (0x00000040U) /*!< Bit mask for FTM_STATUS_CH6F. */
Kojto 90:cb3d968589d8 1014 #define BS_FTM_STATUS_CH6F (1U) /*!< Bit field size in bits for FTM_STATUS_CH6F. */
Kojto 90:cb3d968589d8 1015
Kojto 90:cb3d968589d8 1016 /*! @brief Read current value of the FTM_STATUS_CH6F field. */
Kojto 90:cb3d968589d8 1017 #define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
Kojto 90:cb3d968589d8 1018
Kojto 90:cb3d968589d8 1019 /*! @brief Format value for bitfield FTM_STATUS_CH6F. */
Kojto 90:cb3d968589d8 1020 #define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F)
Kojto 90:cb3d968589d8 1021
Kojto 90:cb3d968589d8 1022 /*! @brief Set the CH6F field to a new value. */
Kojto 90:cb3d968589d8 1023 #define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
Kojto 90:cb3d968589d8 1024 /*@}*/
Kojto 90:cb3d968589d8 1025
Kojto 90:cb3d968589d8 1026 /*!
Kojto 90:cb3d968589d8 1027 * @name Register FTM_STATUS, field CH7F[7] (W1C)
Kojto 90:cb3d968589d8 1028 *
Kojto 90:cb3d968589d8 1029 * See the register description.
Kojto 90:cb3d968589d8 1030 *
Kojto 90:cb3d968589d8 1031 * Values:
Kojto 90:cb3d968589d8 1032 * - 0 - No channel event has occurred.
Kojto 90:cb3d968589d8 1033 * - 1 - A channel event has occurred.
Kojto 90:cb3d968589d8 1034 */
Kojto 90:cb3d968589d8 1035 /*@{*/
Kojto 90:cb3d968589d8 1036 #define BP_FTM_STATUS_CH7F (7U) /*!< Bit position for FTM_STATUS_CH7F. */
Kojto 90:cb3d968589d8 1037 #define BM_FTM_STATUS_CH7F (0x00000080U) /*!< Bit mask for FTM_STATUS_CH7F. */
Kojto 90:cb3d968589d8 1038 #define BS_FTM_STATUS_CH7F (1U) /*!< Bit field size in bits for FTM_STATUS_CH7F. */
Kojto 90:cb3d968589d8 1039
Kojto 90:cb3d968589d8 1040 /*! @brief Read current value of the FTM_STATUS_CH7F field. */
Kojto 90:cb3d968589d8 1041 #define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
Kojto 90:cb3d968589d8 1042
Kojto 90:cb3d968589d8 1043 /*! @brief Format value for bitfield FTM_STATUS_CH7F. */
Kojto 90:cb3d968589d8 1044 #define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F)
Kojto 90:cb3d968589d8 1045
Kojto 90:cb3d968589d8 1046 /*! @brief Set the CH7F field to a new value. */
Kojto 90:cb3d968589d8 1047 #define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
Kojto 90:cb3d968589d8 1048 /*@}*/
Kojto 90:cb3d968589d8 1049
Kojto 90:cb3d968589d8 1050 /*******************************************************************************
Kojto 90:cb3d968589d8 1051 * HW_FTM_MODE - Features Mode Selection
Kojto 90:cb3d968589d8 1052 ******************************************************************************/
Kojto 90:cb3d968589d8 1053
Kojto 90:cb3d968589d8 1054 /*!
Kojto 90:cb3d968589d8 1055 * @brief HW_FTM_MODE - Features Mode Selection (RW)
Kojto 90:cb3d968589d8 1056 *
Kojto 90:cb3d968589d8 1057 * Reset value: 0x00000004U
Kojto 90:cb3d968589d8 1058 *
Kojto 90:cb3d968589d8 1059 * This register contains the global enable bit for FTM-specific features and
Kojto 90:cb3d968589d8 1060 * the control bits used to configure: Fault control mode and interrupt Capture
Kojto 90:cb3d968589d8 1061 * Test mode PWM synchronization Write protection Channel output initialization
Kojto 90:cb3d968589d8 1062 * These controls relate to all channels within this module.
Kojto 90:cb3d968589d8 1063 */
Kojto 90:cb3d968589d8 1064 typedef union _hw_ftm_mode
Kojto 90:cb3d968589d8 1065 {
Kojto 90:cb3d968589d8 1066 uint32_t U;
Kojto 90:cb3d968589d8 1067 struct _hw_ftm_mode_bitfields
Kojto 90:cb3d968589d8 1068 {
Kojto 90:cb3d968589d8 1069 uint32_t FTMEN : 1; /*!< [0] FTM Enable */
Kojto 90:cb3d968589d8 1070 uint32_t INIT : 1; /*!< [1] Initialize The Channels Output */
Kojto 90:cb3d968589d8 1071 uint32_t WPDIS : 1; /*!< [2] Write Protection Disable */
Kojto 90:cb3d968589d8 1072 uint32_t PWMSYNC : 1; /*!< [3] PWM Synchronization Mode */
Kojto 90:cb3d968589d8 1073 uint32_t CAPTEST : 1; /*!< [4] Capture Test Mode Enable */
Kojto 90:cb3d968589d8 1074 uint32_t FAULTM : 2; /*!< [6:5] Fault Control Mode */
Kojto 90:cb3d968589d8 1075 uint32_t FAULTIE : 1; /*!< [7] Fault Interrupt Enable */
Kojto 90:cb3d968589d8 1076 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 1077 } B;
Kojto 90:cb3d968589d8 1078 } hw_ftm_mode_t;
Kojto 90:cb3d968589d8 1079
Kojto 90:cb3d968589d8 1080 /*!
Kojto 90:cb3d968589d8 1081 * @name Constants and macros for entire FTM_MODE register
Kojto 90:cb3d968589d8 1082 */
Kojto 90:cb3d968589d8 1083 /*@{*/
Kojto 90:cb3d968589d8 1084 #define HW_FTM_MODE_ADDR(x) ((x) + 0x54U)
Kojto 90:cb3d968589d8 1085
Kojto 90:cb3d968589d8 1086 #define HW_FTM_MODE(x) (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
Kojto 90:cb3d968589d8 1087 #define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
Kojto 90:cb3d968589d8 1088 #define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
Kojto 90:cb3d968589d8 1089 #define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) | (v)))
Kojto 90:cb3d968589d8 1090 #define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1091 #define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1092 /*@}*/
Kojto 90:cb3d968589d8 1093
Kojto 90:cb3d968589d8 1094 /*
Kojto 90:cb3d968589d8 1095 * Constants & macros for individual FTM_MODE bitfields
Kojto 90:cb3d968589d8 1096 */
Kojto 90:cb3d968589d8 1097
Kojto 90:cb3d968589d8 1098 /*!
Kojto 90:cb3d968589d8 1099 * @name Register FTM_MODE, field FTMEN[0] (RW)
Kojto 90:cb3d968589d8 1100 *
Kojto 90:cb3d968589d8 1101 * This field is write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 1102 *
Kojto 90:cb3d968589d8 1103 * Values:
Kojto 90:cb3d968589d8 1104 * - 0 - Only the TPM-compatible registers (first set of registers) can be used
Kojto 90:cb3d968589d8 1105 * without any restriction. Do not use the FTM-specific registers.
Kojto 90:cb3d968589d8 1106 * - 1 - All registers including the FTM-specific registers (second set of
Kojto 90:cb3d968589d8 1107 * registers) are available for use with no restrictions.
Kojto 90:cb3d968589d8 1108 */
Kojto 90:cb3d968589d8 1109 /*@{*/
Kojto 90:cb3d968589d8 1110 #define BP_FTM_MODE_FTMEN (0U) /*!< Bit position for FTM_MODE_FTMEN. */
Kojto 90:cb3d968589d8 1111 #define BM_FTM_MODE_FTMEN (0x00000001U) /*!< Bit mask for FTM_MODE_FTMEN. */
Kojto 90:cb3d968589d8 1112 #define BS_FTM_MODE_FTMEN (1U) /*!< Bit field size in bits for FTM_MODE_FTMEN. */
Kojto 90:cb3d968589d8 1113
Kojto 90:cb3d968589d8 1114 /*! @brief Read current value of the FTM_MODE_FTMEN field. */
Kojto 90:cb3d968589d8 1115 #define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
Kojto 90:cb3d968589d8 1116
Kojto 90:cb3d968589d8 1117 /*! @brief Format value for bitfield FTM_MODE_FTMEN. */
Kojto 90:cb3d968589d8 1118 #define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN)
Kojto 90:cb3d968589d8 1119
Kojto 90:cb3d968589d8 1120 /*! @brief Set the FTMEN field to a new value. */
Kojto 90:cb3d968589d8 1121 #define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
Kojto 90:cb3d968589d8 1122 /*@}*/
Kojto 90:cb3d968589d8 1123
Kojto 90:cb3d968589d8 1124 /*!
Kojto 90:cb3d968589d8 1125 * @name Register FTM_MODE, field INIT[1] (RW)
Kojto 90:cb3d968589d8 1126 *
Kojto 90:cb3d968589d8 1127 * When a 1 is written to INIT bit the channels output is initialized according
Kojto 90:cb3d968589d8 1128 * to the state of their corresponding bit in the OUTINIT register. Writing a 0
Kojto 90:cb3d968589d8 1129 * to INIT bit has no effect. The INIT bit is always read as 0.
Kojto 90:cb3d968589d8 1130 */
Kojto 90:cb3d968589d8 1131 /*@{*/
Kojto 90:cb3d968589d8 1132 #define BP_FTM_MODE_INIT (1U) /*!< Bit position for FTM_MODE_INIT. */
Kojto 90:cb3d968589d8 1133 #define BM_FTM_MODE_INIT (0x00000002U) /*!< Bit mask for FTM_MODE_INIT. */
Kojto 90:cb3d968589d8 1134 #define BS_FTM_MODE_INIT (1U) /*!< Bit field size in bits for FTM_MODE_INIT. */
Kojto 90:cb3d968589d8 1135
Kojto 90:cb3d968589d8 1136 /*! @brief Read current value of the FTM_MODE_INIT field. */
Kojto 90:cb3d968589d8 1137 #define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
Kojto 90:cb3d968589d8 1138
Kojto 90:cb3d968589d8 1139 /*! @brief Format value for bitfield FTM_MODE_INIT. */
Kojto 90:cb3d968589d8 1140 #define BF_FTM_MODE_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT)
Kojto 90:cb3d968589d8 1141
Kojto 90:cb3d968589d8 1142 /*! @brief Set the INIT field to a new value. */
Kojto 90:cb3d968589d8 1143 #define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
Kojto 90:cb3d968589d8 1144 /*@}*/
Kojto 90:cb3d968589d8 1145
Kojto 90:cb3d968589d8 1146 /*!
Kojto 90:cb3d968589d8 1147 * @name Register FTM_MODE, field WPDIS[2] (RW)
Kojto 90:cb3d968589d8 1148 *
Kojto 90:cb3d968589d8 1149 * When write protection is enabled (WPDIS = 0), write protected bits cannot be
Kojto 90:cb3d968589d8 1150 * written. When write protection is disabled (WPDIS = 1), write protected bits
Kojto 90:cb3d968589d8 1151 * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
Kojto 90:cb3d968589d8 1152 * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
Kojto 90:cb3d968589d8 1153 * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
Kojto 90:cb3d968589d8 1154 *
Kojto 90:cb3d968589d8 1155 * Values:
Kojto 90:cb3d968589d8 1156 * - 0 - Write protection is enabled.
Kojto 90:cb3d968589d8 1157 * - 1 - Write protection is disabled.
Kojto 90:cb3d968589d8 1158 */
Kojto 90:cb3d968589d8 1159 /*@{*/
Kojto 90:cb3d968589d8 1160 #define BP_FTM_MODE_WPDIS (2U) /*!< Bit position for FTM_MODE_WPDIS. */
Kojto 90:cb3d968589d8 1161 #define BM_FTM_MODE_WPDIS (0x00000004U) /*!< Bit mask for FTM_MODE_WPDIS. */
Kojto 90:cb3d968589d8 1162 #define BS_FTM_MODE_WPDIS (1U) /*!< Bit field size in bits for FTM_MODE_WPDIS. */
Kojto 90:cb3d968589d8 1163
Kojto 90:cb3d968589d8 1164 /*! @brief Read current value of the FTM_MODE_WPDIS field. */
Kojto 90:cb3d968589d8 1165 #define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
Kojto 90:cb3d968589d8 1166
Kojto 90:cb3d968589d8 1167 /*! @brief Format value for bitfield FTM_MODE_WPDIS. */
Kojto 90:cb3d968589d8 1168 #define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS)
Kojto 90:cb3d968589d8 1169
Kojto 90:cb3d968589d8 1170 /*! @brief Set the WPDIS field to a new value. */
Kojto 90:cb3d968589d8 1171 #define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
Kojto 90:cb3d968589d8 1172 /*@}*/
Kojto 90:cb3d968589d8 1173
Kojto 90:cb3d968589d8 1174 /*!
Kojto 90:cb3d968589d8 1175 * @name Register FTM_MODE, field PWMSYNC[3] (RW)
Kojto 90:cb3d968589d8 1176 *
Kojto 90:cb3d968589d8 1177 * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
Kojto 90:cb3d968589d8 1178 * synchronization. See PWM synchronization. The PWMSYNC bit configures the
Kojto 90:cb3d968589d8 1179 * synchronization when SYNCMODE is 0.
Kojto 90:cb3d968589d8 1180 *
Kojto 90:cb3d968589d8 1181 * Values:
Kojto 90:cb3d968589d8 1182 * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
Kojto 90:cb3d968589d8 1183 * CnV, OUTMASK, and FTM counter synchronization.
Kojto 90:cb3d968589d8 1184 * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
Kojto 90:cb3d968589d8 1185 * hardware triggers can only be used by OUTMASK and FTM counter
Kojto 90:cb3d968589d8 1186 * synchronization.
Kojto 90:cb3d968589d8 1187 */
Kojto 90:cb3d968589d8 1188 /*@{*/
Kojto 90:cb3d968589d8 1189 #define BP_FTM_MODE_PWMSYNC (3U) /*!< Bit position for FTM_MODE_PWMSYNC. */
Kojto 90:cb3d968589d8 1190 #define BM_FTM_MODE_PWMSYNC (0x00000008U) /*!< Bit mask for FTM_MODE_PWMSYNC. */
Kojto 90:cb3d968589d8 1191 #define BS_FTM_MODE_PWMSYNC (1U) /*!< Bit field size in bits for FTM_MODE_PWMSYNC. */
Kojto 90:cb3d968589d8 1192
Kojto 90:cb3d968589d8 1193 /*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
Kojto 90:cb3d968589d8 1194 #define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
Kojto 90:cb3d968589d8 1195
Kojto 90:cb3d968589d8 1196 /*! @brief Format value for bitfield FTM_MODE_PWMSYNC. */
Kojto 90:cb3d968589d8 1197 #define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC)
Kojto 90:cb3d968589d8 1198
Kojto 90:cb3d968589d8 1199 /*! @brief Set the PWMSYNC field to a new value. */
Kojto 90:cb3d968589d8 1200 #define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
Kojto 90:cb3d968589d8 1201 /*@}*/
Kojto 90:cb3d968589d8 1202
Kojto 90:cb3d968589d8 1203 /*!
Kojto 90:cb3d968589d8 1204 * @name Register FTM_MODE, field CAPTEST[4] (RW)
Kojto 90:cb3d968589d8 1205 *
Kojto 90:cb3d968589d8 1206 * Enables the capture test mode. This field is write protected. It can be
Kojto 90:cb3d968589d8 1207 * written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 1208 *
Kojto 90:cb3d968589d8 1209 * Values:
Kojto 90:cb3d968589d8 1210 * - 0 - Capture test mode is disabled.
Kojto 90:cb3d968589d8 1211 * - 1 - Capture test mode is enabled.
Kojto 90:cb3d968589d8 1212 */
Kojto 90:cb3d968589d8 1213 /*@{*/
Kojto 90:cb3d968589d8 1214 #define BP_FTM_MODE_CAPTEST (4U) /*!< Bit position for FTM_MODE_CAPTEST. */
Kojto 90:cb3d968589d8 1215 #define BM_FTM_MODE_CAPTEST (0x00000010U) /*!< Bit mask for FTM_MODE_CAPTEST. */
Kojto 90:cb3d968589d8 1216 #define BS_FTM_MODE_CAPTEST (1U) /*!< Bit field size in bits for FTM_MODE_CAPTEST. */
Kojto 90:cb3d968589d8 1217
Kojto 90:cb3d968589d8 1218 /*! @brief Read current value of the FTM_MODE_CAPTEST field. */
Kojto 90:cb3d968589d8 1219 #define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
Kojto 90:cb3d968589d8 1220
Kojto 90:cb3d968589d8 1221 /*! @brief Format value for bitfield FTM_MODE_CAPTEST. */
Kojto 90:cb3d968589d8 1222 #define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST)
Kojto 90:cb3d968589d8 1223
Kojto 90:cb3d968589d8 1224 /*! @brief Set the CAPTEST field to a new value. */
Kojto 90:cb3d968589d8 1225 #define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
Kojto 90:cb3d968589d8 1226 /*@}*/
Kojto 90:cb3d968589d8 1227
Kojto 90:cb3d968589d8 1228 /*!
Kojto 90:cb3d968589d8 1229 * @name Register FTM_MODE, field FAULTM[6:5] (RW)
Kojto 90:cb3d968589d8 1230 *
Kojto 90:cb3d968589d8 1231 * Defines the FTM fault control mode. This field is write protected. It can be
Kojto 90:cb3d968589d8 1232 * written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 1233 *
Kojto 90:cb3d968589d8 1234 * Values:
Kojto 90:cb3d968589d8 1235 * - 00 - Fault control is disabled for all channels.
Kojto 90:cb3d968589d8 1236 * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
Kojto 90:cb3d968589d8 1237 * 6), and the selected mode is the manual fault clearing.
Kojto 90:cb3d968589d8 1238 * - 10 - Fault control is enabled for all channels, and the selected mode is
Kojto 90:cb3d968589d8 1239 * the manual fault clearing.
Kojto 90:cb3d968589d8 1240 * - 11 - Fault control is enabled for all channels, and the selected mode is
Kojto 90:cb3d968589d8 1241 * the automatic fault clearing.
Kojto 90:cb3d968589d8 1242 */
Kojto 90:cb3d968589d8 1243 /*@{*/
Kojto 90:cb3d968589d8 1244 #define BP_FTM_MODE_FAULTM (5U) /*!< Bit position for FTM_MODE_FAULTM. */
Kojto 90:cb3d968589d8 1245 #define BM_FTM_MODE_FAULTM (0x00000060U) /*!< Bit mask for FTM_MODE_FAULTM. */
Kojto 90:cb3d968589d8 1246 #define BS_FTM_MODE_FAULTM (2U) /*!< Bit field size in bits for FTM_MODE_FAULTM. */
Kojto 90:cb3d968589d8 1247
Kojto 90:cb3d968589d8 1248 /*! @brief Read current value of the FTM_MODE_FAULTM field. */
Kojto 90:cb3d968589d8 1249 #define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
Kojto 90:cb3d968589d8 1250
Kojto 90:cb3d968589d8 1251 /*! @brief Format value for bitfield FTM_MODE_FAULTM. */
Kojto 90:cb3d968589d8 1252 #define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM)
Kojto 90:cb3d968589d8 1253
Kojto 90:cb3d968589d8 1254 /*! @brief Set the FAULTM field to a new value. */
Kojto 90:cb3d968589d8 1255 #define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
Kojto 90:cb3d968589d8 1256 /*@}*/
Kojto 90:cb3d968589d8 1257
Kojto 90:cb3d968589d8 1258 /*!
Kojto 90:cb3d968589d8 1259 * @name Register FTM_MODE, field FAULTIE[7] (RW)
Kojto 90:cb3d968589d8 1260 *
Kojto 90:cb3d968589d8 1261 * Enables the generation of an interrupt when a fault is detected by FTM and
Kojto 90:cb3d968589d8 1262 * the FTM fault control is enabled.
Kojto 90:cb3d968589d8 1263 *
Kojto 90:cb3d968589d8 1264 * Values:
Kojto 90:cb3d968589d8 1265 * - 0 - Fault control interrupt is disabled.
Kojto 90:cb3d968589d8 1266 * - 1 - Fault control interrupt is enabled.
Kojto 90:cb3d968589d8 1267 */
Kojto 90:cb3d968589d8 1268 /*@{*/
Kojto 90:cb3d968589d8 1269 #define BP_FTM_MODE_FAULTIE (7U) /*!< Bit position for FTM_MODE_FAULTIE. */
Kojto 90:cb3d968589d8 1270 #define BM_FTM_MODE_FAULTIE (0x00000080U) /*!< Bit mask for FTM_MODE_FAULTIE. */
Kojto 90:cb3d968589d8 1271 #define BS_FTM_MODE_FAULTIE (1U) /*!< Bit field size in bits for FTM_MODE_FAULTIE. */
Kojto 90:cb3d968589d8 1272
Kojto 90:cb3d968589d8 1273 /*! @brief Read current value of the FTM_MODE_FAULTIE field. */
Kojto 90:cb3d968589d8 1274 #define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
Kojto 90:cb3d968589d8 1275
Kojto 90:cb3d968589d8 1276 /*! @brief Format value for bitfield FTM_MODE_FAULTIE. */
Kojto 90:cb3d968589d8 1277 #define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE)
Kojto 90:cb3d968589d8 1278
Kojto 90:cb3d968589d8 1279 /*! @brief Set the FAULTIE field to a new value. */
Kojto 90:cb3d968589d8 1280 #define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
Kojto 90:cb3d968589d8 1281 /*@}*/
Kojto 90:cb3d968589d8 1282
Kojto 90:cb3d968589d8 1283 /*******************************************************************************
Kojto 90:cb3d968589d8 1284 * HW_FTM_SYNC - Synchronization
Kojto 90:cb3d968589d8 1285 ******************************************************************************/
Kojto 90:cb3d968589d8 1286
Kojto 90:cb3d968589d8 1287 /*!
Kojto 90:cb3d968589d8 1288 * @brief HW_FTM_SYNC - Synchronization (RW)
Kojto 90:cb3d968589d8 1289 *
Kojto 90:cb3d968589d8 1290 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 1291 *
Kojto 90:cb3d968589d8 1292 * This register configures the PWM synchronization. A synchronization event can
Kojto 90:cb3d968589d8 1293 * perform the synchronized update of MOD, CV, and OUTMASK registers with the
Kojto 90:cb3d968589d8 1294 * value of their write buffer and the FTM counter initialization. The software
Kojto 90:cb3d968589d8 1295 * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
Kojto 90:cb3d968589d8 1296 * potential conflict if used together when SYNCMODE = 0. Use only hardware or
Kojto 90:cb3d968589d8 1297 * software triggers but not both at the same time, otherwise unpredictable behavior
Kojto 90:cb3d968589d8 1298 * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
Kojto 90:cb3d968589d8 1299 * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
Kojto 90:cb3d968589d8 1300 * all enabled channels simultaneously. The use of the loading point selection
Kojto 90:cb3d968589d8 1301 * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
Kojto 90:cb3d968589d8 1302 * bits, is likely to result in unpredictable behavior. The synchronization
Kojto 90:cb3d968589d8 1303 * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
Kojto 90:cb3d968589d8 1304 * register) bits. See PWM synchronization.
Kojto 90:cb3d968589d8 1305 */
Kojto 90:cb3d968589d8 1306 typedef union _hw_ftm_sync
Kojto 90:cb3d968589d8 1307 {
Kojto 90:cb3d968589d8 1308 uint32_t U;
Kojto 90:cb3d968589d8 1309 struct _hw_ftm_sync_bitfields
Kojto 90:cb3d968589d8 1310 {
Kojto 90:cb3d968589d8 1311 uint32_t CNTMIN : 1; /*!< [0] Minimum Loading Point Enable */
Kojto 90:cb3d968589d8 1312 uint32_t CNTMAX : 1; /*!< [1] Maximum Loading Point Enable */
Kojto 90:cb3d968589d8 1313 uint32_t REINIT : 1; /*!< [2] FTM Counter Reinitialization By
Kojto 90:cb3d968589d8 1314 * Synchronization (FTM counter synchronization) */
Kojto 90:cb3d968589d8 1315 uint32_t SYNCHOM : 1; /*!< [3] Output Mask Synchronization */
Kojto 90:cb3d968589d8 1316 uint32_t TRIG0 : 1; /*!< [4] PWM Synchronization Hardware Trigger 0 */
Kojto 90:cb3d968589d8 1317 uint32_t TRIG1 : 1; /*!< [5] PWM Synchronization Hardware Trigger 1 */
Kojto 90:cb3d968589d8 1318 uint32_t TRIG2 : 1; /*!< [6] PWM Synchronization Hardware Trigger 2 */
Kojto 90:cb3d968589d8 1319 uint32_t SWSYNC : 1; /*!< [7] PWM Synchronization Software Trigger */
Kojto 90:cb3d968589d8 1320 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 1321 } B;
Kojto 90:cb3d968589d8 1322 } hw_ftm_sync_t;
Kojto 90:cb3d968589d8 1323
Kojto 90:cb3d968589d8 1324 /*!
Kojto 90:cb3d968589d8 1325 * @name Constants and macros for entire FTM_SYNC register
Kojto 90:cb3d968589d8 1326 */
Kojto 90:cb3d968589d8 1327 /*@{*/
Kojto 90:cb3d968589d8 1328 #define HW_FTM_SYNC_ADDR(x) ((x) + 0x58U)
Kojto 90:cb3d968589d8 1329
Kojto 90:cb3d968589d8 1330 #define HW_FTM_SYNC(x) (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
Kojto 90:cb3d968589d8 1331 #define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
Kojto 90:cb3d968589d8 1332 #define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
Kojto 90:cb3d968589d8 1333 #define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) | (v)))
Kojto 90:cb3d968589d8 1334 #define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1335 #define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1336 /*@}*/
Kojto 90:cb3d968589d8 1337
Kojto 90:cb3d968589d8 1338 /*
Kojto 90:cb3d968589d8 1339 * Constants & macros for individual FTM_SYNC bitfields
Kojto 90:cb3d968589d8 1340 */
Kojto 90:cb3d968589d8 1341
Kojto 90:cb3d968589d8 1342 /*!
Kojto 90:cb3d968589d8 1343 * @name Register FTM_SYNC, field CNTMIN[0] (RW)
Kojto 90:cb3d968589d8 1344 *
Kojto 90:cb3d968589d8 1345 * Selects the minimum loading point to PWM synchronization. See Boundary cycle
Kojto 90:cb3d968589d8 1346 * and loading points. If CNTMIN is one, the selected loading point is when the
Kojto 90:cb3d968589d8 1347 * FTM counter reaches its minimum value (CNTIN register).
Kojto 90:cb3d968589d8 1348 *
Kojto 90:cb3d968589d8 1349 * Values:
Kojto 90:cb3d968589d8 1350 * - 0 - The minimum loading point is disabled.
Kojto 90:cb3d968589d8 1351 * - 1 - The minimum loading point is enabled.
Kojto 90:cb3d968589d8 1352 */
Kojto 90:cb3d968589d8 1353 /*@{*/
Kojto 90:cb3d968589d8 1354 #define BP_FTM_SYNC_CNTMIN (0U) /*!< Bit position for FTM_SYNC_CNTMIN. */
Kojto 90:cb3d968589d8 1355 #define BM_FTM_SYNC_CNTMIN (0x00000001U) /*!< Bit mask for FTM_SYNC_CNTMIN. */
Kojto 90:cb3d968589d8 1356 #define BS_FTM_SYNC_CNTMIN (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMIN. */
Kojto 90:cb3d968589d8 1357
Kojto 90:cb3d968589d8 1358 /*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
Kojto 90:cb3d968589d8 1359 #define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
Kojto 90:cb3d968589d8 1360
Kojto 90:cb3d968589d8 1361 /*! @brief Format value for bitfield FTM_SYNC_CNTMIN. */
Kojto 90:cb3d968589d8 1362 #define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN)
Kojto 90:cb3d968589d8 1363
Kojto 90:cb3d968589d8 1364 /*! @brief Set the CNTMIN field to a new value. */
Kojto 90:cb3d968589d8 1365 #define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
Kojto 90:cb3d968589d8 1366 /*@}*/
Kojto 90:cb3d968589d8 1367
Kojto 90:cb3d968589d8 1368 /*!
Kojto 90:cb3d968589d8 1369 * @name Register FTM_SYNC, field CNTMAX[1] (RW)
Kojto 90:cb3d968589d8 1370 *
Kojto 90:cb3d968589d8 1371 * Selects the maximum loading point to PWM synchronization. See Boundary cycle
Kojto 90:cb3d968589d8 1372 * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
Kojto 90:cb3d968589d8 1373 * counter reaches its maximum value (MOD register).
Kojto 90:cb3d968589d8 1374 *
Kojto 90:cb3d968589d8 1375 * Values:
Kojto 90:cb3d968589d8 1376 * - 0 - The maximum loading point is disabled.
Kojto 90:cb3d968589d8 1377 * - 1 - The maximum loading point is enabled.
Kojto 90:cb3d968589d8 1378 */
Kojto 90:cb3d968589d8 1379 /*@{*/
Kojto 90:cb3d968589d8 1380 #define BP_FTM_SYNC_CNTMAX (1U) /*!< Bit position for FTM_SYNC_CNTMAX. */
Kojto 90:cb3d968589d8 1381 #define BM_FTM_SYNC_CNTMAX (0x00000002U) /*!< Bit mask for FTM_SYNC_CNTMAX. */
Kojto 90:cb3d968589d8 1382 #define BS_FTM_SYNC_CNTMAX (1U) /*!< Bit field size in bits for FTM_SYNC_CNTMAX. */
Kojto 90:cb3d968589d8 1383
Kojto 90:cb3d968589d8 1384 /*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
Kojto 90:cb3d968589d8 1385 #define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
Kojto 90:cb3d968589d8 1386
Kojto 90:cb3d968589d8 1387 /*! @brief Format value for bitfield FTM_SYNC_CNTMAX. */
Kojto 90:cb3d968589d8 1388 #define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX)
Kojto 90:cb3d968589d8 1389
Kojto 90:cb3d968589d8 1390 /*! @brief Set the CNTMAX field to a new value. */
Kojto 90:cb3d968589d8 1391 #define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
Kojto 90:cb3d968589d8 1392 /*@}*/
Kojto 90:cb3d968589d8 1393
Kojto 90:cb3d968589d8 1394 /*!
Kojto 90:cb3d968589d8 1395 * @name Register FTM_SYNC, field REINIT[2] (RW)
Kojto 90:cb3d968589d8 1396 *
Kojto 90:cb3d968589d8 1397 * Determines if the FTM counter is reinitialized when the selected trigger for
Kojto 90:cb3d968589d8 1398 * the synchronization is detected. The REINIT bit configures the synchronization
Kojto 90:cb3d968589d8 1399 * when SYNCMODE is zero.
Kojto 90:cb3d968589d8 1400 *
Kojto 90:cb3d968589d8 1401 * Values:
Kojto 90:cb3d968589d8 1402 * - 0 - FTM counter continues to count normally.
Kojto 90:cb3d968589d8 1403 * - 1 - FTM counter is updated with its initial value when the selected trigger
Kojto 90:cb3d968589d8 1404 * is detected.
Kojto 90:cb3d968589d8 1405 */
Kojto 90:cb3d968589d8 1406 /*@{*/
Kojto 90:cb3d968589d8 1407 #define BP_FTM_SYNC_REINIT (2U) /*!< Bit position for FTM_SYNC_REINIT. */
Kojto 90:cb3d968589d8 1408 #define BM_FTM_SYNC_REINIT (0x00000004U) /*!< Bit mask for FTM_SYNC_REINIT. */
Kojto 90:cb3d968589d8 1409 #define BS_FTM_SYNC_REINIT (1U) /*!< Bit field size in bits for FTM_SYNC_REINIT. */
Kojto 90:cb3d968589d8 1410
Kojto 90:cb3d968589d8 1411 /*! @brief Read current value of the FTM_SYNC_REINIT field. */
Kojto 90:cb3d968589d8 1412 #define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
Kojto 90:cb3d968589d8 1413
Kojto 90:cb3d968589d8 1414 /*! @brief Format value for bitfield FTM_SYNC_REINIT. */
Kojto 90:cb3d968589d8 1415 #define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT)
Kojto 90:cb3d968589d8 1416
Kojto 90:cb3d968589d8 1417 /*! @brief Set the REINIT field to a new value. */
Kojto 90:cb3d968589d8 1418 #define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
Kojto 90:cb3d968589d8 1419 /*@}*/
Kojto 90:cb3d968589d8 1420
Kojto 90:cb3d968589d8 1421 /*!
Kojto 90:cb3d968589d8 1422 * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
Kojto 90:cb3d968589d8 1423 *
Kojto 90:cb3d968589d8 1424 * Selects when the OUTMASK register is updated with the value of its buffer.
Kojto 90:cb3d968589d8 1425 *
Kojto 90:cb3d968589d8 1426 * Values:
Kojto 90:cb3d968589d8 1427 * - 0 - OUTMASK register is updated with the value of its buffer in all rising
Kojto 90:cb3d968589d8 1428 * edges of the system clock.
Kojto 90:cb3d968589d8 1429 * - 1 - OUTMASK register is updated with the value of its buffer only by the
Kojto 90:cb3d968589d8 1430 * PWM synchronization.
Kojto 90:cb3d968589d8 1431 */
Kojto 90:cb3d968589d8 1432 /*@{*/
Kojto 90:cb3d968589d8 1433 #define BP_FTM_SYNC_SYNCHOM (3U) /*!< Bit position for FTM_SYNC_SYNCHOM. */
Kojto 90:cb3d968589d8 1434 #define BM_FTM_SYNC_SYNCHOM (0x00000008U) /*!< Bit mask for FTM_SYNC_SYNCHOM. */
Kojto 90:cb3d968589d8 1435 #define BS_FTM_SYNC_SYNCHOM (1U) /*!< Bit field size in bits for FTM_SYNC_SYNCHOM. */
Kojto 90:cb3d968589d8 1436
Kojto 90:cb3d968589d8 1437 /*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
Kojto 90:cb3d968589d8 1438 #define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
Kojto 90:cb3d968589d8 1439
Kojto 90:cb3d968589d8 1440 /*! @brief Format value for bitfield FTM_SYNC_SYNCHOM. */
Kojto 90:cb3d968589d8 1441 #define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM)
Kojto 90:cb3d968589d8 1442
Kojto 90:cb3d968589d8 1443 /*! @brief Set the SYNCHOM field to a new value. */
Kojto 90:cb3d968589d8 1444 #define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
Kojto 90:cb3d968589d8 1445 /*@}*/
Kojto 90:cb3d968589d8 1446
Kojto 90:cb3d968589d8 1447 /*!
Kojto 90:cb3d968589d8 1448 * @name Register FTM_SYNC, field TRIG0[4] (RW)
Kojto 90:cb3d968589d8 1449 *
Kojto 90:cb3d968589d8 1450 * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
Kojto 90:cb3d968589d8 1451 * occurs when a rising edge is detected at the trigger 0 input signal.
Kojto 90:cb3d968589d8 1452 *
Kojto 90:cb3d968589d8 1453 * Values:
Kojto 90:cb3d968589d8 1454 * - 0 - Trigger is disabled.
Kojto 90:cb3d968589d8 1455 * - 1 - Trigger is enabled.
Kojto 90:cb3d968589d8 1456 */
Kojto 90:cb3d968589d8 1457 /*@{*/
Kojto 90:cb3d968589d8 1458 #define BP_FTM_SYNC_TRIG0 (4U) /*!< Bit position for FTM_SYNC_TRIG0. */
Kojto 90:cb3d968589d8 1459 #define BM_FTM_SYNC_TRIG0 (0x00000010U) /*!< Bit mask for FTM_SYNC_TRIG0. */
Kojto 90:cb3d968589d8 1460 #define BS_FTM_SYNC_TRIG0 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG0. */
Kojto 90:cb3d968589d8 1461
Kojto 90:cb3d968589d8 1462 /*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
Kojto 90:cb3d968589d8 1463 #define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
Kojto 90:cb3d968589d8 1464
Kojto 90:cb3d968589d8 1465 /*! @brief Format value for bitfield FTM_SYNC_TRIG0. */
Kojto 90:cb3d968589d8 1466 #define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0)
Kojto 90:cb3d968589d8 1467
Kojto 90:cb3d968589d8 1468 /*! @brief Set the TRIG0 field to a new value. */
Kojto 90:cb3d968589d8 1469 #define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
Kojto 90:cb3d968589d8 1470 /*@}*/
Kojto 90:cb3d968589d8 1471
Kojto 90:cb3d968589d8 1472 /*!
Kojto 90:cb3d968589d8 1473 * @name Register FTM_SYNC, field TRIG1[5] (RW)
Kojto 90:cb3d968589d8 1474 *
Kojto 90:cb3d968589d8 1475 * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
Kojto 90:cb3d968589d8 1476 * happens when a rising edge is detected at the trigger 1 input signal.
Kojto 90:cb3d968589d8 1477 *
Kojto 90:cb3d968589d8 1478 * Values:
Kojto 90:cb3d968589d8 1479 * - 0 - Trigger is disabled.
Kojto 90:cb3d968589d8 1480 * - 1 - Trigger is enabled.
Kojto 90:cb3d968589d8 1481 */
Kojto 90:cb3d968589d8 1482 /*@{*/
Kojto 90:cb3d968589d8 1483 #define BP_FTM_SYNC_TRIG1 (5U) /*!< Bit position for FTM_SYNC_TRIG1. */
Kojto 90:cb3d968589d8 1484 #define BM_FTM_SYNC_TRIG1 (0x00000020U) /*!< Bit mask for FTM_SYNC_TRIG1. */
Kojto 90:cb3d968589d8 1485 #define BS_FTM_SYNC_TRIG1 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG1. */
Kojto 90:cb3d968589d8 1486
Kojto 90:cb3d968589d8 1487 /*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
Kojto 90:cb3d968589d8 1488 #define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
Kojto 90:cb3d968589d8 1489
Kojto 90:cb3d968589d8 1490 /*! @brief Format value for bitfield FTM_SYNC_TRIG1. */
Kojto 90:cb3d968589d8 1491 #define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1)
Kojto 90:cb3d968589d8 1492
Kojto 90:cb3d968589d8 1493 /*! @brief Set the TRIG1 field to a new value. */
Kojto 90:cb3d968589d8 1494 #define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
Kojto 90:cb3d968589d8 1495 /*@}*/
Kojto 90:cb3d968589d8 1496
Kojto 90:cb3d968589d8 1497 /*!
Kojto 90:cb3d968589d8 1498 * @name Register FTM_SYNC, field TRIG2[6] (RW)
Kojto 90:cb3d968589d8 1499 *
Kojto 90:cb3d968589d8 1500 * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
Kojto 90:cb3d968589d8 1501 * happens when a rising edge is detected at the trigger 2 input signal.
Kojto 90:cb3d968589d8 1502 *
Kojto 90:cb3d968589d8 1503 * Values:
Kojto 90:cb3d968589d8 1504 * - 0 - Trigger is disabled.
Kojto 90:cb3d968589d8 1505 * - 1 - Trigger is enabled.
Kojto 90:cb3d968589d8 1506 */
Kojto 90:cb3d968589d8 1507 /*@{*/
Kojto 90:cb3d968589d8 1508 #define BP_FTM_SYNC_TRIG2 (6U) /*!< Bit position for FTM_SYNC_TRIG2. */
Kojto 90:cb3d968589d8 1509 #define BM_FTM_SYNC_TRIG2 (0x00000040U) /*!< Bit mask for FTM_SYNC_TRIG2. */
Kojto 90:cb3d968589d8 1510 #define BS_FTM_SYNC_TRIG2 (1U) /*!< Bit field size in bits for FTM_SYNC_TRIG2. */
Kojto 90:cb3d968589d8 1511
Kojto 90:cb3d968589d8 1512 /*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
Kojto 90:cb3d968589d8 1513 #define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
Kojto 90:cb3d968589d8 1514
Kojto 90:cb3d968589d8 1515 /*! @brief Format value for bitfield FTM_SYNC_TRIG2. */
Kojto 90:cb3d968589d8 1516 #define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2)
Kojto 90:cb3d968589d8 1517
Kojto 90:cb3d968589d8 1518 /*! @brief Set the TRIG2 field to a new value. */
Kojto 90:cb3d968589d8 1519 #define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
Kojto 90:cb3d968589d8 1520 /*@}*/
Kojto 90:cb3d968589d8 1521
Kojto 90:cb3d968589d8 1522 /*!
Kojto 90:cb3d968589d8 1523 * @name Register FTM_SYNC, field SWSYNC[7] (RW)
Kojto 90:cb3d968589d8 1524 *
Kojto 90:cb3d968589d8 1525 * Selects the software trigger as the PWM synchronization trigger. The software
Kojto 90:cb3d968589d8 1526 * trigger happens when a 1 is written to SWSYNC bit.
Kojto 90:cb3d968589d8 1527 *
Kojto 90:cb3d968589d8 1528 * Values:
Kojto 90:cb3d968589d8 1529 * - 0 - Software trigger is not selected.
Kojto 90:cb3d968589d8 1530 * - 1 - Software trigger is selected.
Kojto 90:cb3d968589d8 1531 */
Kojto 90:cb3d968589d8 1532 /*@{*/
Kojto 90:cb3d968589d8 1533 #define BP_FTM_SYNC_SWSYNC (7U) /*!< Bit position for FTM_SYNC_SWSYNC. */
Kojto 90:cb3d968589d8 1534 #define BM_FTM_SYNC_SWSYNC (0x00000080U) /*!< Bit mask for FTM_SYNC_SWSYNC. */
Kojto 90:cb3d968589d8 1535 #define BS_FTM_SYNC_SWSYNC (1U) /*!< Bit field size in bits for FTM_SYNC_SWSYNC. */
Kojto 90:cb3d968589d8 1536
Kojto 90:cb3d968589d8 1537 /*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
Kojto 90:cb3d968589d8 1538 #define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
Kojto 90:cb3d968589d8 1539
Kojto 90:cb3d968589d8 1540 /*! @brief Format value for bitfield FTM_SYNC_SWSYNC. */
Kojto 90:cb3d968589d8 1541 #define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC)
Kojto 90:cb3d968589d8 1542
Kojto 90:cb3d968589d8 1543 /*! @brief Set the SWSYNC field to a new value. */
Kojto 90:cb3d968589d8 1544 #define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
Kojto 90:cb3d968589d8 1545 /*@}*/
Kojto 90:cb3d968589d8 1546
Kojto 90:cb3d968589d8 1547 /*******************************************************************************
Kojto 90:cb3d968589d8 1548 * HW_FTM_OUTINIT - Initial State For Channels Output
Kojto 90:cb3d968589d8 1549 ******************************************************************************/
Kojto 90:cb3d968589d8 1550
Kojto 90:cb3d968589d8 1551 /*!
Kojto 90:cb3d968589d8 1552 * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
Kojto 90:cb3d968589d8 1553 *
Kojto 90:cb3d968589d8 1554 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 1555 */
Kojto 90:cb3d968589d8 1556 typedef union _hw_ftm_outinit
Kojto 90:cb3d968589d8 1557 {
Kojto 90:cb3d968589d8 1558 uint32_t U;
Kojto 90:cb3d968589d8 1559 struct _hw_ftm_outinit_bitfields
Kojto 90:cb3d968589d8 1560 {
Kojto 90:cb3d968589d8 1561 uint32_t CH0OI : 1; /*!< [0] Channel 0 Output Initialization Value */
Kojto 90:cb3d968589d8 1562 uint32_t CH1OI : 1; /*!< [1] Channel 1 Output Initialization Value */
Kojto 90:cb3d968589d8 1563 uint32_t CH2OI : 1; /*!< [2] Channel 2 Output Initialization Value */
Kojto 90:cb3d968589d8 1564 uint32_t CH3OI : 1; /*!< [3] Channel 3 Output Initialization Value */
Kojto 90:cb3d968589d8 1565 uint32_t CH4OI : 1; /*!< [4] Channel 4 Output Initialization Value */
Kojto 90:cb3d968589d8 1566 uint32_t CH5OI : 1; /*!< [5] Channel 5 Output Initialization Value */
Kojto 90:cb3d968589d8 1567 uint32_t CH6OI : 1; /*!< [6] Channel 6 Output Initialization Value */
Kojto 90:cb3d968589d8 1568 uint32_t CH7OI : 1; /*!< [7] Channel 7 Output Initialization Value */
Kojto 90:cb3d968589d8 1569 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 1570 } B;
Kojto 90:cb3d968589d8 1571 } hw_ftm_outinit_t;
Kojto 90:cb3d968589d8 1572
Kojto 90:cb3d968589d8 1573 /*!
Kojto 90:cb3d968589d8 1574 * @name Constants and macros for entire FTM_OUTINIT register
Kojto 90:cb3d968589d8 1575 */
Kojto 90:cb3d968589d8 1576 /*@{*/
Kojto 90:cb3d968589d8 1577 #define HW_FTM_OUTINIT_ADDR(x) ((x) + 0x5CU)
Kojto 90:cb3d968589d8 1578
Kojto 90:cb3d968589d8 1579 #define HW_FTM_OUTINIT(x) (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
Kojto 90:cb3d968589d8 1580 #define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
Kojto 90:cb3d968589d8 1581 #define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
Kojto 90:cb3d968589d8 1582 #define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) | (v)))
Kojto 90:cb3d968589d8 1583 #define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1584 #define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1585 /*@}*/
Kojto 90:cb3d968589d8 1586
Kojto 90:cb3d968589d8 1587 /*
Kojto 90:cb3d968589d8 1588 * Constants & macros for individual FTM_OUTINIT bitfields
Kojto 90:cb3d968589d8 1589 */
Kojto 90:cb3d968589d8 1590
Kojto 90:cb3d968589d8 1591 /*!
Kojto 90:cb3d968589d8 1592 * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
Kojto 90:cb3d968589d8 1593 *
Kojto 90:cb3d968589d8 1594 * Selects the value that is forced into the channel output when the
Kojto 90:cb3d968589d8 1595 * initialization occurs.
Kojto 90:cb3d968589d8 1596 *
Kojto 90:cb3d968589d8 1597 * Values:
Kojto 90:cb3d968589d8 1598 * - 0 - The initialization value is 0.
Kojto 90:cb3d968589d8 1599 * - 1 - The initialization value is 1.
Kojto 90:cb3d968589d8 1600 */
Kojto 90:cb3d968589d8 1601 /*@{*/
Kojto 90:cb3d968589d8 1602 #define BP_FTM_OUTINIT_CH0OI (0U) /*!< Bit position for FTM_OUTINIT_CH0OI. */
Kojto 90:cb3d968589d8 1603 #define BM_FTM_OUTINIT_CH0OI (0x00000001U) /*!< Bit mask for FTM_OUTINIT_CH0OI. */
Kojto 90:cb3d968589d8 1604 #define BS_FTM_OUTINIT_CH0OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH0OI. */
Kojto 90:cb3d968589d8 1605
Kojto 90:cb3d968589d8 1606 /*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
Kojto 90:cb3d968589d8 1607 #define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
Kojto 90:cb3d968589d8 1608
Kojto 90:cb3d968589d8 1609 /*! @brief Format value for bitfield FTM_OUTINIT_CH0OI. */
Kojto 90:cb3d968589d8 1610 #define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI)
Kojto 90:cb3d968589d8 1611
Kojto 90:cb3d968589d8 1612 /*! @brief Set the CH0OI field to a new value. */
Kojto 90:cb3d968589d8 1613 #define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
Kojto 90:cb3d968589d8 1614 /*@}*/
Kojto 90:cb3d968589d8 1615
Kojto 90:cb3d968589d8 1616 /*!
Kojto 90:cb3d968589d8 1617 * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
Kojto 90:cb3d968589d8 1618 *
Kojto 90:cb3d968589d8 1619 * Selects the value that is forced into the channel output when the
Kojto 90:cb3d968589d8 1620 * initialization occurs.
Kojto 90:cb3d968589d8 1621 *
Kojto 90:cb3d968589d8 1622 * Values:
Kojto 90:cb3d968589d8 1623 * - 0 - The initialization value is 0.
Kojto 90:cb3d968589d8 1624 * - 1 - The initialization value is 1.
Kojto 90:cb3d968589d8 1625 */
Kojto 90:cb3d968589d8 1626 /*@{*/
Kojto 90:cb3d968589d8 1627 #define BP_FTM_OUTINIT_CH1OI (1U) /*!< Bit position for FTM_OUTINIT_CH1OI. */
Kojto 90:cb3d968589d8 1628 #define BM_FTM_OUTINIT_CH1OI (0x00000002U) /*!< Bit mask for FTM_OUTINIT_CH1OI. */
Kojto 90:cb3d968589d8 1629 #define BS_FTM_OUTINIT_CH1OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH1OI. */
Kojto 90:cb3d968589d8 1630
Kojto 90:cb3d968589d8 1631 /*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
Kojto 90:cb3d968589d8 1632 #define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
Kojto 90:cb3d968589d8 1633
Kojto 90:cb3d968589d8 1634 /*! @brief Format value for bitfield FTM_OUTINIT_CH1OI. */
Kojto 90:cb3d968589d8 1635 #define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI)
Kojto 90:cb3d968589d8 1636
Kojto 90:cb3d968589d8 1637 /*! @brief Set the CH1OI field to a new value. */
Kojto 90:cb3d968589d8 1638 #define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
Kojto 90:cb3d968589d8 1639 /*@}*/
Kojto 90:cb3d968589d8 1640
Kojto 90:cb3d968589d8 1641 /*!
Kojto 90:cb3d968589d8 1642 * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
Kojto 90:cb3d968589d8 1643 *
Kojto 90:cb3d968589d8 1644 * Selects the value that is forced into the channel output when the
Kojto 90:cb3d968589d8 1645 * initialization occurs.
Kojto 90:cb3d968589d8 1646 *
Kojto 90:cb3d968589d8 1647 * Values:
Kojto 90:cb3d968589d8 1648 * - 0 - The initialization value is 0.
Kojto 90:cb3d968589d8 1649 * - 1 - The initialization value is 1.
Kojto 90:cb3d968589d8 1650 */
Kojto 90:cb3d968589d8 1651 /*@{*/
Kojto 90:cb3d968589d8 1652 #define BP_FTM_OUTINIT_CH2OI (2U) /*!< Bit position for FTM_OUTINIT_CH2OI. */
Kojto 90:cb3d968589d8 1653 #define BM_FTM_OUTINIT_CH2OI (0x00000004U) /*!< Bit mask for FTM_OUTINIT_CH2OI. */
Kojto 90:cb3d968589d8 1654 #define BS_FTM_OUTINIT_CH2OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH2OI. */
Kojto 90:cb3d968589d8 1655
Kojto 90:cb3d968589d8 1656 /*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
Kojto 90:cb3d968589d8 1657 #define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
Kojto 90:cb3d968589d8 1658
Kojto 90:cb3d968589d8 1659 /*! @brief Format value for bitfield FTM_OUTINIT_CH2OI. */
Kojto 90:cb3d968589d8 1660 #define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI)
Kojto 90:cb3d968589d8 1661
Kojto 90:cb3d968589d8 1662 /*! @brief Set the CH2OI field to a new value. */
Kojto 90:cb3d968589d8 1663 #define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
Kojto 90:cb3d968589d8 1664 /*@}*/
Kojto 90:cb3d968589d8 1665
Kojto 90:cb3d968589d8 1666 /*!
Kojto 90:cb3d968589d8 1667 * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
Kojto 90:cb3d968589d8 1668 *
Kojto 90:cb3d968589d8 1669 * Selects the value that is forced into the channel output when the
Kojto 90:cb3d968589d8 1670 * initialization occurs.
Kojto 90:cb3d968589d8 1671 *
Kojto 90:cb3d968589d8 1672 * Values:
Kojto 90:cb3d968589d8 1673 * - 0 - The initialization value is 0.
Kojto 90:cb3d968589d8 1674 * - 1 - The initialization value is 1.
Kojto 90:cb3d968589d8 1675 */
Kojto 90:cb3d968589d8 1676 /*@{*/
Kojto 90:cb3d968589d8 1677 #define BP_FTM_OUTINIT_CH3OI (3U) /*!< Bit position for FTM_OUTINIT_CH3OI. */
Kojto 90:cb3d968589d8 1678 #define BM_FTM_OUTINIT_CH3OI (0x00000008U) /*!< Bit mask for FTM_OUTINIT_CH3OI. */
Kojto 90:cb3d968589d8 1679 #define BS_FTM_OUTINIT_CH3OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH3OI. */
Kojto 90:cb3d968589d8 1680
Kojto 90:cb3d968589d8 1681 /*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
Kojto 90:cb3d968589d8 1682 #define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
Kojto 90:cb3d968589d8 1683
Kojto 90:cb3d968589d8 1684 /*! @brief Format value for bitfield FTM_OUTINIT_CH3OI. */
Kojto 90:cb3d968589d8 1685 #define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI)
Kojto 90:cb3d968589d8 1686
Kojto 90:cb3d968589d8 1687 /*! @brief Set the CH3OI field to a new value. */
Kojto 90:cb3d968589d8 1688 #define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
Kojto 90:cb3d968589d8 1689 /*@}*/
Kojto 90:cb3d968589d8 1690
Kojto 90:cb3d968589d8 1691 /*!
Kojto 90:cb3d968589d8 1692 * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
Kojto 90:cb3d968589d8 1693 *
Kojto 90:cb3d968589d8 1694 * Selects the value that is forced into the channel output when the
Kojto 90:cb3d968589d8 1695 * initialization occurs.
Kojto 90:cb3d968589d8 1696 *
Kojto 90:cb3d968589d8 1697 * Values:
Kojto 90:cb3d968589d8 1698 * - 0 - The initialization value is 0.
Kojto 90:cb3d968589d8 1699 * - 1 - The initialization value is 1.
Kojto 90:cb3d968589d8 1700 */
Kojto 90:cb3d968589d8 1701 /*@{*/
Kojto 90:cb3d968589d8 1702 #define BP_FTM_OUTINIT_CH4OI (4U) /*!< Bit position for FTM_OUTINIT_CH4OI. */
Kojto 90:cb3d968589d8 1703 #define BM_FTM_OUTINIT_CH4OI (0x00000010U) /*!< Bit mask for FTM_OUTINIT_CH4OI. */
Kojto 90:cb3d968589d8 1704 #define BS_FTM_OUTINIT_CH4OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH4OI. */
Kojto 90:cb3d968589d8 1705
Kojto 90:cb3d968589d8 1706 /*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
Kojto 90:cb3d968589d8 1707 #define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
Kojto 90:cb3d968589d8 1708
Kojto 90:cb3d968589d8 1709 /*! @brief Format value for bitfield FTM_OUTINIT_CH4OI. */
Kojto 90:cb3d968589d8 1710 #define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI)
Kojto 90:cb3d968589d8 1711
Kojto 90:cb3d968589d8 1712 /*! @brief Set the CH4OI field to a new value. */
Kojto 90:cb3d968589d8 1713 #define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
Kojto 90:cb3d968589d8 1714 /*@}*/
Kojto 90:cb3d968589d8 1715
Kojto 90:cb3d968589d8 1716 /*!
Kojto 90:cb3d968589d8 1717 * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
Kojto 90:cb3d968589d8 1718 *
Kojto 90:cb3d968589d8 1719 * Selects the value that is forced into the channel output when the
Kojto 90:cb3d968589d8 1720 * initialization occurs.
Kojto 90:cb3d968589d8 1721 *
Kojto 90:cb3d968589d8 1722 * Values:
Kojto 90:cb3d968589d8 1723 * - 0 - The initialization value is 0.
Kojto 90:cb3d968589d8 1724 * - 1 - The initialization value is 1.
Kojto 90:cb3d968589d8 1725 */
Kojto 90:cb3d968589d8 1726 /*@{*/
Kojto 90:cb3d968589d8 1727 #define BP_FTM_OUTINIT_CH5OI (5U) /*!< Bit position for FTM_OUTINIT_CH5OI. */
Kojto 90:cb3d968589d8 1728 #define BM_FTM_OUTINIT_CH5OI (0x00000020U) /*!< Bit mask for FTM_OUTINIT_CH5OI. */
Kojto 90:cb3d968589d8 1729 #define BS_FTM_OUTINIT_CH5OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH5OI. */
Kojto 90:cb3d968589d8 1730
Kojto 90:cb3d968589d8 1731 /*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
Kojto 90:cb3d968589d8 1732 #define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
Kojto 90:cb3d968589d8 1733
Kojto 90:cb3d968589d8 1734 /*! @brief Format value for bitfield FTM_OUTINIT_CH5OI. */
Kojto 90:cb3d968589d8 1735 #define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI)
Kojto 90:cb3d968589d8 1736
Kojto 90:cb3d968589d8 1737 /*! @brief Set the CH5OI field to a new value. */
Kojto 90:cb3d968589d8 1738 #define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
Kojto 90:cb3d968589d8 1739 /*@}*/
Kojto 90:cb3d968589d8 1740
Kojto 90:cb3d968589d8 1741 /*!
Kojto 90:cb3d968589d8 1742 * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
Kojto 90:cb3d968589d8 1743 *
Kojto 90:cb3d968589d8 1744 * Selects the value that is forced into the channel output when the
Kojto 90:cb3d968589d8 1745 * initialization occurs.
Kojto 90:cb3d968589d8 1746 *
Kojto 90:cb3d968589d8 1747 * Values:
Kojto 90:cb3d968589d8 1748 * - 0 - The initialization value is 0.
Kojto 90:cb3d968589d8 1749 * - 1 - The initialization value is 1.
Kojto 90:cb3d968589d8 1750 */
Kojto 90:cb3d968589d8 1751 /*@{*/
Kojto 90:cb3d968589d8 1752 #define BP_FTM_OUTINIT_CH6OI (6U) /*!< Bit position for FTM_OUTINIT_CH6OI. */
Kojto 90:cb3d968589d8 1753 #define BM_FTM_OUTINIT_CH6OI (0x00000040U) /*!< Bit mask for FTM_OUTINIT_CH6OI. */
Kojto 90:cb3d968589d8 1754 #define BS_FTM_OUTINIT_CH6OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH6OI. */
Kojto 90:cb3d968589d8 1755
Kojto 90:cb3d968589d8 1756 /*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
Kojto 90:cb3d968589d8 1757 #define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
Kojto 90:cb3d968589d8 1758
Kojto 90:cb3d968589d8 1759 /*! @brief Format value for bitfield FTM_OUTINIT_CH6OI. */
Kojto 90:cb3d968589d8 1760 #define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI)
Kojto 90:cb3d968589d8 1761
Kojto 90:cb3d968589d8 1762 /*! @brief Set the CH6OI field to a new value. */
Kojto 90:cb3d968589d8 1763 #define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
Kojto 90:cb3d968589d8 1764 /*@}*/
Kojto 90:cb3d968589d8 1765
Kojto 90:cb3d968589d8 1766 /*!
Kojto 90:cb3d968589d8 1767 * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
Kojto 90:cb3d968589d8 1768 *
Kojto 90:cb3d968589d8 1769 * Selects the value that is forced into the channel output when the
Kojto 90:cb3d968589d8 1770 * initialization occurs.
Kojto 90:cb3d968589d8 1771 *
Kojto 90:cb3d968589d8 1772 * Values:
Kojto 90:cb3d968589d8 1773 * - 0 - The initialization value is 0.
Kojto 90:cb3d968589d8 1774 * - 1 - The initialization value is 1.
Kojto 90:cb3d968589d8 1775 */
Kojto 90:cb3d968589d8 1776 /*@{*/
Kojto 90:cb3d968589d8 1777 #define BP_FTM_OUTINIT_CH7OI (7U) /*!< Bit position for FTM_OUTINIT_CH7OI. */
Kojto 90:cb3d968589d8 1778 #define BM_FTM_OUTINIT_CH7OI (0x00000080U) /*!< Bit mask for FTM_OUTINIT_CH7OI. */
Kojto 90:cb3d968589d8 1779 #define BS_FTM_OUTINIT_CH7OI (1U) /*!< Bit field size in bits for FTM_OUTINIT_CH7OI. */
Kojto 90:cb3d968589d8 1780
Kojto 90:cb3d968589d8 1781 /*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
Kojto 90:cb3d968589d8 1782 #define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
Kojto 90:cb3d968589d8 1783
Kojto 90:cb3d968589d8 1784 /*! @brief Format value for bitfield FTM_OUTINIT_CH7OI. */
Kojto 90:cb3d968589d8 1785 #define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI)
Kojto 90:cb3d968589d8 1786
Kojto 90:cb3d968589d8 1787 /*! @brief Set the CH7OI field to a new value. */
Kojto 90:cb3d968589d8 1788 #define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
Kojto 90:cb3d968589d8 1789 /*@}*/
Kojto 90:cb3d968589d8 1790
Kojto 90:cb3d968589d8 1791 /*******************************************************************************
Kojto 90:cb3d968589d8 1792 * HW_FTM_OUTMASK - Output Mask
Kojto 90:cb3d968589d8 1793 ******************************************************************************/
Kojto 90:cb3d968589d8 1794
Kojto 90:cb3d968589d8 1795 /*!
Kojto 90:cb3d968589d8 1796 * @brief HW_FTM_OUTMASK - Output Mask (RW)
Kojto 90:cb3d968589d8 1797 *
Kojto 90:cb3d968589d8 1798 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 1799 *
Kojto 90:cb3d968589d8 1800 * This register provides a mask for each FTM channel. The mask of a channel
Kojto 90:cb3d968589d8 1801 * determines if its output responds, that is, it is masked or not, when a match
Kojto 90:cb3d968589d8 1802 * occurs. This feature is used for BLDC control where the PWM signal is presented
Kojto 90:cb3d968589d8 1803 * to an electric motor at specific times to provide electronic commutation. Any
Kojto 90:cb3d968589d8 1804 * write to the OUTMASK register, stores the value in its write buffer. The
Kojto 90:cb3d968589d8 1805 * register is updated with the value of its write buffer according to PWM
Kojto 90:cb3d968589d8 1806 * synchronization.
Kojto 90:cb3d968589d8 1807 */
Kojto 90:cb3d968589d8 1808 typedef union _hw_ftm_outmask
Kojto 90:cb3d968589d8 1809 {
Kojto 90:cb3d968589d8 1810 uint32_t U;
Kojto 90:cb3d968589d8 1811 struct _hw_ftm_outmask_bitfields
Kojto 90:cb3d968589d8 1812 {
Kojto 90:cb3d968589d8 1813 uint32_t CH0OM : 1; /*!< [0] Channel 0 Output Mask */
Kojto 90:cb3d968589d8 1814 uint32_t CH1OM : 1; /*!< [1] Channel 1 Output Mask */
Kojto 90:cb3d968589d8 1815 uint32_t CH2OM : 1; /*!< [2] Channel 2 Output Mask */
Kojto 90:cb3d968589d8 1816 uint32_t CH3OM : 1; /*!< [3] Channel 3 Output Mask */
Kojto 90:cb3d968589d8 1817 uint32_t CH4OM : 1; /*!< [4] Channel 4 Output Mask */
Kojto 90:cb3d968589d8 1818 uint32_t CH5OM : 1; /*!< [5] Channel 5 Output Mask */
Kojto 90:cb3d968589d8 1819 uint32_t CH6OM : 1; /*!< [6] Channel 6 Output Mask */
Kojto 90:cb3d968589d8 1820 uint32_t CH7OM : 1; /*!< [7] Channel 7 Output Mask */
Kojto 90:cb3d968589d8 1821 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 1822 } B;
Kojto 90:cb3d968589d8 1823 } hw_ftm_outmask_t;
Kojto 90:cb3d968589d8 1824
Kojto 90:cb3d968589d8 1825 /*!
Kojto 90:cb3d968589d8 1826 * @name Constants and macros for entire FTM_OUTMASK register
Kojto 90:cb3d968589d8 1827 */
Kojto 90:cb3d968589d8 1828 /*@{*/
Kojto 90:cb3d968589d8 1829 #define HW_FTM_OUTMASK_ADDR(x) ((x) + 0x60U)
Kojto 90:cb3d968589d8 1830
Kojto 90:cb3d968589d8 1831 #define HW_FTM_OUTMASK(x) (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
Kojto 90:cb3d968589d8 1832 #define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
Kojto 90:cb3d968589d8 1833 #define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
Kojto 90:cb3d968589d8 1834 #define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) | (v)))
Kojto 90:cb3d968589d8 1835 #define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 1836 #define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 1837 /*@}*/
Kojto 90:cb3d968589d8 1838
Kojto 90:cb3d968589d8 1839 /*
Kojto 90:cb3d968589d8 1840 * Constants & macros for individual FTM_OUTMASK bitfields
Kojto 90:cb3d968589d8 1841 */
Kojto 90:cb3d968589d8 1842
Kojto 90:cb3d968589d8 1843 /*!
Kojto 90:cb3d968589d8 1844 * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
Kojto 90:cb3d968589d8 1845 *
Kojto 90:cb3d968589d8 1846 * Defines if the channel output is masked or unmasked.
Kojto 90:cb3d968589d8 1847 *
Kojto 90:cb3d968589d8 1848 * Values:
Kojto 90:cb3d968589d8 1849 * - 0 - Channel output is not masked. It continues to operate normally.
Kojto 90:cb3d968589d8 1850 * - 1 - Channel output is masked. It is forced to its inactive state.
Kojto 90:cb3d968589d8 1851 */
Kojto 90:cb3d968589d8 1852 /*@{*/
Kojto 90:cb3d968589d8 1853 #define BP_FTM_OUTMASK_CH0OM (0U) /*!< Bit position for FTM_OUTMASK_CH0OM. */
Kojto 90:cb3d968589d8 1854 #define BM_FTM_OUTMASK_CH0OM (0x00000001U) /*!< Bit mask for FTM_OUTMASK_CH0OM. */
Kojto 90:cb3d968589d8 1855 #define BS_FTM_OUTMASK_CH0OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH0OM. */
Kojto 90:cb3d968589d8 1856
Kojto 90:cb3d968589d8 1857 /*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
Kojto 90:cb3d968589d8 1858 #define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
Kojto 90:cb3d968589d8 1859
Kojto 90:cb3d968589d8 1860 /*! @brief Format value for bitfield FTM_OUTMASK_CH0OM. */
Kojto 90:cb3d968589d8 1861 #define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM)
Kojto 90:cb3d968589d8 1862
Kojto 90:cb3d968589d8 1863 /*! @brief Set the CH0OM field to a new value. */
Kojto 90:cb3d968589d8 1864 #define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
Kojto 90:cb3d968589d8 1865 /*@}*/
Kojto 90:cb3d968589d8 1866
Kojto 90:cb3d968589d8 1867 /*!
Kojto 90:cb3d968589d8 1868 * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
Kojto 90:cb3d968589d8 1869 *
Kojto 90:cb3d968589d8 1870 * Defines if the channel output is masked or unmasked.
Kojto 90:cb3d968589d8 1871 *
Kojto 90:cb3d968589d8 1872 * Values:
Kojto 90:cb3d968589d8 1873 * - 0 - Channel output is not masked. It continues to operate normally.
Kojto 90:cb3d968589d8 1874 * - 1 - Channel output is masked. It is forced to its inactive state.
Kojto 90:cb3d968589d8 1875 */
Kojto 90:cb3d968589d8 1876 /*@{*/
Kojto 90:cb3d968589d8 1877 #define BP_FTM_OUTMASK_CH1OM (1U) /*!< Bit position for FTM_OUTMASK_CH1OM. */
Kojto 90:cb3d968589d8 1878 #define BM_FTM_OUTMASK_CH1OM (0x00000002U) /*!< Bit mask for FTM_OUTMASK_CH1OM. */
Kojto 90:cb3d968589d8 1879 #define BS_FTM_OUTMASK_CH1OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH1OM. */
Kojto 90:cb3d968589d8 1880
Kojto 90:cb3d968589d8 1881 /*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
Kojto 90:cb3d968589d8 1882 #define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
Kojto 90:cb3d968589d8 1883
Kojto 90:cb3d968589d8 1884 /*! @brief Format value for bitfield FTM_OUTMASK_CH1OM. */
Kojto 90:cb3d968589d8 1885 #define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM)
Kojto 90:cb3d968589d8 1886
Kojto 90:cb3d968589d8 1887 /*! @brief Set the CH1OM field to a new value. */
Kojto 90:cb3d968589d8 1888 #define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
Kojto 90:cb3d968589d8 1889 /*@}*/
Kojto 90:cb3d968589d8 1890
Kojto 90:cb3d968589d8 1891 /*!
Kojto 90:cb3d968589d8 1892 * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
Kojto 90:cb3d968589d8 1893 *
Kojto 90:cb3d968589d8 1894 * Defines if the channel output is masked or unmasked.
Kojto 90:cb3d968589d8 1895 *
Kojto 90:cb3d968589d8 1896 * Values:
Kojto 90:cb3d968589d8 1897 * - 0 - Channel output is not masked. It continues to operate normally.
Kojto 90:cb3d968589d8 1898 * - 1 - Channel output is masked. It is forced to its inactive state.
Kojto 90:cb3d968589d8 1899 */
Kojto 90:cb3d968589d8 1900 /*@{*/
Kojto 90:cb3d968589d8 1901 #define BP_FTM_OUTMASK_CH2OM (2U) /*!< Bit position for FTM_OUTMASK_CH2OM. */
Kojto 90:cb3d968589d8 1902 #define BM_FTM_OUTMASK_CH2OM (0x00000004U) /*!< Bit mask for FTM_OUTMASK_CH2OM. */
Kojto 90:cb3d968589d8 1903 #define BS_FTM_OUTMASK_CH2OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH2OM. */
Kojto 90:cb3d968589d8 1904
Kojto 90:cb3d968589d8 1905 /*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
Kojto 90:cb3d968589d8 1906 #define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
Kojto 90:cb3d968589d8 1907
Kojto 90:cb3d968589d8 1908 /*! @brief Format value for bitfield FTM_OUTMASK_CH2OM. */
Kojto 90:cb3d968589d8 1909 #define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM)
Kojto 90:cb3d968589d8 1910
Kojto 90:cb3d968589d8 1911 /*! @brief Set the CH2OM field to a new value. */
Kojto 90:cb3d968589d8 1912 #define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
Kojto 90:cb3d968589d8 1913 /*@}*/
Kojto 90:cb3d968589d8 1914
Kojto 90:cb3d968589d8 1915 /*!
Kojto 90:cb3d968589d8 1916 * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
Kojto 90:cb3d968589d8 1917 *
Kojto 90:cb3d968589d8 1918 * Defines if the channel output is masked or unmasked.
Kojto 90:cb3d968589d8 1919 *
Kojto 90:cb3d968589d8 1920 * Values:
Kojto 90:cb3d968589d8 1921 * - 0 - Channel output is not masked. It continues to operate normally.
Kojto 90:cb3d968589d8 1922 * - 1 - Channel output is masked. It is forced to its inactive state.
Kojto 90:cb3d968589d8 1923 */
Kojto 90:cb3d968589d8 1924 /*@{*/
Kojto 90:cb3d968589d8 1925 #define BP_FTM_OUTMASK_CH3OM (3U) /*!< Bit position for FTM_OUTMASK_CH3OM. */
Kojto 90:cb3d968589d8 1926 #define BM_FTM_OUTMASK_CH3OM (0x00000008U) /*!< Bit mask for FTM_OUTMASK_CH3OM. */
Kojto 90:cb3d968589d8 1927 #define BS_FTM_OUTMASK_CH3OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH3OM. */
Kojto 90:cb3d968589d8 1928
Kojto 90:cb3d968589d8 1929 /*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
Kojto 90:cb3d968589d8 1930 #define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
Kojto 90:cb3d968589d8 1931
Kojto 90:cb3d968589d8 1932 /*! @brief Format value for bitfield FTM_OUTMASK_CH3OM. */
Kojto 90:cb3d968589d8 1933 #define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM)
Kojto 90:cb3d968589d8 1934
Kojto 90:cb3d968589d8 1935 /*! @brief Set the CH3OM field to a new value. */
Kojto 90:cb3d968589d8 1936 #define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
Kojto 90:cb3d968589d8 1937 /*@}*/
Kojto 90:cb3d968589d8 1938
Kojto 90:cb3d968589d8 1939 /*!
Kojto 90:cb3d968589d8 1940 * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
Kojto 90:cb3d968589d8 1941 *
Kojto 90:cb3d968589d8 1942 * Defines if the channel output is masked or unmasked.
Kojto 90:cb3d968589d8 1943 *
Kojto 90:cb3d968589d8 1944 * Values:
Kojto 90:cb3d968589d8 1945 * - 0 - Channel output is not masked. It continues to operate normally.
Kojto 90:cb3d968589d8 1946 * - 1 - Channel output is masked. It is forced to its inactive state.
Kojto 90:cb3d968589d8 1947 */
Kojto 90:cb3d968589d8 1948 /*@{*/
Kojto 90:cb3d968589d8 1949 #define BP_FTM_OUTMASK_CH4OM (4U) /*!< Bit position for FTM_OUTMASK_CH4OM. */
Kojto 90:cb3d968589d8 1950 #define BM_FTM_OUTMASK_CH4OM (0x00000010U) /*!< Bit mask for FTM_OUTMASK_CH4OM. */
Kojto 90:cb3d968589d8 1951 #define BS_FTM_OUTMASK_CH4OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH4OM. */
Kojto 90:cb3d968589d8 1952
Kojto 90:cb3d968589d8 1953 /*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
Kojto 90:cb3d968589d8 1954 #define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
Kojto 90:cb3d968589d8 1955
Kojto 90:cb3d968589d8 1956 /*! @brief Format value for bitfield FTM_OUTMASK_CH4OM. */
Kojto 90:cb3d968589d8 1957 #define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM)
Kojto 90:cb3d968589d8 1958
Kojto 90:cb3d968589d8 1959 /*! @brief Set the CH4OM field to a new value. */
Kojto 90:cb3d968589d8 1960 #define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
Kojto 90:cb3d968589d8 1961 /*@}*/
Kojto 90:cb3d968589d8 1962
Kojto 90:cb3d968589d8 1963 /*!
Kojto 90:cb3d968589d8 1964 * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
Kojto 90:cb3d968589d8 1965 *
Kojto 90:cb3d968589d8 1966 * Defines if the channel output is masked or unmasked.
Kojto 90:cb3d968589d8 1967 *
Kojto 90:cb3d968589d8 1968 * Values:
Kojto 90:cb3d968589d8 1969 * - 0 - Channel output is not masked. It continues to operate normally.
Kojto 90:cb3d968589d8 1970 * - 1 - Channel output is masked. It is forced to its inactive state.
Kojto 90:cb3d968589d8 1971 */
Kojto 90:cb3d968589d8 1972 /*@{*/
Kojto 90:cb3d968589d8 1973 #define BP_FTM_OUTMASK_CH5OM (5U) /*!< Bit position for FTM_OUTMASK_CH5OM. */
Kojto 90:cb3d968589d8 1974 #define BM_FTM_OUTMASK_CH5OM (0x00000020U) /*!< Bit mask for FTM_OUTMASK_CH5OM. */
Kojto 90:cb3d968589d8 1975 #define BS_FTM_OUTMASK_CH5OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH5OM. */
Kojto 90:cb3d968589d8 1976
Kojto 90:cb3d968589d8 1977 /*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
Kojto 90:cb3d968589d8 1978 #define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
Kojto 90:cb3d968589d8 1979
Kojto 90:cb3d968589d8 1980 /*! @brief Format value for bitfield FTM_OUTMASK_CH5OM. */
Kojto 90:cb3d968589d8 1981 #define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM)
Kojto 90:cb3d968589d8 1982
Kojto 90:cb3d968589d8 1983 /*! @brief Set the CH5OM field to a new value. */
Kojto 90:cb3d968589d8 1984 #define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
Kojto 90:cb3d968589d8 1985 /*@}*/
Kojto 90:cb3d968589d8 1986
Kojto 90:cb3d968589d8 1987 /*!
Kojto 90:cb3d968589d8 1988 * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
Kojto 90:cb3d968589d8 1989 *
Kojto 90:cb3d968589d8 1990 * Defines if the channel output is masked or unmasked.
Kojto 90:cb3d968589d8 1991 *
Kojto 90:cb3d968589d8 1992 * Values:
Kojto 90:cb3d968589d8 1993 * - 0 - Channel output is not masked. It continues to operate normally.
Kojto 90:cb3d968589d8 1994 * - 1 - Channel output is masked. It is forced to its inactive state.
Kojto 90:cb3d968589d8 1995 */
Kojto 90:cb3d968589d8 1996 /*@{*/
Kojto 90:cb3d968589d8 1997 #define BP_FTM_OUTMASK_CH6OM (6U) /*!< Bit position for FTM_OUTMASK_CH6OM. */
Kojto 90:cb3d968589d8 1998 #define BM_FTM_OUTMASK_CH6OM (0x00000040U) /*!< Bit mask for FTM_OUTMASK_CH6OM. */
Kojto 90:cb3d968589d8 1999 #define BS_FTM_OUTMASK_CH6OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH6OM. */
Kojto 90:cb3d968589d8 2000
Kojto 90:cb3d968589d8 2001 /*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
Kojto 90:cb3d968589d8 2002 #define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
Kojto 90:cb3d968589d8 2003
Kojto 90:cb3d968589d8 2004 /*! @brief Format value for bitfield FTM_OUTMASK_CH6OM. */
Kojto 90:cb3d968589d8 2005 #define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM)
Kojto 90:cb3d968589d8 2006
Kojto 90:cb3d968589d8 2007 /*! @brief Set the CH6OM field to a new value. */
Kojto 90:cb3d968589d8 2008 #define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
Kojto 90:cb3d968589d8 2009 /*@}*/
Kojto 90:cb3d968589d8 2010
Kojto 90:cb3d968589d8 2011 /*!
Kojto 90:cb3d968589d8 2012 * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
Kojto 90:cb3d968589d8 2013 *
Kojto 90:cb3d968589d8 2014 * Defines if the channel output is masked or unmasked.
Kojto 90:cb3d968589d8 2015 *
Kojto 90:cb3d968589d8 2016 * Values:
Kojto 90:cb3d968589d8 2017 * - 0 - Channel output is not masked. It continues to operate normally.
Kojto 90:cb3d968589d8 2018 * - 1 - Channel output is masked. It is forced to its inactive state.
Kojto 90:cb3d968589d8 2019 */
Kojto 90:cb3d968589d8 2020 /*@{*/
Kojto 90:cb3d968589d8 2021 #define BP_FTM_OUTMASK_CH7OM (7U) /*!< Bit position for FTM_OUTMASK_CH7OM. */
Kojto 90:cb3d968589d8 2022 #define BM_FTM_OUTMASK_CH7OM (0x00000080U) /*!< Bit mask for FTM_OUTMASK_CH7OM. */
Kojto 90:cb3d968589d8 2023 #define BS_FTM_OUTMASK_CH7OM (1U) /*!< Bit field size in bits for FTM_OUTMASK_CH7OM. */
Kojto 90:cb3d968589d8 2024
Kojto 90:cb3d968589d8 2025 /*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
Kojto 90:cb3d968589d8 2026 #define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
Kojto 90:cb3d968589d8 2027
Kojto 90:cb3d968589d8 2028 /*! @brief Format value for bitfield FTM_OUTMASK_CH7OM. */
Kojto 90:cb3d968589d8 2029 #define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM)
Kojto 90:cb3d968589d8 2030
Kojto 90:cb3d968589d8 2031 /*! @brief Set the CH7OM field to a new value. */
Kojto 90:cb3d968589d8 2032 #define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
Kojto 90:cb3d968589d8 2033 /*@}*/
Kojto 90:cb3d968589d8 2034
Kojto 90:cb3d968589d8 2035 /*******************************************************************************
Kojto 90:cb3d968589d8 2036 * HW_FTM_COMBINE - Function For Linked Channels
Kojto 90:cb3d968589d8 2037 ******************************************************************************/
Kojto 90:cb3d968589d8 2038
Kojto 90:cb3d968589d8 2039 /*!
Kojto 90:cb3d968589d8 2040 * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
Kojto 90:cb3d968589d8 2041 *
Kojto 90:cb3d968589d8 2042 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 2043 *
Kojto 90:cb3d968589d8 2044 * This register contains the control bits used to configure the fault control,
Kojto 90:cb3d968589d8 2045 * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
Kojto 90:cb3d968589d8 2046 * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
Kojto 90:cb3d968589d8 2047 * 4, and 6.
Kojto 90:cb3d968589d8 2048 */
Kojto 90:cb3d968589d8 2049 typedef union _hw_ftm_combine
Kojto 90:cb3d968589d8 2050 {
Kojto 90:cb3d968589d8 2051 uint32_t U;
Kojto 90:cb3d968589d8 2052 struct _hw_ftm_combine_bitfields
Kojto 90:cb3d968589d8 2053 {
Kojto 90:cb3d968589d8 2054 uint32_t COMBINE0 : 1; /*!< [0] Combine Channels For n = 0 */
Kojto 90:cb3d968589d8 2055 uint32_t COMP0 : 1; /*!< [1] Complement Of Channel (n) For n = 0 */
Kojto 90:cb3d968589d8 2056 uint32_t DECAPEN0 : 1; /*!< [2] Dual Edge Capture Mode Enable For n =
Kojto 90:cb3d968589d8 2057 * 0 */
Kojto 90:cb3d968589d8 2058 uint32_t DECAP0 : 1; /*!< [3] Dual Edge Capture Mode Captures For n =
Kojto 90:cb3d968589d8 2059 * 0 */
Kojto 90:cb3d968589d8 2060 uint32_t DTEN0 : 1; /*!< [4] Deadtime Enable For n = 0 */
Kojto 90:cb3d968589d8 2061 uint32_t SYNCEN0 : 1; /*!< [5] Synchronization Enable For n = 0 */
Kojto 90:cb3d968589d8 2062 uint32_t FAULTEN0 : 1; /*!< [6] Fault Control Enable For n = 0 */
Kojto 90:cb3d968589d8 2063 uint32_t RESERVED0 : 1; /*!< [7] */
Kojto 90:cb3d968589d8 2064 uint32_t COMBINE1 : 1; /*!< [8] Combine Channels For n = 2 */
Kojto 90:cb3d968589d8 2065 uint32_t COMP1 : 1; /*!< [9] Complement Of Channel (n) For n = 2 */
Kojto 90:cb3d968589d8 2066 uint32_t DECAPEN1 : 1; /*!< [10] Dual Edge Capture Mode Enable For n
Kojto 90:cb3d968589d8 2067 * = 2 */
Kojto 90:cb3d968589d8 2068 uint32_t DECAP1 : 1; /*!< [11] Dual Edge Capture Mode Captures For n
Kojto 90:cb3d968589d8 2069 * = 2 */
Kojto 90:cb3d968589d8 2070 uint32_t DTEN1 : 1; /*!< [12] Deadtime Enable For n = 2 */
Kojto 90:cb3d968589d8 2071 uint32_t SYNCEN1 : 1; /*!< [13] Synchronization Enable For n = 2 */
Kojto 90:cb3d968589d8 2072 uint32_t FAULTEN1 : 1; /*!< [14] Fault Control Enable For n = 2 */
Kojto 90:cb3d968589d8 2073 uint32_t RESERVED1 : 1; /*!< [15] */
Kojto 90:cb3d968589d8 2074 uint32_t COMBINE2 : 1; /*!< [16] Combine Channels For n = 4 */
Kojto 90:cb3d968589d8 2075 uint32_t COMP2 : 1; /*!< [17] Complement Of Channel (n) For n = 4 */
Kojto 90:cb3d968589d8 2076 uint32_t DECAPEN2 : 1; /*!< [18] Dual Edge Capture Mode Enable For n
Kojto 90:cb3d968589d8 2077 * = 4 */
Kojto 90:cb3d968589d8 2078 uint32_t DECAP2 : 1; /*!< [19] Dual Edge Capture Mode Captures For n
Kojto 90:cb3d968589d8 2079 * = 4 */
Kojto 90:cb3d968589d8 2080 uint32_t DTEN2 : 1; /*!< [20] Deadtime Enable For n = 4 */
Kojto 90:cb3d968589d8 2081 uint32_t SYNCEN2 : 1; /*!< [21] Synchronization Enable For n = 4 */
Kojto 90:cb3d968589d8 2082 uint32_t FAULTEN2 : 1; /*!< [22] Fault Control Enable For n = 4 */
Kojto 90:cb3d968589d8 2083 uint32_t RESERVED2 : 1; /*!< [23] */
Kojto 90:cb3d968589d8 2084 uint32_t COMBINE3 : 1; /*!< [24] Combine Channels For n = 6 */
Kojto 90:cb3d968589d8 2085 uint32_t COMP3 : 1; /*!< [25] Complement Of Channel (n) for n = 6 */
Kojto 90:cb3d968589d8 2086 uint32_t DECAPEN3 : 1; /*!< [26] Dual Edge Capture Mode Enable For n
Kojto 90:cb3d968589d8 2087 * = 6 */
Kojto 90:cb3d968589d8 2088 uint32_t DECAP3 : 1; /*!< [27] Dual Edge Capture Mode Captures For n
Kojto 90:cb3d968589d8 2089 * = 6 */
Kojto 90:cb3d968589d8 2090 uint32_t DTEN3 : 1; /*!< [28] Deadtime Enable For n = 6 */
Kojto 90:cb3d968589d8 2091 uint32_t SYNCEN3 : 1; /*!< [29] Synchronization Enable For n = 6 */
Kojto 90:cb3d968589d8 2092 uint32_t FAULTEN3 : 1; /*!< [30] Fault Control Enable For n = 6 */
Kojto 90:cb3d968589d8 2093 uint32_t RESERVED3 : 1; /*!< [31] */
Kojto 90:cb3d968589d8 2094 } B;
Kojto 90:cb3d968589d8 2095 } hw_ftm_combine_t;
Kojto 90:cb3d968589d8 2096
Kojto 90:cb3d968589d8 2097 /*!
Kojto 90:cb3d968589d8 2098 * @name Constants and macros for entire FTM_COMBINE register
Kojto 90:cb3d968589d8 2099 */
Kojto 90:cb3d968589d8 2100 /*@{*/
Kojto 90:cb3d968589d8 2101 #define HW_FTM_COMBINE_ADDR(x) ((x) + 0x64U)
Kojto 90:cb3d968589d8 2102
Kojto 90:cb3d968589d8 2103 #define HW_FTM_COMBINE(x) (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
Kojto 90:cb3d968589d8 2104 #define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
Kojto 90:cb3d968589d8 2105 #define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
Kojto 90:cb3d968589d8 2106 #define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) | (v)))
Kojto 90:cb3d968589d8 2107 #define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 2108 #define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 2109 /*@}*/
Kojto 90:cb3d968589d8 2110
Kojto 90:cb3d968589d8 2111 /*
Kojto 90:cb3d968589d8 2112 * Constants & macros for individual FTM_COMBINE bitfields
Kojto 90:cb3d968589d8 2113 */
Kojto 90:cb3d968589d8 2114
Kojto 90:cb3d968589d8 2115 /*!
Kojto 90:cb3d968589d8 2116 * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
Kojto 90:cb3d968589d8 2117 *
Kojto 90:cb3d968589d8 2118 * Enables the combine feature for channels (n) and (n+1). This field is write
Kojto 90:cb3d968589d8 2119 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2120 *
Kojto 90:cb3d968589d8 2121 * Values:
Kojto 90:cb3d968589d8 2122 * - 0 - Channels (n) and (n+1) are independent.
Kojto 90:cb3d968589d8 2123 * - 1 - Channels (n) and (n+1) are combined.
Kojto 90:cb3d968589d8 2124 */
Kojto 90:cb3d968589d8 2125 /*@{*/
Kojto 90:cb3d968589d8 2126 #define BP_FTM_COMBINE_COMBINE0 (0U) /*!< Bit position for FTM_COMBINE_COMBINE0. */
Kojto 90:cb3d968589d8 2127 #define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /*!< Bit mask for FTM_COMBINE_COMBINE0. */
Kojto 90:cb3d968589d8 2128 #define BS_FTM_COMBINE_COMBINE0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE0. */
Kojto 90:cb3d968589d8 2129
Kojto 90:cb3d968589d8 2130 /*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
Kojto 90:cb3d968589d8 2131 #define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
Kojto 90:cb3d968589d8 2132
Kojto 90:cb3d968589d8 2133 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE0. */
Kojto 90:cb3d968589d8 2134 #define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0)
Kojto 90:cb3d968589d8 2135
Kojto 90:cb3d968589d8 2136 /*! @brief Set the COMBINE0 field to a new value. */
Kojto 90:cb3d968589d8 2137 #define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
Kojto 90:cb3d968589d8 2138 /*@}*/
Kojto 90:cb3d968589d8 2139
Kojto 90:cb3d968589d8 2140 /*!
Kojto 90:cb3d968589d8 2141 * @name Register FTM_COMBINE, field COMP0[1] (RW)
Kojto 90:cb3d968589d8 2142 *
Kojto 90:cb3d968589d8 2143 * Enables Complementary mode for the combined channels. In Complementary mode
Kojto 90:cb3d968589d8 2144 * the channel (n+1) output is the inverse of the channel (n) output. This field
Kojto 90:cb3d968589d8 2145 * is write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2146 *
Kojto 90:cb3d968589d8 2147 * Values:
Kojto 90:cb3d968589d8 2148 * - 0 - The channel (n+1) output is the same as the channel (n) output.
Kojto 90:cb3d968589d8 2149 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
Kojto 90:cb3d968589d8 2150 */
Kojto 90:cb3d968589d8 2151 /*@{*/
Kojto 90:cb3d968589d8 2152 #define BP_FTM_COMBINE_COMP0 (1U) /*!< Bit position for FTM_COMBINE_COMP0. */
Kojto 90:cb3d968589d8 2153 #define BM_FTM_COMBINE_COMP0 (0x00000002U) /*!< Bit mask for FTM_COMBINE_COMP0. */
Kojto 90:cb3d968589d8 2154 #define BS_FTM_COMBINE_COMP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP0. */
Kojto 90:cb3d968589d8 2155
Kojto 90:cb3d968589d8 2156 /*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
Kojto 90:cb3d968589d8 2157 #define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
Kojto 90:cb3d968589d8 2158
Kojto 90:cb3d968589d8 2159 /*! @brief Format value for bitfield FTM_COMBINE_COMP0. */
Kojto 90:cb3d968589d8 2160 #define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0)
Kojto 90:cb3d968589d8 2161
Kojto 90:cb3d968589d8 2162 /*! @brief Set the COMP0 field to a new value. */
Kojto 90:cb3d968589d8 2163 #define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
Kojto 90:cb3d968589d8 2164 /*@}*/
Kojto 90:cb3d968589d8 2165
Kojto 90:cb3d968589d8 2166 /*!
Kojto 90:cb3d968589d8 2167 * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
Kojto 90:cb3d968589d8 2168 *
Kojto 90:cb3d968589d8 2169 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
Kojto 90:cb3d968589d8 2170 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
Kojto 90:cb3d968589d8 2171 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
Kojto 90:cb3d968589d8 2172 * when FTMEN = 1. This field is write protected. It can be written only when
Kojto 90:cb3d968589d8 2173 * MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2174 *
Kojto 90:cb3d968589d8 2175 * Values:
Kojto 90:cb3d968589d8 2176 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2177 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2178 */
Kojto 90:cb3d968589d8 2179 /*@{*/
Kojto 90:cb3d968589d8 2180 #define BP_FTM_COMBINE_DECAPEN0 (2U) /*!< Bit position for FTM_COMBINE_DECAPEN0. */
Kojto 90:cb3d968589d8 2181 #define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /*!< Bit mask for FTM_COMBINE_DECAPEN0. */
Kojto 90:cb3d968589d8 2182 #define BS_FTM_COMBINE_DECAPEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN0. */
Kojto 90:cb3d968589d8 2183
Kojto 90:cb3d968589d8 2184 /*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
Kojto 90:cb3d968589d8 2185 #define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
Kojto 90:cb3d968589d8 2186
Kojto 90:cb3d968589d8 2187 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. */
Kojto 90:cb3d968589d8 2188 #define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0)
Kojto 90:cb3d968589d8 2189
Kojto 90:cb3d968589d8 2190 /*! @brief Set the DECAPEN0 field to a new value. */
Kojto 90:cb3d968589d8 2191 #define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
Kojto 90:cb3d968589d8 2192 /*@}*/
Kojto 90:cb3d968589d8 2193
Kojto 90:cb3d968589d8 2194 /*!
Kojto 90:cb3d968589d8 2195 * @name Register FTM_COMBINE, field DECAP0[3] (RW)
Kojto 90:cb3d968589d8 2196 *
Kojto 90:cb3d968589d8 2197 * Enables the capture of the FTM counter value according to the channel (n)
Kojto 90:cb3d968589d8 2198 * input event and the configuration of the dual edge capture bits. This field
Kojto 90:cb3d968589d8 2199 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
Kojto 90:cb3d968589d8 2200 * hardware if dual edge capture - one-shot mode is selected and when the capture
Kojto 90:cb3d968589d8 2201 * of channel (n+1) event is made.
Kojto 90:cb3d968589d8 2202 *
Kojto 90:cb3d968589d8 2203 * Values:
Kojto 90:cb3d968589d8 2204 * - 0 - The dual edge captures are inactive.
Kojto 90:cb3d968589d8 2205 * - 1 - The dual edge captures are active.
Kojto 90:cb3d968589d8 2206 */
Kojto 90:cb3d968589d8 2207 /*@{*/
Kojto 90:cb3d968589d8 2208 #define BP_FTM_COMBINE_DECAP0 (3U) /*!< Bit position for FTM_COMBINE_DECAP0. */
Kojto 90:cb3d968589d8 2209 #define BM_FTM_COMBINE_DECAP0 (0x00000008U) /*!< Bit mask for FTM_COMBINE_DECAP0. */
Kojto 90:cb3d968589d8 2210 #define BS_FTM_COMBINE_DECAP0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP0. */
Kojto 90:cb3d968589d8 2211
Kojto 90:cb3d968589d8 2212 /*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
Kojto 90:cb3d968589d8 2213 #define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
Kojto 90:cb3d968589d8 2214
Kojto 90:cb3d968589d8 2215 /*! @brief Format value for bitfield FTM_COMBINE_DECAP0. */
Kojto 90:cb3d968589d8 2216 #define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0)
Kojto 90:cb3d968589d8 2217
Kojto 90:cb3d968589d8 2218 /*! @brief Set the DECAP0 field to a new value. */
Kojto 90:cb3d968589d8 2219 #define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
Kojto 90:cb3d968589d8 2220 /*@}*/
Kojto 90:cb3d968589d8 2221
Kojto 90:cb3d968589d8 2222 /*!
Kojto 90:cb3d968589d8 2223 * @name Register FTM_COMBINE, field DTEN0[4] (RW)
Kojto 90:cb3d968589d8 2224 *
Kojto 90:cb3d968589d8 2225 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
Kojto 90:cb3d968589d8 2226 * write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2227 *
Kojto 90:cb3d968589d8 2228 * Values:
Kojto 90:cb3d968589d8 2229 * - 0 - The deadtime insertion in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2230 * - 1 - The deadtime insertion in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2231 */
Kojto 90:cb3d968589d8 2232 /*@{*/
Kojto 90:cb3d968589d8 2233 #define BP_FTM_COMBINE_DTEN0 (4U) /*!< Bit position for FTM_COMBINE_DTEN0. */
Kojto 90:cb3d968589d8 2234 #define BM_FTM_COMBINE_DTEN0 (0x00000010U) /*!< Bit mask for FTM_COMBINE_DTEN0. */
Kojto 90:cb3d968589d8 2235 #define BS_FTM_COMBINE_DTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN0. */
Kojto 90:cb3d968589d8 2236
Kojto 90:cb3d968589d8 2237 /*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
Kojto 90:cb3d968589d8 2238 #define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
Kojto 90:cb3d968589d8 2239
Kojto 90:cb3d968589d8 2240 /*! @brief Format value for bitfield FTM_COMBINE_DTEN0. */
Kojto 90:cb3d968589d8 2241 #define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0)
Kojto 90:cb3d968589d8 2242
Kojto 90:cb3d968589d8 2243 /*! @brief Set the DTEN0 field to a new value. */
Kojto 90:cb3d968589d8 2244 #define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
Kojto 90:cb3d968589d8 2245 /*@}*/
Kojto 90:cb3d968589d8 2246
Kojto 90:cb3d968589d8 2247 /*!
Kojto 90:cb3d968589d8 2248 * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
Kojto 90:cb3d968589d8 2249 *
Kojto 90:cb3d968589d8 2250 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
Kojto 90:cb3d968589d8 2251 *
Kojto 90:cb3d968589d8 2252 * Values:
Kojto 90:cb3d968589d8 2253 * - 0 - The PWM synchronization in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2254 * - 1 - The PWM synchronization in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2255 */
Kojto 90:cb3d968589d8 2256 /*@{*/
Kojto 90:cb3d968589d8 2257 #define BP_FTM_COMBINE_SYNCEN0 (5U) /*!< Bit position for FTM_COMBINE_SYNCEN0. */
Kojto 90:cb3d968589d8 2258 #define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /*!< Bit mask for FTM_COMBINE_SYNCEN0. */
Kojto 90:cb3d968589d8 2259 #define BS_FTM_COMBINE_SYNCEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN0. */
Kojto 90:cb3d968589d8 2260
Kojto 90:cb3d968589d8 2261 /*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
Kojto 90:cb3d968589d8 2262 #define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
Kojto 90:cb3d968589d8 2263
Kojto 90:cb3d968589d8 2264 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. */
Kojto 90:cb3d968589d8 2265 #define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0)
Kojto 90:cb3d968589d8 2266
Kojto 90:cb3d968589d8 2267 /*! @brief Set the SYNCEN0 field to a new value. */
Kojto 90:cb3d968589d8 2268 #define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
Kojto 90:cb3d968589d8 2269 /*@}*/
Kojto 90:cb3d968589d8 2270
Kojto 90:cb3d968589d8 2271 /*!
Kojto 90:cb3d968589d8 2272 * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
Kojto 90:cb3d968589d8 2273 *
Kojto 90:cb3d968589d8 2274 * Enables the fault control in channels (n) and (n+1). This field is write
Kojto 90:cb3d968589d8 2275 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2276 *
Kojto 90:cb3d968589d8 2277 * Values:
Kojto 90:cb3d968589d8 2278 * - 0 - The fault control in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2279 * - 1 - The fault control in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2280 */
Kojto 90:cb3d968589d8 2281 /*@{*/
Kojto 90:cb3d968589d8 2282 #define BP_FTM_COMBINE_FAULTEN0 (6U) /*!< Bit position for FTM_COMBINE_FAULTEN0. */
Kojto 90:cb3d968589d8 2283 #define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /*!< Bit mask for FTM_COMBINE_FAULTEN0. */
Kojto 90:cb3d968589d8 2284 #define BS_FTM_COMBINE_FAULTEN0 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN0. */
Kojto 90:cb3d968589d8 2285
Kojto 90:cb3d968589d8 2286 /*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
Kojto 90:cb3d968589d8 2287 #define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
Kojto 90:cb3d968589d8 2288
Kojto 90:cb3d968589d8 2289 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. */
Kojto 90:cb3d968589d8 2290 #define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0)
Kojto 90:cb3d968589d8 2291
Kojto 90:cb3d968589d8 2292 /*! @brief Set the FAULTEN0 field to a new value. */
Kojto 90:cb3d968589d8 2293 #define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
Kojto 90:cb3d968589d8 2294 /*@}*/
Kojto 90:cb3d968589d8 2295
Kojto 90:cb3d968589d8 2296 /*!
Kojto 90:cb3d968589d8 2297 * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
Kojto 90:cb3d968589d8 2298 *
Kojto 90:cb3d968589d8 2299 * Enables the combine feature for channels (n) and (n+1). This field is write
Kojto 90:cb3d968589d8 2300 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2301 *
Kojto 90:cb3d968589d8 2302 * Values:
Kojto 90:cb3d968589d8 2303 * - 0 - Channels (n) and (n+1) are independent.
Kojto 90:cb3d968589d8 2304 * - 1 - Channels (n) and (n+1) are combined.
Kojto 90:cb3d968589d8 2305 */
Kojto 90:cb3d968589d8 2306 /*@{*/
Kojto 90:cb3d968589d8 2307 #define BP_FTM_COMBINE_COMBINE1 (8U) /*!< Bit position for FTM_COMBINE_COMBINE1. */
Kojto 90:cb3d968589d8 2308 #define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /*!< Bit mask for FTM_COMBINE_COMBINE1. */
Kojto 90:cb3d968589d8 2309 #define BS_FTM_COMBINE_COMBINE1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE1. */
Kojto 90:cb3d968589d8 2310
Kojto 90:cb3d968589d8 2311 /*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
Kojto 90:cb3d968589d8 2312 #define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
Kojto 90:cb3d968589d8 2313
Kojto 90:cb3d968589d8 2314 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE1. */
Kojto 90:cb3d968589d8 2315 #define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1)
Kojto 90:cb3d968589d8 2316
Kojto 90:cb3d968589d8 2317 /*! @brief Set the COMBINE1 field to a new value. */
Kojto 90:cb3d968589d8 2318 #define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
Kojto 90:cb3d968589d8 2319 /*@}*/
Kojto 90:cb3d968589d8 2320
Kojto 90:cb3d968589d8 2321 /*!
Kojto 90:cb3d968589d8 2322 * @name Register FTM_COMBINE, field COMP1[9] (RW)
Kojto 90:cb3d968589d8 2323 *
Kojto 90:cb3d968589d8 2324 * Enables Complementary mode for the combined channels. In Complementary mode
Kojto 90:cb3d968589d8 2325 * the channel (n+1) output is the inverse of the channel (n) output. This field
Kojto 90:cb3d968589d8 2326 * is write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2327 *
Kojto 90:cb3d968589d8 2328 * Values:
Kojto 90:cb3d968589d8 2329 * - 0 - The channel (n+1) output is the same as the channel (n) output.
Kojto 90:cb3d968589d8 2330 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
Kojto 90:cb3d968589d8 2331 */
Kojto 90:cb3d968589d8 2332 /*@{*/
Kojto 90:cb3d968589d8 2333 #define BP_FTM_COMBINE_COMP1 (9U) /*!< Bit position for FTM_COMBINE_COMP1. */
Kojto 90:cb3d968589d8 2334 #define BM_FTM_COMBINE_COMP1 (0x00000200U) /*!< Bit mask for FTM_COMBINE_COMP1. */
Kojto 90:cb3d968589d8 2335 #define BS_FTM_COMBINE_COMP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP1. */
Kojto 90:cb3d968589d8 2336
Kojto 90:cb3d968589d8 2337 /*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
Kojto 90:cb3d968589d8 2338 #define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
Kojto 90:cb3d968589d8 2339
Kojto 90:cb3d968589d8 2340 /*! @brief Format value for bitfield FTM_COMBINE_COMP1. */
Kojto 90:cb3d968589d8 2341 #define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1)
Kojto 90:cb3d968589d8 2342
Kojto 90:cb3d968589d8 2343 /*! @brief Set the COMP1 field to a new value. */
Kojto 90:cb3d968589d8 2344 #define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
Kojto 90:cb3d968589d8 2345 /*@}*/
Kojto 90:cb3d968589d8 2346
Kojto 90:cb3d968589d8 2347 /*!
Kojto 90:cb3d968589d8 2348 * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
Kojto 90:cb3d968589d8 2349 *
Kojto 90:cb3d968589d8 2350 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
Kojto 90:cb3d968589d8 2351 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
Kojto 90:cb3d968589d8 2352 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
Kojto 90:cb3d968589d8 2353 * when FTMEN = 1. This field is write protected. It can be written only when
Kojto 90:cb3d968589d8 2354 * MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2355 *
Kojto 90:cb3d968589d8 2356 * Values:
Kojto 90:cb3d968589d8 2357 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2358 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2359 */
Kojto 90:cb3d968589d8 2360 /*@{*/
Kojto 90:cb3d968589d8 2361 #define BP_FTM_COMBINE_DECAPEN1 (10U) /*!< Bit position for FTM_COMBINE_DECAPEN1. */
Kojto 90:cb3d968589d8 2362 #define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /*!< Bit mask for FTM_COMBINE_DECAPEN1. */
Kojto 90:cb3d968589d8 2363 #define BS_FTM_COMBINE_DECAPEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN1. */
Kojto 90:cb3d968589d8 2364
Kojto 90:cb3d968589d8 2365 /*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
Kojto 90:cb3d968589d8 2366 #define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
Kojto 90:cb3d968589d8 2367
Kojto 90:cb3d968589d8 2368 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. */
Kojto 90:cb3d968589d8 2369 #define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1)
Kojto 90:cb3d968589d8 2370
Kojto 90:cb3d968589d8 2371 /*! @brief Set the DECAPEN1 field to a new value. */
Kojto 90:cb3d968589d8 2372 #define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
Kojto 90:cb3d968589d8 2373 /*@}*/
Kojto 90:cb3d968589d8 2374
Kojto 90:cb3d968589d8 2375 /*!
Kojto 90:cb3d968589d8 2376 * @name Register FTM_COMBINE, field DECAP1[11] (RW)
Kojto 90:cb3d968589d8 2377 *
Kojto 90:cb3d968589d8 2378 * Enables the capture of the FTM counter value according to the channel (n)
Kojto 90:cb3d968589d8 2379 * input event and the configuration of the dual edge capture bits. This field
Kojto 90:cb3d968589d8 2380 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
Kojto 90:cb3d968589d8 2381 * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
Kojto 90:cb3d968589d8 2382 * of channel (n+1) event is made.
Kojto 90:cb3d968589d8 2383 *
Kojto 90:cb3d968589d8 2384 * Values:
Kojto 90:cb3d968589d8 2385 * - 0 - The dual edge captures are inactive.
Kojto 90:cb3d968589d8 2386 * - 1 - The dual edge captures are active.
Kojto 90:cb3d968589d8 2387 */
Kojto 90:cb3d968589d8 2388 /*@{*/
Kojto 90:cb3d968589d8 2389 #define BP_FTM_COMBINE_DECAP1 (11U) /*!< Bit position for FTM_COMBINE_DECAP1. */
Kojto 90:cb3d968589d8 2390 #define BM_FTM_COMBINE_DECAP1 (0x00000800U) /*!< Bit mask for FTM_COMBINE_DECAP1. */
Kojto 90:cb3d968589d8 2391 #define BS_FTM_COMBINE_DECAP1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP1. */
Kojto 90:cb3d968589d8 2392
Kojto 90:cb3d968589d8 2393 /*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
Kojto 90:cb3d968589d8 2394 #define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
Kojto 90:cb3d968589d8 2395
Kojto 90:cb3d968589d8 2396 /*! @brief Format value for bitfield FTM_COMBINE_DECAP1. */
Kojto 90:cb3d968589d8 2397 #define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1)
Kojto 90:cb3d968589d8 2398
Kojto 90:cb3d968589d8 2399 /*! @brief Set the DECAP1 field to a new value. */
Kojto 90:cb3d968589d8 2400 #define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
Kojto 90:cb3d968589d8 2401 /*@}*/
Kojto 90:cb3d968589d8 2402
Kojto 90:cb3d968589d8 2403 /*!
Kojto 90:cb3d968589d8 2404 * @name Register FTM_COMBINE, field DTEN1[12] (RW)
Kojto 90:cb3d968589d8 2405 *
Kojto 90:cb3d968589d8 2406 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
Kojto 90:cb3d968589d8 2407 * write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2408 *
Kojto 90:cb3d968589d8 2409 * Values:
Kojto 90:cb3d968589d8 2410 * - 0 - The deadtime insertion in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2411 * - 1 - The deadtime insertion in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2412 */
Kojto 90:cb3d968589d8 2413 /*@{*/
Kojto 90:cb3d968589d8 2414 #define BP_FTM_COMBINE_DTEN1 (12U) /*!< Bit position for FTM_COMBINE_DTEN1. */
Kojto 90:cb3d968589d8 2415 #define BM_FTM_COMBINE_DTEN1 (0x00001000U) /*!< Bit mask for FTM_COMBINE_DTEN1. */
Kojto 90:cb3d968589d8 2416 #define BS_FTM_COMBINE_DTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN1. */
Kojto 90:cb3d968589d8 2417
Kojto 90:cb3d968589d8 2418 /*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
Kojto 90:cb3d968589d8 2419 #define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
Kojto 90:cb3d968589d8 2420
Kojto 90:cb3d968589d8 2421 /*! @brief Format value for bitfield FTM_COMBINE_DTEN1. */
Kojto 90:cb3d968589d8 2422 #define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1)
Kojto 90:cb3d968589d8 2423
Kojto 90:cb3d968589d8 2424 /*! @brief Set the DTEN1 field to a new value. */
Kojto 90:cb3d968589d8 2425 #define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
Kojto 90:cb3d968589d8 2426 /*@}*/
Kojto 90:cb3d968589d8 2427
Kojto 90:cb3d968589d8 2428 /*!
Kojto 90:cb3d968589d8 2429 * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
Kojto 90:cb3d968589d8 2430 *
Kojto 90:cb3d968589d8 2431 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
Kojto 90:cb3d968589d8 2432 *
Kojto 90:cb3d968589d8 2433 * Values:
Kojto 90:cb3d968589d8 2434 * - 0 - The PWM synchronization in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2435 * - 1 - The PWM synchronization in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2436 */
Kojto 90:cb3d968589d8 2437 /*@{*/
Kojto 90:cb3d968589d8 2438 #define BP_FTM_COMBINE_SYNCEN1 (13U) /*!< Bit position for FTM_COMBINE_SYNCEN1. */
Kojto 90:cb3d968589d8 2439 #define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /*!< Bit mask for FTM_COMBINE_SYNCEN1. */
Kojto 90:cb3d968589d8 2440 #define BS_FTM_COMBINE_SYNCEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN1. */
Kojto 90:cb3d968589d8 2441
Kojto 90:cb3d968589d8 2442 /*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
Kojto 90:cb3d968589d8 2443 #define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
Kojto 90:cb3d968589d8 2444
Kojto 90:cb3d968589d8 2445 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. */
Kojto 90:cb3d968589d8 2446 #define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1)
Kojto 90:cb3d968589d8 2447
Kojto 90:cb3d968589d8 2448 /*! @brief Set the SYNCEN1 field to a new value. */
Kojto 90:cb3d968589d8 2449 #define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
Kojto 90:cb3d968589d8 2450 /*@}*/
Kojto 90:cb3d968589d8 2451
Kojto 90:cb3d968589d8 2452 /*!
Kojto 90:cb3d968589d8 2453 * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
Kojto 90:cb3d968589d8 2454 *
Kojto 90:cb3d968589d8 2455 * Enables the fault control in channels (n) and (n+1). This field is write
Kojto 90:cb3d968589d8 2456 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2457 *
Kojto 90:cb3d968589d8 2458 * Values:
Kojto 90:cb3d968589d8 2459 * - 0 - The fault control in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2460 * - 1 - The fault control in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2461 */
Kojto 90:cb3d968589d8 2462 /*@{*/
Kojto 90:cb3d968589d8 2463 #define BP_FTM_COMBINE_FAULTEN1 (14U) /*!< Bit position for FTM_COMBINE_FAULTEN1. */
Kojto 90:cb3d968589d8 2464 #define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /*!< Bit mask for FTM_COMBINE_FAULTEN1. */
Kojto 90:cb3d968589d8 2465 #define BS_FTM_COMBINE_FAULTEN1 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN1. */
Kojto 90:cb3d968589d8 2466
Kojto 90:cb3d968589d8 2467 /*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
Kojto 90:cb3d968589d8 2468 #define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
Kojto 90:cb3d968589d8 2469
Kojto 90:cb3d968589d8 2470 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. */
Kojto 90:cb3d968589d8 2471 #define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1)
Kojto 90:cb3d968589d8 2472
Kojto 90:cb3d968589d8 2473 /*! @brief Set the FAULTEN1 field to a new value. */
Kojto 90:cb3d968589d8 2474 #define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
Kojto 90:cb3d968589d8 2475 /*@}*/
Kojto 90:cb3d968589d8 2476
Kojto 90:cb3d968589d8 2477 /*!
Kojto 90:cb3d968589d8 2478 * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
Kojto 90:cb3d968589d8 2479 *
Kojto 90:cb3d968589d8 2480 * Enables the combine feature for channels (n) and (n+1). This field is write
Kojto 90:cb3d968589d8 2481 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2482 *
Kojto 90:cb3d968589d8 2483 * Values:
Kojto 90:cb3d968589d8 2484 * - 0 - Channels (n) and (n+1) are independent.
Kojto 90:cb3d968589d8 2485 * - 1 - Channels (n) and (n+1) are combined.
Kojto 90:cb3d968589d8 2486 */
Kojto 90:cb3d968589d8 2487 /*@{*/
Kojto 90:cb3d968589d8 2488 #define BP_FTM_COMBINE_COMBINE2 (16U) /*!< Bit position for FTM_COMBINE_COMBINE2. */
Kojto 90:cb3d968589d8 2489 #define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /*!< Bit mask for FTM_COMBINE_COMBINE2. */
Kojto 90:cb3d968589d8 2490 #define BS_FTM_COMBINE_COMBINE2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE2. */
Kojto 90:cb3d968589d8 2491
Kojto 90:cb3d968589d8 2492 /*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
Kojto 90:cb3d968589d8 2493 #define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
Kojto 90:cb3d968589d8 2494
Kojto 90:cb3d968589d8 2495 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE2. */
Kojto 90:cb3d968589d8 2496 #define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2)
Kojto 90:cb3d968589d8 2497
Kojto 90:cb3d968589d8 2498 /*! @brief Set the COMBINE2 field to a new value. */
Kojto 90:cb3d968589d8 2499 #define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
Kojto 90:cb3d968589d8 2500 /*@}*/
Kojto 90:cb3d968589d8 2501
Kojto 90:cb3d968589d8 2502 /*!
Kojto 90:cb3d968589d8 2503 * @name Register FTM_COMBINE, field COMP2[17] (RW)
Kojto 90:cb3d968589d8 2504 *
Kojto 90:cb3d968589d8 2505 * Enables Complementary mode for the combined channels. In Complementary mode
Kojto 90:cb3d968589d8 2506 * the channel (n+1) output is the inverse of the channel (n) output. This field
Kojto 90:cb3d968589d8 2507 * is write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2508 *
Kojto 90:cb3d968589d8 2509 * Values:
Kojto 90:cb3d968589d8 2510 * - 0 - The channel (n+1) output is the same as the channel (n) output.
Kojto 90:cb3d968589d8 2511 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
Kojto 90:cb3d968589d8 2512 */
Kojto 90:cb3d968589d8 2513 /*@{*/
Kojto 90:cb3d968589d8 2514 #define BP_FTM_COMBINE_COMP2 (17U) /*!< Bit position for FTM_COMBINE_COMP2. */
Kojto 90:cb3d968589d8 2515 #define BM_FTM_COMBINE_COMP2 (0x00020000U) /*!< Bit mask for FTM_COMBINE_COMP2. */
Kojto 90:cb3d968589d8 2516 #define BS_FTM_COMBINE_COMP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP2. */
Kojto 90:cb3d968589d8 2517
Kojto 90:cb3d968589d8 2518 /*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
Kojto 90:cb3d968589d8 2519 #define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
Kojto 90:cb3d968589d8 2520
Kojto 90:cb3d968589d8 2521 /*! @brief Format value for bitfield FTM_COMBINE_COMP2. */
Kojto 90:cb3d968589d8 2522 #define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2)
Kojto 90:cb3d968589d8 2523
Kojto 90:cb3d968589d8 2524 /*! @brief Set the COMP2 field to a new value. */
Kojto 90:cb3d968589d8 2525 #define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
Kojto 90:cb3d968589d8 2526 /*@}*/
Kojto 90:cb3d968589d8 2527
Kojto 90:cb3d968589d8 2528 /*!
Kojto 90:cb3d968589d8 2529 * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
Kojto 90:cb3d968589d8 2530 *
Kojto 90:cb3d968589d8 2531 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
Kojto 90:cb3d968589d8 2532 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
Kojto 90:cb3d968589d8 2533 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
Kojto 90:cb3d968589d8 2534 * when FTMEN = 1. This field is write protected. It can be written only when
Kojto 90:cb3d968589d8 2535 * MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2536 *
Kojto 90:cb3d968589d8 2537 * Values:
Kojto 90:cb3d968589d8 2538 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2539 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2540 */
Kojto 90:cb3d968589d8 2541 /*@{*/
Kojto 90:cb3d968589d8 2542 #define BP_FTM_COMBINE_DECAPEN2 (18U) /*!< Bit position for FTM_COMBINE_DECAPEN2. */
Kojto 90:cb3d968589d8 2543 #define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /*!< Bit mask for FTM_COMBINE_DECAPEN2. */
Kojto 90:cb3d968589d8 2544 #define BS_FTM_COMBINE_DECAPEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN2. */
Kojto 90:cb3d968589d8 2545
Kojto 90:cb3d968589d8 2546 /*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
Kojto 90:cb3d968589d8 2547 #define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
Kojto 90:cb3d968589d8 2548
Kojto 90:cb3d968589d8 2549 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. */
Kojto 90:cb3d968589d8 2550 #define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2)
Kojto 90:cb3d968589d8 2551
Kojto 90:cb3d968589d8 2552 /*! @brief Set the DECAPEN2 field to a new value. */
Kojto 90:cb3d968589d8 2553 #define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
Kojto 90:cb3d968589d8 2554 /*@}*/
Kojto 90:cb3d968589d8 2555
Kojto 90:cb3d968589d8 2556 /*!
Kojto 90:cb3d968589d8 2557 * @name Register FTM_COMBINE, field DECAP2[19] (RW)
Kojto 90:cb3d968589d8 2558 *
Kojto 90:cb3d968589d8 2559 * Enables the capture of the FTM counter value according to the channel (n)
Kojto 90:cb3d968589d8 2560 * input event and the configuration of the dual edge capture bits. This field
Kojto 90:cb3d968589d8 2561 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
Kojto 90:cb3d968589d8 2562 * hardware if dual edge capture - one-shot mode is selected and when the capture
Kojto 90:cb3d968589d8 2563 * of channel (n+1) event is made.
Kojto 90:cb3d968589d8 2564 *
Kojto 90:cb3d968589d8 2565 * Values:
Kojto 90:cb3d968589d8 2566 * - 0 - The dual edge captures are inactive.
Kojto 90:cb3d968589d8 2567 * - 1 - The dual edge captures are active.
Kojto 90:cb3d968589d8 2568 */
Kojto 90:cb3d968589d8 2569 /*@{*/
Kojto 90:cb3d968589d8 2570 #define BP_FTM_COMBINE_DECAP2 (19U) /*!< Bit position for FTM_COMBINE_DECAP2. */
Kojto 90:cb3d968589d8 2571 #define BM_FTM_COMBINE_DECAP2 (0x00080000U) /*!< Bit mask for FTM_COMBINE_DECAP2. */
Kojto 90:cb3d968589d8 2572 #define BS_FTM_COMBINE_DECAP2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP2. */
Kojto 90:cb3d968589d8 2573
Kojto 90:cb3d968589d8 2574 /*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
Kojto 90:cb3d968589d8 2575 #define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
Kojto 90:cb3d968589d8 2576
Kojto 90:cb3d968589d8 2577 /*! @brief Format value for bitfield FTM_COMBINE_DECAP2. */
Kojto 90:cb3d968589d8 2578 #define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2)
Kojto 90:cb3d968589d8 2579
Kojto 90:cb3d968589d8 2580 /*! @brief Set the DECAP2 field to a new value. */
Kojto 90:cb3d968589d8 2581 #define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
Kojto 90:cb3d968589d8 2582 /*@}*/
Kojto 90:cb3d968589d8 2583
Kojto 90:cb3d968589d8 2584 /*!
Kojto 90:cb3d968589d8 2585 * @name Register FTM_COMBINE, field DTEN2[20] (RW)
Kojto 90:cb3d968589d8 2586 *
Kojto 90:cb3d968589d8 2587 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
Kojto 90:cb3d968589d8 2588 * write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2589 *
Kojto 90:cb3d968589d8 2590 * Values:
Kojto 90:cb3d968589d8 2591 * - 0 - The deadtime insertion in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2592 * - 1 - The deadtime insertion in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2593 */
Kojto 90:cb3d968589d8 2594 /*@{*/
Kojto 90:cb3d968589d8 2595 #define BP_FTM_COMBINE_DTEN2 (20U) /*!< Bit position for FTM_COMBINE_DTEN2. */
Kojto 90:cb3d968589d8 2596 #define BM_FTM_COMBINE_DTEN2 (0x00100000U) /*!< Bit mask for FTM_COMBINE_DTEN2. */
Kojto 90:cb3d968589d8 2597 #define BS_FTM_COMBINE_DTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN2. */
Kojto 90:cb3d968589d8 2598
Kojto 90:cb3d968589d8 2599 /*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
Kojto 90:cb3d968589d8 2600 #define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
Kojto 90:cb3d968589d8 2601
Kojto 90:cb3d968589d8 2602 /*! @brief Format value for bitfield FTM_COMBINE_DTEN2. */
Kojto 90:cb3d968589d8 2603 #define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2)
Kojto 90:cb3d968589d8 2604
Kojto 90:cb3d968589d8 2605 /*! @brief Set the DTEN2 field to a new value. */
Kojto 90:cb3d968589d8 2606 #define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
Kojto 90:cb3d968589d8 2607 /*@}*/
Kojto 90:cb3d968589d8 2608
Kojto 90:cb3d968589d8 2609 /*!
Kojto 90:cb3d968589d8 2610 * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
Kojto 90:cb3d968589d8 2611 *
Kojto 90:cb3d968589d8 2612 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
Kojto 90:cb3d968589d8 2613 *
Kojto 90:cb3d968589d8 2614 * Values:
Kojto 90:cb3d968589d8 2615 * - 0 - The PWM synchronization in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2616 * - 1 - The PWM synchronization in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2617 */
Kojto 90:cb3d968589d8 2618 /*@{*/
Kojto 90:cb3d968589d8 2619 #define BP_FTM_COMBINE_SYNCEN2 (21U) /*!< Bit position for FTM_COMBINE_SYNCEN2. */
Kojto 90:cb3d968589d8 2620 #define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /*!< Bit mask for FTM_COMBINE_SYNCEN2. */
Kojto 90:cb3d968589d8 2621 #define BS_FTM_COMBINE_SYNCEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN2. */
Kojto 90:cb3d968589d8 2622
Kojto 90:cb3d968589d8 2623 /*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
Kojto 90:cb3d968589d8 2624 #define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
Kojto 90:cb3d968589d8 2625
Kojto 90:cb3d968589d8 2626 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. */
Kojto 90:cb3d968589d8 2627 #define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2)
Kojto 90:cb3d968589d8 2628
Kojto 90:cb3d968589d8 2629 /*! @brief Set the SYNCEN2 field to a new value. */
Kojto 90:cb3d968589d8 2630 #define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
Kojto 90:cb3d968589d8 2631 /*@}*/
Kojto 90:cb3d968589d8 2632
Kojto 90:cb3d968589d8 2633 /*!
Kojto 90:cb3d968589d8 2634 * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
Kojto 90:cb3d968589d8 2635 *
Kojto 90:cb3d968589d8 2636 * Enables the fault control in channels (n) and (n+1). This field is write
Kojto 90:cb3d968589d8 2637 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2638 *
Kojto 90:cb3d968589d8 2639 * Values:
Kojto 90:cb3d968589d8 2640 * - 0 - The fault control in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2641 * - 1 - The fault control in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2642 */
Kojto 90:cb3d968589d8 2643 /*@{*/
Kojto 90:cb3d968589d8 2644 #define BP_FTM_COMBINE_FAULTEN2 (22U) /*!< Bit position for FTM_COMBINE_FAULTEN2. */
Kojto 90:cb3d968589d8 2645 #define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /*!< Bit mask for FTM_COMBINE_FAULTEN2. */
Kojto 90:cb3d968589d8 2646 #define BS_FTM_COMBINE_FAULTEN2 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN2. */
Kojto 90:cb3d968589d8 2647
Kojto 90:cb3d968589d8 2648 /*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
Kojto 90:cb3d968589d8 2649 #define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
Kojto 90:cb3d968589d8 2650
Kojto 90:cb3d968589d8 2651 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. */
Kojto 90:cb3d968589d8 2652 #define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2)
Kojto 90:cb3d968589d8 2653
Kojto 90:cb3d968589d8 2654 /*! @brief Set the FAULTEN2 field to a new value. */
Kojto 90:cb3d968589d8 2655 #define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
Kojto 90:cb3d968589d8 2656 /*@}*/
Kojto 90:cb3d968589d8 2657
Kojto 90:cb3d968589d8 2658 /*!
Kojto 90:cb3d968589d8 2659 * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
Kojto 90:cb3d968589d8 2660 *
Kojto 90:cb3d968589d8 2661 * Enables the combine feature for channels (n) and (n+1). This field is write
Kojto 90:cb3d968589d8 2662 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2663 *
Kojto 90:cb3d968589d8 2664 * Values:
Kojto 90:cb3d968589d8 2665 * - 0 - Channels (n) and (n+1) are independent.
Kojto 90:cb3d968589d8 2666 * - 1 - Channels (n) and (n+1) are combined.
Kojto 90:cb3d968589d8 2667 */
Kojto 90:cb3d968589d8 2668 /*@{*/
Kojto 90:cb3d968589d8 2669 #define BP_FTM_COMBINE_COMBINE3 (24U) /*!< Bit position for FTM_COMBINE_COMBINE3. */
Kojto 90:cb3d968589d8 2670 #define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /*!< Bit mask for FTM_COMBINE_COMBINE3. */
Kojto 90:cb3d968589d8 2671 #define BS_FTM_COMBINE_COMBINE3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMBINE3. */
Kojto 90:cb3d968589d8 2672
Kojto 90:cb3d968589d8 2673 /*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
Kojto 90:cb3d968589d8 2674 #define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
Kojto 90:cb3d968589d8 2675
Kojto 90:cb3d968589d8 2676 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE3. */
Kojto 90:cb3d968589d8 2677 #define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3)
Kojto 90:cb3d968589d8 2678
Kojto 90:cb3d968589d8 2679 /*! @brief Set the COMBINE3 field to a new value. */
Kojto 90:cb3d968589d8 2680 #define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
Kojto 90:cb3d968589d8 2681 /*@}*/
Kojto 90:cb3d968589d8 2682
Kojto 90:cb3d968589d8 2683 /*!
Kojto 90:cb3d968589d8 2684 * @name Register FTM_COMBINE, field COMP3[25] (RW)
Kojto 90:cb3d968589d8 2685 *
Kojto 90:cb3d968589d8 2686 * Enables Complementary mode for the combined channels. In Complementary mode
Kojto 90:cb3d968589d8 2687 * the channel (n+1) output is the inverse of the channel (n) output. This field
Kojto 90:cb3d968589d8 2688 * is write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2689 *
Kojto 90:cb3d968589d8 2690 * Values:
Kojto 90:cb3d968589d8 2691 * - 0 - The channel (n+1) output is the same as the channel (n) output.
Kojto 90:cb3d968589d8 2692 * - 1 - The channel (n+1) output is the complement of the channel (n) output.
Kojto 90:cb3d968589d8 2693 */
Kojto 90:cb3d968589d8 2694 /*@{*/
Kojto 90:cb3d968589d8 2695 #define BP_FTM_COMBINE_COMP3 (25U) /*!< Bit position for FTM_COMBINE_COMP3. */
Kojto 90:cb3d968589d8 2696 #define BM_FTM_COMBINE_COMP3 (0x02000000U) /*!< Bit mask for FTM_COMBINE_COMP3. */
Kojto 90:cb3d968589d8 2697 #define BS_FTM_COMBINE_COMP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_COMP3. */
Kojto 90:cb3d968589d8 2698
Kojto 90:cb3d968589d8 2699 /*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
Kojto 90:cb3d968589d8 2700 #define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
Kojto 90:cb3d968589d8 2701
Kojto 90:cb3d968589d8 2702 /*! @brief Format value for bitfield FTM_COMBINE_COMP3. */
Kojto 90:cb3d968589d8 2703 #define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3)
Kojto 90:cb3d968589d8 2704
Kojto 90:cb3d968589d8 2705 /*! @brief Set the COMP3 field to a new value. */
Kojto 90:cb3d968589d8 2706 #define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
Kojto 90:cb3d968589d8 2707 /*@}*/
Kojto 90:cb3d968589d8 2708
Kojto 90:cb3d968589d8 2709 /*!
Kojto 90:cb3d968589d8 2710 * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
Kojto 90:cb3d968589d8 2711 *
Kojto 90:cb3d968589d8 2712 * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
Kojto 90:cb3d968589d8 2713 * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
Kojto 90:cb3d968589d8 2714 * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
Kojto 90:cb3d968589d8 2715 * when FTMEN = 1. This field is write protected. It can be written only when
Kojto 90:cb3d968589d8 2716 * MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2717 *
Kojto 90:cb3d968589d8 2718 * Values:
Kojto 90:cb3d968589d8 2719 * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2720 * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2721 */
Kojto 90:cb3d968589d8 2722 /*@{*/
Kojto 90:cb3d968589d8 2723 #define BP_FTM_COMBINE_DECAPEN3 (26U) /*!< Bit position for FTM_COMBINE_DECAPEN3. */
Kojto 90:cb3d968589d8 2724 #define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /*!< Bit mask for FTM_COMBINE_DECAPEN3. */
Kojto 90:cb3d968589d8 2725 #define BS_FTM_COMBINE_DECAPEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAPEN3. */
Kojto 90:cb3d968589d8 2726
Kojto 90:cb3d968589d8 2727 /*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
Kojto 90:cb3d968589d8 2728 #define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
Kojto 90:cb3d968589d8 2729
Kojto 90:cb3d968589d8 2730 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. */
Kojto 90:cb3d968589d8 2731 #define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3)
Kojto 90:cb3d968589d8 2732
Kojto 90:cb3d968589d8 2733 /*! @brief Set the DECAPEN3 field to a new value. */
Kojto 90:cb3d968589d8 2734 #define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
Kojto 90:cb3d968589d8 2735 /*@}*/
Kojto 90:cb3d968589d8 2736
Kojto 90:cb3d968589d8 2737 /*!
Kojto 90:cb3d968589d8 2738 * @name Register FTM_COMBINE, field DECAP3[27] (RW)
Kojto 90:cb3d968589d8 2739 *
Kojto 90:cb3d968589d8 2740 * Enables the capture of the FTM counter value according to the channel (n)
Kojto 90:cb3d968589d8 2741 * input event and the configuration of the dual edge capture bits. This field
Kojto 90:cb3d968589d8 2742 * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
Kojto 90:cb3d968589d8 2743 * hardware if dual edge capture - one-shot mode is selected and when the capture
Kojto 90:cb3d968589d8 2744 * of channel (n+1) event is made.
Kojto 90:cb3d968589d8 2745 *
Kojto 90:cb3d968589d8 2746 * Values:
Kojto 90:cb3d968589d8 2747 * - 0 - The dual edge captures are inactive.
Kojto 90:cb3d968589d8 2748 * - 1 - The dual edge captures are active.
Kojto 90:cb3d968589d8 2749 */
Kojto 90:cb3d968589d8 2750 /*@{*/
Kojto 90:cb3d968589d8 2751 #define BP_FTM_COMBINE_DECAP3 (27U) /*!< Bit position for FTM_COMBINE_DECAP3. */
Kojto 90:cb3d968589d8 2752 #define BM_FTM_COMBINE_DECAP3 (0x08000000U) /*!< Bit mask for FTM_COMBINE_DECAP3. */
Kojto 90:cb3d968589d8 2753 #define BS_FTM_COMBINE_DECAP3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DECAP3. */
Kojto 90:cb3d968589d8 2754
Kojto 90:cb3d968589d8 2755 /*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
Kojto 90:cb3d968589d8 2756 #define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
Kojto 90:cb3d968589d8 2757
Kojto 90:cb3d968589d8 2758 /*! @brief Format value for bitfield FTM_COMBINE_DECAP3. */
Kojto 90:cb3d968589d8 2759 #define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3)
Kojto 90:cb3d968589d8 2760
Kojto 90:cb3d968589d8 2761 /*! @brief Set the DECAP3 field to a new value. */
Kojto 90:cb3d968589d8 2762 #define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
Kojto 90:cb3d968589d8 2763 /*@}*/
Kojto 90:cb3d968589d8 2764
Kojto 90:cb3d968589d8 2765 /*!
Kojto 90:cb3d968589d8 2766 * @name Register FTM_COMBINE, field DTEN3[28] (RW)
Kojto 90:cb3d968589d8 2767 *
Kojto 90:cb3d968589d8 2768 * Enables the deadtime insertion in the channels (n) and (n+1). This field is
Kojto 90:cb3d968589d8 2769 * write protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2770 *
Kojto 90:cb3d968589d8 2771 * Values:
Kojto 90:cb3d968589d8 2772 * - 0 - The deadtime insertion in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2773 * - 1 - The deadtime insertion in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2774 */
Kojto 90:cb3d968589d8 2775 /*@{*/
Kojto 90:cb3d968589d8 2776 #define BP_FTM_COMBINE_DTEN3 (28U) /*!< Bit position for FTM_COMBINE_DTEN3. */
Kojto 90:cb3d968589d8 2777 #define BM_FTM_COMBINE_DTEN3 (0x10000000U) /*!< Bit mask for FTM_COMBINE_DTEN3. */
Kojto 90:cb3d968589d8 2778 #define BS_FTM_COMBINE_DTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_DTEN3. */
Kojto 90:cb3d968589d8 2779
Kojto 90:cb3d968589d8 2780 /*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
Kojto 90:cb3d968589d8 2781 #define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
Kojto 90:cb3d968589d8 2782
Kojto 90:cb3d968589d8 2783 /*! @brief Format value for bitfield FTM_COMBINE_DTEN3. */
Kojto 90:cb3d968589d8 2784 #define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3)
Kojto 90:cb3d968589d8 2785
Kojto 90:cb3d968589d8 2786 /*! @brief Set the DTEN3 field to a new value. */
Kojto 90:cb3d968589d8 2787 #define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
Kojto 90:cb3d968589d8 2788 /*@}*/
Kojto 90:cb3d968589d8 2789
Kojto 90:cb3d968589d8 2790 /*!
Kojto 90:cb3d968589d8 2791 * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
Kojto 90:cb3d968589d8 2792 *
Kojto 90:cb3d968589d8 2793 * Enables PWM synchronization of registers C(n)V and C(n+1)V.
Kojto 90:cb3d968589d8 2794 *
Kojto 90:cb3d968589d8 2795 * Values:
Kojto 90:cb3d968589d8 2796 * - 0 - The PWM synchronization in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2797 * - 1 - The PWM synchronization in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2798 */
Kojto 90:cb3d968589d8 2799 /*@{*/
Kojto 90:cb3d968589d8 2800 #define BP_FTM_COMBINE_SYNCEN3 (29U) /*!< Bit position for FTM_COMBINE_SYNCEN3. */
Kojto 90:cb3d968589d8 2801 #define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /*!< Bit mask for FTM_COMBINE_SYNCEN3. */
Kojto 90:cb3d968589d8 2802 #define BS_FTM_COMBINE_SYNCEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_SYNCEN3. */
Kojto 90:cb3d968589d8 2803
Kojto 90:cb3d968589d8 2804 /*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
Kojto 90:cb3d968589d8 2805 #define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
Kojto 90:cb3d968589d8 2806
Kojto 90:cb3d968589d8 2807 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. */
Kojto 90:cb3d968589d8 2808 #define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3)
Kojto 90:cb3d968589d8 2809
Kojto 90:cb3d968589d8 2810 /*! @brief Set the SYNCEN3 field to a new value. */
Kojto 90:cb3d968589d8 2811 #define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
Kojto 90:cb3d968589d8 2812 /*@}*/
Kojto 90:cb3d968589d8 2813
Kojto 90:cb3d968589d8 2814 /*!
Kojto 90:cb3d968589d8 2815 * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
Kojto 90:cb3d968589d8 2816 *
Kojto 90:cb3d968589d8 2817 * Enables the fault control in channels (n) and (n+1). This field is write
Kojto 90:cb3d968589d8 2818 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2819 *
Kojto 90:cb3d968589d8 2820 * Values:
Kojto 90:cb3d968589d8 2821 * - 0 - The fault control in this pair of channels is disabled.
Kojto 90:cb3d968589d8 2822 * - 1 - The fault control in this pair of channels is enabled.
Kojto 90:cb3d968589d8 2823 */
Kojto 90:cb3d968589d8 2824 /*@{*/
Kojto 90:cb3d968589d8 2825 #define BP_FTM_COMBINE_FAULTEN3 (30U) /*!< Bit position for FTM_COMBINE_FAULTEN3. */
Kojto 90:cb3d968589d8 2826 #define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /*!< Bit mask for FTM_COMBINE_FAULTEN3. */
Kojto 90:cb3d968589d8 2827 #define BS_FTM_COMBINE_FAULTEN3 (1U) /*!< Bit field size in bits for FTM_COMBINE_FAULTEN3. */
Kojto 90:cb3d968589d8 2828
Kojto 90:cb3d968589d8 2829 /*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
Kojto 90:cb3d968589d8 2830 #define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
Kojto 90:cb3d968589d8 2831
Kojto 90:cb3d968589d8 2832 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. */
Kojto 90:cb3d968589d8 2833 #define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3)
Kojto 90:cb3d968589d8 2834
Kojto 90:cb3d968589d8 2835 /*! @brief Set the FAULTEN3 field to a new value. */
Kojto 90:cb3d968589d8 2836 #define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
Kojto 90:cb3d968589d8 2837 /*@}*/
Kojto 90:cb3d968589d8 2838
Kojto 90:cb3d968589d8 2839 /*******************************************************************************
Kojto 90:cb3d968589d8 2840 * HW_FTM_DEADTIME - Deadtime Insertion Control
Kojto 90:cb3d968589d8 2841 ******************************************************************************/
Kojto 90:cb3d968589d8 2842
Kojto 90:cb3d968589d8 2843 /*!
Kojto 90:cb3d968589d8 2844 * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
Kojto 90:cb3d968589d8 2845 *
Kojto 90:cb3d968589d8 2846 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 2847 *
Kojto 90:cb3d968589d8 2848 * This register selects the deadtime prescaler factor and deadtime value. All
Kojto 90:cb3d968589d8 2849 * FTM channels use this clock prescaler and this deadtime value for the deadtime
Kojto 90:cb3d968589d8 2850 * insertion.
Kojto 90:cb3d968589d8 2851 */
Kojto 90:cb3d968589d8 2852 typedef union _hw_ftm_deadtime
Kojto 90:cb3d968589d8 2853 {
Kojto 90:cb3d968589d8 2854 uint32_t U;
Kojto 90:cb3d968589d8 2855 struct _hw_ftm_deadtime_bitfields
Kojto 90:cb3d968589d8 2856 {
Kojto 90:cb3d968589d8 2857 uint32_t DTVAL : 6; /*!< [5:0] Deadtime Value */
Kojto 90:cb3d968589d8 2858 uint32_t DTPS : 2; /*!< [7:6] Deadtime Prescaler Value */
Kojto 90:cb3d968589d8 2859 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 2860 } B;
Kojto 90:cb3d968589d8 2861 } hw_ftm_deadtime_t;
Kojto 90:cb3d968589d8 2862
Kojto 90:cb3d968589d8 2863 /*!
Kojto 90:cb3d968589d8 2864 * @name Constants and macros for entire FTM_DEADTIME register
Kojto 90:cb3d968589d8 2865 */
Kojto 90:cb3d968589d8 2866 /*@{*/
Kojto 90:cb3d968589d8 2867 #define HW_FTM_DEADTIME_ADDR(x) ((x) + 0x68U)
Kojto 90:cb3d968589d8 2868
Kojto 90:cb3d968589d8 2869 #define HW_FTM_DEADTIME(x) (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
Kojto 90:cb3d968589d8 2870 #define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
Kojto 90:cb3d968589d8 2871 #define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
Kojto 90:cb3d968589d8 2872 #define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) | (v)))
Kojto 90:cb3d968589d8 2873 #define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 2874 #define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 2875 /*@}*/
Kojto 90:cb3d968589d8 2876
Kojto 90:cb3d968589d8 2877 /*
Kojto 90:cb3d968589d8 2878 * Constants & macros for individual FTM_DEADTIME bitfields
Kojto 90:cb3d968589d8 2879 */
Kojto 90:cb3d968589d8 2880
Kojto 90:cb3d968589d8 2881 /*!
Kojto 90:cb3d968589d8 2882 * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
Kojto 90:cb3d968589d8 2883 *
Kojto 90:cb3d968589d8 2884 * Selects the deadtime insertion value for the deadtime counter. The deadtime
Kojto 90:cb3d968589d8 2885 * counter is clocked by a scaled version of the system clock. See the description
Kojto 90:cb3d968589d8 2886 * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
Kojto 90:cb3d968589d8 2887 * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
Kojto 90:cb3d968589d8 2888 * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
Kojto 90:cb3d968589d8 2889 * This pattern continues up to a possible 63 counts. This field is write
Kojto 90:cb3d968589d8 2890 * protected. It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2891 */
Kojto 90:cb3d968589d8 2892 /*@{*/
Kojto 90:cb3d968589d8 2893 #define BP_FTM_DEADTIME_DTVAL (0U) /*!< Bit position for FTM_DEADTIME_DTVAL. */
Kojto 90:cb3d968589d8 2894 #define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /*!< Bit mask for FTM_DEADTIME_DTVAL. */
Kojto 90:cb3d968589d8 2895 #define BS_FTM_DEADTIME_DTVAL (6U) /*!< Bit field size in bits for FTM_DEADTIME_DTVAL. */
Kojto 90:cb3d968589d8 2896
Kojto 90:cb3d968589d8 2897 /*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
Kojto 90:cb3d968589d8 2898 #define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
Kojto 90:cb3d968589d8 2899
Kojto 90:cb3d968589d8 2900 /*! @brief Format value for bitfield FTM_DEADTIME_DTVAL. */
Kojto 90:cb3d968589d8 2901 #define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL)
Kojto 90:cb3d968589d8 2902
Kojto 90:cb3d968589d8 2903 /*! @brief Set the DTVAL field to a new value. */
Kojto 90:cb3d968589d8 2904 #define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
Kojto 90:cb3d968589d8 2905 /*@}*/
Kojto 90:cb3d968589d8 2906
Kojto 90:cb3d968589d8 2907 /*!
Kojto 90:cb3d968589d8 2908 * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
Kojto 90:cb3d968589d8 2909 *
Kojto 90:cb3d968589d8 2910 * Selects the division factor of the system clock. This prescaled clock is used
Kojto 90:cb3d968589d8 2911 * by the deadtime counter. This field is write protected. It can be written
Kojto 90:cb3d968589d8 2912 * only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 2913 *
Kojto 90:cb3d968589d8 2914 * Values:
Kojto 90:cb3d968589d8 2915 * - 0x - Divide the system clock by 1.
Kojto 90:cb3d968589d8 2916 * - 10 - Divide the system clock by 4.
Kojto 90:cb3d968589d8 2917 * - 11 - Divide the system clock by 16.
Kojto 90:cb3d968589d8 2918 */
Kojto 90:cb3d968589d8 2919 /*@{*/
Kojto 90:cb3d968589d8 2920 #define BP_FTM_DEADTIME_DTPS (6U) /*!< Bit position for FTM_DEADTIME_DTPS. */
Kojto 90:cb3d968589d8 2921 #define BM_FTM_DEADTIME_DTPS (0x000000C0U) /*!< Bit mask for FTM_DEADTIME_DTPS. */
Kojto 90:cb3d968589d8 2922 #define BS_FTM_DEADTIME_DTPS (2U) /*!< Bit field size in bits for FTM_DEADTIME_DTPS. */
Kojto 90:cb3d968589d8 2923
Kojto 90:cb3d968589d8 2924 /*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
Kojto 90:cb3d968589d8 2925 #define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
Kojto 90:cb3d968589d8 2926
Kojto 90:cb3d968589d8 2927 /*! @brief Format value for bitfield FTM_DEADTIME_DTPS. */
Kojto 90:cb3d968589d8 2928 #define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS)
Kojto 90:cb3d968589d8 2929
Kojto 90:cb3d968589d8 2930 /*! @brief Set the DTPS field to a new value. */
Kojto 90:cb3d968589d8 2931 #define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
Kojto 90:cb3d968589d8 2932 /*@}*/
Kojto 90:cb3d968589d8 2933
Kojto 90:cb3d968589d8 2934 /*******************************************************************************
Kojto 90:cb3d968589d8 2935 * HW_FTM_EXTTRIG - FTM External Trigger
Kojto 90:cb3d968589d8 2936 ******************************************************************************/
Kojto 90:cb3d968589d8 2937
Kojto 90:cb3d968589d8 2938 /*!
Kojto 90:cb3d968589d8 2939 * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
Kojto 90:cb3d968589d8 2940 *
Kojto 90:cb3d968589d8 2941 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 2942 *
Kojto 90:cb3d968589d8 2943 * This register: Indicates when a channel trigger was generated Enables the
Kojto 90:cb3d968589d8 2944 * generation of a trigger when the FTM counter is equal to its initial value
Kojto 90:cb3d968589d8 2945 * Selects which channels are used in the generation of the channel triggers Several
Kojto 90:cb3d968589d8 2946 * channels can be selected to generate multiple triggers in one PWM period.
Kojto 90:cb3d968589d8 2947 * Channels 6 and 7 are not used to generate channel triggers.
Kojto 90:cb3d968589d8 2948 */
Kojto 90:cb3d968589d8 2949 typedef union _hw_ftm_exttrig
Kojto 90:cb3d968589d8 2950 {
Kojto 90:cb3d968589d8 2951 uint32_t U;
Kojto 90:cb3d968589d8 2952 struct _hw_ftm_exttrig_bitfields
Kojto 90:cb3d968589d8 2953 {
Kojto 90:cb3d968589d8 2954 uint32_t CH2TRIG : 1; /*!< [0] Channel 2 Trigger Enable */
Kojto 90:cb3d968589d8 2955 uint32_t CH3TRIG : 1; /*!< [1] Channel 3 Trigger Enable */
Kojto 90:cb3d968589d8 2956 uint32_t CH4TRIG : 1; /*!< [2] Channel 4 Trigger Enable */
Kojto 90:cb3d968589d8 2957 uint32_t CH5TRIG : 1; /*!< [3] Channel 5 Trigger Enable */
Kojto 90:cb3d968589d8 2958 uint32_t CH0TRIG : 1; /*!< [4] Channel 0 Trigger Enable */
Kojto 90:cb3d968589d8 2959 uint32_t CH1TRIG : 1; /*!< [5] Channel 1 Trigger Enable */
Kojto 90:cb3d968589d8 2960 uint32_t INITTRIGEN : 1; /*!< [6] Initialization Trigger Enable */
Kojto 90:cb3d968589d8 2961 uint32_t TRIGF : 1; /*!< [7] Channel Trigger Flag */
Kojto 90:cb3d968589d8 2962 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 2963 } B;
Kojto 90:cb3d968589d8 2964 } hw_ftm_exttrig_t;
Kojto 90:cb3d968589d8 2965
Kojto 90:cb3d968589d8 2966 /*!
Kojto 90:cb3d968589d8 2967 * @name Constants and macros for entire FTM_EXTTRIG register
Kojto 90:cb3d968589d8 2968 */
Kojto 90:cb3d968589d8 2969 /*@{*/
Kojto 90:cb3d968589d8 2970 #define HW_FTM_EXTTRIG_ADDR(x) ((x) + 0x6CU)
Kojto 90:cb3d968589d8 2971
Kojto 90:cb3d968589d8 2972 #define HW_FTM_EXTTRIG(x) (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
Kojto 90:cb3d968589d8 2973 #define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
Kojto 90:cb3d968589d8 2974 #define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
Kojto 90:cb3d968589d8 2975 #define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) | (v)))
Kojto 90:cb3d968589d8 2976 #define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 2977 #define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 2978 /*@}*/
Kojto 90:cb3d968589d8 2979
Kojto 90:cb3d968589d8 2980 /*
Kojto 90:cb3d968589d8 2981 * Constants & macros for individual FTM_EXTTRIG bitfields
Kojto 90:cb3d968589d8 2982 */
Kojto 90:cb3d968589d8 2983
Kojto 90:cb3d968589d8 2984 /*!
Kojto 90:cb3d968589d8 2985 * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
Kojto 90:cb3d968589d8 2986 *
Kojto 90:cb3d968589d8 2987 * Enables the generation of the channel trigger when the FTM counter is equal
Kojto 90:cb3d968589d8 2988 * to the CnV register.
Kojto 90:cb3d968589d8 2989 *
Kojto 90:cb3d968589d8 2990 * Values:
Kojto 90:cb3d968589d8 2991 * - 0 - The generation of the channel trigger is disabled.
Kojto 90:cb3d968589d8 2992 * - 1 - The generation of the channel trigger is enabled.
Kojto 90:cb3d968589d8 2993 */
Kojto 90:cb3d968589d8 2994 /*@{*/
Kojto 90:cb3d968589d8 2995 #define BP_FTM_EXTTRIG_CH2TRIG (0U) /*!< Bit position for FTM_EXTTRIG_CH2TRIG. */
Kojto 90:cb3d968589d8 2996 #define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /*!< Bit mask for FTM_EXTTRIG_CH2TRIG. */
Kojto 90:cb3d968589d8 2997 #define BS_FTM_EXTTRIG_CH2TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. */
Kojto 90:cb3d968589d8 2998
Kojto 90:cb3d968589d8 2999 /*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
Kojto 90:cb3d968589d8 3000 #define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
Kojto 90:cb3d968589d8 3001
Kojto 90:cb3d968589d8 3002 /*! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. */
Kojto 90:cb3d968589d8 3003 #define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG)
Kojto 90:cb3d968589d8 3004
Kojto 90:cb3d968589d8 3005 /*! @brief Set the CH2TRIG field to a new value. */
Kojto 90:cb3d968589d8 3006 #define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
Kojto 90:cb3d968589d8 3007 /*@}*/
Kojto 90:cb3d968589d8 3008
Kojto 90:cb3d968589d8 3009 /*!
Kojto 90:cb3d968589d8 3010 * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
Kojto 90:cb3d968589d8 3011 *
Kojto 90:cb3d968589d8 3012 * Enables the generation of the channel trigger when the FTM counter is equal
Kojto 90:cb3d968589d8 3013 * to the CnV register.
Kojto 90:cb3d968589d8 3014 *
Kojto 90:cb3d968589d8 3015 * Values:
Kojto 90:cb3d968589d8 3016 * - 0 - The generation of the channel trigger is disabled.
Kojto 90:cb3d968589d8 3017 * - 1 - The generation of the channel trigger is enabled.
Kojto 90:cb3d968589d8 3018 */
Kojto 90:cb3d968589d8 3019 /*@{*/
Kojto 90:cb3d968589d8 3020 #define BP_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit position for FTM_EXTTRIG_CH3TRIG. */
Kojto 90:cb3d968589d8 3021 #define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /*!< Bit mask for FTM_EXTTRIG_CH3TRIG. */
Kojto 90:cb3d968589d8 3022 #define BS_FTM_EXTTRIG_CH3TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. */
Kojto 90:cb3d968589d8 3023
Kojto 90:cb3d968589d8 3024 /*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
Kojto 90:cb3d968589d8 3025 #define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
Kojto 90:cb3d968589d8 3026
Kojto 90:cb3d968589d8 3027 /*! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. */
Kojto 90:cb3d968589d8 3028 #define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG)
Kojto 90:cb3d968589d8 3029
Kojto 90:cb3d968589d8 3030 /*! @brief Set the CH3TRIG field to a new value. */
Kojto 90:cb3d968589d8 3031 #define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
Kojto 90:cb3d968589d8 3032 /*@}*/
Kojto 90:cb3d968589d8 3033
Kojto 90:cb3d968589d8 3034 /*!
Kojto 90:cb3d968589d8 3035 * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
Kojto 90:cb3d968589d8 3036 *
Kojto 90:cb3d968589d8 3037 * Enables the generation of the channel trigger when the FTM counter is equal
Kojto 90:cb3d968589d8 3038 * to the CnV register.
Kojto 90:cb3d968589d8 3039 *
Kojto 90:cb3d968589d8 3040 * Values:
Kojto 90:cb3d968589d8 3041 * - 0 - The generation of the channel trigger is disabled.
Kojto 90:cb3d968589d8 3042 * - 1 - The generation of the channel trigger is enabled.
Kojto 90:cb3d968589d8 3043 */
Kojto 90:cb3d968589d8 3044 /*@{*/
Kojto 90:cb3d968589d8 3045 #define BP_FTM_EXTTRIG_CH4TRIG (2U) /*!< Bit position for FTM_EXTTRIG_CH4TRIG. */
Kojto 90:cb3d968589d8 3046 #define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /*!< Bit mask for FTM_EXTTRIG_CH4TRIG. */
Kojto 90:cb3d968589d8 3047 #define BS_FTM_EXTTRIG_CH4TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. */
Kojto 90:cb3d968589d8 3048
Kojto 90:cb3d968589d8 3049 /*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
Kojto 90:cb3d968589d8 3050 #define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
Kojto 90:cb3d968589d8 3051
Kojto 90:cb3d968589d8 3052 /*! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. */
Kojto 90:cb3d968589d8 3053 #define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG)
Kojto 90:cb3d968589d8 3054
Kojto 90:cb3d968589d8 3055 /*! @brief Set the CH4TRIG field to a new value. */
Kojto 90:cb3d968589d8 3056 #define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
Kojto 90:cb3d968589d8 3057 /*@}*/
Kojto 90:cb3d968589d8 3058
Kojto 90:cb3d968589d8 3059 /*!
Kojto 90:cb3d968589d8 3060 * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
Kojto 90:cb3d968589d8 3061 *
Kojto 90:cb3d968589d8 3062 * Enables the generation of the channel trigger when the FTM counter is equal
Kojto 90:cb3d968589d8 3063 * to the CnV register.
Kojto 90:cb3d968589d8 3064 *
Kojto 90:cb3d968589d8 3065 * Values:
Kojto 90:cb3d968589d8 3066 * - 0 - The generation of the channel trigger is disabled.
Kojto 90:cb3d968589d8 3067 * - 1 - The generation of the channel trigger is enabled.
Kojto 90:cb3d968589d8 3068 */
Kojto 90:cb3d968589d8 3069 /*@{*/
Kojto 90:cb3d968589d8 3070 #define BP_FTM_EXTTRIG_CH5TRIG (3U) /*!< Bit position for FTM_EXTTRIG_CH5TRIG. */
Kojto 90:cb3d968589d8 3071 #define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /*!< Bit mask for FTM_EXTTRIG_CH5TRIG. */
Kojto 90:cb3d968589d8 3072 #define BS_FTM_EXTTRIG_CH5TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. */
Kojto 90:cb3d968589d8 3073
Kojto 90:cb3d968589d8 3074 /*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
Kojto 90:cb3d968589d8 3075 #define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
Kojto 90:cb3d968589d8 3076
Kojto 90:cb3d968589d8 3077 /*! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. */
Kojto 90:cb3d968589d8 3078 #define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG)
Kojto 90:cb3d968589d8 3079
Kojto 90:cb3d968589d8 3080 /*! @brief Set the CH5TRIG field to a new value. */
Kojto 90:cb3d968589d8 3081 #define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
Kojto 90:cb3d968589d8 3082 /*@}*/
Kojto 90:cb3d968589d8 3083
Kojto 90:cb3d968589d8 3084 /*!
Kojto 90:cb3d968589d8 3085 * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
Kojto 90:cb3d968589d8 3086 *
Kojto 90:cb3d968589d8 3087 * Enables the generation of the channel trigger when the FTM counter is equal
Kojto 90:cb3d968589d8 3088 * to the CnV register.
Kojto 90:cb3d968589d8 3089 *
Kojto 90:cb3d968589d8 3090 * Values:
Kojto 90:cb3d968589d8 3091 * - 0 - The generation of the channel trigger is disabled.
Kojto 90:cb3d968589d8 3092 * - 1 - The generation of the channel trigger is enabled.
Kojto 90:cb3d968589d8 3093 */
Kojto 90:cb3d968589d8 3094 /*@{*/
Kojto 90:cb3d968589d8 3095 #define BP_FTM_EXTTRIG_CH0TRIG (4U) /*!< Bit position for FTM_EXTTRIG_CH0TRIG. */
Kojto 90:cb3d968589d8 3096 #define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /*!< Bit mask for FTM_EXTTRIG_CH0TRIG. */
Kojto 90:cb3d968589d8 3097 #define BS_FTM_EXTTRIG_CH0TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. */
Kojto 90:cb3d968589d8 3098
Kojto 90:cb3d968589d8 3099 /*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
Kojto 90:cb3d968589d8 3100 #define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
Kojto 90:cb3d968589d8 3101
Kojto 90:cb3d968589d8 3102 /*! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. */
Kojto 90:cb3d968589d8 3103 #define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG)
Kojto 90:cb3d968589d8 3104
Kojto 90:cb3d968589d8 3105 /*! @brief Set the CH0TRIG field to a new value. */
Kojto 90:cb3d968589d8 3106 #define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
Kojto 90:cb3d968589d8 3107 /*@}*/
Kojto 90:cb3d968589d8 3108
Kojto 90:cb3d968589d8 3109 /*!
Kojto 90:cb3d968589d8 3110 * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
Kojto 90:cb3d968589d8 3111 *
Kojto 90:cb3d968589d8 3112 * Enables the generation of the channel trigger when the FTM counter is equal
Kojto 90:cb3d968589d8 3113 * to the CnV register.
Kojto 90:cb3d968589d8 3114 *
Kojto 90:cb3d968589d8 3115 * Values:
Kojto 90:cb3d968589d8 3116 * - 0 - The generation of the channel trigger is disabled.
Kojto 90:cb3d968589d8 3117 * - 1 - The generation of the channel trigger is enabled.
Kojto 90:cb3d968589d8 3118 */
Kojto 90:cb3d968589d8 3119 /*@{*/
Kojto 90:cb3d968589d8 3120 #define BP_FTM_EXTTRIG_CH1TRIG (5U) /*!< Bit position for FTM_EXTTRIG_CH1TRIG. */
Kojto 90:cb3d968589d8 3121 #define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /*!< Bit mask for FTM_EXTTRIG_CH1TRIG. */
Kojto 90:cb3d968589d8 3122 #define BS_FTM_EXTTRIG_CH1TRIG (1U) /*!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. */
Kojto 90:cb3d968589d8 3123
Kojto 90:cb3d968589d8 3124 /*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
Kojto 90:cb3d968589d8 3125 #define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
Kojto 90:cb3d968589d8 3126
Kojto 90:cb3d968589d8 3127 /*! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. */
Kojto 90:cb3d968589d8 3128 #define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG)
Kojto 90:cb3d968589d8 3129
Kojto 90:cb3d968589d8 3130 /*! @brief Set the CH1TRIG field to a new value. */
Kojto 90:cb3d968589d8 3131 #define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
Kojto 90:cb3d968589d8 3132 /*@}*/
Kojto 90:cb3d968589d8 3133
Kojto 90:cb3d968589d8 3134 /*!
Kojto 90:cb3d968589d8 3135 * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
Kojto 90:cb3d968589d8 3136 *
Kojto 90:cb3d968589d8 3137 * Enables the generation of the trigger when the FTM counter is equal to the
Kojto 90:cb3d968589d8 3138 * CNTIN register.
Kojto 90:cb3d968589d8 3139 *
Kojto 90:cb3d968589d8 3140 * Values:
Kojto 90:cb3d968589d8 3141 * - 0 - The generation of initialization trigger is disabled.
Kojto 90:cb3d968589d8 3142 * - 1 - The generation of initialization trigger is enabled.
Kojto 90:cb3d968589d8 3143 */
Kojto 90:cb3d968589d8 3144 /*@{*/
Kojto 90:cb3d968589d8 3145 #define BP_FTM_EXTTRIG_INITTRIGEN (6U) /*!< Bit position for FTM_EXTTRIG_INITTRIGEN. */
Kojto 90:cb3d968589d8 3146 #define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /*!< Bit mask for FTM_EXTTRIG_INITTRIGEN. */
Kojto 90:cb3d968589d8 3147 #define BS_FTM_EXTTRIG_INITTRIGEN (1U) /*!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. */
Kojto 90:cb3d968589d8 3148
Kojto 90:cb3d968589d8 3149 /*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
Kojto 90:cb3d968589d8 3150 #define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
Kojto 90:cb3d968589d8 3151
Kojto 90:cb3d968589d8 3152 /*! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. */
Kojto 90:cb3d968589d8 3153 #define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN)
Kojto 90:cb3d968589d8 3154
Kojto 90:cb3d968589d8 3155 /*! @brief Set the INITTRIGEN field to a new value. */
Kojto 90:cb3d968589d8 3156 #define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
Kojto 90:cb3d968589d8 3157 /*@}*/
Kojto 90:cb3d968589d8 3158
Kojto 90:cb3d968589d8 3159 /*!
Kojto 90:cb3d968589d8 3160 * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
Kojto 90:cb3d968589d8 3161 *
Kojto 90:cb3d968589d8 3162 * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
Kojto 90:cb3d968589d8 3163 * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
Kojto 90:cb3d968589d8 3164 * has no effect. If another channel trigger is generated before the clearing
Kojto 90:cb3d968589d8 3165 * sequence is completed, the sequence is reset so TRIGF remains set after the clear
Kojto 90:cb3d968589d8 3166 * sequence is completed for the earlier TRIGF.
Kojto 90:cb3d968589d8 3167 *
Kojto 90:cb3d968589d8 3168 * Values:
Kojto 90:cb3d968589d8 3169 * - 0 - No channel trigger was generated.
Kojto 90:cb3d968589d8 3170 * - 1 - A channel trigger was generated.
Kojto 90:cb3d968589d8 3171 */
Kojto 90:cb3d968589d8 3172 /*@{*/
Kojto 90:cb3d968589d8 3173 #define BP_FTM_EXTTRIG_TRIGF (7U) /*!< Bit position for FTM_EXTTRIG_TRIGF. */
Kojto 90:cb3d968589d8 3174 #define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /*!< Bit mask for FTM_EXTTRIG_TRIGF. */
Kojto 90:cb3d968589d8 3175 #define BS_FTM_EXTTRIG_TRIGF (1U) /*!< Bit field size in bits for FTM_EXTTRIG_TRIGF. */
Kojto 90:cb3d968589d8 3176
Kojto 90:cb3d968589d8 3177 /*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
Kojto 90:cb3d968589d8 3178 #define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
Kojto 90:cb3d968589d8 3179
Kojto 90:cb3d968589d8 3180 /*! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. */
Kojto 90:cb3d968589d8 3181 #define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF)
Kojto 90:cb3d968589d8 3182
Kojto 90:cb3d968589d8 3183 /*! @brief Set the TRIGF field to a new value. */
Kojto 90:cb3d968589d8 3184 #define BW_FTM_EXTTRIG_TRIGF(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF) = (v))
Kojto 90:cb3d968589d8 3185 /*@}*/
Kojto 90:cb3d968589d8 3186
Kojto 90:cb3d968589d8 3187 /*******************************************************************************
Kojto 90:cb3d968589d8 3188 * HW_FTM_POL - Channels Polarity
Kojto 90:cb3d968589d8 3189 ******************************************************************************/
Kojto 90:cb3d968589d8 3190
Kojto 90:cb3d968589d8 3191 /*!
Kojto 90:cb3d968589d8 3192 * @brief HW_FTM_POL - Channels Polarity (RW)
Kojto 90:cb3d968589d8 3193 *
Kojto 90:cb3d968589d8 3194 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 3195 *
Kojto 90:cb3d968589d8 3196 * This register defines the output polarity of the FTM channels. The safe value
Kojto 90:cb3d968589d8 3197 * that is driven in a channel output when the fault control is enabled and a
Kojto 90:cb3d968589d8 3198 * fault condition is detected is the inactive state of the channel. That is, the
Kojto 90:cb3d968589d8 3199 * safe value of a channel is the value of its POL bit.
Kojto 90:cb3d968589d8 3200 */
Kojto 90:cb3d968589d8 3201 typedef union _hw_ftm_pol
Kojto 90:cb3d968589d8 3202 {
Kojto 90:cb3d968589d8 3203 uint32_t U;
Kojto 90:cb3d968589d8 3204 struct _hw_ftm_pol_bitfields
Kojto 90:cb3d968589d8 3205 {
Kojto 90:cb3d968589d8 3206 uint32_t POL0 : 1; /*!< [0] Channel 0 Polarity */
Kojto 90:cb3d968589d8 3207 uint32_t POL1 : 1; /*!< [1] Channel 1 Polarity */
Kojto 90:cb3d968589d8 3208 uint32_t POL2 : 1; /*!< [2] Channel 2 Polarity */
Kojto 90:cb3d968589d8 3209 uint32_t POL3 : 1; /*!< [3] Channel 3 Polarity */
Kojto 90:cb3d968589d8 3210 uint32_t POL4 : 1; /*!< [4] Channel 4 Polarity */
Kojto 90:cb3d968589d8 3211 uint32_t POL5 : 1; /*!< [5] Channel 5 Polarity */
Kojto 90:cb3d968589d8 3212 uint32_t POL6 : 1; /*!< [6] Channel 6 Polarity */
Kojto 90:cb3d968589d8 3213 uint32_t POL7 : 1; /*!< [7] Channel 7 Polarity */
Kojto 90:cb3d968589d8 3214 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 3215 } B;
Kojto 90:cb3d968589d8 3216 } hw_ftm_pol_t;
Kojto 90:cb3d968589d8 3217
Kojto 90:cb3d968589d8 3218 /*!
Kojto 90:cb3d968589d8 3219 * @name Constants and macros for entire FTM_POL register
Kojto 90:cb3d968589d8 3220 */
Kojto 90:cb3d968589d8 3221 /*@{*/
Kojto 90:cb3d968589d8 3222 #define HW_FTM_POL_ADDR(x) ((x) + 0x70U)
Kojto 90:cb3d968589d8 3223
Kojto 90:cb3d968589d8 3224 #define HW_FTM_POL(x) (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
Kojto 90:cb3d968589d8 3225 #define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
Kojto 90:cb3d968589d8 3226 #define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
Kojto 90:cb3d968589d8 3227 #define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) | (v)))
Kojto 90:cb3d968589d8 3228 #define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 3229 #define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 3230 /*@}*/
Kojto 90:cb3d968589d8 3231
Kojto 90:cb3d968589d8 3232 /*
Kojto 90:cb3d968589d8 3233 * Constants & macros for individual FTM_POL bitfields
Kojto 90:cb3d968589d8 3234 */
Kojto 90:cb3d968589d8 3235
Kojto 90:cb3d968589d8 3236 /*!
Kojto 90:cb3d968589d8 3237 * @name Register FTM_POL, field POL0[0] (RW)
Kojto 90:cb3d968589d8 3238 *
Kojto 90:cb3d968589d8 3239 * Defines the polarity of the channel output. This field is write protected. It
Kojto 90:cb3d968589d8 3240 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3241 *
Kojto 90:cb3d968589d8 3242 * Values:
Kojto 90:cb3d968589d8 3243 * - 0 - The channel polarity is active high.
Kojto 90:cb3d968589d8 3244 * - 1 - The channel polarity is active low.
Kojto 90:cb3d968589d8 3245 */
Kojto 90:cb3d968589d8 3246 /*@{*/
Kojto 90:cb3d968589d8 3247 #define BP_FTM_POL_POL0 (0U) /*!< Bit position for FTM_POL_POL0. */
Kojto 90:cb3d968589d8 3248 #define BM_FTM_POL_POL0 (0x00000001U) /*!< Bit mask for FTM_POL_POL0. */
Kojto 90:cb3d968589d8 3249 #define BS_FTM_POL_POL0 (1U) /*!< Bit field size in bits for FTM_POL_POL0. */
Kojto 90:cb3d968589d8 3250
Kojto 90:cb3d968589d8 3251 /*! @brief Read current value of the FTM_POL_POL0 field. */
Kojto 90:cb3d968589d8 3252 #define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
Kojto 90:cb3d968589d8 3253
Kojto 90:cb3d968589d8 3254 /*! @brief Format value for bitfield FTM_POL_POL0. */
Kojto 90:cb3d968589d8 3255 #define BF_FTM_POL_POL0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0)
Kojto 90:cb3d968589d8 3256
Kojto 90:cb3d968589d8 3257 /*! @brief Set the POL0 field to a new value. */
Kojto 90:cb3d968589d8 3258 #define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
Kojto 90:cb3d968589d8 3259 /*@}*/
Kojto 90:cb3d968589d8 3260
Kojto 90:cb3d968589d8 3261 /*!
Kojto 90:cb3d968589d8 3262 * @name Register FTM_POL, field POL1[1] (RW)
Kojto 90:cb3d968589d8 3263 *
Kojto 90:cb3d968589d8 3264 * Defines the polarity of the channel output. This field is write protected. It
Kojto 90:cb3d968589d8 3265 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3266 *
Kojto 90:cb3d968589d8 3267 * Values:
Kojto 90:cb3d968589d8 3268 * - 0 - The channel polarity is active high.
Kojto 90:cb3d968589d8 3269 * - 1 - The channel polarity is active low.
Kojto 90:cb3d968589d8 3270 */
Kojto 90:cb3d968589d8 3271 /*@{*/
Kojto 90:cb3d968589d8 3272 #define BP_FTM_POL_POL1 (1U) /*!< Bit position for FTM_POL_POL1. */
Kojto 90:cb3d968589d8 3273 #define BM_FTM_POL_POL1 (0x00000002U) /*!< Bit mask for FTM_POL_POL1. */
Kojto 90:cb3d968589d8 3274 #define BS_FTM_POL_POL1 (1U) /*!< Bit field size in bits for FTM_POL_POL1. */
Kojto 90:cb3d968589d8 3275
Kojto 90:cb3d968589d8 3276 /*! @brief Read current value of the FTM_POL_POL1 field. */
Kojto 90:cb3d968589d8 3277 #define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
Kojto 90:cb3d968589d8 3278
Kojto 90:cb3d968589d8 3279 /*! @brief Format value for bitfield FTM_POL_POL1. */
Kojto 90:cb3d968589d8 3280 #define BF_FTM_POL_POL1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1)
Kojto 90:cb3d968589d8 3281
Kojto 90:cb3d968589d8 3282 /*! @brief Set the POL1 field to a new value. */
Kojto 90:cb3d968589d8 3283 #define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
Kojto 90:cb3d968589d8 3284 /*@}*/
Kojto 90:cb3d968589d8 3285
Kojto 90:cb3d968589d8 3286 /*!
Kojto 90:cb3d968589d8 3287 * @name Register FTM_POL, field POL2[2] (RW)
Kojto 90:cb3d968589d8 3288 *
Kojto 90:cb3d968589d8 3289 * Defines the polarity of the channel output. This field is write protected. It
Kojto 90:cb3d968589d8 3290 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3291 *
Kojto 90:cb3d968589d8 3292 * Values:
Kojto 90:cb3d968589d8 3293 * - 0 - The channel polarity is active high.
Kojto 90:cb3d968589d8 3294 * - 1 - The channel polarity is active low.
Kojto 90:cb3d968589d8 3295 */
Kojto 90:cb3d968589d8 3296 /*@{*/
Kojto 90:cb3d968589d8 3297 #define BP_FTM_POL_POL2 (2U) /*!< Bit position for FTM_POL_POL2. */
Kojto 90:cb3d968589d8 3298 #define BM_FTM_POL_POL2 (0x00000004U) /*!< Bit mask for FTM_POL_POL2. */
Kojto 90:cb3d968589d8 3299 #define BS_FTM_POL_POL2 (1U) /*!< Bit field size in bits for FTM_POL_POL2. */
Kojto 90:cb3d968589d8 3300
Kojto 90:cb3d968589d8 3301 /*! @brief Read current value of the FTM_POL_POL2 field. */
Kojto 90:cb3d968589d8 3302 #define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
Kojto 90:cb3d968589d8 3303
Kojto 90:cb3d968589d8 3304 /*! @brief Format value for bitfield FTM_POL_POL2. */
Kojto 90:cb3d968589d8 3305 #define BF_FTM_POL_POL2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2)
Kojto 90:cb3d968589d8 3306
Kojto 90:cb3d968589d8 3307 /*! @brief Set the POL2 field to a new value. */
Kojto 90:cb3d968589d8 3308 #define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
Kojto 90:cb3d968589d8 3309 /*@}*/
Kojto 90:cb3d968589d8 3310
Kojto 90:cb3d968589d8 3311 /*!
Kojto 90:cb3d968589d8 3312 * @name Register FTM_POL, field POL3[3] (RW)
Kojto 90:cb3d968589d8 3313 *
Kojto 90:cb3d968589d8 3314 * Defines the polarity of the channel output. This field is write protected. It
Kojto 90:cb3d968589d8 3315 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3316 *
Kojto 90:cb3d968589d8 3317 * Values:
Kojto 90:cb3d968589d8 3318 * - 0 - The channel polarity is active high.
Kojto 90:cb3d968589d8 3319 * - 1 - The channel polarity is active low.
Kojto 90:cb3d968589d8 3320 */
Kojto 90:cb3d968589d8 3321 /*@{*/
Kojto 90:cb3d968589d8 3322 #define BP_FTM_POL_POL3 (3U) /*!< Bit position for FTM_POL_POL3. */
Kojto 90:cb3d968589d8 3323 #define BM_FTM_POL_POL3 (0x00000008U) /*!< Bit mask for FTM_POL_POL3. */
Kojto 90:cb3d968589d8 3324 #define BS_FTM_POL_POL3 (1U) /*!< Bit field size in bits for FTM_POL_POL3. */
Kojto 90:cb3d968589d8 3325
Kojto 90:cb3d968589d8 3326 /*! @brief Read current value of the FTM_POL_POL3 field. */
Kojto 90:cb3d968589d8 3327 #define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
Kojto 90:cb3d968589d8 3328
Kojto 90:cb3d968589d8 3329 /*! @brief Format value for bitfield FTM_POL_POL3. */
Kojto 90:cb3d968589d8 3330 #define BF_FTM_POL_POL3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3)
Kojto 90:cb3d968589d8 3331
Kojto 90:cb3d968589d8 3332 /*! @brief Set the POL3 field to a new value. */
Kojto 90:cb3d968589d8 3333 #define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
Kojto 90:cb3d968589d8 3334 /*@}*/
Kojto 90:cb3d968589d8 3335
Kojto 90:cb3d968589d8 3336 /*!
Kojto 90:cb3d968589d8 3337 * @name Register FTM_POL, field POL4[4] (RW)
Kojto 90:cb3d968589d8 3338 *
Kojto 90:cb3d968589d8 3339 * Defines the polarity of the channel output. This field is write protected. It
Kojto 90:cb3d968589d8 3340 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3341 *
Kojto 90:cb3d968589d8 3342 * Values:
Kojto 90:cb3d968589d8 3343 * - 0 - The channel polarity is active high.
Kojto 90:cb3d968589d8 3344 * - 1 - The channel polarity is active low.
Kojto 90:cb3d968589d8 3345 */
Kojto 90:cb3d968589d8 3346 /*@{*/
Kojto 90:cb3d968589d8 3347 #define BP_FTM_POL_POL4 (4U) /*!< Bit position for FTM_POL_POL4. */
Kojto 90:cb3d968589d8 3348 #define BM_FTM_POL_POL4 (0x00000010U) /*!< Bit mask for FTM_POL_POL4. */
Kojto 90:cb3d968589d8 3349 #define BS_FTM_POL_POL4 (1U) /*!< Bit field size in bits for FTM_POL_POL4. */
Kojto 90:cb3d968589d8 3350
Kojto 90:cb3d968589d8 3351 /*! @brief Read current value of the FTM_POL_POL4 field. */
Kojto 90:cb3d968589d8 3352 #define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
Kojto 90:cb3d968589d8 3353
Kojto 90:cb3d968589d8 3354 /*! @brief Format value for bitfield FTM_POL_POL4. */
Kojto 90:cb3d968589d8 3355 #define BF_FTM_POL_POL4(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4)
Kojto 90:cb3d968589d8 3356
Kojto 90:cb3d968589d8 3357 /*! @brief Set the POL4 field to a new value. */
Kojto 90:cb3d968589d8 3358 #define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
Kojto 90:cb3d968589d8 3359 /*@}*/
Kojto 90:cb3d968589d8 3360
Kojto 90:cb3d968589d8 3361 /*!
Kojto 90:cb3d968589d8 3362 * @name Register FTM_POL, field POL5[5] (RW)
Kojto 90:cb3d968589d8 3363 *
Kojto 90:cb3d968589d8 3364 * Defines the polarity of the channel output. This field is write protected. It
Kojto 90:cb3d968589d8 3365 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3366 *
Kojto 90:cb3d968589d8 3367 * Values:
Kojto 90:cb3d968589d8 3368 * - 0 - The channel polarity is active high.
Kojto 90:cb3d968589d8 3369 * - 1 - The channel polarity is active low.
Kojto 90:cb3d968589d8 3370 */
Kojto 90:cb3d968589d8 3371 /*@{*/
Kojto 90:cb3d968589d8 3372 #define BP_FTM_POL_POL5 (5U) /*!< Bit position for FTM_POL_POL5. */
Kojto 90:cb3d968589d8 3373 #define BM_FTM_POL_POL5 (0x00000020U) /*!< Bit mask for FTM_POL_POL5. */
Kojto 90:cb3d968589d8 3374 #define BS_FTM_POL_POL5 (1U) /*!< Bit field size in bits for FTM_POL_POL5. */
Kojto 90:cb3d968589d8 3375
Kojto 90:cb3d968589d8 3376 /*! @brief Read current value of the FTM_POL_POL5 field. */
Kojto 90:cb3d968589d8 3377 #define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
Kojto 90:cb3d968589d8 3378
Kojto 90:cb3d968589d8 3379 /*! @brief Format value for bitfield FTM_POL_POL5. */
Kojto 90:cb3d968589d8 3380 #define BF_FTM_POL_POL5(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5)
Kojto 90:cb3d968589d8 3381
Kojto 90:cb3d968589d8 3382 /*! @brief Set the POL5 field to a new value. */
Kojto 90:cb3d968589d8 3383 #define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
Kojto 90:cb3d968589d8 3384 /*@}*/
Kojto 90:cb3d968589d8 3385
Kojto 90:cb3d968589d8 3386 /*!
Kojto 90:cb3d968589d8 3387 * @name Register FTM_POL, field POL6[6] (RW)
Kojto 90:cb3d968589d8 3388 *
Kojto 90:cb3d968589d8 3389 * Defines the polarity of the channel output. This field is write protected. It
Kojto 90:cb3d968589d8 3390 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3391 *
Kojto 90:cb3d968589d8 3392 * Values:
Kojto 90:cb3d968589d8 3393 * - 0 - The channel polarity is active high.
Kojto 90:cb3d968589d8 3394 * - 1 - The channel polarity is active low.
Kojto 90:cb3d968589d8 3395 */
Kojto 90:cb3d968589d8 3396 /*@{*/
Kojto 90:cb3d968589d8 3397 #define BP_FTM_POL_POL6 (6U) /*!< Bit position for FTM_POL_POL6. */
Kojto 90:cb3d968589d8 3398 #define BM_FTM_POL_POL6 (0x00000040U) /*!< Bit mask for FTM_POL_POL6. */
Kojto 90:cb3d968589d8 3399 #define BS_FTM_POL_POL6 (1U) /*!< Bit field size in bits for FTM_POL_POL6. */
Kojto 90:cb3d968589d8 3400
Kojto 90:cb3d968589d8 3401 /*! @brief Read current value of the FTM_POL_POL6 field. */
Kojto 90:cb3d968589d8 3402 #define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
Kojto 90:cb3d968589d8 3403
Kojto 90:cb3d968589d8 3404 /*! @brief Format value for bitfield FTM_POL_POL6. */
Kojto 90:cb3d968589d8 3405 #define BF_FTM_POL_POL6(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6)
Kojto 90:cb3d968589d8 3406
Kojto 90:cb3d968589d8 3407 /*! @brief Set the POL6 field to a new value. */
Kojto 90:cb3d968589d8 3408 #define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
Kojto 90:cb3d968589d8 3409 /*@}*/
Kojto 90:cb3d968589d8 3410
Kojto 90:cb3d968589d8 3411 /*!
Kojto 90:cb3d968589d8 3412 * @name Register FTM_POL, field POL7[7] (RW)
Kojto 90:cb3d968589d8 3413 *
Kojto 90:cb3d968589d8 3414 * Defines the polarity of the channel output. This field is write protected. It
Kojto 90:cb3d968589d8 3415 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3416 *
Kojto 90:cb3d968589d8 3417 * Values:
Kojto 90:cb3d968589d8 3418 * - 0 - The channel polarity is active high.
Kojto 90:cb3d968589d8 3419 * - 1 - The channel polarity is active low.
Kojto 90:cb3d968589d8 3420 */
Kojto 90:cb3d968589d8 3421 /*@{*/
Kojto 90:cb3d968589d8 3422 #define BP_FTM_POL_POL7 (7U) /*!< Bit position for FTM_POL_POL7. */
Kojto 90:cb3d968589d8 3423 #define BM_FTM_POL_POL7 (0x00000080U) /*!< Bit mask for FTM_POL_POL7. */
Kojto 90:cb3d968589d8 3424 #define BS_FTM_POL_POL7 (1U) /*!< Bit field size in bits for FTM_POL_POL7. */
Kojto 90:cb3d968589d8 3425
Kojto 90:cb3d968589d8 3426 /*! @brief Read current value of the FTM_POL_POL7 field. */
Kojto 90:cb3d968589d8 3427 #define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
Kojto 90:cb3d968589d8 3428
Kojto 90:cb3d968589d8 3429 /*! @brief Format value for bitfield FTM_POL_POL7. */
Kojto 90:cb3d968589d8 3430 #define BF_FTM_POL_POL7(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7)
Kojto 90:cb3d968589d8 3431
Kojto 90:cb3d968589d8 3432 /*! @brief Set the POL7 field to a new value. */
Kojto 90:cb3d968589d8 3433 #define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
Kojto 90:cb3d968589d8 3434 /*@}*/
Kojto 90:cb3d968589d8 3435
Kojto 90:cb3d968589d8 3436 /*******************************************************************************
Kojto 90:cb3d968589d8 3437 * HW_FTM_FMS - Fault Mode Status
Kojto 90:cb3d968589d8 3438 ******************************************************************************/
Kojto 90:cb3d968589d8 3439
Kojto 90:cb3d968589d8 3440 /*!
Kojto 90:cb3d968589d8 3441 * @brief HW_FTM_FMS - Fault Mode Status (RW)
Kojto 90:cb3d968589d8 3442 *
Kojto 90:cb3d968589d8 3443 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 3444 *
Kojto 90:cb3d968589d8 3445 * This register contains the fault detection flags, write protection enable
Kojto 90:cb3d968589d8 3446 * bit, and the logic OR of the enabled fault inputs.
Kojto 90:cb3d968589d8 3447 */
Kojto 90:cb3d968589d8 3448 typedef union _hw_ftm_fms
Kojto 90:cb3d968589d8 3449 {
Kojto 90:cb3d968589d8 3450 uint32_t U;
Kojto 90:cb3d968589d8 3451 struct _hw_ftm_fms_bitfields
Kojto 90:cb3d968589d8 3452 {
Kojto 90:cb3d968589d8 3453 uint32_t FAULTF0 : 1; /*!< [0] Fault Detection Flag 0 */
Kojto 90:cb3d968589d8 3454 uint32_t FAULTF1 : 1; /*!< [1] Fault Detection Flag 1 */
Kojto 90:cb3d968589d8 3455 uint32_t FAULTF2 : 1; /*!< [2] Fault Detection Flag 2 */
Kojto 90:cb3d968589d8 3456 uint32_t FAULTF3 : 1; /*!< [3] Fault Detection Flag 3 */
Kojto 90:cb3d968589d8 3457 uint32_t RESERVED0 : 1; /*!< [4] */
Kojto 90:cb3d968589d8 3458 uint32_t FAULTIN : 1; /*!< [5] Fault Inputs */
Kojto 90:cb3d968589d8 3459 uint32_t WPEN : 1; /*!< [6] Write Protection Enable */
Kojto 90:cb3d968589d8 3460 uint32_t FAULTF : 1; /*!< [7] Fault Detection Flag */
Kojto 90:cb3d968589d8 3461 uint32_t RESERVED1 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 3462 } B;
Kojto 90:cb3d968589d8 3463 } hw_ftm_fms_t;
Kojto 90:cb3d968589d8 3464
Kojto 90:cb3d968589d8 3465 /*!
Kojto 90:cb3d968589d8 3466 * @name Constants and macros for entire FTM_FMS register
Kojto 90:cb3d968589d8 3467 */
Kojto 90:cb3d968589d8 3468 /*@{*/
Kojto 90:cb3d968589d8 3469 #define HW_FTM_FMS_ADDR(x) ((x) + 0x74U)
Kojto 90:cb3d968589d8 3470
Kojto 90:cb3d968589d8 3471 #define HW_FTM_FMS(x) (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
Kojto 90:cb3d968589d8 3472 #define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
Kojto 90:cb3d968589d8 3473 #define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
Kojto 90:cb3d968589d8 3474 #define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) | (v)))
Kojto 90:cb3d968589d8 3475 #define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 3476 #define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 3477 /*@}*/
Kojto 90:cb3d968589d8 3478
Kojto 90:cb3d968589d8 3479 /*
Kojto 90:cb3d968589d8 3480 * Constants & macros for individual FTM_FMS bitfields
Kojto 90:cb3d968589d8 3481 */
Kojto 90:cb3d968589d8 3482
Kojto 90:cb3d968589d8 3483 /*!
Kojto 90:cb3d968589d8 3484 * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
Kojto 90:cb3d968589d8 3485 *
Kojto 90:cb3d968589d8 3486 * Set by hardware when fault control is enabled, the corresponding fault input
Kojto 90:cb3d968589d8 3487 * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
Kojto 90:cb3d968589d8 3488 * by reading the FMS register while FAULTF0 is set and then writing a 0 to
Kojto 90:cb3d968589d8 3489 * FAULTF0 while there is no existing fault condition at the corresponding fault
Kojto 90:cb3d968589d8 3490 * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
Kojto 90:cb3d968589d8 3491 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
Kojto 90:cb3d968589d8 3492 * fault input before the clearing sequence is completed, the sequence is reset
Kojto 90:cb3d968589d8 3493 * so FAULTF0 remains set after the clearing sequence is completed for the
Kojto 90:cb3d968589d8 3494 * earlier fault condition.
Kojto 90:cb3d968589d8 3495 *
Kojto 90:cb3d968589d8 3496 * Values:
Kojto 90:cb3d968589d8 3497 * - 0 - No fault condition was detected at the fault input.
Kojto 90:cb3d968589d8 3498 * - 1 - A fault condition was detected at the fault input.
Kojto 90:cb3d968589d8 3499 */
Kojto 90:cb3d968589d8 3500 /*@{*/
Kojto 90:cb3d968589d8 3501 #define BP_FTM_FMS_FAULTF0 (0U) /*!< Bit position for FTM_FMS_FAULTF0. */
Kojto 90:cb3d968589d8 3502 #define BM_FTM_FMS_FAULTF0 (0x00000001U) /*!< Bit mask for FTM_FMS_FAULTF0. */
Kojto 90:cb3d968589d8 3503 #define BS_FTM_FMS_FAULTF0 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF0. */
Kojto 90:cb3d968589d8 3504
Kojto 90:cb3d968589d8 3505 /*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
Kojto 90:cb3d968589d8 3506 #define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
Kojto 90:cb3d968589d8 3507
Kojto 90:cb3d968589d8 3508 /*! @brief Format value for bitfield FTM_FMS_FAULTF0. */
Kojto 90:cb3d968589d8 3509 #define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0)
Kojto 90:cb3d968589d8 3510
Kojto 90:cb3d968589d8 3511 /*! @brief Set the FAULTF0 field to a new value. */
Kojto 90:cb3d968589d8 3512 #define BW_FTM_FMS_FAULTF0(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0) = (v))
Kojto 90:cb3d968589d8 3513 /*@}*/
Kojto 90:cb3d968589d8 3514
Kojto 90:cb3d968589d8 3515 /*!
Kojto 90:cb3d968589d8 3516 * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
Kojto 90:cb3d968589d8 3517 *
Kojto 90:cb3d968589d8 3518 * Set by hardware when fault control is enabled, the corresponding fault input
Kojto 90:cb3d968589d8 3519 * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
Kojto 90:cb3d968589d8 3520 * by reading the FMS register while FAULTF1 is set and then writing a 0 to
Kojto 90:cb3d968589d8 3521 * FAULTF1 while there is no existing fault condition at the corresponding fault
Kojto 90:cb3d968589d8 3522 * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
Kojto 90:cb3d968589d8 3523 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
Kojto 90:cb3d968589d8 3524 * fault input before the clearing sequence is completed, the sequence is reset
Kojto 90:cb3d968589d8 3525 * so FAULTF1 remains set after the clearing sequence is completed for the
Kojto 90:cb3d968589d8 3526 * earlier fault condition.
Kojto 90:cb3d968589d8 3527 *
Kojto 90:cb3d968589d8 3528 * Values:
Kojto 90:cb3d968589d8 3529 * - 0 - No fault condition was detected at the fault input.
Kojto 90:cb3d968589d8 3530 * - 1 - A fault condition was detected at the fault input.
Kojto 90:cb3d968589d8 3531 */
Kojto 90:cb3d968589d8 3532 /*@{*/
Kojto 90:cb3d968589d8 3533 #define BP_FTM_FMS_FAULTF1 (1U) /*!< Bit position for FTM_FMS_FAULTF1. */
Kojto 90:cb3d968589d8 3534 #define BM_FTM_FMS_FAULTF1 (0x00000002U) /*!< Bit mask for FTM_FMS_FAULTF1. */
Kojto 90:cb3d968589d8 3535 #define BS_FTM_FMS_FAULTF1 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF1. */
Kojto 90:cb3d968589d8 3536
Kojto 90:cb3d968589d8 3537 /*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
Kojto 90:cb3d968589d8 3538 #define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
Kojto 90:cb3d968589d8 3539
Kojto 90:cb3d968589d8 3540 /*! @brief Format value for bitfield FTM_FMS_FAULTF1. */
Kojto 90:cb3d968589d8 3541 #define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1)
Kojto 90:cb3d968589d8 3542
Kojto 90:cb3d968589d8 3543 /*! @brief Set the FAULTF1 field to a new value. */
Kojto 90:cb3d968589d8 3544 #define BW_FTM_FMS_FAULTF1(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1) = (v))
Kojto 90:cb3d968589d8 3545 /*@}*/
Kojto 90:cb3d968589d8 3546
Kojto 90:cb3d968589d8 3547 /*!
Kojto 90:cb3d968589d8 3548 * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
Kojto 90:cb3d968589d8 3549 *
Kojto 90:cb3d968589d8 3550 * Set by hardware when fault control is enabled, the corresponding fault input
Kojto 90:cb3d968589d8 3551 * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
Kojto 90:cb3d968589d8 3552 * by reading the FMS register while FAULTF2 is set and then writing a 0 to
Kojto 90:cb3d968589d8 3553 * FAULTF2 while there is no existing fault condition at the corresponding fault
Kojto 90:cb3d968589d8 3554 * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
Kojto 90:cb3d968589d8 3555 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
Kojto 90:cb3d968589d8 3556 * fault input before the clearing sequence is completed, the sequence is reset
Kojto 90:cb3d968589d8 3557 * so FAULTF2 remains set after the clearing sequence is completed for the
Kojto 90:cb3d968589d8 3558 * earlier fault condition.
Kojto 90:cb3d968589d8 3559 *
Kojto 90:cb3d968589d8 3560 * Values:
Kojto 90:cb3d968589d8 3561 * - 0 - No fault condition was detected at the fault input.
Kojto 90:cb3d968589d8 3562 * - 1 - A fault condition was detected at the fault input.
Kojto 90:cb3d968589d8 3563 */
Kojto 90:cb3d968589d8 3564 /*@{*/
Kojto 90:cb3d968589d8 3565 #define BP_FTM_FMS_FAULTF2 (2U) /*!< Bit position for FTM_FMS_FAULTF2. */
Kojto 90:cb3d968589d8 3566 #define BM_FTM_FMS_FAULTF2 (0x00000004U) /*!< Bit mask for FTM_FMS_FAULTF2. */
Kojto 90:cb3d968589d8 3567 #define BS_FTM_FMS_FAULTF2 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF2. */
Kojto 90:cb3d968589d8 3568
Kojto 90:cb3d968589d8 3569 /*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
Kojto 90:cb3d968589d8 3570 #define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
Kojto 90:cb3d968589d8 3571
Kojto 90:cb3d968589d8 3572 /*! @brief Format value for bitfield FTM_FMS_FAULTF2. */
Kojto 90:cb3d968589d8 3573 #define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2)
Kojto 90:cb3d968589d8 3574
Kojto 90:cb3d968589d8 3575 /*! @brief Set the FAULTF2 field to a new value. */
Kojto 90:cb3d968589d8 3576 #define BW_FTM_FMS_FAULTF2(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2) = (v))
Kojto 90:cb3d968589d8 3577 /*@}*/
Kojto 90:cb3d968589d8 3578
Kojto 90:cb3d968589d8 3579 /*!
Kojto 90:cb3d968589d8 3580 * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
Kojto 90:cb3d968589d8 3581 *
Kojto 90:cb3d968589d8 3582 * Set by hardware when fault control is enabled, the corresponding fault input
Kojto 90:cb3d968589d8 3583 * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
Kojto 90:cb3d968589d8 3584 * by reading the FMS register while FAULTF3 is set and then writing a 0 to
Kojto 90:cb3d968589d8 3585 * FAULTF3 while there is no existing fault condition at the corresponding fault
Kojto 90:cb3d968589d8 3586 * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
Kojto 90:cb3d968589d8 3587 * FAULTF bit is cleared. If another fault condition is detected at the corresponding
Kojto 90:cb3d968589d8 3588 * fault input before the clearing sequence is completed, the sequence is reset
Kojto 90:cb3d968589d8 3589 * so FAULTF3 remains set after the clearing sequence is completed for the
Kojto 90:cb3d968589d8 3590 * earlier fault condition.
Kojto 90:cb3d968589d8 3591 *
Kojto 90:cb3d968589d8 3592 * Values:
Kojto 90:cb3d968589d8 3593 * - 0 - No fault condition was detected at the fault input.
Kojto 90:cb3d968589d8 3594 * - 1 - A fault condition was detected at the fault input.
Kojto 90:cb3d968589d8 3595 */
Kojto 90:cb3d968589d8 3596 /*@{*/
Kojto 90:cb3d968589d8 3597 #define BP_FTM_FMS_FAULTF3 (3U) /*!< Bit position for FTM_FMS_FAULTF3. */
Kojto 90:cb3d968589d8 3598 #define BM_FTM_FMS_FAULTF3 (0x00000008U) /*!< Bit mask for FTM_FMS_FAULTF3. */
Kojto 90:cb3d968589d8 3599 #define BS_FTM_FMS_FAULTF3 (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF3. */
Kojto 90:cb3d968589d8 3600
Kojto 90:cb3d968589d8 3601 /*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
Kojto 90:cb3d968589d8 3602 #define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
Kojto 90:cb3d968589d8 3603
Kojto 90:cb3d968589d8 3604 /*! @brief Format value for bitfield FTM_FMS_FAULTF3. */
Kojto 90:cb3d968589d8 3605 #define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3)
Kojto 90:cb3d968589d8 3606
Kojto 90:cb3d968589d8 3607 /*! @brief Set the FAULTF3 field to a new value. */
Kojto 90:cb3d968589d8 3608 #define BW_FTM_FMS_FAULTF3(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3) = (v))
Kojto 90:cb3d968589d8 3609 /*@}*/
Kojto 90:cb3d968589d8 3610
Kojto 90:cb3d968589d8 3611 /*!
Kojto 90:cb3d968589d8 3612 * @name Register FTM_FMS, field FAULTIN[5] (RO)
Kojto 90:cb3d968589d8 3613 *
Kojto 90:cb3d968589d8 3614 * Represents the logic OR of the enabled fault inputs after their filter (if
Kojto 90:cb3d968589d8 3615 * their filter is enabled) when fault control is enabled.
Kojto 90:cb3d968589d8 3616 *
Kojto 90:cb3d968589d8 3617 * Values:
Kojto 90:cb3d968589d8 3618 * - 0 - The logic OR of the enabled fault inputs is 0.
Kojto 90:cb3d968589d8 3619 * - 1 - The logic OR of the enabled fault inputs is 1.
Kojto 90:cb3d968589d8 3620 */
Kojto 90:cb3d968589d8 3621 /*@{*/
Kojto 90:cb3d968589d8 3622 #define BP_FTM_FMS_FAULTIN (5U) /*!< Bit position for FTM_FMS_FAULTIN. */
Kojto 90:cb3d968589d8 3623 #define BM_FTM_FMS_FAULTIN (0x00000020U) /*!< Bit mask for FTM_FMS_FAULTIN. */
Kojto 90:cb3d968589d8 3624 #define BS_FTM_FMS_FAULTIN (1U) /*!< Bit field size in bits for FTM_FMS_FAULTIN. */
Kojto 90:cb3d968589d8 3625
Kojto 90:cb3d968589d8 3626 /*! @brief Read current value of the FTM_FMS_FAULTIN field. */
Kojto 90:cb3d968589d8 3627 #define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
Kojto 90:cb3d968589d8 3628 /*@}*/
Kojto 90:cb3d968589d8 3629
Kojto 90:cb3d968589d8 3630 /*!
Kojto 90:cb3d968589d8 3631 * @name Register FTM_FMS, field WPEN[6] (RW)
Kojto 90:cb3d968589d8 3632 *
Kojto 90:cb3d968589d8 3633 * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
Kojto 90:cb3d968589d8 3634 * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
Kojto 90:cb3d968589d8 3635 * WPDIS. Writing 0 to WPEN has no effect.
Kojto 90:cb3d968589d8 3636 *
Kojto 90:cb3d968589d8 3637 * Values:
Kojto 90:cb3d968589d8 3638 * - 0 - Write protection is disabled. Write protected bits can be written.
Kojto 90:cb3d968589d8 3639 * - 1 - Write protection is enabled. Write protected bits cannot be written.
Kojto 90:cb3d968589d8 3640 */
Kojto 90:cb3d968589d8 3641 /*@{*/
Kojto 90:cb3d968589d8 3642 #define BP_FTM_FMS_WPEN (6U) /*!< Bit position for FTM_FMS_WPEN. */
Kojto 90:cb3d968589d8 3643 #define BM_FTM_FMS_WPEN (0x00000040U) /*!< Bit mask for FTM_FMS_WPEN. */
Kojto 90:cb3d968589d8 3644 #define BS_FTM_FMS_WPEN (1U) /*!< Bit field size in bits for FTM_FMS_WPEN. */
Kojto 90:cb3d968589d8 3645
Kojto 90:cb3d968589d8 3646 /*! @brief Read current value of the FTM_FMS_WPEN field. */
Kojto 90:cb3d968589d8 3647 #define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
Kojto 90:cb3d968589d8 3648
Kojto 90:cb3d968589d8 3649 /*! @brief Format value for bitfield FTM_FMS_WPEN. */
Kojto 90:cb3d968589d8 3650 #define BF_FTM_FMS_WPEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN)
Kojto 90:cb3d968589d8 3651
Kojto 90:cb3d968589d8 3652 /*! @brief Set the WPEN field to a new value. */
Kojto 90:cb3d968589d8 3653 #define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
Kojto 90:cb3d968589d8 3654 /*@}*/
Kojto 90:cb3d968589d8 3655
Kojto 90:cb3d968589d8 3656 /*!
Kojto 90:cb3d968589d8 3657 * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
Kojto 90:cb3d968589d8 3658 *
Kojto 90:cb3d968589d8 3659 * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
Kojto 90:cb3d968589d8 3660 * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
Kojto 90:cb3d968589d8 3661 * a 0 to FAULTF while there is no existing fault condition at the enabled fault
Kojto 90:cb3d968589d8 3662 * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
Kojto 90:cb3d968589d8 3663 * detected in an enabled fault input before the clearing sequence is completed, the
Kojto 90:cb3d968589d8 3664 * sequence is reset so FAULTF remains set after the clearing sequence is
Kojto 90:cb3d968589d8 3665 * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
Kojto 90:cb3d968589d8 3666 * are cleared individually.
Kojto 90:cb3d968589d8 3667 *
Kojto 90:cb3d968589d8 3668 * Values:
Kojto 90:cb3d968589d8 3669 * - 0 - No fault condition was detected.
Kojto 90:cb3d968589d8 3670 * - 1 - A fault condition was detected.
Kojto 90:cb3d968589d8 3671 */
Kojto 90:cb3d968589d8 3672 /*@{*/
Kojto 90:cb3d968589d8 3673 #define BP_FTM_FMS_FAULTF (7U) /*!< Bit position for FTM_FMS_FAULTF. */
Kojto 90:cb3d968589d8 3674 #define BM_FTM_FMS_FAULTF (0x00000080U) /*!< Bit mask for FTM_FMS_FAULTF. */
Kojto 90:cb3d968589d8 3675 #define BS_FTM_FMS_FAULTF (1U) /*!< Bit field size in bits for FTM_FMS_FAULTF. */
Kojto 90:cb3d968589d8 3676
Kojto 90:cb3d968589d8 3677 /*! @brief Read current value of the FTM_FMS_FAULTF field. */
Kojto 90:cb3d968589d8 3678 #define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
Kojto 90:cb3d968589d8 3679
Kojto 90:cb3d968589d8 3680 /*! @brief Format value for bitfield FTM_FMS_FAULTF. */
Kojto 90:cb3d968589d8 3681 #define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF)
Kojto 90:cb3d968589d8 3682
Kojto 90:cb3d968589d8 3683 /*! @brief Set the FAULTF field to a new value. */
Kojto 90:cb3d968589d8 3684 #define BW_FTM_FMS_FAULTF(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF) = (v))
Kojto 90:cb3d968589d8 3685 /*@}*/
Kojto 90:cb3d968589d8 3686
Kojto 90:cb3d968589d8 3687 /*******************************************************************************
Kojto 90:cb3d968589d8 3688 * HW_FTM_FILTER - Input Capture Filter Control
Kojto 90:cb3d968589d8 3689 ******************************************************************************/
Kojto 90:cb3d968589d8 3690
Kojto 90:cb3d968589d8 3691 /*!
Kojto 90:cb3d968589d8 3692 * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
Kojto 90:cb3d968589d8 3693 *
Kojto 90:cb3d968589d8 3694 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 3695 *
Kojto 90:cb3d968589d8 3696 * This register selects the filter value for the inputs of channels. Channels
Kojto 90:cb3d968589d8 3697 * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
Kojto 90:cb3d968589d8 3698 * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
Kojto 90:cb3d968589d8 3699 * in input modes. Failure to do this could result in a missing valid signal.
Kojto 90:cb3d968589d8 3700 */
Kojto 90:cb3d968589d8 3701 typedef union _hw_ftm_filter
Kojto 90:cb3d968589d8 3702 {
Kojto 90:cb3d968589d8 3703 uint32_t U;
Kojto 90:cb3d968589d8 3704 struct _hw_ftm_filter_bitfields
Kojto 90:cb3d968589d8 3705 {
Kojto 90:cb3d968589d8 3706 uint32_t CH0FVAL : 4; /*!< [3:0] Channel 0 Input Filter */
Kojto 90:cb3d968589d8 3707 uint32_t CH1FVAL : 4; /*!< [7:4] Channel 1 Input Filter */
Kojto 90:cb3d968589d8 3708 uint32_t CH2FVAL : 4; /*!< [11:8] Channel 2 Input Filter */
Kojto 90:cb3d968589d8 3709 uint32_t CH3FVAL : 4; /*!< [15:12] Channel 3 Input Filter */
Kojto 90:cb3d968589d8 3710 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 3711 } B;
Kojto 90:cb3d968589d8 3712 } hw_ftm_filter_t;
Kojto 90:cb3d968589d8 3713
Kojto 90:cb3d968589d8 3714 /*!
Kojto 90:cb3d968589d8 3715 * @name Constants and macros for entire FTM_FILTER register
Kojto 90:cb3d968589d8 3716 */
Kojto 90:cb3d968589d8 3717 /*@{*/
Kojto 90:cb3d968589d8 3718 #define HW_FTM_FILTER_ADDR(x) ((x) + 0x78U)
Kojto 90:cb3d968589d8 3719
Kojto 90:cb3d968589d8 3720 #define HW_FTM_FILTER(x) (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
Kojto 90:cb3d968589d8 3721 #define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
Kojto 90:cb3d968589d8 3722 #define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
Kojto 90:cb3d968589d8 3723 #define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) | (v)))
Kojto 90:cb3d968589d8 3724 #define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 3725 #define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 3726 /*@}*/
Kojto 90:cb3d968589d8 3727
Kojto 90:cb3d968589d8 3728 /*
Kojto 90:cb3d968589d8 3729 * Constants & macros for individual FTM_FILTER bitfields
Kojto 90:cb3d968589d8 3730 */
Kojto 90:cb3d968589d8 3731
Kojto 90:cb3d968589d8 3732 /*!
Kojto 90:cb3d968589d8 3733 * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
Kojto 90:cb3d968589d8 3734 *
Kojto 90:cb3d968589d8 3735 * Selects the filter value for the channel input. The filter is disabled when
Kojto 90:cb3d968589d8 3736 * the value is zero.
Kojto 90:cb3d968589d8 3737 */
Kojto 90:cb3d968589d8 3738 /*@{*/
Kojto 90:cb3d968589d8 3739 #define BP_FTM_FILTER_CH0FVAL (0U) /*!< Bit position for FTM_FILTER_CH0FVAL. */
Kojto 90:cb3d968589d8 3740 #define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /*!< Bit mask for FTM_FILTER_CH0FVAL. */
Kojto 90:cb3d968589d8 3741 #define BS_FTM_FILTER_CH0FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH0FVAL. */
Kojto 90:cb3d968589d8 3742
Kojto 90:cb3d968589d8 3743 /*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
Kojto 90:cb3d968589d8 3744 #define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
Kojto 90:cb3d968589d8 3745
Kojto 90:cb3d968589d8 3746 /*! @brief Format value for bitfield FTM_FILTER_CH0FVAL. */
Kojto 90:cb3d968589d8 3747 #define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL)
Kojto 90:cb3d968589d8 3748
Kojto 90:cb3d968589d8 3749 /*! @brief Set the CH0FVAL field to a new value. */
Kojto 90:cb3d968589d8 3750 #define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
Kojto 90:cb3d968589d8 3751 /*@}*/
Kojto 90:cb3d968589d8 3752
Kojto 90:cb3d968589d8 3753 /*!
Kojto 90:cb3d968589d8 3754 * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
Kojto 90:cb3d968589d8 3755 *
Kojto 90:cb3d968589d8 3756 * Selects the filter value for the channel input. The filter is disabled when
Kojto 90:cb3d968589d8 3757 * the value is zero.
Kojto 90:cb3d968589d8 3758 */
Kojto 90:cb3d968589d8 3759 /*@{*/
Kojto 90:cb3d968589d8 3760 #define BP_FTM_FILTER_CH1FVAL (4U) /*!< Bit position for FTM_FILTER_CH1FVAL. */
Kojto 90:cb3d968589d8 3761 #define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /*!< Bit mask for FTM_FILTER_CH1FVAL. */
Kojto 90:cb3d968589d8 3762 #define BS_FTM_FILTER_CH1FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH1FVAL. */
Kojto 90:cb3d968589d8 3763
Kojto 90:cb3d968589d8 3764 /*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
Kojto 90:cb3d968589d8 3765 #define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
Kojto 90:cb3d968589d8 3766
Kojto 90:cb3d968589d8 3767 /*! @brief Format value for bitfield FTM_FILTER_CH1FVAL. */
Kojto 90:cb3d968589d8 3768 #define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL)
Kojto 90:cb3d968589d8 3769
Kojto 90:cb3d968589d8 3770 /*! @brief Set the CH1FVAL field to a new value. */
Kojto 90:cb3d968589d8 3771 #define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
Kojto 90:cb3d968589d8 3772 /*@}*/
Kojto 90:cb3d968589d8 3773
Kojto 90:cb3d968589d8 3774 /*!
Kojto 90:cb3d968589d8 3775 * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
Kojto 90:cb3d968589d8 3776 *
Kojto 90:cb3d968589d8 3777 * Selects the filter value for the channel input. The filter is disabled when
Kojto 90:cb3d968589d8 3778 * the value is zero.
Kojto 90:cb3d968589d8 3779 */
Kojto 90:cb3d968589d8 3780 /*@{*/
Kojto 90:cb3d968589d8 3781 #define BP_FTM_FILTER_CH2FVAL (8U) /*!< Bit position for FTM_FILTER_CH2FVAL. */
Kojto 90:cb3d968589d8 3782 #define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /*!< Bit mask for FTM_FILTER_CH2FVAL. */
Kojto 90:cb3d968589d8 3783 #define BS_FTM_FILTER_CH2FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH2FVAL. */
Kojto 90:cb3d968589d8 3784
Kojto 90:cb3d968589d8 3785 /*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
Kojto 90:cb3d968589d8 3786 #define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
Kojto 90:cb3d968589d8 3787
Kojto 90:cb3d968589d8 3788 /*! @brief Format value for bitfield FTM_FILTER_CH2FVAL. */
Kojto 90:cb3d968589d8 3789 #define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL)
Kojto 90:cb3d968589d8 3790
Kojto 90:cb3d968589d8 3791 /*! @brief Set the CH2FVAL field to a new value. */
Kojto 90:cb3d968589d8 3792 #define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
Kojto 90:cb3d968589d8 3793 /*@}*/
Kojto 90:cb3d968589d8 3794
Kojto 90:cb3d968589d8 3795 /*!
Kojto 90:cb3d968589d8 3796 * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
Kojto 90:cb3d968589d8 3797 *
Kojto 90:cb3d968589d8 3798 * Selects the filter value for the channel input. The filter is disabled when
Kojto 90:cb3d968589d8 3799 * the value is zero.
Kojto 90:cb3d968589d8 3800 */
Kojto 90:cb3d968589d8 3801 /*@{*/
Kojto 90:cb3d968589d8 3802 #define BP_FTM_FILTER_CH3FVAL (12U) /*!< Bit position for FTM_FILTER_CH3FVAL. */
Kojto 90:cb3d968589d8 3803 #define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /*!< Bit mask for FTM_FILTER_CH3FVAL. */
Kojto 90:cb3d968589d8 3804 #define BS_FTM_FILTER_CH3FVAL (4U) /*!< Bit field size in bits for FTM_FILTER_CH3FVAL. */
Kojto 90:cb3d968589d8 3805
Kojto 90:cb3d968589d8 3806 /*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
Kojto 90:cb3d968589d8 3807 #define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
Kojto 90:cb3d968589d8 3808
Kojto 90:cb3d968589d8 3809 /*! @brief Format value for bitfield FTM_FILTER_CH3FVAL. */
Kojto 90:cb3d968589d8 3810 #define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL)
Kojto 90:cb3d968589d8 3811
Kojto 90:cb3d968589d8 3812 /*! @brief Set the CH3FVAL field to a new value. */
Kojto 90:cb3d968589d8 3813 #define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
Kojto 90:cb3d968589d8 3814 /*@}*/
Kojto 90:cb3d968589d8 3815
Kojto 90:cb3d968589d8 3816 /*******************************************************************************
Kojto 90:cb3d968589d8 3817 * HW_FTM_FLTCTRL - Fault Control
Kojto 90:cb3d968589d8 3818 ******************************************************************************/
Kojto 90:cb3d968589d8 3819
Kojto 90:cb3d968589d8 3820 /*!
Kojto 90:cb3d968589d8 3821 * @brief HW_FTM_FLTCTRL - Fault Control (RW)
Kojto 90:cb3d968589d8 3822 *
Kojto 90:cb3d968589d8 3823 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 3824 *
Kojto 90:cb3d968589d8 3825 * This register selects the filter value for the fault inputs, enables the
Kojto 90:cb3d968589d8 3826 * fault inputs and the fault inputs filter.
Kojto 90:cb3d968589d8 3827 */
Kojto 90:cb3d968589d8 3828 typedef union _hw_ftm_fltctrl
Kojto 90:cb3d968589d8 3829 {
Kojto 90:cb3d968589d8 3830 uint32_t U;
Kojto 90:cb3d968589d8 3831 struct _hw_ftm_fltctrl_bitfields
Kojto 90:cb3d968589d8 3832 {
Kojto 90:cb3d968589d8 3833 uint32_t FAULT0EN : 1; /*!< [0] Fault Input 0 Enable */
Kojto 90:cb3d968589d8 3834 uint32_t FAULT1EN : 1; /*!< [1] Fault Input 1 Enable */
Kojto 90:cb3d968589d8 3835 uint32_t FAULT2EN : 1; /*!< [2] Fault Input 2 Enable */
Kojto 90:cb3d968589d8 3836 uint32_t FAULT3EN : 1; /*!< [3] Fault Input 3 Enable */
Kojto 90:cb3d968589d8 3837 uint32_t FFLTR0EN : 1; /*!< [4] Fault Input 0 Filter Enable */
Kojto 90:cb3d968589d8 3838 uint32_t FFLTR1EN : 1; /*!< [5] Fault Input 1 Filter Enable */
Kojto 90:cb3d968589d8 3839 uint32_t FFLTR2EN : 1; /*!< [6] Fault Input 2 Filter Enable */
Kojto 90:cb3d968589d8 3840 uint32_t FFLTR3EN : 1; /*!< [7] Fault Input 3 Filter Enable */
Kojto 90:cb3d968589d8 3841 uint32_t FFVAL : 4; /*!< [11:8] Fault Input Filter */
Kojto 90:cb3d968589d8 3842 uint32_t RESERVED0 : 20; /*!< [31:12] */
Kojto 90:cb3d968589d8 3843 } B;
Kojto 90:cb3d968589d8 3844 } hw_ftm_fltctrl_t;
Kojto 90:cb3d968589d8 3845
Kojto 90:cb3d968589d8 3846 /*!
Kojto 90:cb3d968589d8 3847 * @name Constants and macros for entire FTM_FLTCTRL register
Kojto 90:cb3d968589d8 3848 */
Kojto 90:cb3d968589d8 3849 /*@{*/
Kojto 90:cb3d968589d8 3850 #define HW_FTM_FLTCTRL_ADDR(x) ((x) + 0x7CU)
Kojto 90:cb3d968589d8 3851
Kojto 90:cb3d968589d8 3852 #define HW_FTM_FLTCTRL(x) (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
Kojto 90:cb3d968589d8 3853 #define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
Kojto 90:cb3d968589d8 3854 #define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
Kojto 90:cb3d968589d8 3855 #define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) | (v)))
Kojto 90:cb3d968589d8 3856 #define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 3857 #define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 3858 /*@}*/
Kojto 90:cb3d968589d8 3859
Kojto 90:cb3d968589d8 3860 /*
Kojto 90:cb3d968589d8 3861 * Constants & macros for individual FTM_FLTCTRL bitfields
Kojto 90:cb3d968589d8 3862 */
Kojto 90:cb3d968589d8 3863
Kojto 90:cb3d968589d8 3864 /*!
Kojto 90:cb3d968589d8 3865 * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
Kojto 90:cb3d968589d8 3866 *
Kojto 90:cb3d968589d8 3867 * Enables the fault input. This field is write protected. It can be written
Kojto 90:cb3d968589d8 3868 * only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3869 *
Kojto 90:cb3d968589d8 3870 * Values:
Kojto 90:cb3d968589d8 3871 * - 0 - Fault input is disabled.
Kojto 90:cb3d968589d8 3872 * - 1 - Fault input is enabled.
Kojto 90:cb3d968589d8 3873 */
Kojto 90:cb3d968589d8 3874 /*@{*/
Kojto 90:cb3d968589d8 3875 #define BP_FTM_FLTCTRL_FAULT0EN (0U) /*!< Bit position for FTM_FLTCTRL_FAULT0EN. */
Kojto 90:cb3d968589d8 3876 #define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /*!< Bit mask for FTM_FLTCTRL_FAULT0EN. */
Kojto 90:cb3d968589d8 3877 #define BS_FTM_FLTCTRL_FAULT0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. */
Kojto 90:cb3d968589d8 3878
Kojto 90:cb3d968589d8 3879 /*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
Kojto 90:cb3d968589d8 3880 #define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
Kojto 90:cb3d968589d8 3881
Kojto 90:cb3d968589d8 3882 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. */
Kojto 90:cb3d968589d8 3883 #define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN)
Kojto 90:cb3d968589d8 3884
Kojto 90:cb3d968589d8 3885 /*! @brief Set the FAULT0EN field to a new value. */
Kojto 90:cb3d968589d8 3886 #define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
Kojto 90:cb3d968589d8 3887 /*@}*/
Kojto 90:cb3d968589d8 3888
Kojto 90:cb3d968589d8 3889 /*!
Kojto 90:cb3d968589d8 3890 * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
Kojto 90:cb3d968589d8 3891 *
Kojto 90:cb3d968589d8 3892 * Enables the fault input. This field is write protected. It can be written
Kojto 90:cb3d968589d8 3893 * only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3894 *
Kojto 90:cb3d968589d8 3895 * Values:
Kojto 90:cb3d968589d8 3896 * - 0 - Fault input is disabled.
Kojto 90:cb3d968589d8 3897 * - 1 - Fault input is enabled.
Kojto 90:cb3d968589d8 3898 */
Kojto 90:cb3d968589d8 3899 /*@{*/
Kojto 90:cb3d968589d8 3900 #define BP_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit position for FTM_FLTCTRL_FAULT1EN. */
Kojto 90:cb3d968589d8 3901 #define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /*!< Bit mask for FTM_FLTCTRL_FAULT1EN. */
Kojto 90:cb3d968589d8 3902 #define BS_FTM_FLTCTRL_FAULT1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. */
Kojto 90:cb3d968589d8 3903
Kojto 90:cb3d968589d8 3904 /*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
Kojto 90:cb3d968589d8 3905 #define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
Kojto 90:cb3d968589d8 3906
Kojto 90:cb3d968589d8 3907 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. */
Kojto 90:cb3d968589d8 3908 #define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN)
Kojto 90:cb3d968589d8 3909
Kojto 90:cb3d968589d8 3910 /*! @brief Set the FAULT1EN field to a new value. */
Kojto 90:cb3d968589d8 3911 #define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
Kojto 90:cb3d968589d8 3912 /*@}*/
Kojto 90:cb3d968589d8 3913
Kojto 90:cb3d968589d8 3914 /*!
Kojto 90:cb3d968589d8 3915 * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
Kojto 90:cb3d968589d8 3916 *
Kojto 90:cb3d968589d8 3917 * Enables the fault input. This field is write protected. It can be written
Kojto 90:cb3d968589d8 3918 * only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3919 *
Kojto 90:cb3d968589d8 3920 * Values:
Kojto 90:cb3d968589d8 3921 * - 0 - Fault input is disabled.
Kojto 90:cb3d968589d8 3922 * - 1 - Fault input is enabled.
Kojto 90:cb3d968589d8 3923 */
Kojto 90:cb3d968589d8 3924 /*@{*/
Kojto 90:cb3d968589d8 3925 #define BP_FTM_FLTCTRL_FAULT2EN (2U) /*!< Bit position for FTM_FLTCTRL_FAULT2EN. */
Kojto 90:cb3d968589d8 3926 #define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /*!< Bit mask for FTM_FLTCTRL_FAULT2EN. */
Kojto 90:cb3d968589d8 3927 #define BS_FTM_FLTCTRL_FAULT2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. */
Kojto 90:cb3d968589d8 3928
Kojto 90:cb3d968589d8 3929 /*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
Kojto 90:cb3d968589d8 3930 #define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
Kojto 90:cb3d968589d8 3931
Kojto 90:cb3d968589d8 3932 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. */
Kojto 90:cb3d968589d8 3933 #define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN)
Kojto 90:cb3d968589d8 3934
Kojto 90:cb3d968589d8 3935 /*! @brief Set the FAULT2EN field to a new value. */
Kojto 90:cb3d968589d8 3936 #define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
Kojto 90:cb3d968589d8 3937 /*@}*/
Kojto 90:cb3d968589d8 3938
Kojto 90:cb3d968589d8 3939 /*!
Kojto 90:cb3d968589d8 3940 * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
Kojto 90:cb3d968589d8 3941 *
Kojto 90:cb3d968589d8 3942 * Enables the fault input. This field is write protected. It can be written
Kojto 90:cb3d968589d8 3943 * only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3944 *
Kojto 90:cb3d968589d8 3945 * Values:
Kojto 90:cb3d968589d8 3946 * - 0 - Fault input is disabled.
Kojto 90:cb3d968589d8 3947 * - 1 - Fault input is enabled.
Kojto 90:cb3d968589d8 3948 */
Kojto 90:cb3d968589d8 3949 /*@{*/
Kojto 90:cb3d968589d8 3950 #define BP_FTM_FLTCTRL_FAULT3EN (3U) /*!< Bit position for FTM_FLTCTRL_FAULT3EN. */
Kojto 90:cb3d968589d8 3951 #define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /*!< Bit mask for FTM_FLTCTRL_FAULT3EN. */
Kojto 90:cb3d968589d8 3952 #define BS_FTM_FLTCTRL_FAULT3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. */
Kojto 90:cb3d968589d8 3953
Kojto 90:cb3d968589d8 3954 /*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
Kojto 90:cb3d968589d8 3955 #define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
Kojto 90:cb3d968589d8 3956
Kojto 90:cb3d968589d8 3957 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. */
Kojto 90:cb3d968589d8 3958 #define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN)
Kojto 90:cb3d968589d8 3959
Kojto 90:cb3d968589d8 3960 /*! @brief Set the FAULT3EN field to a new value. */
Kojto 90:cb3d968589d8 3961 #define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
Kojto 90:cb3d968589d8 3962 /*@}*/
Kojto 90:cb3d968589d8 3963
Kojto 90:cb3d968589d8 3964 /*!
Kojto 90:cb3d968589d8 3965 * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
Kojto 90:cb3d968589d8 3966 *
Kojto 90:cb3d968589d8 3967 * Enables the filter for the fault input. This field is write protected. It can
Kojto 90:cb3d968589d8 3968 * be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3969 *
Kojto 90:cb3d968589d8 3970 * Values:
Kojto 90:cb3d968589d8 3971 * - 0 - Fault input filter is disabled.
Kojto 90:cb3d968589d8 3972 * - 1 - Fault input filter is enabled.
Kojto 90:cb3d968589d8 3973 */
Kojto 90:cb3d968589d8 3974 /*@{*/
Kojto 90:cb3d968589d8 3975 #define BP_FTM_FLTCTRL_FFLTR0EN (4U) /*!< Bit position for FTM_FLTCTRL_FFLTR0EN. */
Kojto 90:cb3d968589d8 3976 #define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /*!< Bit mask for FTM_FLTCTRL_FFLTR0EN. */
Kojto 90:cb3d968589d8 3977 #define BS_FTM_FLTCTRL_FFLTR0EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. */
Kojto 90:cb3d968589d8 3978
Kojto 90:cb3d968589d8 3979 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
Kojto 90:cb3d968589d8 3980 #define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
Kojto 90:cb3d968589d8 3981
Kojto 90:cb3d968589d8 3982 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. */
Kojto 90:cb3d968589d8 3983 #define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN)
Kojto 90:cb3d968589d8 3984
Kojto 90:cb3d968589d8 3985 /*! @brief Set the FFLTR0EN field to a new value. */
Kojto 90:cb3d968589d8 3986 #define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
Kojto 90:cb3d968589d8 3987 /*@}*/
Kojto 90:cb3d968589d8 3988
Kojto 90:cb3d968589d8 3989 /*!
Kojto 90:cb3d968589d8 3990 * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
Kojto 90:cb3d968589d8 3991 *
Kojto 90:cb3d968589d8 3992 * Enables the filter for the fault input. This field is write protected. It can
Kojto 90:cb3d968589d8 3993 * be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 3994 *
Kojto 90:cb3d968589d8 3995 * Values:
Kojto 90:cb3d968589d8 3996 * - 0 - Fault input filter is disabled.
Kojto 90:cb3d968589d8 3997 * - 1 - Fault input filter is enabled.
Kojto 90:cb3d968589d8 3998 */
Kojto 90:cb3d968589d8 3999 /*@{*/
Kojto 90:cb3d968589d8 4000 #define BP_FTM_FLTCTRL_FFLTR1EN (5U) /*!< Bit position for FTM_FLTCTRL_FFLTR1EN. */
Kojto 90:cb3d968589d8 4001 #define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /*!< Bit mask for FTM_FLTCTRL_FFLTR1EN. */
Kojto 90:cb3d968589d8 4002 #define BS_FTM_FLTCTRL_FFLTR1EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. */
Kojto 90:cb3d968589d8 4003
Kojto 90:cb3d968589d8 4004 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
Kojto 90:cb3d968589d8 4005 #define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
Kojto 90:cb3d968589d8 4006
Kojto 90:cb3d968589d8 4007 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. */
Kojto 90:cb3d968589d8 4008 #define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN)
Kojto 90:cb3d968589d8 4009
Kojto 90:cb3d968589d8 4010 /*! @brief Set the FFLTR1EN field to a new value. */
Kojto 90:cb3d968589d8 4011 #define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
Kojto 90:cb3d968589d8 4012 /*@}*/
Kojto 90:cb3d968589d8 4013
Kojto 90:cb3d968589d8 4014 /*!
Kojto 90:cb3d968589d8 4015 * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
Kojto 90:cb3d968589d8 4016 *
Kojto 90:cb3d968589d8 4017 * Enables the filter for the fault input. This field is write protected. It can
Kojto 90:cb3d968589d8 4018 * be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 4019 *
Kojto 90:cb3d968589d8 4020 * Values:
Kojto 90:cb3d968589d8 4021 * - 0 - Fault input filter is disabled.
Kojto 90:cb3d968589d8 4022 * - 1 - Fault input filter is enabled.
Kojto 90:cb3d968589d8 4023 */
Kojto 90:cb3d968589d8 4024 /*@{*/
Kojto 90:cb3d968589d8 4025 #define BP_FTM_FLTCTRL_FFLTR2EN (6U) /*!< Bit position for FTM_FLTCTRL_FFLTR2EN. */
Kojto 90:cb3d968589d8 4026 #define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /*!< Bit mask for FTM_FLTCTRL_FFLTR2EN. */
Kojto 90:cb3d968589d8 4027 #define BS_FTM_FLTCTRL_FFLTR2EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. */
Kojto 90:cb3d968589d8 4028
Kojto 90:cb3d968589d8 4029 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
Kojto 90:cb3d968589d8 4030 #define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
Kojto 90:cb3d968589d8 4031
Kojto 90:cb3d968589d8 4032 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. */
Kojto 90:cb3d968589d8 4033 #define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN)
Kojto 90:cb3d968589d8 4034
Kojto 90:cb3d968589d8 4035 /*! @brief Set the FFLTR2EN field to a new value. */
Kojto 90:cb3d968589d8 4036 #define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
Kojto 90:cb3d968589d8 4037 /*@}*/
Kojto 90:cb3d968589d8 4038
Kojto 90:cb3d968589d8 4039 /*!
Kojto 90:cb3d968589d8 4040 * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
Kojto 90:cb3d968589d8 4041 *
Kojto 90:cb3d968589d8 4042 * Enables the filter for the fault input. This field is write protected. It can
Kojto 90:cb3d968589d8 4043 * be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 4044 *
Kojto 90:cb3d968589d8 4045 * Values:
Kojto 90:cb3d968589d8 4046 * - 0 - Fault input filter is disabled.
Kojto 90:cb3d968589d8 4047 * - 1 - Fault input filter is enabled.
Kojto 90:cb3d968589d8 4048 */
Kojto 90:cb3d968589d8 4049 /*@{*/
Kojto 90:cb3d968589d8 4050 #define BP_FTM_FLTCTRL_FFLTR3EN (7U) /*!< Bit position for FTM_FLTCTRL_FFLTR3EN. */
Kojto 90:cb3d968589d8 4051 #define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /*!< Bit mask for FTM_FLTCTRL_FFLTR3EN. */
Kojto 90:cb3d968589d8 4052 #define BS_FTM_FLTCTRL_FFLTR3EN (1U) /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. */
Kojto 90:cb3d968589d8 4053
Kojto 90:cb3d968589d8 4054 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
Kojto 90:cb3d968589d8 4055 #define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
Kojto 90:cb3d968589d8 4056
Kojto 90:cb3d968589d8 4057 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. */
Kojto 90:cb3d968589d8 4058 #define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN)
Kojto 90:cb3d968589d8 4059
Kojto 90:cb3d968589d8 4060 /*! @brief Set the FFLTR3EN field to a new value. */
Kojto 90:cb3d968589d8 4061 #define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
Kojto 90:cb3d968589d8 4062 /*@}*/
Kojto 90:cb3d968589d8 4063
Kojto 90:cb3d968589d8 4064 /*!
Kojto 90:cb3d968589d8 4065 * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
Kojto 90:cb3d968589d8 4066 *
Kojto 90:cb3d968589d8 4067 * Selects the filter value for the fault inputs. The fault filter is disabled
Kojto 90:cb3d968589d8 4068 * when the value is zero. Writing to this field has immediate effect and must be
Kojto 90:cb3d968589d8 4069 * done only when the fault control or all fault inputs are disabled. Failure to
Kojto 90:cb3d968589d8 4070 * do this could result in a missing fault detection.
Kojto 90:cb3d968589d8 4071 */
Kojto 90:cb3d968589d8 4072 /*@{*/
Kojto 90:cb3d968589d8 4073 #define BP_FTM_FLTCTRL_FFVAL (8U) /*!< Bit position for FTM_FLTCTRL_FFVAL. */
Kojto 90:cb3d968589d8 4074 #define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /*!< Bit mask for FTM_FLTCTRL_FFVAL. */
Kojto 90:cb3d968589d8 4075 #define BS_FTM_FLTCTRL_FFVAL (4U) /*!< Bit field size in bits for FTM_FLTCTRL_FFVAL. */
Kojto 90:cb3d968589d8 4076
Kojto 90:cb3d968589d8 4077 /*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
Kojto 90:cb3d968589d8 4078 #define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
Kojto 90:cb3d968589d8 4079
Kojto 90:cb3d968589d8 4080 /*! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. */
Kojto 90:cb3d968589d8 4081 #define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL)
Kojto 90:cb3d968589d8 4082
Kojto 90:cb3d968589d8 4083 /*! @brief Set the FFVAL field to a new value. */
Kojto 90:cb3d968589d8 4084 #define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
Kojto 90:cb3d968589d8 4085 /*@}*/
Kojto 90:cb3d968589d8 4086
Kojto 90:cb3d968589d8 4087 /*******************************************************************************
Kojto 90:cb3d968589d8 4088 * HW_FTM_QDCTRL - Quadrature Decoder Control And Status
Kojto 90:cb3d968589d8 4089 ******************************************************************************/
Kojto 90:cb3d968589d8 4090
Kojto 90:cb3d968589d8 4091 /*!
Kojto 90:cb3d968589d8 4092 * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
Kojto 90:cb3d968589d8 4093 *
Kojto 90:cb3d968589d8 4094 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 4095 *
Kojto 90:cb3d968589d8 4096 * This register has the control and status bits for the Quadrature Decoder mode.
Kojto 90:cb3d968589d8 4097 */
Kojto 90:cb3d968589d8 4098 typedef union _hw_ftm_qdctrl
Kojto 90:cb3d968589d8 4099 {
Kojto 90:cb3d968589d8 4100 uint32_t U;
Kojto 90:cb3d968589d8 4101 struct _hw_ftm_qdctrl_bitfields
Kojto 90:cb3d968589d8 4102 {
Kojto 90:cb3d968589d8 4103 uint32_t QUADEN : 1; /*!< [0] Quadrature Decoder Mode Enable */
Kojto 90:cb3d968589d8 4104 uint32_t TOFDIR : 1; /*!< [1] Timer Overflow Direction In Quadrature
Kojto 90:cb3d968589d8 4105 * Decoder Mode */
Kojto 90:cb3d968589d8 4106 uint32_t QUADIR : 1; /*!< [2] FTM Counter Direction In Quadrature
Kojto 90:cb3d968589d8 4107 * Decoder Mode */
Kojto 90:cb3d968589d8 4108 uint32_t QUADMODE : 1; /*!< [3] Quadrature Decoder Mode */
Kojto 90:cb3d968589d8 4109 uint32_t PHBPOL : 1; /*!< [4] Phase B Input Polarity */
Kojto 90:cb3d968589d8 4110 uint32_t PHAPOL : 1; /*!< [5] Phase A Input Polarity */
Kojto 90:cb3d968589d8 4111 uint32_t PHBFLTREN : 1; /*!< [6] Phase B Input Filter Enable */
Kojto 90:cb3d968589d8 4112 uint32_t PHAFLTREN : 1; /*!< [7] Phase A Input Filter Enable */
Kojto 90:cb3d968589d8 4113 uint32_t RESERVED0 : 24; /*!< [31:8] */
Kojto 90:cb3d968589d8 4114 } B;
Kojto 90:cb3d968589d8 4115 } hw_ftm_qdctrl_t;
Kojto 90:cb3d968589d8 4116
Kojto 90:cb3d968589d8 4117 /*!
Kojto 90:cb3d968589d8 4118 * @name Constants and macros for entire FTM_QDCTRL register
Kojto 90:cb3d968589d8 4119 */
Kojto 90:cb3d968589d8 4120 /*@{*/
Kojto 90:cb3d968589d8 4121 #define HW_FTM_QDCTRL_ADDR(x) ((x) + 0x80U)
Kojto 90:cb3d968589d8 4122
Kojto 90:cb3d968589d8 4123 #define HW_FTM_QDCTRL(x) (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
Kojto 90:cb3d968589d8 4124 #define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
Kojto 90:cb3d968589d8 4125 #define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
Kojto 90:cb3d968589d8 4126 #define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) | (v)))
Kojto 90:cb3d968589d8 4127 #define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 4128 #define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 4129 /*@}*/
Kojto 90:cb3d968589d8 4130
Kojto 90:cb3d968589d8 4131 /*
Kojto 90:cb3d968589d8 4132 * Constants & macros for individual FTM_QDCTRL bitfields
Kojto 90:cb3d968589d8 4133 */
Kojto 90:cb3d968589d8 4134
Kojto 90:cb3d968589d8 4135 /*!
Kojto 90:cb3d968589d8 4136 * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
Kojto 90:cb3d968589d8 4137 *
Kojto 90:cb3d968589d8 4138 * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
Kojto 90:cb3d968589d8 4139 * signals control the FTM counter direction. The Quadrature Decoder mode has
Kojto 90:cb3d968589d8 4140 * precedence over the other modes. See #ModeSel1Table. This field is write protected.
Kojto 90:cb3d968589d8 4141 * It can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 4142 *
Kojto 90:cb3d968589d8 4143 * Values:
Kojto 90:cb3d968589d8 4144 * - 0 - Quadrature Decoder mode is disabled.
Kojto 90:cb3d968589d8 4145 * - 1 - Quadrature Decoder mode is enabled.
Kojto 90:cb3d968589d8 4146 */
Kojto 90:cb3d968589d8 4147 /*@{*/
Kojto 90:cb3d968589d8 4148 #define BP_FTM_QDCTRL_QUADEN (0U) /*!< Bit position for FTM_QDCTRL_QUADEN. */
Kojto 90:cb3d968589d8 4149 #define BM_FTM_QDCTRL_QUADEN (0x00000001U) /*!< Bit mask for FTM_QDCTRL_QUADEN. */
Kojto 90:cb3d968589d8 4150 #define BS_FTM_QDCTRL_QUADEN (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADEN. */
Kojto 90:cb3d968589d8 4151
Kojto 90:cb3d968589d8 4152 /*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
Kojto 90:cb3d968589d8 4153 #define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
Kojto 90:cb3d968589d8 4154
Kojto 90:cb3d968589d8 4155 /*! @brief Format value for bitfield FTM_QDCTRL_QUADEN. */
Kojto 90:cb3d968589d8 4156 #define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN)
Kojto 90:cb3d968589d8 4157
Kojto 90:cb3d968589d8 4158 /*! @brief Set the QUADEN field to a new value. */
Kojto 90:cb3d968589d8 4159 #define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
Kojto 90:cb3d968589d8 4160 /*@}*/
Kojto 90:cb3d968589d8 4161
Kojto 90:cb3d968589d8 4162 /*!
Kojto 90:cb3d968589d8 4163 * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
Kojto 90:cb3d968589d8 4164 *
Kojto 90:cb3d968589d8 4165 * Indicates if the TOF bit was set on the top or the bottom of counting.
Kojto 90:cb3d968589d8 4166 *
Kojto 90:cb3d968589d8 4167 * Values:
Kojto 90:cb3d968589d8 4168 * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
Kojto 90:cb3d968589d8 4169 * decrement and FTM counter changes from its minimum value (CNTIN register) to
Kojto 90:cb3d968589d8 4170 * its maximum value (MOD register).
Kojto 90:cb3d968589d8 4171 * - 1 - TOF bit was set on the top of counting. There was an FTM counter
Kojto 90:cb3d968589d8 4172 * increment and FTM counter changes from its maximum value (MOD register) to its
Kojto 90:cb3d968589d8 4173 * minimum value (CNTIN register).
Kojto 90:cb3d968589d8 4174 */
Kojto 90:cb3d968589d8 4175 /*@{*/
Kojto 90:cb3d968589d8 4176 #define BP_FTM_QDCTRL_TOFDIR (1U) /*!< Bit position for FTM_QDCTRL_TOFDIR. */
Kojto 90:cb3d968589d8 4177 #define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /*!< Bit mask for FTM_QDCTRL_TOFDIR. */
Kojto 90:cb3d968589d8 4178 #define BS_FTM_QDCTRL_TOFDIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_TOFDIR. */
Kojto 90:cb3d968589d8 4179
Kojto 90:cb3d968589d8 4180 /*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
Kojto 90:cb3d968589d8 4181 #define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
Kojto 90:cb3d968589d8 4182 /*@}*/
Kojto 90:cb3d968589d8 4183
Kojto 90:cb3d968589d8 4184 /*!
Kojto 90:cb3d968589d8 4185 * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
Kojto 90:cb3d968589d8 4186 *
Kojto 90:cb3d968589d8 4187 * Indicates the counting direction.
Kojto 90:cb3d968589d8 4188 *
Kojto 90:cb3d968589d8 4189 * Values:
Kojto 90:cb3d968589d8 4190 * - 0 - Counting direction is decreasing (FTM counter decrement).
Kojto 90:cb3d968589d8 4191 * - 1 - Counting direction is increasing (FTM counter increment).
Kojto 90:cb3d968589d8 4192 */
Kojto 90:cb3d968589d8 4193 /*@{*/
Kojto 90:cb3d968589d8 4194 #define BP_FTM_QDCTRL_QUADIR (2U) /*!< Bit position for FTM_QDCTRL_QUADIR. */
Kojto 90:cb3d968589d8 4195 #define BM_FTM_QDCTRL_QUADIR (0x00000004U) /*!< Bit mask for FTM_QDCTRL_QUADIR. */
Kojto 90:cb3d968589d8 4196 #define BS_FTM_QDCTRL_QUADIR (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADIR. */
Kojto 90:cb3d968589d8 4197
Kojto 90:cb3d968589d8 4198 /*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
Kojto 90:cb3d968589d8 4199 #define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
Kojto 90:cb3d968589d8 4200 /*@}*/
Kojto 90:cb3d968589d8 4201
Kojto 90:cb3d968589d8 4202 /*!
Kojto 90:cb3d968589d8 4203 * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
Kojto 90:cb3d968589d8 4204 *
Kojto 90:cb3d968589d8 4205 * Selects the encoding mode used in the Quadrature Decoder mode.
Kojto 90:cb3d968589d8 4206 *
Kojto 90:cb3d968589d8 4207 * Values:
Kojto 90:cb3d968589d8 4208 * - 0 - Phase A and phase B encoding mode.
Kojto 90:cb3d968589d8 4209 * - 1 - Count and direction encoding mode.
Kojto 90:cb3d968589d8 4210 */
Kojto 90:cb3d968589d8 4211 /*@{*/
Kojto 90:cb3d968589d8 4212 #define BP_FTM_QDCTRL_QUADMODE (3U) /*!< Bit position for FTM_QDCTRL_QUADMODE. */
Kojto 90:cb3d968589d8 4213 #define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /*!< Bit mask for FTM_QDCTRL_QUADMODE. */
Kojto 90:cb3d968589d8 4214 #define BS_FTM_QDCTRL_QUADMODE (1U) /*!< Bit field size in bits for FTM_QDCTRL_QUADMODE. */
Kojto 90:cb3d968589d8 4215
Kojto 90:cb3d968589d8 4216 /*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
Kojto 90:cb3d968589d8 4217 #define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
Kojto 90:cb3d968589d8 4218
Kojto 90:cb3d968589d8 4219 /*! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. */
Kojto 90:cb3d968589d8 4220 #define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE)
Kojto 90:cb3d968589d8 4221
Kojto 90:cb3d968589d8 4222 /*! @brief Set the QUADMODE field to a new value. */
Kojto 90:cb3d968589d8 4223 #define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
Kojto 90:cb3d968589d8 4224 /*@}*/
Kojto 90:cb3d968589d8 4225
Kojto 90:cb3d968589d8 4226 /*!
Kojto 90:cb3d968589d8 4227 * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
Kojto 90:cb3d968589d8 4228 *
Kojto 90:cb3d968589d8 4229 * Selects the polarity for the quadrature decoder phase B input.
Kojto 90:cb3d968589d8 4230 *
Kojto 90:cb3d968589d8 4231 * Values:
Kojto 90:cb3d968589d8 4232 * - 0 - Normal polarity. Phase B input signal is not inverted before
Kojto 90:cb3d968589d8 4233 * identifying the rising and falling edges of this signal.
Kojto 90:cb3d968589d8 4234 * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
Kojto 90:cb3d968589d8 4235 * the rising and falling edges of this signal.
Kojto 90:cb3d968589d8 4236 */
Kojto 90:cb3d968589d8 4237 /*@{*/
Kojto 90:cb3d968589d8 4238 #define BP_FTM_QDCTRL_PHBPOL (4U) /*!< Bit position for FTM_QDCTRL_PHBPOL. */
Kojto 90:cb3d968589d8 4239 #define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /*!< Bit mask for FTM_QDCTRL_PHBPOL. */
Kojto 90:cb3d968589d8 4240 #define BS_FTM_QDCTRL_PHBPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBPOL. */
Kojto 90:cb3d968589d8 4241
Kojto 90:cb3d968589d8 4242 /*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
Kojto 90:cb3d968589d8 4243 #define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
Kojto 90:cb3d968589d8 4244
Kojto 90:cb3d968589d8 4245 /*! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. */
Kojto 90:cb3d968589d8 4246 #define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL)
Kojto 90:cb3d968589d8 4247
Kojto 90:cb3d968589d8 4248 /*! @brief Set the PHBPOL field to a new value. */
Kojto 90:cb3d968589d8 4249 #define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
Kojto 90:cb3d968589d8 4250 /*@}*/
Kojto 90:cb3d968589d8 4251
Kojto 90:cb3d968589d8 4252 /*!
Kojto 90:cb3d968589d8 4253 * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
Kojto 90:cb3d968589d8 4254 *
Kojto 90:cb3d968589d8 4255 * Selects the polarity for the quadrature decoder phase A input.
Kojto 90:cb3d968589d8 4256 *
Kojto 90:cb3d968589d8 4257 * Values:
Kojto 90:cb3d968589d8 4258 * - 0 - Normal polarity. Phase A input signal is not inverted before
Kojto 90:cb3d968589d8 4259 * identifying the rising and falling edges of this signal.
Kojto 90:cb3d968589d8 4260 * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
Kojto 90:cb3d968589d8 4261 * the rising and falling edges of this signal.
Kojto 90:cb3d968589d8 4262 */
Kojto 90:cb3d968589d8 4263 /*@{*/
Kojto 90:cb3d968589d8 4264 #define BP_FTM_QDCTRL_PHAPOL (5U) /*!< Bit position for FTM_QDCTRL_PHAPOL. */
Kojto 90:cb3d968589d8 4265 #define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /*!< Bit mask for FTM_QDCTRL_PHAPOL. */
Kojto 90:cb3d968589d8 4266 #define BS_FTM_QDCTRL_PHAPOL (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAPOL. */
Kojto 90:cb3d968589d8 4267
Kojto 90:cb3d968589d8 4268 /*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
Kojto 90:cb3d968589d8 4269 #define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
Kojto 90:cb3d968589d8 4270
Kojto 90:cb3d968589d8 4271 /*! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. */
Kojto 90:cb3d968589d8 4272 #define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL)
Kojto 90:cb3d968589d8 4273
Kojto 90:cb3d968589d8 4274 /*! @brief Set the PHAPOL field to a new value. */
Kojto 90:cb3d968589d8 4275 #define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
Kojto 90:cb3d968589d8 4276 /*@}*/
Kojto 90:cb3d968589d8 4277
Kojto 90:cb3d968589d8 4278 /*!
Kojto 90:cb3d968589d8 4279 * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
Kojto 90:cb3d968589d8 4280 *
Kojto 90:cb3d968589d8 4281 * Enables the filter for the quadrature decoder phase B input. The filter value
Kojto 90:cb3d968589d8 4282 * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
Kojto 90:cb3d968589d8 4283 * filter is also disabled when CH1FVAL is zero.
Kojto 90:cb3d968589d8 4284 *
Kojto 90:cb3d968589d8 4285 * Values:
Kojto 90:cb3d968589d8 4286 * - 0 - Phase B input filter is disabled.
Kojto 90:cb3d968589d8 4287 * - 1 - Phase B input filter is enabled.
Kojto 90:cb3d968589d8 4288 */
Kojto 90:cb3d968589d8 4289 /*@{*/
Kojto 90:cb3d968589d8 4290 #define BP_FTM_QDCTRL_PHBFLTREN (6U) /*!< Bit position for FTM_QDCTRL_PHBFLTREN. */
Kojto 90:cb3d968589d8 4291 #define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /*!< Bit mask for FTM_QDCTRL_PHBFLTREN. */
Kojto 90:cb3d968589d8 4292 #define BS_FTM_QDCTRL_PHBFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. */
Kojto 90:cb3d968589d8 4293
Kojto 90:cb3d968589d8 4294 /*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
Kojto 90:cb3d968589d8 4295 #define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
Kojto 90:cb3d968589d8 4296
Kojto 90:cb3d968589d8 4297 /*! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. */
Kojto 90:cb3d968589d8 4298 #define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN)
Kojto 90:cb3d968589d8 4299
Kojto 90:cb3d968589d8 4300 /*! @brief Set the PHBFLTREN field to a new value. */
Kojto 90:cb3d968589d8 4301 #define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
Kojto 90:cb3d968589d8 4302 /*@}*/
Kojto 90:cb3d968589d8 4303
Kojto 90:cb3d968589d8 4304 /*!
Kojto 90:cb3d968589d8 4305 * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
Kojto 90:cb3d968589d8 4306 *
Kojto 90:cb3d968589d8 4307 * Enables the filter for the quadrature decoder phase A input. The filter value
Kojto 90:cb3d968589d8 4308 * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
Kojto 90:cb3d968589d8 4309 * filter is also disabled when CH0FVAL is zero.
Kojto 90:cb3d968589d8 4310 *
Kojto 90:cb3d968589d8 4311 * Values:
Kojto 90:cb3d968589d8 4312 * - 0 - Phase A input filter is disabled.
Kojto 90:cb3d968589d8 4313 * - 1 - Phase A input filter is enabled.
Kojto 90:cb3d968589d8 4314 */
Kojto 90:cb3d968589d8 4315 /*@{*/
Kojto 90:cb3d968589d8 4316 #define BP_FTM_QDCTRL_PHAFLTREN (7U) /*!< Bit position for FTM_QDCTRL_PHAFLTREN. */
Kojto 90:cb3d968589d8 4317 #define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /*!< Bit mask for FTM_QDCTRL_PHAFLTREN. */
Kojto 90:cb3d968589d8 4318 #define BS_FTM_QDCTRL_PHAFLTREN (1U) /*!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. */
Kojto 90:cb3d968589d8 4319
Kojto 90:cb3d968589d8 4320 /*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
Kojto 90:cb3d968589d8 4321 #define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
Kojto 90:cb3d968589d8 4322
Kojto 90:cb3d968589d8 4323 /*! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. */
Kojto 90:cb3d968589d8 4324 #define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN)
Kojto 90:cb3d968589d8 4325
Kojto 90:cb3d968589d8 4326 /*! @brief Set the PHAFLTREN field to a new value. */
Kojto 90:cb3d968589d8 4327 #define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
Kojto 90:cb3d968589d8 4328 /*@}*/
Kojto 90:cb3d968589d8 4329
Kojto 90:cb3d968589d8 4330 /*******************************************************************************
Kojto 90:cb3d968589d8 4331 * HW_FTM_CONF - Configuration
Kojto 90:cb3d968589d8 4332 ******************************************************************************/
Kojto 90:cb3d968589d8 4333
Kojto 90:cb3d968589d8 4334 /*!
Kojto 90:cb3d968589d8 4335 * @brief HW_FTM_CONF - Configuration (RW)
Kojto 90:cb3d968589d8 4336 *
Kojto 90:cb3d968589d8 4337 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 4338 *
Kojto 90:cb3d968589d8 4339 * This register selects the number of times that the FTM counter overflow
Kojto 90:cb3d968589d8 4340 * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
Kojto 90:cb3d968589d8 4341 * of an external global time base, and the global time base signal generation.
Kojto 90:cb3d968589d8 4342 */
Kojto 90:cb3d968589d8 4343 typedef union _hw_ftm_conf
Kojto 90:cb3d968589d8 4344 {
Kojto 90:cb3d968589d8 4345 uint32_t U;
Kojto 90:cb3d968589d8 4346 struct _hw_ftm_conf_bitfields
Kojto 90:cb3d968589d8 4347 {
Kojto 90:cb3d968589d8 4348 uint32_t NUMTOF : 5; /*!< [4:0] TOF Frequency */
Kojto 90:cb3d968589d8 4349 uint32_t RESERVED0 : 1; /*!< [5] */
Kojto 90:cb3d968589d8 4350 uint32_t BDMMODE : 2; /*!< [7:6] BDM Mode */
Kojto 90:cb3d968589d8 4351 uint32_t RESERVED1 : 1; /*!< [8] */
Kojto 90:cb3d968589d8 4352 uint32_t GTBEEN : 1; /*!< [9] Global Time Base Enable */
Kojto 90:cb3d968589d8 4353 uint32_t GTBEOUT : 1; /*!< [10] Global Time Base Output */
Kojto 90:cb3d968589d8 4354 uint32_t RESERVED2 : 21; /*!< [31:11] */
Kojto 90:cb3d968589d8 4355 } B;
Kojto 90:cb3d968589d8 4356 } hw_ftm_conf_t;
Kojto 90:cb3d968589d8 4357
Kojto 90:cb3d968589d8 4358 /*!
Kojto 90:cb3d968589d8 4359 * @name Constants and macros for entire FTM_CONF register
Kojto 90:cb3d968589d8 4360 */
Kojto 90:cb3d968589d8 4361 /*@{*/
Kojto 90:cb3d968589d8 4362 #define HW_FTM_CONF_ADDR(x) ((x) + 0x84U)
Kojto 90:cb3d968589d8 4363
Kojto 90:cb3d968589d8 4364 #define HW_FTM_CONF(x) (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
Kojto 90:cb3d968589d8 4365 #define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
Kojto 90:cb3d968589d8 4366 #define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
Kojto 90:cb3d968589d8 4367 #define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) | (v)))
Kojto 90:cb3d968589d8 4368 #define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 4369 #define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 4370 /*@}*/
Kojto 90:cb3d968589d8 4371
Kojto 90:cb3d968589d8 4372 /*
Kojto 90:cb3d968589d8 4373 * Constants & macros for individual FTM_CONF bitfields
Kojto 90:cb3d968589d8 4374 */
Kojto 90:cb3d968589d8 4375
Kojto 90:cb3d968589d8 4376 /*!
Kojto 90:cb3d968589d8 4377 * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
Kojto 90:cb3d968589d8 4378 *
Kojto 90:cb3d968589d8 4379 * Selects the ratio between the number of counter overflows to the number of
Kojto 90:cb3d968589d8 4380 * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
Kojto 90:cb3d968589d8 4381 * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
Kojto 90:cb3d968589d8 4382 * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
Kojto 90:cb3d968589d8 4383 * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
Kojto 90:cb3d968589d8 4384 * first counter overflow but not for the next 3 overflows. This pattern continues
Kojto 90:cb3d968589d8 4385 * up to a maximum of 31.
Kojto 90:cb3d968589d8 4386 */
Kojto 90:cb3d968589d8 4387 /*@{*/
Kojto 90:cb3d968589d8 4388 #define BP_FTM_CONF_NUMTOF (0U) /*!< Bit position for FTM_CONF_NUMTOF. */
Kojto 90:cb3d968589d8 4389 #define BM_FTM_CONF_NUMTOF (0x0000001FU) /*!< Bit mask for FTM_CONF_NUMTOF. */
Kojto 90:cb3d968589d8 4390 #define BS_FTM_CONF_NUMTOF (5U) /*!< Bit field size in bits for FTM_CONF_NUMTOF. */
Kojto 90:cb3d968589d8 4391
Kojto 90:cb3d968589d8 4392 /*! @brief Read current value of the FTM_CONF_NUMTOF field. */
Kojto 90:cb3d968589d8 4393 #define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
Kojto 90:cb3d968589d8 4394
Kojto 90:cb3d968589d8 4395 /*! @brief Format value for bitfield FTM_CONF_NUMTOF. */
Kojto 90:cb3d968589d8 4396 #define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF)
Kojto 90:cb3d968589d8 4397
Kojto 90:cb3d968589d8 4398 /*! @brief Set the NUMTOF field to a new value. */
Kojto 90:cb3d968589d8 4399 #define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
Kojto 90:cb3d968589d8 4400 /*@}*/
Kojto 90:cb3d968589d8 4401
Kojto 90:cb3d968589d8 4402 /*!
Kojto 90:cb3d968589d8 4403 * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
Kojto 90:cb3d968589d8 4404 *
Kojto 90:cb3d968589d8 4405 * Selects the FTM behavior in BDM mode. See BDM mode.
Kojto 90:cb3d968589d8 4406 */
Kojto 90:cb3d968589d8 4407 /*@{*/
Kojto 90:cb3d968589d8 4408 #define BP_FTM_CONF_BDMMODE (6U) /*!< Bit position for FTM_CONF_BDMMODE. */
Kojto 90:cb3d968589d8 4409 #define BM_FTM_CONF_BDMMODE (0x000000C0U) /*!< Bit mask for FTM_CONF_BDMMODE. */
Kojto 90:cb3d968589d8 4410 #define BS_FTM_CONF_BDMMODE (2U) /*!< Bit field size in bits for FTM_CONF_BDMMODE. */
Kojto 90:cb3d968589d8 4411
Kojto 90:cb3d968589d8 4412 /*! @brief Read current value of the FTM_CONF_BDMMODE field. */
Kojto 90:cb3d968589d8 4413 #define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
Kojto 90:cb3d968589d8 4414
Kojto 90:cb3d968589d8 4415 /*! @brief Format value for bitfield FTM_CONF_BDMMODE. */
Kojto 90:cb3d968589d8 4416 #define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE)
Kojto 90:cb3d968589d8 4417
Kojto 90:cb3d968589d8 4418 /*! @brief Set the BDMMODE field to a new value. */
Kojto 90:cb3d968589d8 4419 #define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
Kojto 90:cb3d968589d8 4420 /*@}*/
Kojto 90:cb3d968589d8 4421
Kojto 90:cb3d968589d8 4422 /*!
Kojto 90:cb3d968589d8 4423 * @name Register FTM_CONF, field GTBEEN[9] (RW)
Kojto 90:cb3d968589d8 4424 *
Kojto 90:cb3d968589d8 4425 * Configures the FTM to use an external global time base signal that is
Kojto 90:cb3d968589d8 4426 * generated by another FTM.
Kojto 90:cb3d968589d8 4427 *
Kojto 90:cb3d968589d8 4428 * Values:
Kojto 90:cb3d968589d8 4429 * - 0 - Use of an external global time base is disabled.
Kojto 90:cb3d968589d8 4430 * - 1 - Use of an external global time base is enabled.
Kojto 90:cb3d968589d8 4431 */
Kojto 90:cb3d968589d8 4432 /*@{*/
Kojto 90:cb3d968589d8 4433 #define BP_FTM_CONF_GTBEEN (9U) /*!< Bit position for FTM_CONF_GTBEEN. */
Kojto 90:cb3d968589d8 4434 #define BM_FTM_CONF_GTBEEN (0x00000200U) /*!< Bit mask for FTM_CONF_GTBEEN. */
Kojto 90:cb3d968589d8 4435 #define BS_FTM_CONF_GTBEEN (1U) /*!< Bit field size in bits for FTM_CONF_GTBEEN. */
Kojto 90:cb3d968589d8 4436
Kojto 90:cb3d968589d8 4437 /*! @brief Read current value of the FTM_CONF_GTBEEN field. */
Kojto 90:cb3d968589d8 4438 #define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
Kojto 90:cb3d968589d8 4439
Kojto 90:cb3d968589d8 4440 /*! @brief Format value for bitfield FTM_CONF_GTBEEN. */
Kojto 90:cb3d968589d8 4441 #define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN)
Kojto 90:cb3d968589d8 4442
Kojto 90:cb3d968589d8 4443 /*! @brief Set the GTBEEN field to a new value. */
Kojto 90:cb3d968589d8 4444 #define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
Kojto 90:cb3d968589d8 4445 /*@}*/
Kojto 90:cb3d968589d8 4446
Kojto 90:cb3d968589d8 4447 /*!
Kojto 90:cb3d968589d8 4448 * @name Register FTM_CONF, field GTBEOUT[10] (RW)
Kojto 90:cb3d968589d8 4449 *
Kojto 90:cb3d968589d8 4450 * Enables the global time base signal generation to other FTMs.
Kojto 90:cb3d968589d8 4451 *
Kojto 90:cb3d968589d8 4452 * Values:
Kojto 90:cb3d968589d8 4453 * - 0 - A global time base signal generation is disabled.
Kojto 90:cb3d968589d8 4454 * - 1 - A global time base signal generation is enabled.
Kojto 90:cb3d968589d8 4455 */
Kojto 90:cb3d968589d8 4456 /*@{*/
Kojto 90:cb3d968589d8 4457 #define BP_FTM_CONF_GTBEOUT (10U) /*!< Bit position for FTM_CONF_GTBEOUT. */
Kojto 90:cb3d968589d8 4458 #define BM_FTM_CONF_GTBEOUT (0x00000400U) /*!< Bit mask for FTM_CONF_GTBEOUT. */
Kojto 90:cb3d968589d8 4459 #define BS_FTM_CONF_GTBEOUT (1U) /*!< Bit field size in bits for FTM_CONF_GTBEOUT. */
Kojto 90:cb3d968589d8 4460
Kojto 90:cb3d968589d8 4461 /*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
Kojto 90:cb3d968589d8 4462 #define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
Kojto 90:cb3d968589d8 4463
Kojto 90:cb3d968589d8 4464 /*! @brief Format value for bitfield FTM_CONF_GTBEOUT. */
Kojto 90:cb3d968589d8 4465 #define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT)
Kojto 90:cb3d968589d8 4466
Kojto 90:cb3d968589d8 4467 /*! @brief Set the GTBEOUT field to a new value. */
Kojto 90:cb3d968589d8 4468 #define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
Kojto 90:cb3d968589d8 4469 /*@}*/
Kojto 90:cb3d968589d8 4470
Kojto 90:cb3d968589d8 4471 /*******************************************************************************
Kojto 90:cb3d968589d8 4472 * HW_FTM_FLTPOL - FTM Fault Input Polarity
Kojto 90:cb3d968589d8 4473 ******************************************************************************/
Kojto 90:cb3d968589d8 4474
Kojto 90:cb3d968589d8 4475 /*!
Kojto 90:cb3d968589d8 4476 * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
Kojto 90:cb3d968589d8 4477 *
Kojto 90:cb3d968589d8 4478 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 4479 *
Kojto 90:cb3d968589d8 4480 * This register defines the fault inputs polarity.
Kojto 90:cb3d968589d8 4481 */
Kojto 90:cb3d968589d8 4482 typedef union _hw_ftm_fltpol
Kojto 90:cb3d968589d8 4483 {
Kojto 90:cb3d968589d8 4484 uint32_t U;
Kojto 90:cb3d968589d8 4485 struct _hw_ftm_fltpol_bitfields
Kojto 90:cb3d968589d8 4486 {
Kojto 90:cb3d968589d8 4487 uint32_t FLT0POL : 1; /*!< [0] Fault Input 0 Polarity */
Kojto 90:cb3d968589d8 4488 uint32_t FLT1POL : 1; /*!< [1] Fault Input 1 Polarity */
Kojto 90:cb3d968589d8 4489 uint32_t FLT2POL : 1; /*!< [2] Fault Input 2 Polarity */
Kojto 90:cb3d968589d8 4490 uint32_t FLT3POL : 1; /*!< [3] Fault Input 3 Polarity */
Kojto 90:cb3d968589d8 4491 uint32_t RESERVED0 : 28; /*!< [31:4] */
Kojto 90:cb3d968589d8 4492 } B;
Kojto 90:cb3d968589d8 4493 } hw_ftm_fltpol_t;
Kojto 90:cb3d968589d8 4494
Kojto 90:cb3d968589d8 4495 /*!
Kojto 90:cb3d968589d8 4496 * @name Constants and macros for entire FTM_FLTPOL register
Kojto 90:cb3d968589d8 4497 */
Kojto 90:cb3d968589d8 4498 /*@{*/
Kojto 90:cb3d968589d8 4499 #define HW_FTM_FLTPOL_ADDR(x) ((x) + 0x88U)
Kojto 90:cb3d968589d8 4500
Kojto 90:cb3d968589d8 4501 #define HW_FTM_FLTPOL(x) (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
Kojto 90:cb3d968589d8 4502 #define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
Kojto 90:cb3d968589d8 4503 #define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
Kojto 90:cb3d968589d8 4504 #define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) | (v)))
Kojto 90:cb3d968589d8 4505 #define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 4506 #define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 4507 /*@}*/
Kojto 90:cb3d968589d8 4508
Kojto 90:cb3d968589d8 4509 /*
Kojto 90:cb3d968589d8 4510 * Constants & macros for individual FTM_FLTPOL bitfields
Kojto 90:cb3d968589d8 4511 */
Kojto 90:cb3d968589d8 4512
Kojto 90:cb3d968589d8 4513 /*!
Kojto 90:cb3d968589d8 4514 * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
Kojto 90:cb3d968589d8 4515 *
Kojto 90:cb3d968589d8 4516 * Defines the polarity of the fault input. This field is write protected. It
Kojto 90:cb3d968589d8 4517 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 4518 *
Kojto 90:cb3d968589d8 4519 * Values:
Kojto 90:cb3d968589d8 4520 * - 0 - The fault input polarity is active high. A 1 at the fault input
Kojto 90:cb3d968589d8 4521 * indicates a fault.
Kojto 90:cb3d968589d8 4522 * - 1 - The fault input polarity is active low. A 0 at the fault input
Kojto 90:cb3d968589d8 4523 * indicates a fault.
Kojto 90:cb3d968589d8 4524 */
Kojto 90:cb3d968589d8 4525 /*@{*/
Kojto 90:cb3d968589d8 4526 #define BP_FTM_FLTPOL_FLT0POL (0U) /*!< Bit position for FTM_FLTPOL_FLT0POL. */
Kojto 90:cb3d968589d8 4527 #define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /*!< Bit mask for FTM_FLTPOL_FLT0POL. */
Kojto 90:cb3d968589d8 4528 #define BS_FTM_FLTPOL_FLT0POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT0POL. */
Kojto 90:cb3d968589d8 4529
Kojto 90:cb3d968589d8 4530 /*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
Kojto 90:cb3d968589d8 4531 #define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
Kojto 90:cb3d968589d8 4532
Kojto 90:cb3d968589d8 4533 /*! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. */
Kojto 90:cb3d968589d8 4534 #define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL)
Kojto 90:cb3d968589d8 4535
Kojto 90:cb3d968589d8 4536 /*! @brief Set the FLT0POL field to a new value. */
Kojto 90:cb3d968589d8 4537 #define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
Kojto 90:cb3d968589d8 4538 /*@}*/
Kojto 90:cb3d968589d8 4539
Kojto 90:cb3d968589d8 4540 /*!
Kojto 90:cb3d968589d8 4541 * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
Kojto 90:cb3d968589d8 4542 *
Kojto 90:cb3d968589d8 4543 * Defines the polarity of the fault input. This field is write protected. It
Kojto 90:cb3d968589d8 4544 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 4545 *
Kojto 90:cb3d968589d8 4546 * Values:
Kojto 90:cb3d968589d8 4547 * - 0 - The fault input polarity is active high. A 1 at the fault input
Kojto 90:cb3d968589d8 4548 * indicates a fault.
Kojto 90:cb3d968589d8 4549 * - 1 - The fault input polarity is active low. A 0 at the fault input
Kojto 90:cb3d968589d8 4550 * indicates a fault.
Kojto 90:cb3d968589d8 4551 */
Kojto 90:cb3d968589d8 4552 /*@{*/
Kojto 90:cb3d968589d8 4553 #define BP_FTM_FLTPOL_FLT1POL (1U) /*!< Bit position for FTM_FLTPOL_FLT1POL. */
Kojto 90:cb3d968589d8 4554 #define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /*!< Bit mask for FTM_FLTPOL_FLT1POL. */
Kojto 90:cb3d968589d8 4555 #define BS_FTM_FLTPOL_FLT1POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT1POL. */
Kojto 90:cb3d968589d8 4556
Kojto 90:cb3d968589d8 4557 /*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
Kojto 90:cb3d968589d8 4558 #define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
Kojto 90:cb3d968589d8 4559
Kojto 90:cb3d968589d8 4560 /*! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. */
Kojto 90:cb3d968589d8 4561 #define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL)
Kojto 90:cb3d968589d8 4562
Kojto 90:cb3d968589d8 4563 /*! @brief Set the FLT1POL field to a new value. */
Kojto 90:cb3d968589d8 4564 #define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
Kojto 90:cb3d968589d8 4565 /*@}*/
Kojto 90:cb3d968589d8 4566
Kojto 90:cb3d968589d8 4567 /*!
Kojto 90:cb3d968589d8 4568 * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
Kojto 90:cb3d968589d8 4569 *
Kojto 90:cb3d968589d8 4570 * Defines the polarity of the fault input. This field is write protected. It
Kojto 90:cb3d968589d8 4571 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 4572 *
Kojto 90:cb3d968589d8 4573 * Values:
Kojto 90:cb3d968589d8 4574 * - 0 - The fault input polarity is active high. A 1 at the fault input
Kojto 90:cb3d968589d8 4575 * indicates a fault.
Kojto 90:cb3d968589d8 4576 * - 1 - The fault input polarity is active low. A 0 at the fault input
Kojto 90:cb3d968589d8 4577 * indicates a fault.
Kojto 90:cb3d968589d8 4578 */
Kojto 90:cb3d968589d8 4579 /*@{*/
Kojto 90:cb3d968589d8 4580 #define BP_FTM_FLTPOL_FLT2POL (2U) /*!< Bit position for FTM_FLTPOL_FLT2POL. */
Kojto 90:cb3d968589d8 4581 #define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /*!< Bit mask for FTM_FLTPOL_FLT2POL. */
Kojto 90:cb3d968589d8 4582 #define BS_FTM_FLTPOL_FLT2POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT2POL. */
Kojto 90:cb3d968589d8 4583
Kojto 90:cb3d968589d8 4584 /*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
Kojto 90:cb3d968589d8 4585 #define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
Kojto 90:cb3d968589d8 4586
Kojto 90:cb3d968589d8 4587 /*! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. */
Kojto 90:cb3d968589d8 4588 #define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL)
Kojto 90:cb3d968589d8 4589
Kojto 90:cb3d968589d8 4590 /*! @brief Set the FLT2POL field to a new value. */
Kojto 90:cb3d968589d8 4591 #define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
Kojto 90:cb3d968589d8 4592 /*@}*/
Kojto 90:cb3d968589d8 4593
Kojto 90:cb3d968589d8 4594 /*!
Kojto 90:cb3d968589d8 4595 * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
Kojto 90:cb3d968589d8 4596 *
Kojto 90:cb3d968589d8 4597 * Defines the polarity of the fault input. This field is write protected. It
Kojto 90:cb3d968589d8 4598 * can be written only when MODE[WPDIS] = 1.
Kojto 90:cb3d968589d8 4599 *
Kojto 90:cb3d968589d8 4600 * Values:
Kojto 90:cb3d968589d8 4601 * - 0 - The fault input polarity is active high. A 1 at the fault input
Kojto 90:cb3d968589d8 4602 * indicates a fault.
Kojto 90:cb3d968589d8 4603 * - 1 - The fault input polarity is active low. A 0 at the fault input
Kojto 90:cb3d968589d8 4604 * indicates a fault.
Kojto 90:cb3d968589d8 4605 */
Kojto 90:cb3d968589d8 4606 /*@{*/
Kojto 90:cb3d968589d8 4607 #define BP_FTM_FLTPOL_FLT3POL (3U) /*!< Bit position for FTM_FLTPOL_FLT3POL. */
Kojto 90:cb3d968589d8 4608 #define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /*!< Bit mask for FTM_FLTPOL_FLT3POL. */
Kojto 90:cb3d968589d8 4609 #define BS_FTM_FLTPOL_FLT3POL (1U) /*!< Bit field size in bits for FTM_FLTPOL_FLT3POL. */
Kojto 90:cb3d968589d8 4610
Kojto 90:cb3d968589d8 4611 /*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
Kojto 90:cb3d968589d8 4612 #define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
Kojto 90:cb3d968589d8 4613
Kojto 90:cb3d968589d8 4614 /*! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. */
Kojto 90:cb3d968589d8 4615 #define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL)
Kojto 90:cb3d968589d8 4616
Kojto 90:cb3d968589d8 4617 /*! @brief Set the FLT3POL field to a new value. */
Kojto 90:cb3d968589d8 4618 #define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
Kojto 90:cb3d968589d8 4619 /*@}*/
Kojto 90:cb3d968589d8 4620
Kojto 90:cb3d968589d8 4621 /*******************************************************************************
Kojto 90:cb3d968589d8 4622 * HW_FTM_SYNCONF - Synchronization Configuration
Kojto 90:cb3d968589d8 4623 ******************************************************************************/
Kojto 90:cb3d968589d8 4624
Kojto 90:cb3d968589d8 4625 /*!
Kojto 90:cb3d968589d8 4626 * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
Kojto 90:cb3d968589d8 4627 *
Kojto 90:cb3d968589d8 4628 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 4629 *
Kojto 90:cb3d968589d8 4630 * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
Kojto 90:cb3d968589d8 4631 * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
Kojto 90:cb3d968589d8 4632 * 0, 1, 2, when the hardware trigger j is detected.
Kojto 90:cb3d968589d8 4633 */
Kojto 90:cb3d968589d8 4634 typedef union _hw_ftm_synconf
Kojto 90:cb3d968589d8 4635 {
Kojto 90:cb3d968589d8 4636 uint32_t U;
Kojto 90:cb3d968589d8 4637 struct _hw_ftm_synconf_bitfields
Kojto 90:cb3d968589d8 4638 {
Kojto 90:cb3d968589d8 4639 uint32_t HWTRIGMODE : 1; /*!< [0] Hardware Trigger Mode */
Kojto 90:cb3d968589d8 4640 uint32_t RESERVED0 : 1; /*!< [1] */
Kojto 90:cb3d968589d8 4641 uint32_t CNTINC : 1; /*!< [2] CNTIN Register Synchronization */
Kojto 90:cb3d968589d8 4642 uint32_t RESERVED1 : 1; /*!< [3] */
Kojto 90:cb3d968589d8 4643 uint32_t INVC : 1; /*!< [4] INVCTRL Register Synchronization */
Kojto 90:cb3d968589d8 4644 uint32_t SWOC : 1; /*!< [5] SWOCTRL Register Synchronization */
Kojto 90:cb3d968589d8 4645 uint32_t RESERVED2 : 1; /*!< [6] */
Kojto 90:cb3d968589d8 4646 uint32_t SYNCMODE : 1; /*!< [7] Synchronization Mode */
Kojto 90:cb3d968589d8 4647 uint32_t SWRSTCNT : 1; /*!< [8] */
Kojto 90:cb3d968589d8 4648 uint32_t SWWRBUF : 1; /*!< [9] */
Kojto 90:cb3d968589d8 4649 uint32_t SWOM : 1; /*!< [10] */
Kojto 90:cb3d968589d8 4650 uint32_t SWINVC : 1; /*!< [11] */
Kojto 90:cb3d968589d8 4651 uint32_t SWSOC : 1; /*!< [12] */
Kojto 90:cb3d968589d8 4652 uint32_t RESERVED3 : 3; /*!< [15:13] */
Kojto 90:cb3d968589d8 4653 uint32_t HWRSTCNT : 1; /*!< [16] */
Kojto 90:cb3d968589d8 4654 uint32_t HWWRBUF : 1; /*!< [17] */
Kojto 90:cb3d968589d8 4655 uint32_t HWOM : 1; /*!< [18] */
Kojto 90:cb3d968589d8 4656 uint32_t HWINVC : 1; /*!< [19] */
Kojto 90:cb3d968589d8 4657 uint32_t HWSOC : 1; /*!< [20] */
Kojto 90:cb3d968589d8 4658 uint32_t RESERVED4 : 11; /*!< [31:21] */
Kojto 90:cb3d968589d8 4659 } B;
Kojto 90:cb3d968589d8 4660 } hw_ftm_synconf_t;
Kojto 90:cb3d968589d8 4661
Kojto 90:cb3d968589d8 4662 /*!
Kojto 90:cb3d968589d8 4663 * @name Constants and macros for entire FTM_SYNCONF register
Kojto 90:cb3d968589d8 4664 */
Kojto 90:cb3d968589d8 4665 /*@{*/
Kojto 90:cb3d968589d8 4666 #define HW_FTM_SYNCONF_ADDR(x) ((x) + 0x8CU)
Kojto 90:cb3d968589d8 4667
Kojto 90:cb3d968589d8 4668 #define HW_FTM_SYNCONF(x) (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
Kojto 90:cb3d968589d8 4669 #define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
Kojto 90:cb3d968589d8 4670 #define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
Kojto 90:cb3d968589d8 4671 #define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) | (v)))
Kojto 90:cb3d968589d8 4672 #define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 4673 #define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 4674 /*@}*/
Kojto 90:cb3d968589d8 4675
Kojto 90:cb3d968589d8 4676 /*
Kojto 90:cb3d968589d8 4677 * Constants & macros for individual FTM_SYNCONF bitfields
Kojto 90:cb3d968589d8 4678 */
Kojto 90:cb3d968589d8 4679
Kojto 90:cb3d968589d8 4680 /*!
Kojto 90:cb3d968589d8 4681 * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
Kojto 90:cb3d968589d8 4682 *
Kojto 90:cb3d968589d8 4683 * Values:
Kojto 90:cb3d968589d8 4684 * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
Kojto 90:cb3d968589d8 4685 * j = 0, 1,2.
Kojto 90:cb3d968589d8 4686 * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
Kojto 90:cb3d968589d8 4687 * detected, where j = 0, 1,2.
Kojto 90:cb3d968589d8 4688 */
Kojto 90:cb3d968589d8 4689 /*@{*/
Kojto 90:cb3d968589d8 4690 #define BP_FTM_SYNCONF_HWTRIGMODE (0U) /*!< Bit position for FTM_SYNCONF_HWTRIGMODE. */
Kojto 90:cb3d968589d8 4691 #define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /*!< Bit mask for FTM_SYNCONF_HWTRIGMODE. */
Kojto 90:cb3d968589d8 4692 #define BS_FTM_SYNCONF_HWTRIGMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. */
Kojto 90:cb3d968589d8 4693
Kojto 90:cb3d968589d8 4694 /*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
Kojto 90:cb3d968589d8 4695 #define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
Kojto 90:cb3d968589d8 4696
Kojto 90:cb3d968589d8 4697 /*! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. */
Kojto 90:cb3d968589d8 4698 #define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE)
Kojto 90:cb3d968589d8 4699
Kojto 90:cb3d968589d8 4700 /*! @brief Set the HWTRIGMODE field to a new value. */
Kojto 90:cb3d968589d8 4701 #define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
Kojto 90:cb3d968589d8 4702 /*@}*/
Kojto 90:cb3d968589d8 4703
Kojto 90:cb3d968589d8 4704 /*!
Kojto 90:cb3d968589d8 4705 * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
Kojto 90:cb3d968589d8 4706 *
Kojto 90:cb3d968589d8 4707 * Values:
Kojto 90:cb3d968589d8 4708 * - 0 - CNTIN register is updated with its buffer value at all rising edges of
Kojto 90:cb3d968589d8 4709 * system clock.
Kojto 90:cb3d968589d8 4710 * - 1 - CNTIN register is updated with its buffer value by the PWM
Kojto 90:cb3d968589d8 4711 * synchronization.
Kojto 90:cb3d968589d8 4712 */
Kojto 90:cb3d968589d8 4713 /*@{*/
Kojto 90:cb3d968589d8 4714 #define BP_FTM_SYNCONF_CNTINC (2U) /*!< Bit position for FTM_SYNCONF_CNTINC. */
Kojto 90:cb3d968589d8 4715 #define BM_FTM_SYNCONF_CNTINC (0x00000004U) /*!< Bit mask for FTM_SYNCONF_CNTINC. */
Kojto 90:cb3d968589d8 4716 #define BS_FTM_SYNCONF_CNTINC (1U) /*!< Bit field size in bits for FTM_SYNCONF_CNTINC. */
Kojto 90:cb3d968589d8 4717
Kojto 90:cb3d968589d8 4718 /*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
Kojto 90:cb3d968589d8 4719 #define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
Kojto 90:cb3d968589d8 4720
Kojto 90:cb3d968589d8 4721 /*! @brief Format value for bitfield FTM_SYNCONF_CNTINC. */
Kojto 90:cb3d968589d8 4722 #define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC)
Kojto 90:cb3d968589d8 4723
Kojto 90:cb3d968589d8 4724 /*! @brief Set the CNTINC field to a new value. */
Kojto 90:cb3d968589d8 4725 #define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
Kojto 90:cb3d968589d8 4726 /*@}*/
Kojto 90:cb3d968589d8 4727
Kojto 90:cb3d968589d8 4728 /*!
Kojto 90:cb3d968589d8 4729 * @name Register FTM_SYNCONF, field INVC[4] (RW)
Kojto 90:cb3d968589d8 4730 *
Kojto 90:cb3d968589d8 4731 * Values:
Kojto 90:cb3d968589d8 4732 * - 0 - INVCTRL register is updated with its buffer value at all rising edges
Kojto 90:cb3d968589d8 4733 * of system clock.
Kojto 90:cb3d968589d8 4734 * - 1 - INVCTRL register is updated with its buffer value by the PWM
Kojto 90:cb3d968589d8 4735 * synchronization.
Kojto 90:cb3d968589d8 4736 */
Kojto 90:cb3d968589d8 4737 /*@{*/
Kojto 90:cb3d968589d8 4738 #define BP_FTM_SYNCONF_INVC (4U) /*!< Bit position for FTM_SYNCONF_INVC. */
Kojto 90:cb3d968589d8 4739 #define BM_FTM_SYNCONF_INVC (0x00000010U) /*!< Bit mask for FTM_SYNCONF_INVC. */
Kojto 90:cb3d968589d8 4740 #define BS_FTM_SYNCONF_INVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_INVC. */
Kojto 90:cb3d968589d8 4741
Kojto 90:cb3d968589d8 4742 /*! @brief Read current value of the FTM_SYNCONF_INVC field. */
Kojto 90:cb3d968589d8 4743 #define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
Kojto 90:cb3d968589d8 4744
Kojto 90:cb3d968589d8 4745 /*! @brief Format value for bitfield FTM_SYNCONF_INVC. */
Kojto 90:cb3d968589d8 4746 #define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC)
Kojto 90:cb3d968589d8 4747
Kojto 90:cb3d968589d8 4748 /*! @brief Set the INVC field to a new value. */
Kojto 90:cb3d968589d8 4749 #define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
Kojto 90:cb3d968589d8 4750 /*@}*/
Kojto 90:cb3d968589d8 4751
Kojto 90:cb3d968589d8 4752 /*!
Kojto 90:cb3d968589d8 4753 * @name Register FTM_SYNCONF, field SWOC[5] (RW)
Kojto 90:cb3d968589d8 4754 *
Kojto 90:cb3d968589d8 4755 * Values:
Kojto 90:cb3d968589d8 4756 * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
Kojto 90:cb3d968589d8 4757 * of system clock.
Kojto 90:cb3d968589d8 4758 * - 1 - SWOCTRL register is updated with its buffer value by the PWM
Kojto 90:cb3d968589d8 4759 * synchronization.
Kojto 90:cb3d968589d8 4760 */
Kojto 90:cb3d968589d8 4761 /*@{*/
Kojto 90:cb3d968589d8 4762 #define BP_FTM_SYNCONF_SWOC (5U) /*!< Bit position for FTM_SYNCONF_SWOC. */
Kojto 90:cb3d968589d8 4763 #define BM_FTM_SYNCONF_SWOC (0x00000020U) /*!< Bit mask for FTM_SYNCONF_SWOC. */
Kojto 90:cb3d968589d8 4764 #define BS_FTM_SYNCONF_SWOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOC. */
Kojto 90:cb3d968589d8 4765
Kojto 90:cb3d968589d8 4766 /*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
Kojto 90:cb3d968589d8 4767 #define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
Kojto 90:cb3d968589d8 4768
Kojto 90:cb3d968589d8 4769 /*! @brief Format value for bitfield FTM_SYNCONF_SWOC. */
Kojto 90:cb3d968589d8 4770 #define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC)
Kojto 90:cb3d968589d8 4771
Kojto 90:cb3d968589d8 4772 /*! @brief Set the SWOC field to a new value. */
Kojto 90:cb3d968589d8 4773 #define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
Kojto 90:cb3d968589d8 4774 /*@}*/
Kojto 90:cb3d968589d8 4775
Kojto 90:cb3d968589d8 4776 /*!
Kojto 90:cb3d968589d8 4777 * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
Kojto 90:cb3d968589d8 4778 *
Kojto 90:cb3d968589d8 4779 * Selects the PWM Synchronization mode.
Kojto 90:cb3d968589d8 4780 *
Kojto 90:cb3d968589d8 4781 * Values:
Kojto 90:cb3d968589d8 4782 * - 0 - Legacy PWM synchronization is selected.
Kojto 90:cb3d968589d8 4783 * - 1 - Enhanced PWM synchronization is selected.
Kojto 90:cb3d968589d8 4784 */
Kojto 90:cb3d968589d8 4785 /*@{*/
Kojto 90:cb3d968589d8 4786 #define BP_FTM_SYNCONF_SYNCMODE (7U) /*!< Bit position for FTM_SYNCONF_SYNCMODE. */
Kojto 90:cb3d968589d8 4787 #define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /*!< Bit mask for FTM_SYNCONF_SYNCMODE. */
Kojto 90:cb3d968589d8 4788 #define BS_FTM_SYNCONF_SYNCMODE (1U) /*!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. */
Kojto 90:cb3d968589d8 4789
Kojto 90:cb3d968589d8 4790 /*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
Kojto 90:cb3d968589d8 4791 #define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
Kojto 90:cb3d968589d8 4792
Kojto 90:cb3d968589d8 4793 /*! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. */
Kojto 90:cb3d968589d8 4794 #define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE)
Kojto 90:cb3d968589d8 4795
Kojto 90:cb3d968589d8 4796 /*! @brief Set the SYNCMODE field to a new value. */
Kojto 90:cb3d968589d8 4797 #define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
Kojto 90:cb3d968589d8 4798 /*@}*/
Kojto 90:cb3d968589d8 4799
Kojto 90:cb3d968589d8 4800 /*!
Kojto 90:cb3d968589d8 4801 * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
Kojto 90:cb3d968589d8 4802 *
Kojto 90:cb3d968589d8 4803 * FTM counter synchronization is activated by the software trigger.
Kojto 90:cb3d968589d8 4804 *
Kojto 90:cb3d968589d8 4805 * Values:
Kojto 90:cb3d968589d8 4806 * - 0 - The software trigger does not activate the FTM counter synchronization.
Kojto 90:cb3d968589d8 4807 * - 1 - The software trigger activates the FTM counter synchronization.
Kojto 90:cb3d968589d8 4808 */
Kojto 90:cb3d968589d8 4809 /*@{*/
Kojto 90:cb3d968589d8 4810 #define BP_FTM_SYNCONF_SWRSTCNT (8U) /*!< Bit position for FTM_SYNCONF_SWRSTCNT. */
Kojto 90:cb3d968589d8 4811 #define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /*!< Bit mask for FTM_SYNCONF_SWRSTCNT. */
Kojto 90:cb3d968589d8 4812 #define BS_FTM_SYNCONF_SWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. */
Kojto 90:cb3d968589d8 4813
Kojto 90:cb3d968589d8 4814 /*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
Kojto 90:cb3d968589d8 4815 #define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
Kojto 90:cb3d968589d8 4816
Kojto 90:cb3d968589d8 4817 /*! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. */
Kojto 90:cb3d968589d8 4818 #define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT)
Kojto 90:cb3d968589d8 4819
Kojto 90:cb3d968589d8 4820 /*! @brief Set the SWRSTCNT field to a new value. */
Kojto 90:cb3d968589d8 4821 #define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
Kojto 90:cb3d968589d8 4822 /*@}*/
Kojto 90:cb3d968589d8 4823
Kojto 90:cb3d968589d8 4824 /*!
Kojto 90:cb3d968589d8 4825 * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
Kojto 90:cb3d968589d8 4826 *
Kojto 90:cb3d968589d8 4827 * MOD, CNTIN, and CV registers synchronization is activated by the software
Kojto 90:cb3d968589d8 4828 * trigger.
Kojto 90:cb3d968589d8 4829 *
Kojto 90:cb3d968589d8 4830 * Values:
Kojto 90:cb3d968589d8 4831 * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
Kojto 90:cb3d968589d8 4832 * synchronization.
Kojto 90:cb3d968589d8 4833 * - 1 - The software trigger activates MOD, CNTIN, and CV registers
Kojto 90:cb3d968589d8 4834 * synchronization.
Kojto 90:cb3d968589d8 4835 */
Kojto 90:cb3d968589d8 4836 /*@{*/
Kojto 90:cb3d968589d8 4837 #define BP_FTM_SYNCONF_SWWRBUF (9U) /*!< Bit position for FTM_SYNCONF_SWWRBUF. */
Kojto 90:cb3d968589d8 4838 #define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /*!< Bit mask for FTM_SYNCONF_SWWRBUF. */
Kojto 90:cb3d968589d8 4839 #define BS_FTM_SYNCONF_SWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. */
Kojto 90:cb3d968589d8 4840
Kojto 90:cb3d968589d8 4841 /*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
Kojto 90:cb3d968589d8 4842 #define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
Kojto 90:cb3d968589d8 4843
Kojto 90:cb3d968589d8 4844 /*! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. */
Kojto 90:cb3d968589d8 4845 #define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF)
Kojto 90:cb3d968589d8 4846
Kojto 90:cb3d968589d8 4847 /*! @brief Set the SWWRBUF field to a new value. */
Kojto 90:cb3d968589d8 4848 #define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
Kojto 90:cb3d968589d8 4849 /*@}*/
Kojto 90:cb3d968589d8 4850
Kojto 90:cb3d968589d8 4851 /*!
Kojto 90:cb3d968589d8 4852 * @name Register FTM_SYNCONF, field SWOM[10] (RW)
Kojto 90:cb3d968589d8 4853 *
Kojto 90:cb3d968589d8 4854 * Output mask synchronization is activated by the software trigger.
Kojto 90:cb3d968589d8 4855 *
Kojto 90:cb3d968589d8 4856 * Values:
Kojto 90:cb3d968589d8 4857 * - 0 - The software trigger does not activate the OUTMASK register
Kojto 90:cb3d968589d8 4858 * synchronization.
Kojto 90:cb3d968589d8 4859 * - 1 - The software trigger activates the OUTMASK register synchronization.
Kojto 90:cb3d968589d8 4860 */
Kojto 90:cb3d968589d8 4861 /*@{*/
Kojto 90:cb3d968589d8 4862 #define BP_FTM_SYNCONF_SWOM (10U) /*!< Bit position for FTM_SYNCONF_SWOM. */
Kojto 90:cb3d968589d8 4863 #define BM_FTM_SYNCONF_SWOM (0x00000400U) /*!< Bit mask for FTM_SYNCONF_SWOM. */
Kojto 90:cb3d968589d8 4864 #define BS_FTM_SYNCONF_SWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWOM. */
Kojto 90:cb3d968589d8 4865
Kojto 90:cb3d968589d8 4866 /*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
Kojto 90:cb3d968589d8 4867 #define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
Kojto 90:cb3d968589d8 4868
Kojto 90:cb3d968589d8 4869 /*! @brief Format value for bitfield FTM_SYNCONF_SWOM. */
Kojto 90:cb3d968589d8 4870 #define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM)
Kojto 90:cb3d968589d8 4871
Kojto 90:cb3d968589d8 4872 /*! @brief Set the SWOM field to a new value. */
Kojto 90:cb3d968589d8 4873 #define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
Kojto 90:cb3d968589d8 4874 /*@}*/
Kojto 90:cb3d968589d8 4875
Kojto 90:cb3d968589d8 4876 /*!
Kojto 90:cb3d968589d8 4877 * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
Kojto 90:cb3d968589d8 4878 *
Kojto 90:cb3d968589d8 4879 * Inverting control synchronization is activated by the software trigger.
Kojto 90:cb3d968589d8 4880 *
Kojto 90:cb3d968589d8 4881 * Values:
Kojto 90:cb3d968589d8 4882 * - 0 - The software trigger does not activate the INVCTRL register
Kojto 90:cb3d968589d8 4883 * synchronization.
Kojto 90:cb3d968589d8 4884 * - 1 - The software trigger activates the INVCTRL register synchronization.
Kojto 90:cb3d968589d8 4885 */
Kojto 90:cb3d968589d8 4886 /*@{*/
Kojto 90:cb3d968589d8 4887 #define BP_FTM_SYNCONF_SWINVC (11U) /*!< Bit position for FTM_SYNCONF_SWINVC. */
Kojto 90:cb3d968589d8 4888 #define BM_FTM_SYNCONF_SWINVC (0x00000800U) /*!< Bit mask for FTM_SYNCONF_SWINVC. */
Kojto 90:cb3d968589d8 4889 #define BS_FTM_SYNCONF_SWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWINVC. */
Kojto 90:cb3d968589d8 4890
Kojto 90:cb3d968589d8 4891 /*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
Kojto 90:cb3d968589d8 4892 #define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
Kojto 90:cb3d968589d8 4893
Kojto 90:cb3d968589d8 4894 /*! @brief Format value for bitfield FTM_SYNCONF_SWINVC. */
Kojto 90:cb3d968589d8 4895 #define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC)
Kojto 90:cb3d968589d8 4896
Kojto 90:cb3d968589d8 4897 /*! @brief Set the SWINVC field to a new value. */
Kojto 90:cb3d968589d8 4898 #define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
Kojto 90:cb3d968589d8 4899 /*@}*/
Kojto 90:cb3d968589d8 4900
Kojto 90:cb3d968589d8 4901 /*!
Kojto 90:cb3d968589d8 4902 * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
Kojto 90:cb3d968589d8 4903 *
Kojto 90:cb3d968589d8 4904 * Software output control synchronization is activated by the software trigger.
Kojto 90:cb3d968589d8 4905 *
Kojto 90:cb3d968589d8 4906 * Values:
Kojto 90:cb3d968589d8 4907 * - 0 - The software trigger does not activate the SWOCTRL register
Kojto 90:cb3d968589d8 4908 * synchronization.
Kojto 90:cb3d968589d8 4909 * - 1 - The software trigger activates the SWOCTRL register synchronization.
Kojto 90:cb3d968589d8 4910 */
Kojto 90:cb3d968589d8 4911 /*@{*/
Kojto 90:cb3d968589d8 4912 #define BP_FTM_SYNCONF_SWSOC (12U) /*!< Bit position for FTM_SYNCONF_SWSOC. */
Kojto 90:cb3d968589d8 4913 #define BM_FTM_SYNCONF_SWSOC (0x00001000U) /*!< Bit mask for FTM_SYNCONF_SWSOC. */
Kojto 90:cb3d968589d8 4914 #define BS_FTM_SYNCONF_SWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_SWSOC. */
Kojto 90:cb3d968589d8 4915
Kojto 90:cb3d968589d8 4916 /*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
Kojto 90:cb3d968589d8 4917 #define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
Kojto 90:cb3d968589d8 4918
Kojto 90:cb3d968589d8 4919 /*! @brief Format value for bitfield FTM_SYNCONF_SWSOC. */
Kojto 90:cb3d968589d8 4920 #define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC)
Kojto 90:cb3d968589d8 4921
Kojto 90:cb3d968589d8 4922 /*! @brief Set the SWSOC field to a new value. */
Kojto 90:cb3d968589d8 4923 #define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
Kojto 90:cb3d968589d8 4924 /*@}*/
Kojto 90:cb3d968589d8 4925
Kojto 90:cb3d968589d8 4926 /*!
Kojto 90:cb3d968589d8 4927 * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
Kojto 90:cb3d968589d8 4928 *
Kojto 90:cb3d968589d8 4929 * FTM counter synchronization is activated by a hardware trigger.
Kojto 90:cb3d968589d8 4930 *
Kojto 90:cb3d968589d8 4931 * Values:
Kojto 90:cb3d968589d8 4932 * - 0 - A hardware trigger does not activate the FTM counter synchronization.
Kojto 90:cb3d968589d8 4933 * - 1 - A hardware trigger activates the FTM counter synchronization.
Kojto 90:cb3d968589d8 4934 */
Kojto 90:cb3d968589d8 4935 /*@{*/
Kojto 90:cb3d968589d8 4936 #define BP_FTM_SYNCONF_HWRSTCNT (16U) /*!< Bit position for FTM_SYNCONF_HWRSTCNT. */
Kojto 90:cb3d968589d8 4937 #define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /*!< Bit mask for FTM_SYNCONF_HWRSTCNT. */
Kojto 90:cb3d968589d8 4938 #define BS_FTM_SYNCONF_HWRSTCNT (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. */
Kojto 90:cb3d968589d8 4939
Kojto 90:cb3d968589d8 4940 /*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
Kojto 90:cb3d968589d8 4941 #define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
Kojto 90:cb3d968589d8 4942
Kojto 90:cb3d968589d8 4943 /*! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. */
Kojto 90:cb3d968589d8 4944 #define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT)
Kojto 90:cb3d968589d8 4945
Kojto 90:cb3d968589d8 4946 /*! @brief Set the HWRSTCNT field to a new value. */
Kojto 90:cb3d968589d8 4947 #define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
Kojto 90:cb3d968589d8 4948 /*@}*/
Kojto 90:cb3d968589d8 4949
Kojto 90:cb3d968589d8 4950 /*!
Kojto 90:cb3d968589d8 4951 * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
Kojto 90:cb3d968589d8 4952 *
Kojto 90:cb3d968589d8 4953 * MOD, CNTIN, and CV registers synchronization is activated by a hardware
Kojto 90:cb3d968589d8 4954 * trigger.
Kojto 90:cb3d968589d8 4955 *
Kojto 90:cb3d968589d8 4956 * Values:
Kojto 90:cb3d968589d8 4957 * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
Kojto 90:cb3d968589d8 4958 * synchronization.
Kojto 90:cb3d968589d8 4959 * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
Kojto 90:cb3d968589d8 4960 * synchronization.
Kojto 90:cb3d968589d8 4961 */
Kojto 90:cb3d968589d8 4962 /*@{*/
Kojto 90:cb3d968589d8 4963 #define BP_FTM_SYNCONF_HWWRBUF (17U) /*!< Bit position for FTM_SYNCONF_HWWRBUF. */
Kojto 90:cb3d968589d8 4964 #define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /*!< Bit mask for FTM_SYNCONF_HWWRBUF. */
Kojto 90:cb3d968589d8 4965 #define BS_FTM_SYNCONF_HWWRBUF (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. */
Kojto 90:cb3d968589d8 4966
Kojto 90:cb3d968589d8 4967 /*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
Kojto 90:cb3d968589d8 4968 #define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
Kojto 90:cb3d968589d8 4969
Kojto 90:cb3d968589d8 4970 /*! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. */
Kojto 90:cb3d968589d8 4971 #define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF)
Kojto 90:cb3d968589d8 4972
Kojto 90:cb3d968589d8 4973 /*! @brief Set the HWWRBUF field to a new value. */
Kojto 90:cb3d968589d8 4974 #define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
Kojto 90:cb3d968589d8 4975 /*@}*/
Kojto 90:cb3d968589d8 4976
Kojto 90:cb3d968589d8 4977 /*!
Kojto 90:cb3d968589d8 4978 * @name Register FTM_SYNCONF, field HWOM[18] (RW)
Kojto 90:cb3d968589d8 4979 *
Kojto 90:cb3d968589d8 4980 * Output mask synchronization is activated by a hardware trigger.
Kojto 90:cb3d968589d8 4981 *
Kojto 90:cb3d968589d8 4982 * Values:
Kojto 90:cb3d968589d8 4983 * - 0 - A hardware trigger does not activate the OUTMASK register
Kojto 90:cb3d968589d8 4984 * synchronization.
Kojto 90:cb3d968589d8 4985 * - 1 - A hardware trigger activates the OUTMASK register synchronization.
Kojto 90:cb3d968589d8 4986 */
Kojto 90:cb3d968589d8 4987 /*@{*/
Kojto 90:cb3d968589d8 4988 #define BP_FTM_SYNCONF_HWOM (18U) /*!< Bit position for FTM_SYNCONF_HWOM. */
Kojto 90:cb3d968589d8 4989 #define BM_FTM_SYNCONF_HWOM (0x00040000U) /*!< Bit mask for FTM_SYNCONF_HWOM. */
Kojto 90:cb3d968589d8 4990 #define BS_FTM_SYNCONF_HWOM (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWOM. */
Kojto 90:cb3d968589d8 4991
Kojto 90:cb3d968589d8 4992 /*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
Kojto 90:cb3d968589d8 4993 #define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
Kojto 90:cb3d968589d8 4994
Kojto 90:cb3d968589d8 4995 /*! @brief Format value for bitfield FTM_SYNCONF_HWOM. */
Kojto 90:cb3d968589d8 4996 #define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM)
Kojto 90:cb3d968589d8 4997
Kojto 90:cb3d968589d8 4998 /*! @brief Set the HWOM field to a new value. */
Kojto 90:cb3d968589d8 4999 #define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
Kojto 90:cb3d968589d8 5000 /*@}*/
Kojto 90:cb3d968589d8 5001
Kojto 90:cb3d968589d8 5002 /*!
Kojto 90:cb3d968589d8 5003 * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
Kojto 90:cb3d968589d8 5004 *
Kojto 90:cb3d968589d8 5005 * Inverting control synchronization is activated by a hardware trigger.
Kojto 90:cb3d968589d8 5006 *
Kojto 90:cb3d968589d8 5007 * Values:
Kojto 90:cb3d968589d8 5008 * - 0 - A hardware trigger does not activate the INVCTRL register
Kojto 90:cb3d968589d8 5009 * synchronization.
Kojto 90:cb3d968589d8 5010 * - 1 - A hardware trigger activates the INVCTRL register synchronization.
Kojto 90:cb3d968589d8 5011 */
Kojto 90:cb3d968589d8 5012 /*@{*/
Kojto 90:cb3d968589d8 5013 #define BP_FTM_SYNCONF_HWINVC (19U) /*!< Bit position for FTM_SYNCONF_HWINVC. */
Kojto 90:cb3d968589d8 5014 #define BM_FTM_SYNCONF_HWINVC (0x00080000U) /*!< Bit mask for FTM_SYNCONF_HWINVC. */
Kojto 90:cb3d968589d8 5015 #define BS_FTM_SYNCONF_HWINVC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWINVC. */
Kojto 90:cb3d968589d8 5016
Kojto 90:cb3d968589d8 5017 /*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
Kojto 90:cb3d968589d8 5018 #define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
Kojto 90:cb3d968589d8 5019
Kojto 90:cb3d968589d8 5020 /*! @brief Format value for bitfield FTM_SYNCONF_HWINVC. */
Kojto 90:cb3d968589d8 5021 #define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC)
Kojto 90:cb3d968589d8 5022
Kojto 90:cb3d968589d8 5023 /*! @brief Set the HWINVC field to a new value. */
Kojto 90:cb3d968589d8 5024 #define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
Kojto 90:cb3d968589d8 5025 /*@}*/
Kojto 90:cb3d968589d8 5026
Kojto 90:cb3d968589d8 5027 /*!
Kojto 90:cb3d968589d8 5028 * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
Kojto 90:cb3d968589d8 5029 *
Kojto 90:cb3d968589d8 5030 * Software output control synchronization is activated by a hardware trigger.
Kojto 90:cb3d968589d8 5031 *
Kojto 90:cb3d968589d8 5032 * Values:
Kojto 90:cb3d968589d8 5033 * - 0 - A hardware trigger does not activate the SWOCTRL register
Kojto 90:cb3d968589d8 5034 * synchronization.
Kojto 90:cb3d968589d8 5035 * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
Kojto 90:cb3d968589d8 5036 */
Kojto 90:cb3d968589d8 5037 /*@{*/
Kojto 90:cb3d968589d8 5038 #define BP_FTM_SYNCONF_HWSOC (20U) /*!< Bit position for FTM_SYNCONF_HWSOC. */
Kojto 90:cb3d968589d8 5039 #define BM_FTM_SYNCONF_HWSOC (0x00100000U) /*!< Bit mask for FTM_SYNCONF_HWSOC. */
Kojto 90:cb3d968589d8 5040 #define BS_FTM_SYNCONF_HWSOC (1U) /*!< Bit field size in bits for FTM_SYNCONF_HWSOC. */
Kojto 90:cb3d968589d8 5041
Kojto 90:cb3d968589d8 5042 /*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
Kojto 90:cb3d968589d8 5043 #define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
Kojto 90:cb3d968589d8 5044
Kojto 90:cb3d968589d8 5045 /*! @brief Format value for bitfield FTM_SYNCONF_HWSOC. */
Kojto 90:cb3d968589d8 5046 #define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC)
Kojto 90:cb3d968589d8 5047
Kojto 90:cb3d968589d8 5048 /*! @brief Set the HWSOC field to a new value. */
Kojto 90:cb3d968589d8 5049 #define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
Kojto 90:cb3d968589d8 5050 /*@}*/
Kojto 90:cb3d968589d8 5051
Kojto 90:cb3d968589d8 5052 /*******************************************************************************
Kojto 90:cb3d968589d8 5053 * HW_FTM_INVCTRL - FTM Inverting Control
Kojto 90:cb3d968589d8 5054 ******************************************************************************/
Kojto 90:cb3d968589d8 5055
Kojto 90:cb3d968589d8 5056 /*!
Kojto 90:cb3d968589d8 5057 * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
Kojto 90:cb3d968589d8 5058 *
Kojto 90:cb3d968589d8 5059 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 5060 *
Kojto 90:cb3d968589d8 5061 * This register controls when the channel (n) output becomes the channel (n+1)
Kojto 90:cb3d968589d8 5062 * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
Kojto 90:cb3d968589d8 5063 * bit enables the inverting operation for the corresponding pair channels m. This
Kojto 90:cb3d968589d8 5064 * register has a write buffer. The INVmEN bit is updated by the INVCTRL
Kojto 90:cb3d968589d8 5065 * register synchronization.
Kojto 90:cb3d968589d8 5066 */
Kojto 90:cb3d968589d8 5067 typedef union _hw_ftm_invctrl
Kojto 90:cb3d968589d8 5068 {
Kojto 90:cb3d968589d8 5069 uint32_t U;
Kojto 90:cb3d968589d8 5070 struct _hw_ftm_invctrl_bitfields
Kojto 90:cb3d968589d8 5071 {
Kojto 90:cb3d968589d8 5072 uint32_t INV0EN : 1; /*!< [0] Pair Channels 0 Inverting Enable */
Kojto 90:cb3d968589d8 5073 uint32_t INV1EN : 1; /*!< [1] Pair Channels 1 Inverting Enable */
Kojto 90:cb3d968589d8 5074 uint32_t INV2EN : 1; /*!< [2] Pair Channels 2 Inverting Enable */
Kojto 90:cb3d968589d8 5075 uint32_t INV3EN : 1; /*!< [3] Pair Channels 3 Inverting Enable */
Kojto 90:cb3d968589d8 5076 uint32_t RESERVED0 : 28; /*!< [31:4] */
Kojto 90:cb3d968589d8 5077 } B;
Kojto 90:cb3d968589d8 5078 } hw_ftm_invctrl_t;
Kojto 90:cb3d968589d8 5079
Kojto 90:cb3d968589d8 5080 /*!
Kojto 90:cb3d968589d8 5081 * @name Constants and macros for entire FTM_INVCTRL register
Kojto 90:cb3d968589d8 5082 */
Kojto 90:cb3d968589d8 5083 /*@{*/
Kojto 90:cb3d968589d8 5084 #define HW_FTM_INVCTRL_ADDR(x) ((x) + 0x90U)
Kojto 90:cb3d968589d8 5085
Kojto 90:cb3d968589d8 5086 #define HW_FTM_INVCTRL(x) (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
Kojto 90:cb3d968589d8 5087 #define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
Kojto 90:cb3d968589d8 5088 #define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
Kojto 90:cb3d968589d8 5089 #define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) | (v)))
Kojto 90:cb3d968589d8 5090 #define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 5091 #define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 5092 /*@}*/
Kojto 90:cb3d968589d8 5093
Kojto 90:cb3d968589d8 5094 /*
Kojto 90:cb3d968589d8 5095 * Constants & macros for individual FTM_INVCTRL bitfields
Kojto 90:cb3d968589d8 5096 */
Kojto 90:cb3d968589d8 5097
Kojto 90:cb3d968589d8 5098 /*!
Kojto 90:cb3d968589d8 5099 * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
Kojto 90:cb3d968589d8 5100 *
Kojto 90:cb3d968589d8 5101 * Values:
Kojto 90:cb3d968589d8 5102 * - 0 - Inverting is disabled.
Kojto 90:cb3d968589d8 5103 * - 1 - Inverting is enabled.
Kojto 90:cb3d968589d8 5104 */
Kojto 90:cb3d968589d8 5105 /*@{*/
Kojto 90:cb3d968589d8 5106 #define BP_FTM_INVCTRL_INV0EN (0U) /*!< Bit position for FTM_INVCTRL_INV0EN. */
Kojto 90:cb3d968589d8 5107 #define BM_FTM_INVCTRL_INV0EN (0x00000001U) /*!< Bit mask for FTM_INVCTRL_INV0EN. */
Kojto 90:cb3d968589d8 5108 #define BS_FTM_INVCTRL_INV0EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV0EN. */
Kojto 90:cb3d968589d8 5109
Kojto 90:cb3d968589d8 5110 /*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
Kojto 90:cb3d968589d8 5111 #define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
Kojto 90:cb3d968589d8 5112
Kojto 90:cb3d968589d8 5113 /*! @brief Format value for bitfield FTM_INVCTRL_INV0EN. */
Kojto 90:cb3d968589d8 5114 #define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN)
Kojto 90:cb3d968589d8 5115
Kojto 90:cb3d968589d8 5116 /*! @brief Set the INV0EN field to a new value. */
Kojto 90:cb3d968589d8 5117 #define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
Kojto 90:cb3d968589d8 5118 /*@}*/
Kojto 90:cb3d968589d8 5119
Kojto 90:cb3d968589d8 5120 /*!
Kojto 90:cb3d968589d8 5121 * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
Kojto 90:cb3d968589d8 5122 *
Kojto 90:cb3d968589d8 5123 * Values:
Kojto 90:cb3d968589d8 5124 * - 0 - Inverting is disabled.
Kojto 90:cb3d968589d8 5125 * - 1 - Inverting is enabled.
Kojto 90:cb3d968589d8 5126 */
Kojto 90:cb3d968589d8 5127 /*@{*/
Kojto 90:cb3d968589d8 5128 #define BP_FTM_INVCTRL_INV1EN (1U) /*!< Bit position for FTM_INVCTRL_INV1EN. */
Kojto 90:cb3d968589d8 5129 #define BM_FTM_INVCTRL_INV1EN (0x00000002U) /*!< Bit mask for FTM_INVCTRL_INV1EN. */
Kojto 90:cb3d968589d8 5130 #define BS_FTM_INVCTRL_INV1EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV1EN. */
Kojto 90:cb3d968589d8 5131
Kojto 90:cb3d968589d8 5132 /*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
Kojto 90:cb3d968589d8 5133 #define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
Kojto 90:cb3d968589d8 5134
Kojto 90:cb3d968589d8 5135 /*! @brief Format value for bitfield FTM_INVCTRL_INV1EN. */
Kojto 90:cb3d968589d8 5136 #define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN)
Kojto 90:cb3d968589d8 5137
Kojto 90:cb3d968589d8 5138 /*! @brief Set the INV1EN field to a new value. */
Kojto 90:cb3d968589d8 5139 #define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
Kojto 90:cb3d968589d8 5140 /*@}*/
Kojto 90:cb3d968589d8 5141
Kojto 90:cb3d968589d8 5142 /*!
Kojto 90:cb3d968589d8 5143 * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
Kojto 90:cb3d968589d8 5144 *
Kojto 90:cb3d968589d8 5145 * Values:
Kojto 90:cb3d968589d8 5146 * - 0 - Inverting is disabled.
Kojto 90:cb3d968589d8 5147 * - 1 - Inverting is enabled.
Kojto 90:cb3d968589d8 5148 */
Kojto 90:cb3d968589d8 5149 /*@{*/
Kojto 90:cb3d968589d8 5150 #define BP_FTM_INVCTRL_INV2EN (2U) /*!< Bit position for FTM_INVCTRL_INV2EN. */
Kojto 90:cb3d968589d8 5151 #define BM_FTM_INVCTRL_INV2EN (0x00000004U) /*!< Bit mask for FTM_INVCTRL_INV2EN. */
Kojto 90:cb3d968589d8 5152 #define BS_FTM_INVCTRL_INV2EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV2EN. */
Kojto 90:cb3d968589d8 5153
Kojto 90:cb3d968589d8 5154 /*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
Kojto 90:cb3d968589d8 5155 #define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
Kojto 90:cb3d968589d8 5156
Kojto 90:cb3d968589d8 5157 /*! @brief Format value for bitfield FTM_INVCTRL_INV2EN. */
Kojto 90:cb3d968589d8 5158 #define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN)
Kojto 90:cb3d968589d8 5159
Kojto 90:cb3d968589d8 5160 /*! @brief Set the INV2EN field to a new value. */
Kojto 90:cb3d968589d8 5161 #define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
Kojto 90:cb3d968589d8 5162 /*@}*/
Kojto 90:cb3d968589d8 5163
Kojto 90:cb3d968589d8 5164 /*!
Kojto 90:cb3d968589d8 5165 * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
Kojto 90:cb3d968589d8 5166 *
Kojto 90:cb3d968589d8 5167 * Values:
Kojto 90:cb3d968589d8 5168 * - 0 - Inverting is disabled.
Kojto 90:cb3d968589d8 5169 * - 1 - Inverting is enabled.
Kojto 90:cb3d968589d8 5170 */
Kojto 90:cb3d968589d8 5171 /*@{*/
Kojto 90:cb3d968589d8 5172 #define BP_FTM_INVCTRL_INV3EN (3U) /*!< Bit position for FTM_INVCTRL_INV3EN. */
Kojto 90:cb3d968589d8 5173 #define BM_FTM_INVCTRL_INV3EN (0x00000008U) /*!< Bit mask for FTM_INVCTRL_INV3EN. */
Kojto 90:cb3d968589d8 5174 #define BS_FTM_INVCTRL_INV3EN (1U) /*!< Bit field size in bits for FTM_INVCTRL_INV3EN. */
Kojto 90:cb3d968589d8 5175
Kojto 90:cb3d968589d8 5176 /*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
Kojto 90:cb3d968589d8 5177 #define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
Kojto 90:cb3d968589d8 5178
Kojto 90:cb3d968589d8 5179 /*! @brief Format value for bitfield FTM_INVCTRL_INV3EN. */
Kojto 90:cb3d968589d8 5180 #define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN)
Kojto 90:cb3d968589d8 5181
Kojto 90:cb3d968589d8 5182 /*! @brief Set the INV3EN field to a new value. */
Kojto 90:cb3d968589d8 5183 #define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
Kojto 90:cb3d968589d8 5184 /*@}*/
Kojto 90:cb3d968589d8 5185
Kojto 90:cb3d968589d8 5186 /*******************************************************************************
Kojto 90:cb3d968589d8 5187 * HW_FTM_SWOCTRL - FTM Software Output Control
Kojto 90:cb3d968589d8 5188 ******************************************************************************/
Kojto 90:cb3d968589d8 5189
Kojto 90:cb3d968589d8 5190 /*!
Kojto 90:cb3d968589d8 5191 * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
Kojto 90:cb3d968589d8 5192 *
Kojto 90:cb3d968589d8 5193 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 5194 *
Kojto 90:cb3d968589d8 5195 * This register enables software control of channel (n) output and defines the
Kojto 90:cb3d968589d8 5196 * value forced to the channel (n) output: The CHnOC bits enable the control of
Kojto 90:cb3d968589d8 5197 * the corresponding channel (n) output by software. The CHnOCV bits select the
Kojto 90:cb3d968589d8 5198 * value that is forced at the corresponding channel (n) output. This register has
Kojto 90:cb3d968589d8 5199 * a write buffer. The fields are updated by the SWOCTRL register synchronization.
Kojto 90:cb3d968589d8 5200 */
Kojto 90:cb3d968589d8 5201 typedef union _hw_ftm_swoctrl
Kojto 90:cb3d968589d8 5202 {
Kojto 90:cb3d968589d8 5203 uint32_t U;
Kojto 90:cb3d968589d8 5204 struct _hw_ftm_swoctrl_bitfields
Kojto 90:cb3d968589d8 5205 {
Kojto 90:cb3d968589d8 5206 uint32_t CH0OC : 1; /*!< [0] Channel 0 Software Output Control Enable
Kojto 90:cb3d968589d8 5207 * */
Kojto 90:cb3d968589d8 5208 uint32_t CH1OC : 1; /*!< [1] Channel 1 Software Output Control Enable
Kojto 90:cb3d968589d8 5209 * */
Kojto 90:cb3d968589d8 5210 uint32_t CH2OC : 1; /*!< [2] Channel 2 Software Output Control Enable
Kojto 90:cb3d968589d8 5211 * */
Kojto 90:cb3d968589d8 5212 uint32_t CH3OC : 1; /*!< [3] Channel 3 Software Output Control Enable
Kojto 90:cb3d968589d8 5213 * */
Kojto 90:cb3d968589d8 5214 uint32_t CH4OC : 1; /*!< [4] Channel 4 Software Output Control Enable
Kojto 90:cb3d968589d8 5215 * */
Kojto 90:cb3d968589d8 5216 uint32_t CH5OC : 1; /*!< [5] Channel 5 Software Output Control Enable
Kojto 90:cb3d968589d8 5217 * */
Kojto 90:cb3d968589d8 5218 uint32_t CH6OC : 1; /*!< [6] Channel 6 Software Output Control Enable
Kojto 90:cb3d968589d8 5219 * */
Kojto 90:cb3d968589d8 5220 uint32_t CH7OC : 1; /*!< [7] Channel 7 Software Output Control Enable
Kojto 90:cb3d968589d8 5221 * */
Kojto 90:cb3d968589d8 5222 uint32_t CH0OCV : 1; /*!< [8] Channel 0 Software Output Control Value
Kojto 90:cb3d968589d8 5223 * */
Kojto 90:cb3d968589d8 5224 uint32_t CH1OCV : 1; /*!< [9] Channel 1 Software Output Control Value
Kojto 90:cb3d968589d8 5225 * */
Kojto 90:cb3d968589d8 5226 uint32_t CH2OCV : 1; /*!< [10] Channel 2 Software Output Control
Kojto 90:cb3d968589d8 5227 * Value */
Kojto 90:cb3d968589d8 5228 uint32_t CH3OCV : 1; /*!< [11] Channel 3 Software Output Control
Kojto 90:cb3d968589d8 5229 * Value */
Kojto 90:cb3d968589d8 5230 uint32_t CH4OCV : 1; /*!< [12] Channel 4 Software Output Control
Kojto 90:cb3d968589d8 5231 * Value */
Kojto 90:cb3d968589d8 5232 uint32_t CH5OCV : 1; /*!< [13] Channel 5 Software Output Control
Kojto 90:cb3d968589d8 5233 * Value */
Kojto 90:cb3d968589d8 5234 uint32_t CH6OCV : 1; /*!< [14] Channel 6 Software Output Control
Kojto 90:cb3d968589d8 5235 * Value */
Kojto 90:cb3d968589d8 5236 uint32_t CH7OCV : 1; /*!< [15] Channel 7 Software Output Control
Kojto 90:cb3d968589d8 5237 * Value */
Kojto 90:cb3d968589d8 5238 uint32_t RESERVED0 : 16; /*!< [31:16] */
Kojto 90:cb3d968589d8 5239 } B;
Kojto 90:cb3d968589d8 5240 } hw_ftm_swoctrl_t;
Kojto 90:cb3d968589d8 5241
Kojto 90:cb3d968589d8 5242 /*!
Kojto 90:cb3d968589d8 5243 * @name Constants and macros for entire FTM_SWOCTRL register
Kojto 90:cb3d968589d8 5244 */
Kojto 90:cb3d968589d8 5245 /*@{*/
Kojto 90:cb3d968589d8 5246 #define HW_FTM_SWOCTRL_ADDR(x) ((x) + 0x94U)
Kojto 90:cb3d968589d8 5247
Kojto 90:cb3d968589d8 5248 #define HW_FTM_SWOCTRL(x) (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
Kojto 90:cb3d968589d8 5249 #define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
Kojto 90:cb3d968589d8 5250 #define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
Kojto 90:cb3d968589d8 5251 #define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) | (v)))
Kojto 90:cb3d968589d8 5252 #define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 5253 #define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 5254 /*@}*/
Kojto 90:cb3d968589d8 5255
Kojto 90:cb3d968589d8 5256 /*
Kojto 90:cb3d968589d8 5257 * Constants & macros for individual FTM_SWOCTRL bitfields
Kojto 90:cb3d968589d8 5258 */
Kojto 90:cb3d968589d8 5259
Kojto 90:cb3d968589d8 5260 /*!
Kojto 90:cb3d968589d8 5261 * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
Kojto 90:cb3d968589d8 5262 *
Kojto 90:cb3d968589d8 5263 * Values:
Kojto 90:cb3d968589d8 5264 * - 0 - The channel output is not affected by software output control.
Kojto 90:cb3d968589d8 5265 * - 1 - The channel output is affected by software output control.
Kojto 90:cb3d968589d8 5266 */
Kojto 90:cb3d968589d8 5267 /*@{*/
Kojto 90:cb3d968589d8 5268 #define BP_FTM_SWOCTRL_CH0OC (0U) /*!< Bit position for FTM_SWOCTRL_CH0OC. */
Kojto 90:cb3d968589d8 5269 #define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /*!< Bit mask for FTM_SWOCTRL_CH0OC. */
Kojto 90:cb3d968589d8 5270 #define BS_FTM_SWOCTRL_CH0OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OC. */
Kojto 90:cb3d968589d8 5271
Kojto 90:cb3d968589d8 5272 /*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
Kojto 90:cb3d968589d8 5273 #define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
Kojto 90:cb3d968589d8 5274
Kojto 90:cb3d968589d8 5275 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. */
Kojto 90:cb3d968589d8 5276 #define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC)
Kojto 90:cb3d968589d8 5277
Kojto 90:cb3d968589d8 5278 /*! @brief Set the CH0OC field to a new value. */
Kojto 90:cb3d968589d8 5279 #define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
Kojto 90:cb3d968589d8 5280 /*@}*/
Kojto 90:cb3d968589d8 5281
Kojto 90:cb3d968589d8 5282 /*!
Kojto 90:cb3d968589d8 5283 * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
Kojto 90:cb3d968589d8 5284 *
Kojto 90:cb3d968589d8 5285 * Values:
Kojto 90:cb3d968589d8 5286 * - 0 - The channel output is not affected by software output control.
Kojto 90:cb3d968589d8 5287 * - 1 - The channel output is affected by software output control.
Kojto 90:cb3d968589d8 5288 */
Kojto 90:cb3d968589d8 5289 /*@{*/
Kojto 90:cb3d968589d8 5290 #define BP_FTM_SWOCTRL_CH1OC (1U) /*!< Bit position for FTM_SWOCTRL_CH1OC. */
Kojto 90:cb3d968589d8 5291 #define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /*!< Bit mask for FTM_SWOCTRL_CH1OC. */
Kojto 90:cb3d968589d8 5292 #define BS_FTM_SWOCTRL_CH1OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OC. */
Kojto 90:cb3d968589d8 5293
Kojto 90:cb3d968589d8 5294 /*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
Kojto 90:cb3d968589d8 5295 #define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
Kojto 90:cb3d968589d8 5296
Kojto 90:cb3d968589d8 5297 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. */
Kojto 90:cb3d968589d8 5298 #define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC)
Kojto 90:cb3d968589d8 5299
Kojto 90:cb3d968589d8 5300 /*! @brief Set the CH1OC field to a new value. */
Kojto 90:cb3d968589d8 5301 #define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
Kojto 90:cb3d968589d8 5302 /*@}*/
Kojto 90:cb3d968589d8 5303
Kojto 90:cb3d968589d8 5304 /*!
Kojto 90:cb3d968589d8 5305 * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
Kojto 90:cb3d968589d8 5306 *
Kojto 90:cb3d968589d8 5307 * Values:
Kojto 90:cb3d968589d8 5308 * - 0 - The channel output is not affected by software output control.
Kojto 90:cb3d968589d8 5309 * - 1 - The channel output is affected by software output control.
Kojto 90:cb3d968589d8 5310 */
Kojto 90:cb3d968589d8 5311 /*@{*/
Kojto 90:cb3d968589d8 5312 #define BP_FTM_SWOCTRL_CH2OC (2U) /*!< Bit position for FTM_SWOCTRL_CH2OC. */
Kojto 90:cb3d968589d8 5313 #define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /*!< Bit mask for FTM_SWOCTRL_CH2OC. */
Kojto 90:cb3d968589d8 5314 #define BS_FTM_SWOCTRL_CH2OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OC. */
Kojto 90:cb3d968589d8 5315
Kojto 90:cb3d968589d8 5316 /*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
Kojto 90:cb3d968589d8 5317 #define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
Kojto 90:cb3d968589d8 5318
Kojto 90:cb3d968589d8 5319 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. */
Kojto 90:cb3d968589d8 5320 #define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC)
Kojto 90:cb3d968589d8 5321
Kojto 90:cb3d968589d8 5322 /*! @brief Set the CH2OC field to a new value. */
Kojto 90:cb3d968589d8 5323 #define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
Kojto 90:cb3d968589d8 5324 /*@}*/
Kojto 90:cb3d968589d8 5325
Kojto 90:cb3d968589d8 5326 /*!
Kojto 90:cb3d968589d8 5327 * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
Kojto 90:cb3d968589d8 5328 *
Kojto 90:cb3d968589d8 5329 * Values:
Kojto 90:cb3d968589d8 5330 * - 0 - The channel output is not affected by software output control.
Kojto 90:cb3d968589d8 5331 * - 1 - The channel output is affected by software output control.
Kojto 90:cb3d968589d8 5332 */
Kojto 90:cb3d968589d8 5333 /*@{*/
Kojto 90:cb3d968589d8 5334 #define BP_FTM_SWOCTRL_CH3OC (3U) /*!< Bit position for FTM_SWOCTRL_CH3OC. */
Kojto 90:cb3d968589d8 5335 #define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /*!< Bit mask for FTM_SWOCTRL_CH3OC. */
Kojto 90:cb3d968589d8 5336 #define BS_FTM_SWOCTRL_CH3OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OC. */
Kojto 90:cb3d968589d8 5337
Kojto 90:cb3d968589d8 5338 /*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
Kojto 90:cb3d968589d8 5339 #define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
Kojto 90:cb3d968589d8 5340
Kojto 90:cb3d968589d8 5341 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. */
Kojto 90:cb3d968589d8 5342 #define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC)
Kojto 90:cb3d968589d8 5343
Kojto 90:cb3d968589d8 5344 /*! @brief Set the CH3OC field to a new value. */
Kojto 90:cb3d968589d8 5345 #define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
Kojto 90:cb3d968589d8 5346 /*@}*/
Kojto 90:cb3d968589d8 5347
Kojto 90:cb3d968589d8 5348 /*!
Kojto 90:cb3d968589d8 5349 * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
Kojto 90:cb3d968589d8 5350 *
Kojto 90:cb3d968589d8 5351 * Values:
Kojto 90:cb3d968589d8 5352 * - 0 - The channel output is not affected by software output control.
Kojto 90:cb3d968589d8 5353 * - 1 - The channel output is affected by software output control.
Kojto 90:cb3d968589d8 5354 */
Kojto 90:cb3d968589d8 5355 /*@{*/
Kojto 90:cb3d968589d8 5356 #define BP_FTM_SWOCTRL_CH4OC (4U) /*!< Bit position for FTM_SWOCTRL_CH4OC. */
Kojto 90:cb3d968589d8 5357 #define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /*!< Bit mask for FTM_SWOCTRL_CH4OC. */
Kojto 90:cb3d968589d8 5358 #define BS_FTM_SWOCTRL_CH4OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OC. */
Kojto 90:cb3d968589d8 5359
Kojto 90:cb3d968589d8 5360 /*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
Kojto 90:cb3d968589d8 5361 #define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
Kojto 90:cb3d968589d8 5362
Kojto 90:cb3d968589d8 5363 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. */
Kojto 90:cb3d968589d8 5364 #define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC)
Kojto 90:cb3d968589d8 5365
Kojto 90:cb3d968589d8 5366 /*! @brief Set the CH4OC field to a new value. */
Kojto 90:cb3d968589d8 5367 #define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
Kojto 90:cb3d968589d8 5368 /*@}*/
Kojto 90:cb3d968589d8 5369
Kojto 90:cb3d968589d8 5370 /*!
Kojto 90:cb3d968589d8 5371 * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
Kojto 90:cb3d968589d8 5372 *
Kojto 90:cb3d968589d8 5373 * Values:
Kojto 90:cb3d968589d8 5374 * - 0 - The channel output is not affected by software output control.
Kojto 90:cb3d968589d8 5375 * - 1 - The channel output is affected by software output control.
Kojto 90:cb3d968589d8 5376 */
Kojto 90:cb3d968589d8 5377 /*@{*/
Kojto 90:cb3d968589d8 5378 #define BP_FTM_SWOCTRL_CH5OC (5U) /*!< Bit position for FTM_SWOCTRL_CH5OC. */
Kojto 90:cb3d968589d8 5379 #define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /*!< Bit mask for FTM_SWOCTRL_CH5OC. */
Kojto 90:cb3d968589d8 5380 #define BS_FTM_SWOCTRL_CH5OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OC. */
Kojto 90:cb3d968589d8 5381
Kojto 90:cb3d968589d8 5382 /*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
Kojto 90:cb3d968589d8 5383 #define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
Kojto 90:cb3d968589d8 5384
Kojto 90:cb3d968589d8 5385 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. */
Kojto 90:cb3d968589d8 5386 #define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC)
Kojto 90:cb3d968589d8 5387
Kojto 90:cb3d968589d8 5388 /*! @brief Set the CH5OC field to a new value. */
Kojto 90:cb3d968589d8 5389 #define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
Kojto 90:cb3d968589d8 5390 /*@}*/
Kojto 90:cb3d968589d8 5391
Kojto 90:cb3d968589d8 5392 /*!
Kojto 90:cb3d968589d8 5393 * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
Kojto 90:cb3d968589d8 5394 *
Kojto 90:cb3d968589d8 5395 * Values:
Kojto 90:cb3d968589d8 5396 * - 0 - The channel output is not affected by software output control.
Kojto 90:cb3d968589d8 5397 * - 1 - The channel output is affected by software output control.
Kojto 90:cb3d968589d8 5398 */
Kojto 90:cb3d968589d8 5399 /*@{*/
Kojto 90:cb3d968589d8 5400 #define BP_FTM_SWOCTRL_CH6OC (6U) /*!< Bit position for FTM_SWOCTRL_CH6OC. */
Kojto 90:cb3d968589d8 5401 #define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /*!< Bit mask for FTM_SWOCTRL_CH6OC. */
Kojto 90:cb3d968589d8 5402 #define BS_FTM_SWOCTRL_CH6OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OC. */
Kojto 90:cb3d968589d8 5403
Kojto 90:cb3d968589d8 5404 /*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
Kojto 90:cb3d968589d8 5405 #define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
Kojto 90:cb3d968589d8 5406
Kojto 90:cb3d968589d8 5407 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. */
Kojto 90:cb3d968589d8 5408 #define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC)
Kojto 90:cb3d968589d8 5409
Kojto 90:cb3d968589d8 5410 /*! @brief Set the CH6OC field to a new value. */
Kojto 90:cb3d968589d8 5411 #define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
Kojto 90:cb3d968589d8 5412 /*@}*/
Kojto 90:cb3d968589d8 5413
Kojto 90:cb3d968589d8 5414 /*!
Kojto 90:cb3d968589d8 5415 * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
Kojto 90:cb3d968589d8 5416 *
Kojto 90:cb3d968589d8 5417 * Values:
Kojto 90:cb3d968589d8 5418 * - 0 - The channel output is not affected by software output control.
Kojto 90:cb3d968589d8 5419 * - 1 - The channel output is affected by software output control.
Kojto 90:cb3d968589d8 5420 */
Kojto 90:cb3d968589d8 5421 /*@{*/
Kojto 90:cb3d968589d8 5422 #define BP_FTM_SWOCTRL_CH7OC (7U) /*!< Bit position for FTM_SWOCTRL_CH7OC. */
Kojto 90:cb3d968589d8 5423 #define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /*!< Bit mask for FTM_SWOCTRL_CH7OC. */
Kojto 90:cb3d968589d8 5424 #define BS_FTM_SWOCTRL_CH7OC (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OC. */
Kojto 90:cb3d968589d8 5425
Kojto 90:cb3d968589d8 5426 /*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
Kojto 90:cb3d968589d8 5427 #define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
Kojto 90:cb3d968589d8 5428
Kojto 90:cb3d968589d8 5429 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. */
Kojto 90:cb3d968589d8 5430 #define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC)
Kojto 90:cb3d968589d8 5431
Kojto 90:cb3d968589d8 5432 /*! @brief Set the CH7OC field to a new value. */
Kojto 90:cb3d968589d8 5433 #define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
Kojto 90:cb3d968589d8 5434 /*@}*/
Kojto 90:cb3d968589d8 5435
Kojto 90:cb3d968589d8 5436 /*!
Kojto 90:cb3d968589d8 5437 * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
Kojto 90:cb3d968589d8 5438 *
Kojto 90:cb3d968589d8 5439 * Values:
Kojto 90:cb3d968589d8 5440 * - 0 - The software output control forces 0 to the channel output.
Kojto 90:cb3d968589d8 5441 * - 1 - The software output control forces 1 to the channel output.
Kojto 90:cb3d968589d8 5442 */
Kojto 90:cb3d968589d8 5443 /*@{*/
Kojto 90:cb3d968589d8 5444 #define BP_FTM_SWOCTRL_CH0OCV (8U) /*!< Bit position for FTM_SWOCTRL_CH0OCV. */
Kojto 90:cb3d968589d8 5445 #define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /*!< Bit mask for FTM_SWOCTRL_CH0OCV. */
Kojto 90:cb3d968589d8 5446 #define BS_FTM_SWOCTRL_CH0OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. */
Kojto 90:cb3d968589d8 5447
Kojto 90:cb3d968589d8 5448 /*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
Kojto 90:cb3d968589d8 5449 #define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
Kojto 90:cb3d968589d8 5450
Kojto 90:cb3d968589d8 5451 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. */
Kojto 90:cb3d968589d8 5452 #define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV)
Kojto 90:cb3d968589d8 5453
Kojto 90:cb3d968589d8 5454 /*! @brief Set the CH0OCV field to a new value. */
Kojto 90:cb3d968589d8 5455 #define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
Kojto 90:cb3d968589d8 5456 /*@}*/
Kojto 90:cb3d968589d8 5457
Kojto 90:cb3d968589d8 5458 /*!
Kojto 90:cb3d968589d8 5459 * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
Kojto 90:cb3d968589d8 5460 *
Kojto 90:cb3d968589d8 5461 * Values:
Kojto 90:cb3d968589d8 5462 * - 0 - The software output control forces 0 to the channel output.
Kojto 90:cb3d968589d8 5463 * - 1 - The software output control forces 1 to the channel output.
Kojto 90:cb3d968589d8 5464 */
Kojto 90:cb3d968589d8 5465 /*@{*/
Kojto 90:cb3d968589d8 5466 #define BP_FTM_SWOCTRL_CH1OCV (9U) /*!< Bit position for FTM_SWOCTRL_CH1OCV. */
Kojto 90:cb3d968589d8 5467 #define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /*!< Bit mask for FTM_SWOCTRL_CH1OCV. */
Kojto 90:cb3d968589d8 5468 #define BS_FTM_SWOCTRL_CH1OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. */
Kojto 90:cb3d968589d8 5469
Kojto 90:cb3d968589d8 5470 /*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
Kojto 90:cb3d968589d8 5471 #define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
Kojto 90:cb3d968589d8 5472
Kojto 90:cb3d968589d8 5473 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. */
Kojto 90:cb3d968589d8 5474 #define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV)
Kojto 90:cb3d968589d8 5475
Kojto 90:cb3d968589d8 5476 /*! @brief Set the CH1OCV field to a new value. */
Kojto 90:cb3d968589d8 5477 #define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
Kojto 90:cb3d968589d8 5478 /*@}*/
Kojto 90:cb3d968589d8 5479
Kojto 90:cb3d968589d8 5480 /*!
Kojto 90:cb3d968589d8 5481 * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
Kojto 90:cb3d968589d8 5482 *
Kojto 90:cb3d968589d8 5483 * Values:
Kojto 90:cb3d968589d8 5484 * - 0 - The software output control forces 0 to the channel output.
Kojto 90:cb3d968589d8 5485 * - 1 - The software output control forces 1 to the channel output.
Kojto 90:cb3d968589d8 5486 */
Kojto 90:cb3d968589d8 5487 /*@{*/
Kojto 90:cb3d968589d8 5488 #define BP_FTM_SWOCTRL_CH2OCV (10U) /*!< Bit position for FTM_SWOCTRL_CH2OCV. */
Kojto 90:cb3d968589d8 5489 #define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /*!< Bit mask for FTM_SWOCTRL_CH2OCV. */
Kojto 90:cb3d968589d8 5490 #define BS_FTM_SWOCTRL_CH2OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. */
Kojto 90:cb3d968589d8 5491
Kojto 90:cb3d968589d8 5492 /*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
Kojto 90:cb3d968589d8 5493 #define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
Kojto 90:cb3d968589d8 5494
Kojto 90:cb3d968589d8 5495 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. */
Kojto 90:cb3d968589d8 5496 #define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV)
Kojto 90:cb3d968589d8 5497
Kojto 90:cb3d968589d8 5498 /*! @brief Set the CH2OCV field to a new value. */
Kojto 90:cb3d968589d8 5499 #define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
Kojto 90:cb3d968589d8 5500 /*@}*/
Kojto 90:cb3d968589d8 5501
Kojto 90:cb3d968589d8 5502 /*!
Kojto 90:cb3d968589d8 5503 * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
Kojto 90:cb3d968589d8 5504 *
Kojto 90:cb3d968589d8 5505 * Values:
Kojto 90:cb3d968589d8 5506 * - 0 - The software output control forces 0 to the channel output.
Kojto 90:cb3d968589d8 5507 * - 1 - The software output control forces 1 to the channel output.
Kojto 90:cb3d968589d8 5508 */
Kojto 90:cb3d968589d8 5509 /*@{*/
Kojto 90:cb3d968589d8 5510 #define BP_FTM_SWOCTRL_CH3OCV (11U) /*!< Bit position for FTM_SWOCTRL_CH3OCV. */
Kojto 90:cb3d968589d8 5511 #define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /*!< Bit mask for FTM_SWOCTRL_CH3OCV. */
Kojto 90:cb3d968589d8 5512 #define BS_FTM_SWOCTRL_CH3OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. */
Kojto 90:cb3d968589d8 5513
Kojto 90:cb3d968589d8 5514 /*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
Kojto 90:cb3d968589d8 5515 #define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
Kojto 90:cb3d968589d8 5516
Kojto 90:cb3d968589d8 5517 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. */
Kojto 90:cb3d968589d8 5518 #define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV)
Kojto 90:cb3d968589d8 5519
Kojto 90:cb3d968589d8 5520 /*! @brief Set the CH3OCV field to a new value. */
Kojto 90:cb3d968589d8 5521 #define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
Kojto 90:cb3d968589d8 5522 /*@}*/
Kojto 90:cb3d968589d8 5523
Kojto 90:cb3d968589d8 5524 /*!
Kojto 90:cb3d968589d8 5525 * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
Kojto 90:cb3d968589d8 5526 *
Kojto 90:cb3d968589d8 5527 * Values:
Kojto 90:cb3d968589d8 5528 * - 0 - The software output control forces 0 to the channel output.
Kojto 90:cb3d968589d8 5529 * - 1 - The software output control forces 1 to the channel output.
Kojto 90:cb3d968589d8 5530 */
Kojto 90:cb3d968589d8 5531 /*@{*/
Kojto 90:cb3d968589d8 5532 #define BP_FTM_SWOCTRL_CH4OCV (12U) /*!< Bit position for FTM_SWOCTRL_CH4OCV. */
Kojto 90:cb3d968589d8 5533 #define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /*!< Bit mask for FTM_SWOCTRL_CH4OCV. */
Kojto 90:cb3d968589d8 5534 #define BS_FTM_SWOCTRL_CH4OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. */
Kojto 90:cb3d968589d8 5535
Kojto 90:cb3d968589d8 5536 /*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
Kojto 90:cb3d968589d8 5537 #define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
Kojto 90:cb3d968589d8 5538
Kojto 90:cb3d968589d8 5539 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. */
Kojto 90:cb3d968589d8 5540 #define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV)
Kojto 90:cb3d968589d8 5541
Kojto 90:cb3d968589d8 5542 /*! @brief Set the CH4OCV field to a new value. */
Kojto 90:cb3d968589d8 5543 #define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
Kojto 90:cb3d968589d8 5544 /*@}*/
Kojto 90:cb3d968589d8 5545
Kojto 90:cb3d968589d8 5546 /*!
Kojto 90:cb3d968589d8 5547 * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
Kojto 90:cb3d968589d8 5548 *
Kojto 90:cb3d968589d8 5549 * Values:
Kojto 90:cb3d968589d8 5550 * - 0 - The software output control forces 0 to the channel output.
Kojto 90:cb3d968589d8 5551 * - 1 - The software output control forces 1 to the channel output.
Kojto 90:cb3d968589d8 5552 */
Kojto 90:cb3d968589d8 5553 /*@{*/
Kojto 90:cb3d968589d8 5554 #define BP_FTM_SWOCTRL_CH5OCV (13U) /*!< Bit position for FTM_SWOCTRL_CH5OCV. */
Kojto 90:cb3d968589d8 5555 #define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /*!< Bit mask for FTM_SWOCTRL_CH5OCV. */
Kojto 90:cb3d968589d8 5556 #define BS_FTM_SWOCTRL_CH5OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. */
Kojto 90:cb3d968589d8 5557
Kojto 90:cb3d968589d8 5558 /*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
Kojto 90:cb3d968589d8 5559 #define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
Kojto 90:cb3d968589d8 5560
Kojto 90:cb3d968589d8 5561 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. */
Kojto 90:cb3d968589d8 5562 #define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV)
Kojto 90:cb3d968589d8 5563
Kojto 90:cb3d968589d8 5564 /*! @brief Set the CH5OCV field to a new value. */
Kojto 90:cb3d968589d8 5565 #define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
Kojto 90:cb3d968589d8 5566 /*@}*/
Kojto 90:cb3d968589d8 5567
Kojto 90:cb3d968589d8 5568 /*!
Kojto 90:cb3d968589d8 5569 * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
Kojto 90:cb3d968589d8 5570 *
Kojto 90:cb3d968589d8 5571 * Values:
Kojto 90:cb3d968589d8 5572 * - 0 - The software output control forces 0 to the channel output.
Kojto 90:cb3d968589d8 5573 * - 1 - The software output control forces 1 to the channel output.
Kojto 90:cb3d968589d8 5574 */
Kojto 90:cb3d968589d8 5575 /*@{*/
Kojto 90:cb3d968589d8 5576 #define BP_FTM_SWOCTRL_CH6OCV (14U) /*!< Bit position for FTM_SWOCTRL_CH6OCV. */
Kojto 90:cb3d968589d8 5577 #define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /*!< Bit mask for FTM_SWOCTRL_CH6OCV. */
Kojto 90:cb3d968589d8 5578 #define BS_FTM_SWOCTRL_CH6OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. */
Kojto 90:cb3d968589d8 5579
Kojto 90:cb3d968589d8 5580 /*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
Kojto 90:cb3d968589d8 5581 #define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
Kojto 90:cb3d968589d8 5582
Kojto 90:cb3d968589d8 5583 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. */
Kojto 90:cb3d968589d8 5584 #define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV)
Kojto 90:cb3d968589d8 5585
Kojto 90:cb3d968589d8 5586 /*! @brief Set the CH6OCV field to a new value. */
Kojto 90:cb3d968589d8 5587 #define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
Kojto 90:cb3d968589d8 5588 /*@}*/
Kojto 90:cb3d968589d8 5589
Kojto 90:cb3d968589d8 5590 /*!
Kojto 90:cb3d968589d8 5591 * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
Kojto 90:cb3d968589d8 5592 *
Kojto 90:cb3d968589d8 5593 * Values:
Kojto 90:cb3d968589d8 5594 * - 0 - The software output control forces 0 to the channel output.
Kojto 90:cb3d968589d8 5595 * - 1 - The software output control forces 1 to the channel output.
Kojto 90:cb3d968589d8 5596 */
Kojto 90:cb3d968589d8 5597 /*@{*/
Kojto 90:cb3d968589d8 5598 #define BP_FTM_SWOCTRL_CH7OCV (15U) /*!< Bit position for FTM_SWOCTRL_CH7OCV. */
Kojto 90:cb3d968589d8 5599 #define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /*!< Bit mask for FTM_SWOCTRL_CH7OCV. */
Kojto 90:cb3d968589d8 5600 #define BS_FTM_SWOCTRL_CH7OCV (1U) /*!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. */
Kojto 90:cb3d968589d8 5601
Kojto 90:cb3d968589d8 5602 /*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
Kojto 90:cb3d968589d8 5603 #define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
Kojto 90:cb3d968589d8 5604
Kojto 90:cb3d968589d8 5605 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. */
Kojto 90:cb3d968589d8 5606 #define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV)
Kojto 90:cb3d968589d8 5607
Kojto 90:cb3d968589d8 5608 /*! @brief Set the CH7OCV field to a new value. */
Kojto 90:cb3d968589d8 5609 #define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
Kojto 90:cb3d968589d8 5610 /*@}*/
Kojto 90:cb3d968589d8 5611
Kojto 90:cb3d968589d8 5612 /*******************************************************************************
Kojto 90:cb3d968589d8 5613 * HW_FTM_PWMLOAD - FTM PWM Load
Kojto 90:cb3d968589d8 5614 ******************************************************************************/
Kojto 90:cb3d968589d8 5615
Kojto 90:cb3d968589d8 5616 /*!
Kojto 90:cb3d968589d8 5617 * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
Kojto 90:cb3d968589d8 5618 *
Kojto 90:cb3d968589d8 5619 * Reset value: 0x00000000U
Kojto 90:cb3d968589d8 5620 *
Kojto 90:cb3d968589d8 5621 * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
Kojto 90:cb3d968589d8 5622 * values of their write buffers when the FTM counter changes from the MOD
Kojto 90:cb3d968589d8 5623 * register value to its next value or when a channel (j) match occurs. A match occurs
Kojto 90:cb3d968589d8 5624 * for the channel (j) when FTM counter = C(j)V.
Kojto 90:cb3d968589d8 5625 */
Kojto 90:cb3d968589d8 5626 typedef union _hw_ftm_pwmload
Kojto 90:cb3d968589d8 5627 {
Kojto 90:cb3d968589d8 5628 uint32_t U;
Kojto 90:cb3d968589d8 5629 struct _hw_ftm_pwmload_bitfields
Kojto 90:cb3d968589d8 5630 {
Kojto 90:cb3d968589d8 5631 uint32_t CH0SEL : 1; /*!< [0] Channel 0 Select */
Kojto 90:cb3d968589d8 5632 uint32_t CH1SEL : 1; /*!< [1] Channel 1 Select */
Kojto 90:cb3d968589d8 5633 uint32_t CH2SEL : 1; /*!< [2] Channel 2 Select */
Kojto 90:cb3d968589d8 5634 uint32_t CH3SEL : 1; /*!< [3] Channel 3 Select */
Kojto 90:cb3d968589d8 5635 uint32_t CH4SEL : 1; /*!< [4] Channel 4 Select */
Kojto 90:cb3d968589d8 5636 uint32_t CH5SEL : 1; /*!< [5] Channel 5 Select */
Kojto 90:cb3d968589d8 5637 uint32_t CH6SEL : 1; /*!< [6] Channel 6 Select */
Kojto 90:cb3d968589d8 5638 uint32_t CH7SEL : 1; /*!< [7] Channel 7 Select */
Kojto 90:cb3d968589d8 5639 uint32_t RESERVED0 : 1; /*!< [8] */
Kojto 90:cb3d968589d8 5640 uint32_t LDOK : 1; /*!< [9] Load Enable */
Kojto 90:cb3d968589d8 5641 uint32_t RESERVED1 : 22; /*!< [31:10] */
Kojto 90:cb3d968589d8 5642 } B;
Kojto 90:cb3d968589d8 5643 } hw_ftm_pwmload_t;
Kojto 90:cb3d968589d8 5644
Kojto 90:cb3d968589d8 5645 /*!
Kojto 90:cb3d968589d8 5646 * @name Constants and macros for entire FTM_PWMLOAD register
Kojto 90:cb3d968589d8 5647 */
Kojto 90:cb3d968589d8 5648 /*@{*/
Kojto 90:cb3d968589d8 5649 #define HW_FTM_PWMLOAD_ADDR(x) ((x) + 0x98U)
Kojto 90:cb3d968589d8 5650
Kojto 90:cb3d968589d8 5651 #define HW_FTM_PWMLOAD(x) (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
Kojto 90:cb3d968589d8 5652 #define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
Kojto 90:cb3d968589d8 5653 #define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
Kojto 90:cb3d968589d8 5654 #define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) | (v)))
Kojto 90:cb3d968589d8 5655 #define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
Kojto 90:cb3d968589d8 5656 #define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
Kojto 90:cb3d968589d8 5657 /*@}*/
Kojto 90:cb3d968589d8 5658
Kojto 90:cb3d968589d8 5659 /*
Kojto 90:cb3d968589d8 5660 * Constants & macros for individual FTM_PWMLOAD bitfields
Kojto 90:cb3d968589d8 5661 */
Kojto 90:cb3d968589d8 5662
Kojto 90:cb3d968589d8 5663 /*!
Kojto 90:cb3d968589d8 5664 * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
Kojto 90:cb3d968589d8 5665 *
Kojto 90:cb3d968589d8 5666 * Values:
Kojto 90:cb3d968589d8 5667 * - 0 - Do not include the channel in the matching process.
Kojto 90:cb3d968589d8 5668 * - 1 - Include the channel in the matching process.
Kojto 90:cb3d968589d8 5669 */
Kojto 90:cb3d968589d8 5670 /*@{*/
Kojto 90:cb3d968589d8 5671 #define BP_FTM_PWMLOAD_CH0SEL (0U) /*!< Bit position for FTM_PWMLOAD_CH0SEL. */
Kojto 90:cb3d968589d8 5672 #define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /*!< Bit mask for FTM_PWMLOAD_CH0SEL. */
Kojto 90:cb3d968589d8 5673 #define BS_FTM_PWMLOAD_CH0SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. */
Kojto 90:cb3d968589d8 5674
Kojto 90:cb3d968589d8 5675 /*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
Kojto 90:cb3d968589d8 5676 #define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
Kojto 90:cb3d968589d8 5677
Kojto 90:cb3d968589d8 5678 /*! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. */
Kojto 90:cb3d968589d8 5679 #define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL)
Kojto 90:cb3d968589d8 5680
Kojto 90:cb3d968589d8 5681 /*! @brief Set the CH0SEL field to a new value. */
Kojto 90:cb3d968589d8 5682 #define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
Kojto 90:cb3d968589d8 5683 /*@}*/
Kojto 90:cb3d968589d8 5684
Kojto 90:cb3d968589d8 5685 /*!
Kojto 90:cb3d968589d8 5686 * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
Kojto 90:cb3d968589d8 5687 *
Kojto 90:cb3d968589d8 5688 * Values:
Kojto 90:cb3d968589d8 5689 * - 0 - Do not include the channel in the matching process.
Kojto 90:cb3d968589d8 5690 * - 1 - Include the channel in the matching process.
Kojto 90:cb3d968589d8 5691 */
Kojto 90:cb3d968589d8 5692 /*@{*/
Kojto 90:cb3d968589d8 5693 #define BP_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit position for FTM_PWMLOAD_CH1SEL. */
Kojto 90:cb3d968589d8 5694 #define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /*!< Bit mask for FTM_PWMLOAD_CH1SEL. */
Kojto 90:cb3d968589d8 5695 #define BS_FTM_PWMLOAD_CH1SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. */
Kojto 90:cb3d968589d8 5696
Kojto 90:cb3d968589d8 5697 /*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
Kojto 90:cb3d968589d8 5698 #define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
Kojto 90:cb3d968589d8 5699
Kojto 90:cb3d968589d8 5700 /*! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. */
Kojto 90:cb3d968589d8 5701 #define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL)
Kojto 90:cb3d968589d8 5702
Kojto 90:cb3d968589d8 5703 /*! @brief Set the CH1SEL field to a new value. */
Kojto 90:cb3d968589d8 5704 #define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
Kojto 90:cb3d968589d8 5705 /*@}*/
Kojto 90:cb3d968589d8 5706
Kojto 90:cb3d968589d8 5707 /*!
Kojto 90:cb3d968589d8 5708 * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
Kojto 90:cb3d968589d8 5709 *
Kojto 90:cb3d968589d8 5710 * Values:
Kojto 90:cb3d968589d8 5711 * - 0 - Do not include the channel in the matching process.
Kojto 90:cb3d968589d8 5712 * - 1 - Include the channel in the matching process.
Kojto 90:cb3d968589d8 5713 */
Kojto 90:cb3d968589d8 5714 /*@{*/
Kojto 90:cb3d968589d8 5715 #define BP_FTM_PWMLOAD_CH2SEL (2U) /*!< Bit position for FTM_PWMLOAD_CH2SEL. */
Kojto 90:cb3d968589d8 5716 #define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /*!< Bit mask for FTM_PWMLOAD_CH2SEL. */
Kojto 90:cb3d968589d8 5717 #define BS_FTM_PWMLOAD_CH2SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. */
Kojto 90:cb3d968589d8 5718
Kojto 90:cb3d968589d8 5719 /*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
Kojto 90:cb3d968589d8 5720 #define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
Kojto 90:cb3d968589d8 5721
Kojto 90:cb3d968589d8 5722 /*! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. */
Kojto 90:cb3d968589d8 5723 #define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL)
Kojto 90:cb3d968589d8 5724
Kojto 90:cb3d968589d8 5725 /*! @brief Set the CH2SEL field to a new value. */
Kojto 90:cb3d968589d8 5726 #define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
Kojto 90:cb3d968589d8 5727 /*@}*/
Kojto 90:cb3d968589d8 5728
Kojto 90:cb3d968589d8 5729 /*!
Kojto 90:cb3d968589d8 5730 * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
Kojto 90:cb3d968589d8 5731 *
Kojto 90:cb3d968589d8 5732 * Values:
Kojto 90:cb3d968589d8 5733 * - 0 - Do not include the channel in the matching process.
Kojto 90:cb3d968589d8 5734 * - 1 - Include the channel in the matching process.
Kojto 90:cb3d968589d8 5735 */
Kojto 90:cb3d968589d8 5736 /*@{*/
Kojto 90:cb3d968589d8 5737 #define BP_FTM_PWMLOAD_CH3SEL (3U) /*!< Bit position for FTM_PWMLOAD_CH3SEL. */
Kojto 90:cb3d968589d8 5738 #define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /*!< Bit mask for FTM_PWMLOAD_CH3SEL. */
Kojto 90:cb3d968589d8 5739 #define BS_FTM_PWMLOAD_CH3SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. */
Kojto 90:cb3d968589d8 5740
Kojto 90:cb3d968589d8 5741 /*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
Kojto 90:cb3d968589d8 5742 #define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
Kojto 90:cb3d968589d8 5743
Kojto 90:cb3d968589d8 5744 /*! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. */
Kojto 90:cb3d968589d8 5745 #define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL)
Kojto 90:cb3d968589d8 5746
Kojto 90:cb3d968589d8 5747 /*! @brief Set the CH3SEL field to a new value. */
Kojto 90:cb3d968589d8 5748 #define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
Kojto 90:cb3d968589d8 5749 /*@}*/
Kojto 90:cb3d968589d8 5750
Kojto 90:cb3d968589d8 5751 /*!
Kojto 90:cb3d968589d8 5752 * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
Kojto 90:cb3d968589d8 5753 *
Kojto 90:cb3d968589d8 5754 * Values:
Kojto 90:cb3d968589d8 5755 * - 0 - Do not include the channel in the matching process.
Kojto 90:cb3d968589d8 5756 * - 1 - Include the channel in the matching process.
Kojto 90:cb3d968589d8 5757 */
Kojto 90:cb3d968589d8 5758 /*@{*/
Kojto 90:cb3d968589d8 5759 #define BP_FTM_PWMLOAD_CH4SEL (4U) /*!< Bit position for FTM_PWMLOAD_CH4SEL. */
Kojto 90:cb3d968589d8 5760 #define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /*!< Bit mask for FTM_PWMLOAD_CH4SEL. */
Kojto 90:cb3d968589d8 5761 #define BS_FTM_PWMLOAD_CH4SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. */
Kojto 90:cb3d968589d8 5762
Kojto 90:cb3d968589d8 5763 /*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
Kojto 90:cb3d968589d8 5764 #define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
Kojto 90:cb3d968589d8 5765
Kojto 90:cb3d968589d8 5766 /*! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. */
Kojto 90:cb3d968589d8 5767 #define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL)
Kojto 90:cb3d968589d8 5768
Kojto 90:cb3d968589d8 5769 /*! @brief Set the CH4SEL field to a new value. */
Kojto 90:cb3d968589d8 5770 #define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
Kojto 90:cb3d968589d8 5771 /*@}*/
Kojto 90:cb3d968589d8 5772
Kojto 90:cb3d968589d8 5773 /*!
Kojto 90:cb3d968589d8 5774 * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
Kojto 90:cb3d968589d8 5775 *
Kojto 90:cb3d968589d8 5776 * Values:
Kojto 90:cb3d968589d8 5777 * - 0 - Do not include the channel in the matching process.
Kojto 90:cb3d968589d8 5778 * - 1 - Include the channel in the matching process.
Kojto 90:cb3d968589d8 5779 */
Kojto 90:cb3d968589d8 5780 /*@{*/
Kojto 90:cb3d968589d8 5781 #define BP_FTM_PWMLOAD_CH5SEL (5U) /*!< Bit position for FTM_PWMLOAD_CH5SEL. */
Kojto 90:cb3d968589d8 5782 #define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /*!< Bit mask for FTM_PWMLOAD_CH5SEL. */
Kojto 90:cb3d968589d8 5783 #define BS_FTM_PWMLOAD_CH5SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. */
Kojto 90:cb3d968589d8 5784
Kojto 90:cb3d968589d8 5785 /*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
Kojto 90:cb3d968589d8 5786 #define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
Kojto 90:cb3d968589d8 5787
Kojto 90:cb3d968589d8 5788 /*! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. */
Kojto 90:cb3d968589d8 5789 #define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL)
Kojto 90:cb3d968589d8 5790
Kojto 90:cb3d968589d8 5791 /*! @brief Set the CH5SEL field to a new value. */
Kojto 90:cb3d968589d8 5792 #define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
Kojto 90:cb3d968589d8 5793 /*@}*/
Kojto 90:cb3d968589d8 5794
Kojto 90:cb3d968589d8 5795 /*!
Kojto 90:cb3d968589d8 5796 * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
Kojto 90:cb3d968589d8 5797 *
Kojto 90:cb3d968589d8 5798 * Values:
Kojto 90:cb3d968589d8 5799 * - 0 - Do not include the channel in the matching process.
Kojto 90:cb3d968589d8 5800 * - 1 - Include the channel in the matching process.
Kojto 90:cb3d968589d8 5801 */
Kojto 90:cb3d968589d8 5802 /*@{*/
Kojto 90:cb3d968589d8 5803 #define BP_FTM_PWMLOAD_CH6SEL (6U) /*!< Bit position for FTM_PWMLOAD_CH6SEL. */
Kojto 90:cb3d968589d8 5804 #define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /*!< Bit mask for FTM_PWMLOAD_CH6SEL. */
Kojto 90:cb3d968589d8 5805 #define BS_FTM_PWMLOAD_CH6SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. */
Kojto 90:cb3d968589d8 5806
Kojto 90:cb3d968589d8 5807 /*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
Kojto 90:cb3d968589d8 5808 #define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
Kojto 90:cb3d968589d8 5809
Kojto 90:cb3d968589d8 5810 /*! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. */
Kojto 90:cb3d968589d8 5811 #define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL)
Kojto 90:cb3d968589d8 5812
Kojto 90:cb3d968589d8 5813 /*! @brief Set the CH6SEL field to a new value. */
Kojto 90:cb3d968589d8 5814 #define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
Kojto 90:cb3d968589d8 5815 /*@}*/
Kojto 90:cb3d968589d8 5816
Kojto 90:cb3d968589d8 5817 /*!
Kojto 90:cb3d968589d8 5818 * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
Kojto 90:cb3d968589d8 5819 *
Kojto 90:cb3d968589d8 5820 * Values:
Kojto 90:cb3d968589d8 5821 * - 0 - Do not include the channel in the matching process.
Kojto 90:cb3d968589d8 5822 * - 1 - Include the channel in the matching process.
Kojto 90:cb3d968589d8 5823 */
Kojto 90:cb3d968589d8 5824 /*@{*/
Kojto 90:cb3d968589d8 5825 #define BP_FTM_PWMLOAD_CH7SEL (7U) /*!< Bit position for FTM_PWMLOAD_CH7SEL. */
Kojto 90:cb3d968589d8 5826 #define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /*!< Bit mask for FTM_PWMLOAD_CH7SEL. */
Kojto 90:cb3d968589d8 5827 #define BS_FTM_PWMLOAD_CH7SEL (1U) /*!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. */
Kojto 90:cb3d968589d8 5828
Kojto 90:cb3d968589d8 5829 /*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
Kojto 90:cb3d968589d8 5830 #define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
Kojto 90:cb3d968589d8 5831
Kojto 90:cb3d968589d8 5832 /*! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. */
Kojto 90:cb3d968589d8 5833 #define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL)
Kojto 90:cb3d968589d8 5834
Kojto 90:cb3d968589d8 5835 /*! @brief Set the CH7SEL field to a new value. */
Kojto 90:cb3d968589d8 5836 #define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
Kojto 90:cb3d968589d8 5837 /*@}*/
Kojto 90:cb3d968589d8 5838
Kojto 90:cb3d968589d8 5839 /*!
Kojto 90:cb3d968589d8 5840 * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
Kojto 90:cb3d968589d8 5841 *
Kojto 90:cb3d968589d8 5842 * Enables the loading of the MOD, CNTIN, and CV registers with the values of
Kojto 90:cb3d968589d8 5843 * their write buffers.
Kojto 90:cb3d968589d8 5844 *
Kojto 90:cb3d968589d8 5845 * Values:
Kojto 90:cb3d968589d8 5846 * - 0 - Loading updated values is disabled.
Kojto 90:cb3d968589d8 5847 * - 1 - Loading updated values is enabled.
Kojto 90:cb3d968589d8 5848 */
Kojto 90:cb3d968589d8 5849 /*@{*/
Kojto 90:cb3d968589d8 5850 #define BP_FTM_PWMLOAD_LDOK (9U) /*!< Bit position for FTM_PWMLOAD_LDOK. */
Kojto 90:cb3d968589d8 5851 #define BM_FTM_PWMLOAD_LDOK (0x00000200U) /*!< Bit mask for FTM_PWMLOAD_LDOK. */
Kojto 90:cb3d968589d8 5852 #define BS_FTM_PWMLOAD_LDOK (1U) /*!< Bit field size in bits for FTM_PWMLOAD_LDOK. */
Kojto 90:cb3d968589d8 5853
Kojto 90:cb3d968589d8 5854 /*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
Kojto 90:cb3d968589d8 5855 #define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
Kojto 90:cb3d968589d8 5856
Kojto 90:cb3d968589d8 5857 /*! @brief Format value for bitfield FTM_PWMLOAD_LDOK. */
Kojto 90:cb3d968589d8 5858 #define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK)
Kojto 90:cb3d968589d8 5859
Kojto 90:cb3d968589d8 5860 /*! @brief Set the LDOK field to a new value. */
Kojto 90:cb3d968589d8 5861 #define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
Kojto 90:cb3d968589d8 5862 /*@}*/
Kojto 90:cb3d968589d8 5863
Kojto 90:cb3d968589d8 5864 /*******************************************************************************
Kojto 90:cb3d968589d8 5865 * hw_ftm_t - module struct
Kojto 90:cb3d968589d8 5866 ******************************************************************************/
Kojto 90:cb3d968589d8 5867 /*!
Kojto 90:cb3d968589d8 5868 * @brief All FTM module registers.
Kojto 90:cb3d968589d8 5869 */
Kojto 90:cb3d968589d8 5870 #pragma pack(1)
Kojto 90:cb3d968589d8 5871 typedef struct _hw_ftm
Kojto 90:cb3d968589d8 5872 {
Kojto 90:cb3d968589d8 5873 __IO hw_ftm_sc_t SC; /*!< [0x0] Status And Control */
Kojto 90:cb3d968589d8 5874 __IO hw_ftm_cnt_t CNT; /*!< [0x4] Counter */
Kojto 90:cb3d968589d8 5875 __IO hw_ftm_mod_t MOD; /*!< [0x8] Modulo */
Kojto 90:cb3d968589d8 5876 struct {
Kojto 90:cb3d968589d8 5877 __IO hw_ftm_cnsc_t CnSC; /*!< [0xC] Channel (n) Status And Control */
Kojto 90:cb3d968589d8 5878 __IO hw_ftm_cnv_t CnV; /*!< [0x10] Channel (n) Value */
Kojto 90:cb3d968589d8 5879 } CONTROLS[8];
Kojto 90:cb3d968589d8 5880 __IO hw_ftm_cntin_t CNTIN; /*!< [0x4C] Counter Initial Value */
Kojto 90:cb3d968589d8 5881 __IO hw_ftm_status_t STATUS; /*!< [0x50] Capture And Compare Status */
Kojto 90:cb3d968589d8 5882 __IO hw_ftm_mode_t MODE; /*!< [0x54] Features Mode Selection */
Kojto 90:cb3d968589d8 5883 __IO hw_ftm_sync_t SYNC; /*!< [0x58] Synchronization */
Kojto 90:cb3d968589d8 5884 __IO hw_ftm_outinit_t OUTINIT; /*!< [0x5C] Initial State For Channels Output */
Kojto 90:cb3d968589d8 5885 __IO hw_ftm_outmask_t OUTMASK; /*!< [0x60] Output Mask */
Kojto 90:cb3d968589d8 5886 __IO hw_ftm_combine_t COMBINE; /*!< [0x64] Function For Linked Channels */
Kojto 90:cb3d968589d8 5887 __IO hw_ftm_deadtime_t DEADTIME; /*!< [0x68] Deadtime Insertion Control */
Kojto 90:cb3d968589d8 5888 __IO hw_ftm_exttrig_t EXTTRIG; /*!< [0x6C] FTM External Trigger */
Kojto 90:cb3d968589d8 5889 __IO hw_ftm_pol_t POL; /*!< [0x70] Channels Polarity */
Kojto 90:cb3d968589d8 5890 __IO hw_ftm_fms_t FMS; /*!< [0x74] Fault Mode Status */
Kojto 90:cb3d968589d8 5891 __IO hw_ftm_filter_t FILTER; /*!< [0x78] Input Capture Filter Control */
Kojto 90:cb3d968589d8 5892 __IO hw_ftm_fltctrl_t FLTCTRL; /*!< [0x7C] Fault Control */
Kojto 90:cb3d968589d8 5893 __IO hw_ftm_qdctrl_t QDCTRL; /*!< [0x80] Quadrature Decoder Control And Status */
Kojto 90:cb3d968589d8 5894 __IO hw_ftm_conf_t CONF; /*!< [0x84] Configuration */
Kojto 90:cb3d968589d8 5895 __IO hw_ftm_fltpol_t FLTPOL; /*!< [0x88] FTM Fault Input Polarity */
Kojto 90:cb3d968589d8 5896 __IO hw_ftm_synconf_t SYNCONF; /*!< [0x8C] Synchronization Configuration */
Kojto 90:cb3d968589d8 5897 __IO hw_ftm_invctrl_t INVCTRL; /*!< [0x90] FTM Inverting Control */
Kojto 90:cb3d968589d8 5898 __IO hw_ftm_swoctrl_t SWOCTRL; /*!< [0x94] FTM Software Output Control */
Kojto 90:cb3d968589d8 5899 __IO hw_ftm_pwmload_t PWMLOAD; /*!< [0x98] FTM PWM Load */
Kojto 90:cb3d968589d8 5900 } hw_ftm_t;
Kojto 90:cb3d968589d8 5901 #pragma pack()
Kojto 90:cb3d968589d8 5902
Kojto 90:cb3d968589d8 5903 /*! @brief Macro to access all FTM registers. */
Kojto 90:cb3d968589d8 5904 /*! @param x FTM module instance base address. */
Kojto 90:cb3d968589d8 5905 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 5906 * use the '&' operator, like <code>&HW_FTM(FTM0_BASE)</code>. */
Kojto 90:cb3d968589d8 5907 #define HW_FTM(x) (*(hw_ftm_t *)(x))
Kojto 90:cb3d968589d8 5908
Kojto 90:cb3d968589d8 5909 #endif /* __HW_FTM_REGISTERS_H__ */
Kojto 90:cb3d968589d8 5910 /* EOF */