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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_fmc.h@104:b9ad9a133dc7, 2015-08-05 (annotated)
- Committer:
- Kojto
- Date:
- Wed Aug 05 13:16:35 2015 +0100
- Revision:
- 104:b9ad9a133dc7
- Parent:
- 90:cb3d968589d8
Release 104 of the mbed library:
Changes:
- new platforms: nrf51 microbit
- MAXxxx - fix pwm array search
- LPC8xx - usart enable fix
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 90:cb3d968589d8 | 1 | /* |
Kojto | 90:cb3d968589d8 | 2 | ** ################################################################### |
Kojto | 90:cb3d968589d8 | 3 | ** Compilers: Keil ARM C/C++ Compiler |
Kojto | 90:cb3d968589d8 | 4 | ** Freescale C/C++ for Embedded ARM |
Kojto | 90:cb3d968589d8 | 5 | ** GNU C Compiler |
Kojto | 90:cb3d968589d8 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
Kojto | 90:cb3d968589d8 | 7 | ** |
Kojto | 90:cb3d968589d8 | 8 | ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 |
Kojto | 90:cb3d968589d8 | 9 | ** Version: rev. 2.5, 2014-02-10 |
Kojto | 90:cb3d968589d8 | 10 | ** Build: b140604 |
Kojto | 90:cb3d968589d8 | 11 | ** |
Kojto | 90:cb3d968589d8 | 12 | ** Abstract: |
Kojto | 90:cb3d968589d8 | 13 | ** Extension to the CMSIS register access layer header. |
Kojto | 90:cb3d968589d8 | 14 | ** |
Kojto | 90:cb3d968589d8 | 15 | ** Copyright (c) 2014 Freescale Semiconductor, Inc. |
Kojto | 90:cb3d968589d8 | 16 | ** All rights reserved. |
Kojto | 90:cb3d968589d8 | 17 | ** |
Kojto | 90:cb3d968589d8 | 18 | ** Redistribution and use in source and binary forms, with or without modification, |
Kojto | 90:cb3d968589d8 | 19 | ** are permitted provided that the following conditions are met: |
Kojto | 90:cb3d968589d8 | 20 | ** |
Kojto | 90:cb3d968589d8 | 21 | ** o Redistributions of source code must retain the above copyright notice, this list |
Kojto | 90:cb3d968589d8 | 22 | ** of conditions and the following disclaimer. |
Kojto | 90:cb3d968589d8 | 23 | ** |
Kojto | 90:cb3d968589d8 | 24 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
Kojto | 90:cb3d968589d8 | 25 | ** list of conditions and the following disclaimer in the documentation and/or |
Kojto | 90:cb3d968589d8 | 26 | ** other materials provided with the distribution. |
Kojto | 90:cb3d968589d8 | 27 | ** |
Kojto | 90:cb3d968589d8 | 28 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
Kojto | 90:cb3d968589d8 | 29 | ** contributors may be used to endorse or promote products derived from this |
Kojto | 90:cb3d968589d8 | 30 | ** software without specific prior written permission. |
Kojto | 90:cb3d968589d8 | 31 | ** |
Kojto | 90:cb3d968589d8 | 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
Kojto | 90:cb3d968589d8 | 33 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
Kojto | 90:cb3d968589d8 | 34 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Kojto | 90:cb3d968589d8 | 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
Kojto | 90:cb3d968589d8 | 36 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
Kojto | 90:cb3d968589d8 | 37 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
Kojto | 90:cb3d968589d8 | 38 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
Kojto | 90:cb3d968589d8 | 39 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
Kojto | 90:cb3d968589d8 | 40 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
Kojto | 90:cb3d968589d8 | 41 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Kojto | 90:cb3d968589d8 | 42 | ** |
Kojto | 90:cb3d968589d8 | 43 | ** http: www.freescale.com |
Kojto | 90:cb3d968589d8 | 44 | ** mail: support@freescale.com |
Kojto | 90:cb3d968589d8 | 45 | ** |
Kojto | 90:cb3d968589d8 | 46 | ** Revisions: |
Kojto | 90:cb3d968589d8 | 47 | ** - rev. 1.0 (2013-08-12) |
Kojto | 90:cb3d968589d8 | 48 | ** Initial version. |
Kojto | 90:cb3d968589d8 | 49 | ** - rev. 2.0 (2013-10-29) |
Kojto | 90:cb3d968589d8 | 50 | ** Register accessor macros added to the memory map. |
Kojto | 90:cb3d968589d8 | 51 | ** Symbols for Processor Expert memory map compatibility added to the memory map. |
Kojto | 90:cb3d968589d8 | 52 | ** Startup file for gcc has been updated according to CMSIS 3.2. |
Kojto | 90:cb3d968589d8 | 53 | ** System initialization updated. |
Kojto | 90:cb3d968589d8 | 54 | ** MCG - registers updated. |
Kojto | 90:cb3d968589d8 | 55 | ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. |
Kojto | 90:cb3d968589d8 | 56 | ** - rev. 2.1 (2013-10-30) |
Kojto | 90:cb3d968589d8 | 57 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. |
Kojto | 90:cb3d968589d8 | 58 | ** - rev. 2.2 (2013-12-09) |
Kojto | 90:cb3d968589d8 | 59 | ** DMA - EARS register removed. |
Kojto | 90:cb3d968589d8 | 60 | ** AIPS0, AIPS1 - MPRA register updated. |
Kojto | 90:cb3d968589d8 | 61 | ** - rev. 2.3 (2014-01-24) |
Kojto | 90:cb3d968589d8 | 62 | ** Update according to reference manual rev. 2 |
Kojto | 90:cb3d968589d8 | 63 | ** ENET, MCG, MCM, SIM, USB - registers updated |
Kojto | 90:cb3d968589d8 | 64 | ** - rev. 2.4 (2014-02-10) |
Kojto | 90:cb3d968589d8 | 65 | ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h |
Kojto | 90:cb3d968589d8 | 66 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. |
Kojto | 90:cb3d968589d8 | 67 | ** - rev. 2.5 (2014-02-10) |
Kojto | 90:cb3d968589d8 | 68 | ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h |
Kojto | 90:cb3d968589d8 | 69 | ** Update of SystemInit() and SystemCoreClockUpdate() functions. |
Kojto | 90:cb3d968589d8 | 70 | ** Module access macro module_BASES replaced by module_BASE_PTRS. |
Kojto | 90:cb3d968589d8 | 71 | ** |
Kojto | 90:cb3d968589d8 | 72 | ** ################################################################### |
Kojto | 90:cb3d968589d8 | 73 | */ |
Kojto | 90:cb3d968589d8 | 74 | |
Kojto | 90:cb3d968589d8 | 75 | /* |
Kojto | 90:cb3d968589d8 | 76 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
Kojto | 90:cb3d968589d8 | 77 | * |
Kojto | 90:cb3d968589d8 | 78 | * This file was generated automatically and any changes may be lost. |
Kojto | 90:cb3d968589d8 | 79 | */ |
Kojto | 90:cb3d968589d8 | 80 | #ifndef __HW_FMC_REGISTERS_H__ |
Kojto | 90:cb3d968589d8 | 81 | #define __HW_FMC_REGISTERS_H__ |
Kojto | 90:cb3d968589d8 | 82 | |
Kojto | 90:cb3d968589d8 | 83 | #include "MK64F12.h" |
Kojto | 90:cb3d968589d8 | 84 | #include "fsl_bitaccess.h" |
Kojto | 90:cb3d968589d8 | 85 | |
Kojto | 90:cb3d968589d8 | 86 | /* |
Kojto | 90:cb3d968589d8 | 87 | * MK64F12 FMC |
Kojto | 90:cb3d968589d8 | 88 | * |
Kojto | 90:cb3d968589d8 | 89 | * Flash Memory Controller |
Kojto | 90:cb3d968589d8 | 90 | * |
Kojto | 90:cb3d968589d8 | 91 | * Registers defined in this header file: |
Kojto | 90:cb3d968589d8 | 92 | * - HW_FMC_PFAPR - Flash Access Protection Register |
Kojto | 90:cb3d968589d8 | 93 | * - HW_FMC_PFB0CR - Flash Bank 0 Control Register |
Kojto | 90:cb3d968589d8 | 94 | * - HW_FMC_PFB1CR - Flash Bank 1 Control Register |
Kojto | 90:cb3d968589d8 | 95 | * - HW_FMC_TAGVDW0Sn - Cache Tag Storage |
Kojto | 90:cb3d968589d8 | 96 | * - HW_FMC_TAGVDW1Sn - Cache Tag Storage |
Kojto | 90:cb3d968589d8 | 97 | * - HW_FMC_TAGVDW2Sn - Cache Tag Storage |
Kojto | 90:cb3d968589d8 | 98 | * - HW_FMC_TAGVDW3Sn - Cache Tag Storage |
Kojto | 90:cb3d968589d8 | 99 | * - HW_FMC_DATAW0SnU - Cache Data Storage (upper word) |
Kojto | 90:cb3d968589d8 | 100 | * - HW_FMC_DATAW0SnL - Cache Data Storage (lower word) |
Kojto | 90:cb3d968589d8 | 101 | * - HW_FMC_DATAW1SnU - Cache Data Storage (upper word) |
Kojto | 90:cb3d968589d8 | 102 | * - HW_FMC_DATAW1SnL - Cache Data Storage (lower word) |
Kojto | 90:cb3d968589d8 | 103 | * - HW_FMC_DATAW2SnU - Cache Data Storage (upper word) |
Kojto | 90:cb3d968589d8 | 104 | * - HW_FMC_DATAW2SnL - Cache Data Storage (lower word) |
Kojto | 90:cb3d968589d8 | 105 | * - HW_FMC_DATAW3SnU - Cache Data Storage (upper word) |
Kojto | 90:cb3d968589d8 | 106 | * - HW_FMC_DATAW3SnL - Cache Data Storage (lower word) |
Kojto | 90:cb3d968589d8 | 107 | * |
Kojto | 90:cb3d968589d8 | 108 | * - hw_fmc_t - Struct containing all module registers. |
Kojto | 90:cb3d968589d8 | 109 | */ |
Kojto | 90:cb3d968589d8 | 110 | |
Kojto | 90:cb3d968589d8 | 111 | #define HW_FMC_INSTANCE_COUNT (1U) /*!< Number of instances of the FMC module. */ |
Kojto | 90:cb3d968589d8 | 112 | |
Kojto | 90:cb3d968589d8 | 113 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 114 | * HW_FMC_PFAPR - Flash Access Protection Register |
Kojto | 90:cb3d968589d8 | 115 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 116 | |
Kojto | 90:cb3d968589d8 | 117 | /*! |
Kojto | 90:cb3d968589d8 | 118 | * @brief HW_FMC_PFAPR - Flash Access Protection Register (RW) |
Kojto | 90:cb3d968589d8 | 119 | * |
Kojto | 90:cb3d968589d8 | 120 | * Reset value: 0x00F8003FU |
Kojto | 90:cb3d968589d8 | 121 | */ |
Kojto | 90:cb3d968589d8 | 122 | typedef union _hw_fmc_pfapr |
Kojto | 90:cb3d968589d8 | 123 | { |
Kojto | 90:cb3d968589d8 | 124 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 125 | struct _hw_fmc_pfapr_bitfields |
Kojto | 90:cb3d968589d8 | 126 | { |
Kojto | 90:cb3d968589d8 | 127 | uint32_t M0AP : 2; /*!< [1:0] Master 0 Access Protection */ |
Kojto | 90:cb3d968589d8 | 128 | uint32_t M1AP : 2; /*!< [3:2] Master 1 Access Protection */ |
Kojto | 90:cb3d968589d8 | 129 | uint32_t M2AP : 2; /*!< [5:4] Master 2 Access Protection */ |
Kojto | 90:cb3d968589d8 | 130 | uint32_t M3AP : 2; /*!< [7:6] Master 3 Access Protection */ |
Kojto | 90:cb3d968589d8 | 131 | uint32_t M4AP : 2; /*!< [9:8] Master 4 Access Protection */ |
Kojto | 90:cb3d968589d8 | 132 | uint32_t M5AP : 2; /*!< [11:10] Master 5 Access Protection */ |
Kojto | 90:cb3d968589d8 | 133 | uint32_t M6AP : 2; /*!< [13:12] Master 6 Access Protection */ |
Kojto | 90:cb3d968589d8 | 134 | uint32_t M7AP : 2; /*!< [15:14] Master 7 Access Protection */ |
Kojto | 90:cb3d968589d8 | 135 | uint32_t M0PFD : 1; /*!< [16] Master 0 Prefetch Disable */ |
Kojto | 90:cb3d968589d8 | 136 | uint32_t M1PFD : 1; /*!< [17] Master 1 Prefetch Disable */ |
Kojto | 90:cb3d968589d8 | 137 | uint32_t M2PFD : 1; /*!< [18] Master 2 Prefetch Disable */ |
Kojto | 90:cb3d968589d8 | 138 | uint32_t M3PFD : 1; /*!< [19] Master 3 Prefetch Disable */ |
Kojto | 90:cb3d968589d8 | 139 | uint32_t M4PFD : 1; /*!< [20] Master 4 Prefetch Disable */ |
Kojto | 90:cb3d968589d8 | 140 | uint32_t M5PFD : 1; /*!< [21] Master 5 Prefetch Disable */ |
Kojto | 90:cb3d968589d8 | 141 | uint32_t M6PFD : 1; /*!< [22] Master 6 Prefetch Disable */ |
Kojto | 90:cb3d968589d8 | 142 | uint32_t M7PFD : 1; /*!< [23] Master 7 Prefetch Disable */ |
Kojto | 90:cb3d968589d8 | 143 | uint32_t RESERVED0 : 8; /*!< [31:24] */ |
Kojto | 90:cb3d968589d8 | 144 | } B; |
Kojto | 90:cb3d968589d8 | 145 | } hw_fmc_pfapr_t; |
Kojto | 90:cb3d968589d8 | 146 | |
Kojto | 90:cb3d968589d8 | 147 | /*! |
Kojto | 90:cb3d968589d8 | 148 | * @name Constants and macros for entire FMC_PFAPR register |
Kojto | 90:cb3d968589d8 | 149 | */ |
Kojto | 90:cb3d968589d8 | 150 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 151 | #define HW_FMC_PFAPR_ADDR(x) ((x) + 0x0U) |
Kojto | 90:cb3d968589d8 | 152 | |
Kojto | 90:cb3d968589d8 | 153 | #define HW_FMC_PFAPR(x) (*(__IO hw_fmc_pfapr_t *) HW_FMC_PFAPR_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 154 | #define HW_FMC_PFAPR_RD(x) (HW_FMC_PFAPR(x).U) |
Kojto | 90:cb3d968589d8 | 155 | #define HW_FMC_PFAPR_WR(x, v) (HW_FMC_PFAPR(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 156 | #define HW_FMC_PFAPR_SET(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 157 | #define HW_FMC_PFAPR_CLR(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 158 | #define HW_FMC_PFAPR_TOG(x, v) (HW_FMC_PFAPR_WR(x, HW_FMC_PFAPR_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 159 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 160 | |
Kojto | 90:cb3d968589d8 | 161 | /* |
Kojto | 90:cb3d968589d8 | 162 | * Constants & macros for individual FMC_PFAPR bitfields |
Kojto | 90:cb3d968589d8 | 163 | */ |
Kojto | 90:cb3d968589d8 | 164 | |
Kojto | 90:cb3d968589d8 | 165 | /*! |
Kojto | 90:cb3d968589d8 | 166 | * @name Register FMC_PFAPR, field M0AP[1:0] (RW) |
Kojto | 90:cb3d968589d8 | 167 | * |
Kojto | 90:cb3d968589d8 | 168 | * This field controls whether read and write access to the flash are allowed |
Kojto | 90:cb3d968589d8 | 169 | * based on the logical master number of the requesting crossbar switch master. |
Kojto | 90:cb3d968589d8 | 170 | * |
Kojto | 90:cb3d968589d8 | 171 | * Values: |
Kojto | 90:cb3d968589d8 | 172 | * - 00 - No access may be performed by this master |
Kojto | 90:cb3d968589d8 | 173 | * - 01 - Only read accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 174 | * - 10 - Only write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 175 | * - 11 - Both read and write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 176 | */ |
Kojto | 90:cb3d968589d8 | 177 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 178 | #define BP_FMC_PFAPR_M0AP (0U) /*!< Bit position for FMC_PFAPR_M0AP. */ |
Kojto | 90:cb3d968589d8 | 179 | #define BM_FMC_PFAPR_M0AP (0x00000003U) /*!< Bit mask for FMC_PFAPR_M0AP. */ |
Kojto | 90:cb3d968589d8 | 180 | #define BS_FMC_PFAPR_M0AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M0AP. */ |
Kojto | 90:cb3d968589d8 | 181 | |
Kojto | 90:cb3d968589d8 | 182 | /*! @brief Read current value of the FMC_PFAPR_M0AP field. */ |
Kojto | 90:cb3d968589d8 | 183 | #define BR_FMC_PFAPR_M0AP(x) (HW_FMC_PFAPR(x).B.M0AP) |
Kojto | 90:cb3d968589d8 | 184 | |
Kojto | 90:cb3d968589d8 | 185 | /*! @brief Format value for bitfield FMC_PFAPR_M0AP. */ |
Kojto | 90:cb3d968589d8 | 186 | #define BF_FMC_PFAPR_M0AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0AP) & BM_FMC_PFAPR_M0AP) |
Kojto | 90:cb3d968589d8 | 187 | |
Kojto | 90:cb3d968589d8 | 188 | /*! @brief Set the M0AP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 189 | #define BW_FMC_PFAPR_M0AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M0AP) | BF_FMC_PFAPR_M0AP(v))) |
Kojto | 90:cb3d968589d8 | 190 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 191 | |
Kojto | 90:cb3d968589d8 | 192 | /*! |
Kojto | 90:cb3d968589d8 | 193 | * @name Register FMC_PFAPR, field M1AP[3:2] (RW) |
Kojto | 90:cb3d968589d8 | 194 | * |
Kojto | 90:cb3d968589d8 | 195 | * This field controls whether read and write access to the flash are allowed |
Kojto | 90:cb3d968589d8 | 196 | * based on the logical master number of the requesting crossbar switch master. |
Kojto | 90:cb3d968589d8 | 197 | * |
Kojto | 90:cb3d968589d8 | 198 | * Values: |
Kojto | 90:cb3d968589d8 | 199 | * - 00 - No access may be performed by this master |
Kojto | 90:cb3d968589d8 | 200 | * - 01 - Only read accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 201 | * - 10 - Only write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 202 | * - 11 - Both read and write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 203 | */ |
Kojto | 90:cb3d968589d8 | 204 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 205 | #define BP_FMC_PFAPR_M1AP (2U) /*!< Bit position for FMC_PFAPR_M1AP. */ |
Kojto | 90:cb3d968589d8 | 206 | #define BM_FMC_PFAPR_M1AP (0x0000000CU) /*!< Bit mask for FMC_PFAPR_M1AP. */ |
Kojto | 90:cb3d968589d8 | 207 | #define BS_FMC_PFAPR_M1AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M1AP. */ |
Kojto | 90:cb3d968589d8 | 208 | |
Kojto | 90:cb3d968589d8 | 209 | /*! @brief Read current value of the FMC_PFAPR_M1AP field. */ |
Kojto | 90:cb3d968589d8 | 210 | #define BR_FMC_PFAPR_M1AP(x) (HW_FMC_PFAPR(x).B.M1AP) |
Kojto | 90:cb3d968589d8 | 211 | |
Kojto | 90:cb3d968589d8 | 212 | /*! @brief Format value for bitfield FMC_PFAPR_M1AP. */ |
Kojto | 90:cb3d968589d8 | 213 | #define BF_FMC_PFAPR_M1AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1AP) & BM_FMC_PFAPR_M1AP) |
Kojto | 90:cb3d968589d8 | 214 | |
Kojto | 90:cb3d968589d8 | 215 | /*! @brief Set the M1AP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 216 | #define BW_FMC_PFAPR_M1AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M1AP) | BF_FMC_PFAPR_M1AP(v))) |
Kojto | 90:cb3d968589d8 | 217 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 218 | |
Kojto | 90:cb3d968589d8 | 219 | /*! |
Kojto | 90:cb3d968589d8 | 220 | * @name Register FMC_PFAPR, field M2AP[5:4] (RW) |
Kojto | 90:cb3d968589d8 | 221 | * |
Kojto | 90:cb3d968589d8 | 222 | * This field controls whether read and write access to the flash are allowed |
Kojto | 90:cb3d968589d8 | 223 | * based on the logical master number of the requesting crossbar switch master. |
Kojto | 90:cb3d968589d8 | 224 | * |
Kojto | 90:cb3d968589d8 | 225 | * Values: |
Kojto | 90:cb3d968589d8 | 226 | * - 00 - No access may be performed by this master |
Kojto | 90:cb3d968589d8 | 227 | * - 01 - Only read accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 228 | * - 10 - Only write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 229 | * - 11 - Both read and write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 230 | */ |
Kojto | 90:cb3d968589d8 | 231 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 232 | #define BP_FMC_PFAPR_M2AP (4U) /*!< Bit position for FMC_PFAPR_M2AP. */ |
Kojto | 90:cb3d968589d8 | 233 | #define BM_FMC_PFAPR_M2AP (0x00000030U) /*!< Bit mask for FMC_PFAPR_M2AP. */ |
Kojto | 90:cb3d968589d8 | 234 | #define BS_FMC_PFAPR_M2AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M2AP. */ |
Kojto | 90:cb3d968589d8 | 235 | |
Kojto | 90:cb3d968589d8 | 236 | /*! @brief Read current value of the FMC_PFAPR_M2AP field. */ |
Kojto | 90:cb3d968589d8 | 237 | #define BR_FMC_PFAPR_M2AP(x) (HW_FMC_PFAPR(x).B.M2AP) |
Kojto | 90:cb3d968589d8 | 238 | |
Kojto | 90:cb3d968589d8 | 239 | /*! @brief Format value for bitfield FMC_PFAPR_M2AP. */ |
Kojto | 90:cb3d968589d8 | 240 | #define BF_FMC_PFAPR_M2AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2AP) & BM_FMC_PFAPR_M2AP) |
Kojto | 90:cb3d968589d8 | 241 | |
Kojto | 90:cb3d968589d8 | 242 | /*! @brief Set the M2AP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 243 | #define BW_FMC_PFAPR_M2AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M2AP) | BF_FMC_PFAPR_M2AP(v))) |
Kojto | 90:cb3d968589d8 | 244 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 245 | |
Kojto | 90:cb3d968589d8 | 246 | /*! |
Kojto | 90:cb3d968589d8 | 247 | * @name Register FMC_PFAPR, field M3AP[7:6] (RW) |
Kojto | 90:cb3d968589d8 | 248 | * |
Kojto | 90:cb3d968589d8 | 249 | * This field controls whether read and write access to the flash are allowed |
Kojto | 90:cb3d968589d8 | 250 | * based on the logical master number of the requesting crossbar switch master. |
Kojto | 90:cb3d968589d8 | 251 | * |
Kojto | 90:cb3d968589d8 | 252 | * Values: |
Kojto | 90:cb3d968589d8 | 253 | * - 00 - No access may be performed by this master |
Kojto | 90:cb3d968589d8 | 254 | * - 01 - Only read accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 255 | * - 10 - Only write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 256 | * - 11 - Both read and write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 257 | */ |
Kojto | 90:cb3d968589d8 | 258 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 259 | #define BP_FMC_PFAPR_M3AP (6U) /*!< Bit position for FMC_PFAPR_M3AP. */ |
Kojto | 90:cb3d968589d8 | 260 | #define BM_FMC_PFAPR_M3AP (0x000000C0U) /*!< Bit mask for FMC_PFAPR_M3AP. */ |
Kojto | 90:cb3d968589d8 | 261 | #define BS_FMC_PFAPR_M3AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M3AP. */ |
Kojto | 90:cb3d968589d8 | 262 | |
Kojto | 90:cb3d968589d8 | 263 | /*! @brief Read current value of the FMC_PFAPR_M3AP field. */ |
Kojto | 90:cb3d968589d8 | 264 | #define BR_FMC_PFAPR_M3AP(x) (HW_FMC_PFAPR(x).B.M3AP) |
Kojto | 90:cb3d968589d8 | 265 | |
Kojto | 90:cb3d968589d8 | 266 | /*! @brief Format value for bitfield FMC_PFAPR_M3AP. */ |
Kojto | 90:cb3d968589d8 | 267 | #define BF_FMC_PFAPR_M3AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3AP) & BM_FMC_PFAPR_M3AP) |
Kojto | 90:cb3d968589d8 | 268 | |
Kojto | 90:cb3d968589d8 | 269 | /*! @brief Set the M3AP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 270 | #define BW_FMC_PFAPR_M3AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M3AP) | BF_FMC_PFAPR_M3AP(v))) |
Kojto | 90:cb3d968589d8 | 271 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 272 | |
Kojto | 90:cb3d968589d8 | 273 | /*! |
Kojto | 90:cb3d968589d8 | 274 | * @name Register FMC_PFAPR, field M4AP[9:8] (RW) |
Kojto | 90:cb3d968589d8 | 275 | * |
Kojto | 90:cb3d968589d8 | 276 | * This field controls whether read and write access to the flash are allowed |
Kojto | 90:cb3d968589d8 | 277 | * based on the logical master number of the requesting crossbar switch master. |
Kojto | 90:cb3d968589d8 | 278 | * |
Kojto | 90:cb3d968589d8 | 279 | * Values: |
Kojto | 90:cb3d968589d8 | 280 | * - 00 - No access may be performed by this master |
Kojto | 90:cb3d968589d8 | 281 | * - 01 - Only read accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 282 | * - 10 - Only write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 283 | * - 11 - Both read and write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 284 | */ |
Kojto | 90:cb3d968589d8 | 285 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 286 | #define BP_FMC_PFAPR_M4AP (8U) /*!< Bit position for FMC_PFAPR_M4AP. */ |
Kojto | 90:cb3d968589d8 | 287 | #define BM_FMC_PFAPR_M4AP (0x00000300U) /*!< Bit mask for FMC_PFAPR_M4AP. */ |
Kojto | 90:cb3d968589d8 | 288 | #define BS_FMC_PFAPR_M4AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M4AP. */ |
Kojto | 90:cb3d968589d8 | 289 | |
Kojto | 90:cb3d968589d8 | 290 | /*! @brief Read current value of the FMC_PFAPR_M4AP field. */ |
Kojto | 90:cb3d968589d8 | 291 | #define BR_FMC_PFAPR_M4AP(x) (HW_FMC_PFAPR(x).B.M4AP) |
Kojto | 90:cb3d968589d8 | 292 | |
Kojto | 90:cb3d968589d8 | 293 | /*! @brief Format value for bitfield FMC_PFAPR_M4AP. */ |
Kojto | 90:cb3d968589d8 | 294 | #define BF_FMC_PFAPR_M4AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4AP) & BM_FMC_PFAPR_M4AP) |
Kojto | 90:cb3d968589d8 | 295 | |
Kojto | 90:cb3d968589d8 | 296 | /*! @brief Set the M4AP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 297 | #define BW_FMC_PFAPR_M4AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M4AP) | BF_FMC_PFAPR_M4AP(v))) |
Kojto | 90:cb3d968589d8 | 298 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 299 | |
Kojto | 90:cb3d968589d8 | 300 | /*! |
Kojto | 90:cb3d968589d8 | 301 | * @name Register FMC_PFAPR, field M5AP[11:10] (RW) |
Kojto | 90:cb3d968589d8 | 302 | * |
Kojto | 90:cb3d968589d8 | 303 | * This field controls whether read and write access to the flash are allowed |
Kojto | 90:cb3d968589d8 | 304 | * based on the logical master number of the requesting crossbar switch master. |
Kojto | 90:cb3d968589d8 | 305 | * |
Kojto | 90:cb3d968589d8 | 306 | * Values: |
Kojto | 90:cb3d968589d8 | 307 | * - 00 - No access may be performed by this master |
Kojto | 90:cb3d968589d8 | 308 | * - 01 - Only read accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 309 | * - 10 - Only write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 310 | * - 11 - Both read and write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 311 | */ |
Kojto | 90:cb3d968589d8 | 312 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 313 | #define BP_FMC_PFAPR_M5AP (10U) /*!< Bit position for FMC_PFAPR_M5AP. */ |
Kojto | 90:cb3d968589d8 | 314 | #define BM_FMC_PFAPR_M5AP (0x00000C00U) /*!< Bit mask for FMC_PFAPR_M5AP. */ |
Kojto | 90:cb3d968589d8 | 315 | #define BS_FMC_PFAPR_M5AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M5AP. */ |
Kojto | 90:cb3d968589d8 | 316 | |
Kojto | 90:cb3d968589d8 | 317 | /*! @brief Read current value of the FMC_PFAPR_M5AP field. */ |
Kojto | 90:cb3d968589d8 | 318 | #define BR_FMC_PFAPR_M5AP(x) (HW_FMC_PFAPR(x).B.M5AP) |
Kojto | 90:cb3d968589d8 | 319 | |
Kojto | 90:cb3d968589d8 | 320 | /*! @brief Format value for bitfield FMC_PFAPR_M5AP. */ |
Kojto | 90:cb3d968589d8 | 321 | #define BF_FMC_PFAPR_M5AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5AP) & BM_FMC_PFAPR_M5AP) |
Kojto | 90:cb3d968589d8 | 322 | |
Kojto | 90:cb3d968589d8 | 323 | /*! @brief Set the M5AP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 324 | #define BW_FMC_PFAPR_M5AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M5AP) | BF_FMC_PFAPR_M5AP(v))) |
Kojto | 90:cb3d968589d8 | 325 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 326 | |
Kojto | 90:cb3d968589d8 | 327 | /*! |
Kojto | 90:cb3d968589d8 | 328 | * @name Register FMC_PFAPR, field M6AP[13:12] (RW) |
Kojto | 90:cb3d968589d8 | 329 | * |
Kojto | 90:cb3d968589d8 | 330 | * This field controls whether read and write access to the flash are allowed |
Kojto | 90:cb3d968589d8 | 331 | * based on the logical master number of the requesting crossbar switch master. |
Kojto | 90:cb3d968589d8 | 332 | * |
Kojto | 90:cb3d968589d8 | 333 | * Values: |
Kojto | 90:cb3d968589d8 | 334 | * - 00 - No access may be performed by this master |
Kojto | 90:cb3d968589d8 | 335 | * - 01 - Only read accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 336 | * - 10 - Only write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 337 | * - 11 - Both read and write accesses may be performed by this master |
Kojto | 90:cb3d968589d8 | 338 | */ |
Kojto | 90:cb3d968589d8 | 339 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 340 | #define BP_FMC_PFAPR_M6AP (12U) /*!< Bit position for FMC_PFAPR_M6AP. */ |
Kojto | 90:cb3d968589d8 | 341 | #define BM_FMC_PFAPR_M6AP (0x00003000U) /*!< Bit mask for FMC_PFAPR_M6AP. */ |
Kojto | 90:cb3d968589d8 | 342 | #define BS_FMC_PFAPR_M6AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M6AP. */ |
Kojto | 90:cb3d968589d8 | 343 | |
Kojto | 90:cb3d968589d8 | 344 | /*! @brief Read current value of the FMC_PFAPR_M6AP field. */ |
Kojto | 90:cb3d968589d8 | 345 | #define BR_FMC_PFAPR_M6AP(x) (HW_FMC_PFAPR(x).B.M6AP) |
Kojto | 90:cb3d968589d8 | 346 | |
Kojto | 90:cb3d968589d8 | 347 | /*! @brief Format value for bitfield FMC_PFAPR_M6AP. */ |
Kojto | 90:cb3d968589d8 | 348 | #define BF_FMC_PFAPR_M6AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6AP) & BM_FMC_PFAPR_M6AP) |
Kojto | 90:cb3d968589d8 | 349 | |
Kojto | 90:cb3d968589d8 | 350 | /*! @brief Set the M6AP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 351 | #define BW_FMC_PFAPR_M6AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M6AP) | BF_FMC_PFAPR_M6AP(v))) |
Kojto | 90:cb3d968589d8 | 352 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 353 | |
Kojto | 90:cb3d968589d8 | 354 | /*! |
Kojto | 90:cb3d968589d8 | 355 | * @name Register FMC_PFAPR, field M7AP[15:14] (RW) |
Kojto | 90:cb3d968589d8 | 356 | * |
Kojto | 90:cb3d968589d8 | 357 | * This field controls whether read and write access to the flash are allowed |
Kojto | 90:cb3d968589d8 | 358 | * based on the logical master number of the requesting crossbar switch master. |
Kojto | 90:cb3d968589d8 | 359 | * |
Kojto | 90:cb3d968589d8 | 360 | * Values: |
Kojto | 90:cb3d968589d8 | 361 | * - 00 - No access may be performed by this master. |
Kojto | 90:cb3d968589d8 | 362 | * - 01 - Only read accesses may be performed by this master. |
Kojto | 90:cb3d968589d8 | 363 | * - 10 - Only write accesses may be performed by this master. |
Kojto | 90:cb3d968589d8 | 364 | * - 11 - Both read and write accesses may be performed by this master. |
Kojto | 90:cb3d968589d8 | 365 | */ |
Kojto | 90:cb3d968589d8 | 366 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 367 | #define BP_FMC_PFAPR_M7AP (14U) /*!< Bit position for FMC_PFAPR_M7AP. */ |
Kojto | 90:cb3d968589d8 | 368 | #define BM_FMC_PFAPR_M7AP (0x0000C000U) /*!< Bit mask for FMC_PFAPR_M7AP. */ |
Kojto | 90:cb3d968589d8 | 369 | #define BS_FMC_PFAPR_M7AP (2U) /*!< Bit field size in bits for FMC_PFAPR_M7AP. */ |
Kojto | 90:cb3d968589d8 | 370 | |
Kojto | 90:cb3d968589d8 | 371 | /*! @brief Read current value of the FMC_PFAPR_M7AP field. */ |
Kojto | 90:cb3d968589d8 | 372 | #define BR_FMC_PFAPR_M7AP(x) (HW_FMC_PFAPR(x).B.M7AP) |
Kojto | 90:cb3d968589d8 | 373 | |
Kojto | 90:cb3d968589d8 | 374 | /*! @brief Format value for bitfield FMC_PFAPR_M7AP. */ |
Kojto | 90:cb3d968589d8 | 375 | #define BF_FMC_PFAPR_M7AP(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7AP) & BM_FMC_PFAPR_M7AP) |
Kojto | 90:cb3d968589d8 | 376 | |
Kojto | 90:cb3d968589d8 | 377 | /*! @brief Set the M7AP field to a new value. */ |
Kojto | 90:cb3d968589d8 | 378 | #define BW_FMC_PFAPR_M7AP(x, v) (HW_FMC_PFAPR_WR(x, (HW_FMC_PFAPR_RD(x) & ~BM_FMC_PFAPR_M7AP) | BF_FMC_PFAPR_M7AP(v))) |
Kojto | 90:cb3d968589d8 | 379 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 380 | |
Kojto | 90:cb3d968589d8 | 381 | /*! |
Kojto | 90:cb3d968589d8 | 382 | * @name Register FMC_PFAPR, field M0PFD[16] (RW) |
Kojto | 90:cb3d968589d8 | 383 | * |
Kojto | 90:cb3d968589d8 | 384 | * These bits control whether prefetching is enabled based on the logical number |
Kojto | 90:cb3d968589d8 | 385 | * of the requesting crossbar switch master. This field is further qualified by |
Kojto | 90:cb3d968589d8 | 386 | * the PFBnCR[BxDPE,BxIPE] bits. |
Kojto | 90:cb3d968589d8 | 387 | * |
Kojto | 90:cb3d968589d8 | 388 | * Values: |
Kojto | 90:cb3d968589d8 | 389 | * - 0 - Prefetching for this master is enabled. |
Kojto | 90:cb3d968589d8 | 390 | * - 1 - Prefetching for this master is disabled. |
Kojto | 90:cb3d968589d8 | 391 | */ |
Kojto | 90:cb3d968589d8 | 392 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 393 | #define BP_FMC_PFAPR_M0PFD (16U) /*!< Bit position for FMC_PFAPR_M0PFD. */ |
Kojto | 90:cb3d968589d8 | 394 | #define BM_FMC_PFAPR_M0PFD (0x00010000U) /*!< Bit mask for FMC_PFAPR_M0PFD. */ |
Kojto | 90:cb3d968589d8 | 395 | #define BS_FMC_PFAPR_M0PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M0PFD. */ |
Kojto | 90:cb3d968589d8 | 396 | |
Kojto | 90:cb3d968589d8 | 397 | /*! @brief Read current value of the FMC_PFAPR_M0PFD field. */ |
Kojto | 90:cb3d968589d8 | 398 | #define BR_FMC_PFAPR_M0PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD)) |
Kojto | 90:cb3d968589d8 | 399 | |
Kojto | 90:cb3d968589d8 | 400 | /*! @brief Format value for bitfield FMC_PFAPR_M0PFD. */ |
Kojto | 90:cb3d968589d8 | 401 | #define BF_FMC_PFAPR_M0PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M0PFD) & BM_FMC_PFAPR_M0PFD) |
Kojto | 90:cb3d968589d8 | 402 | |
Kojto | 90:cb3d968589d8 | 403 | /*! @brief Set the M0PFD field to a new value. */ |
Kojto | 90:cb3d968589d8 | 404 | #define BW_FMC_PFAPR_M0PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M0PFD) = (v)) |
Kojto | 90:cb3d968589d8 | 405 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 406 | |
Kojto | 90:cb3d968589d8 | 407 | /*! |
Kojto | 90:cb3d968589d8 | 408 | * @name Register FMC_PFAPR, field M1PFD[17] (RW) |
Kojto | 90:cb3d968589d8 | 409 | * |
Kojto | 90:cb3d968589d8 | 410 | * These bits control whether prefetching is enabled based on the logical number |
Kojto | 90:cb3d968589d8 | 411 | * of the requesting crossbar switch master. This field is further qualified by |
Kojto | 90:cb3d968589d8 | 412 | * the PFBnCR[BxDPE,BxIPE] bits. |
Kojto | 90:cb3d968589d8 | 413 | * |
Kojto | 90:cb3d968589d8 | 414 | * Values: |
Kojto | 90:cb3d968589d8 | 415 | * - 0 - Prefetching for this master is enabled. |
Kojto | 90:cb3d968589d8 | 416 | * - 1 - Prefetching for this master is disabled. |
Kojto | 90:cb3d968589d8 | 417 | */ |
Kojto | 90:cb3d968589d8 | 418 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 419 | #define BP_FMC_PFAPR_M1PFD (17U) /*!< Bit position for FMC_PFAPR_M1PFD. */ |
Kojto | 90:cb3d968589d8 | 420 | #define BM_FMC_PFAPR_M1PFD (0x00020000U) /*!< Bit mask for FMC_PFAPR_M1PFD. */ |
Kojto | 90:cb3d968589d8 | 421 | #define BS_FMC_PFAPR_M1PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M1PFD. */ |
Kojto | 90:cb3d968589d8 | 422 | |
Kojto | 90:cb3d968589d8 | 423 | /*! @brief Read current value of the FMC_PFAPR_M1PFD field. */ |
Kojto | 90:cb3d968589d8 | 424 | #define BR_FMC_PFAPR_M1PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD)) |
Kojto | 90:cb3d968589d8 | 425 | |
Kojto | 90:cb3d968589d8 | 426 | /*! @brief Format value for bitfield FMC_PFAPR_M1PFD. */ |
Kojto | 90:cb3d968589d8 | 427 | #define BF_FMC_PFAPR_M1PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M1PFD) & BM_FMC_PFAPR_M1PFD) |
Kojto | 90:cb3d968589d8 | 428 | |
Kojto | 90:cb3d968589d8 | 429 | /*! @brief Set the M1PFD field to a new value. */ |
Kojto | 90:cb3d968589d8 | 430 | #define BW_FMC_PFAPR_M1PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M1PFD) = (v)) |
Kojto | 90:cb3d968589d8 | 431 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 432 | |
Kojto | 90:cb3d968589d8 | 433 | /*! |
Kojto | 90:cb3d968589d8 | 434 | * @name Register FMC_PFAPR, field M2PFD[18] (RW) |
Kojto | 90:cb3d968589d8 | 435 | * |
Kojto | 90:cb3d968589d8 | 436 | * These bits control whether prefetching is enabled based on the logical number |
Kojto | 90:cb3d968589d8 | 437 | * of the requesting crossbar switch master. This field is further qualified by |
Kojto | 90:cb3d968589d8 | 438 | * the PFBnCR[BxDPE,BxIPE] bits. |
Kojto | 90:cb3d968589d8 | 439 | * |
Kojto | 90:cb3d968589d8 | 440 | * Values: |
Kojto | 90:cb3d968589d8 | 441 | * - 0 - Prefetching for this master is enabled. |
Kojto | 90:cb3d968589d8 | 442 | * - 1 - Prefetching for this master is disabled. |
Kojto | 90:cb3d968589d8 | 443 | */ |
Kojto | 90:cb3d968589d8 | 444 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 445 | #define BP_FMC_PFAPR_M2PFD (18U) /*!< Bit position for FMC_PFAPR_M2PFD. */ |
Kojto | 90:cb3d968589d8 | 446 | #define BM_FMC_PFAPR_M2PFD (0x00040000U) /*!< Bit mask for FMC_PFAPR_M2PFD. */ |
Kojto | 90:cb3d968589d8 | 447 | #define BS_FMC_PFAPR_M2PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M2PFD. */ |
Kojto | 90:cb3d968589d8 | 448 | |
Kojto | 90:cb3d968589d8 | 449 | /*! @brief Read current value of the FMC_PFAPR_M2PFD field. */ |
Kojto | 90:cb3d968589d8 | 450 | #define BR_FMC_PFAPR_M2PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD)) |
Kojto | 90:cb3d968589d8 | 451 | |
Kojto | 90:cb3d968589d8 | 452 | /*! @brief Format value for bitfield FMC_PFAPR_M2PFD. */ |
Kojto | 90:cb3d968589d8 | 453 | #define BF_FMC_PFAPR_M2PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M2PFD) & BM_FMC_PFAPR_M2PFD) |
Kojto | 90:cb3d968589d8 | 454 | |
Kojto | 90:cb3d968589d8 | 455 | /*! @brief Set the M2PFD field to a new value. */ |
Kojto | 90:cb3d968589d8 | 456 | #define BW_FMC_PFAPR_M2PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M2PFD) = (v)) |
Kojto | 90:cb3d968589d8 | 457 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 458 | |
Kojto | 90:cb3d968589d8 | 459 | /*! |
Kojto | 90:cb3d968589d8 | 460 | * @name Register FMC_PFAPR, field M3PFD[19] (RW) |
Kojto | 90:cb3d968589d8 | 461 | * |
Kojto | 90:cb3d968589d8 | 462 | * These bits control whether prefetching is enabled based on the logical number |
Kojto | 90:cb3d968589d8 | 463 | * of the requesting crossbar switch master. This field is further qualified by |
Kojto | 90:cb3d968589d8 | 464 | * the PFBnCR[BxDPE,BxIPE] bits. |
Kojto | 90:cb3d968589d8 | 465 | * |
Kojto | 90:cb3d968589d8 | 466 | * Values: |
Kojto | 90:cb3d968589d8 | 467 | * - 0 - Prefetching for this master is enabled. |
Kojto | 90:cb3d968589d8 | 468 | * - 1 - Prefetching for this master is disabled. |
Kojto | 90:cb3d968589d8 | 469 | */ |
Kojto | 90:cb3d968589d8 | 470 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 471 | #define BP_FMC_PFAPR_M3PFD (19U) /*!< Bit position for FMC_PFAPR_M3PFD. */ |
Kojto | 90:cb3d968589d8 | 472 | #define BM_FMC_PFAPR_M3PFD (0x00080000U) /*!< Bit mask for FMC_PFAPR_M3PFD. */ |
Kojto | 90:cb3d968589d8 | 473 | #define BS_FMC_PFAPR_M3PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M3PFD. */ |
Kojto | 90:cb3d968589d8 | 474 | |
Kojto | 90:cb3d968589d8 | 475 | /*! @brief Read current value of the FMC_PFAPR_M3PFD field. */ |
Kojto | 90:cb3d968589d8 | 476 | #define BR_FMC_PFAPR_M3PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD)) |
Kojto | 90:cb3d968589d8 | 477 | |
Kojto | 90:cb3d968589d8 | 478 | /*! @brief Format value for bitfield FMC_PFAPR_M3PFD. */ |
Kojto | 90:cb3d968589d8 | 479 | #define BF_FMC_PFAPR_M3PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M3PFD) & BM_FMC_PFAPR_M3PFD) |
Kojto | 90:cb3d968589d8 | 480 | |
Kojto | 90:cb3d968589d8 | 481 | /*! @brief Set the M3PFD field to a new value. */ |
Kojto | 90:cb3d968589d8 | 482 | #define BW_FMC_PFAPR_M3PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M3PFD) = (v)) |
Kojto | 90:cb3d968589d8 | 483 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 484 | |
Kojto | 90:cb3d968589d8 | 485 | /*! |
Kojto | 90:cb3d968589d8 | 486 | * @name Register FMC_PFAPR, field M4PFD[20] (RW) |
Kojto | 90:cb3d968589d8 | 487 | * |
Kojto | 90:cb3d968589d8 | 488 | * These bits control whether prefetching is enabled based on the logical number |
Kojto | 90:cb3d968589d8 | 489 | * of the requesting crossbar switch master. This field is further qualified by |
Kojto | 90:cb3d968589d8 | 490 | * the PFBnCR[BxDPE,BxIPE] bits. |
Kojto | 90:cb3d968589d8 | 491 | * |
Kojto | 90:cb3d968589d8 | 492 | * Values: |
Kojto | 90:cb3d968589d8 | 493 | * - 0 - Prefetching for this master is enabled. |
Kojto | 90:cb3d968589d8 | 494 | * - 1 - Prefetching for this master is disabled. |
Kojto | 90:cb3d968589d8 | 495 | */ |
Kojto | 90:cb3d968589d8 | 496 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 497 | #define BP_FMC_PFAPR_M4PFD (20U) /*!< Bit position for FMC_PFAPR_M4PFD. */ |
Kojto | 90:cb3d968589d8 | 498 | #define BM_FMC_PFAPR_M4PFD (0x00100000U) /*!< Bit mask for FMC_PFAPR_M4PFD. */ |
Kojto | 90:cb3d968589d8 | 499 | #define BS_FMC_PFAPR_M4PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M4PFD. */ |
Kojto | 90:cb3d968589d8 | 500 | |
Kojto | 90:cb3d968589d8 | 501 | /*! @brief Read current value of the FMC_PFAPR_M4PFD field. */ |
Kojto | 90:cb3d968589d8 | 502 | #define BR_FMC_PFAPR_M4PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD)) |
Kojto | 90:cb3d968589d8 | 503 | |
Kojto | 90:cb3d968589d8 | 504 | /*! @brief Format value for bitfield FMC_PFAPR_M4PFD. */ |
Kojto | 90:cb3d968589d8 | 505 | #define BF_FMC_PFAPR_M4PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M4PFD) & BM_FMC_PFAPR_M4PFD) |
Kojto | 90:cb3d968589d8 | 506 | |
Kojto | 90:cb3d968589d8 | 507 | /*! @brief Set the M4PFD field to a new value. */ |
Kojto | 90:cb3d968589d8 | 508 | #define BW_FMC_PFAPR_M4PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M4PFD) = (v)) |
Kojto | 90:cb3d968589d8 | 509 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 510 | |
Kojto | 90:cb3d968589d8 | 511 | /*! |
Kojto | 90:cb3d968589d8 | 512 | * @name Register FMC_PFAPR, field M5PFD[21] (RW) |
Kojto | 90:cb3d968589d8 | 513 | * |
Kojto | 90:cb3d968589d8 | 514 | * These bits control whether prefetching is enabled based on the logical number |
Kojto | 90:cb3d968589d8 | 515 | * of the requesting crossbar switch master. This field is further qualified by |
Kojto | 90:cb3d968589d8 | 516 | * the PFBnCR[BxDPE,BxIPE] bits. |
Kojto | 90:cb3d968589d8 | 517 | * |
Kojto | 90:cb3d968589d8 | 518 | * Values: |
Kojto | 90:cb3d968589d8 | 519 | * - 0 - Prefetching for this master is enabled. |
Kojto | 90:cb3d968589d8 | 520 | * - 1 - Prefetching for this master is disabled. |
Kojto | 90:cb3d968589d8 | 521 | */ |
Kojto | 90:cb3d968589d8 | 522 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 523 | #define BP_FMC_PFAPR_M5PFD (21U) /*!< Bit position for FMC_PFAPR_M5PFD. */ |
Kojto | 90:cb3d968589d8 | 524 | #define BM_FMC_PFAPR_M5PFD (0x00200000U) /*!< Bit mask for FMC_PFAPR_M5PFD. */ |
Kojto | 90:cb3d968589d8 | 525 | #define BS_FMC_PFAPR_M5PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M5PFD. */ |
Kojto | 90:cb3d968589d8 | 526 | |
Kojto | 90:cb3d968589d8 | 527 | /*! @brief Read current value of the FMC_PFAPR_M5PFD field. */ |
Kojto | 90:cb3d968589d8 | 528 | #define BR_FMC_PFAPR_M5PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD)) |
Kojto | 90:cb3d968589d8 | 529 | |
Kojto | 90:cb3d968589d8 | 530 | /*! @brief Format value for bitfield FMC_PFAPR_M5PFD. */ |
Kojto | 90:cb3d968589d8 | 531 | #define BF_FMC_PFAPR_M5PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M5PFD) & BM_FMC_PFAPR_M5PFD) |
Kojto | 90:cb3d968589d8 | 532 | |
Kojto | 90:cb3d968589d8 | 533 | /*! @brief Set the M5PFD field to a new value. */ |
Kojto | 90:cb3d968589d8 | 534 | #define BW_FMC_PFAPR_M5PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M5PFD) = (v)) |
Kojto | 90:cb3d968589d8 | 535 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 536 | |
Kojto | 90:cb3d968589d8 | 537 | /*! |
Kojto | 90:cb3d968589d8 | 538 | * @name Register FMC_PFAPR, field M6PFD[22] (RW) |
Kojto | 90:cb3d968589d8 | 539 | * |
Kojto | 90:cb3d968589d8 | 540 | * These bits control whether prefetching is enabled based on the logical number |
Kojto | 90:cb3d968589d8 | 541 | * of the requesting crossbar switch master. This field is further qualified by |
Kojto | 90:cb3d968589d8 | 542 | * the PFBnCR[BxDPE,BxIPE] bits. |
Kojto | 90:cb3d968589d8 | 543 | * |
Kojto | 90:cb3d968589d8 | 544 | * Values: |
Kojto | 90:cb3d968589d8 | 545 | * - 0 - Prefetching for this master is enabled. |
Kojto | 90:cb3d968589d8 | 546 | * - 1 - Prefetching for this master is disabled. |
Kojto | 90:cb3d968589d8 | 547 | */ |
Kojto | 90:cb3d968589d8 | 548 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 549 | #define BP_FMC_PFAPR_M6PFD (22U) /*!< Bit position for FMC_PFAPR_M6PFD. */ |
Kojto | 90:cb3d968589d8 | 550 | #define BM_FMC_PFAPR_M6PFD (0x00400000U) /*!< Bit mask for FMC_PFAPR_M6PFD. */ |
Kojto | 90:cb3d968589d8 | 551 | #define BS_FMC_PFAPR_M6PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M6PFD. */ |
Kojto | 90:cb3d968589d8 | 552 | |
Kojto | 90:cb3d968589d8 | 553 | /*! @brief Read current value of the FMC_PFAPR_M6PFD field. */ |
Kojto | 90:cb3d968589d8 | 554 | #define BR_FMC_PFAPR_M6PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD)) |
Kojto | 90:cb3d968589d8 | 555 | |
Kojto | 90:cb3d968589d8 | 556 | /*! @brief Format value for bitfield FMC_PFAPR_M6PFD. */ |
Kojto | 90:cb3d968589d8 | 557 | #define BF_FMC_PFAPR_M6PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M6PFD) & BM_FMC_PFAPR_M6PFD) |
Kojto | 90:cb3d968589d8 | 558 | |
Kojto | 90:cb3d968589d8 | 559 | /*! @brief Set the M6PFD field to a new value. */ |
Kojto | 90:cb3d968589d8 | 560 | #define BW_FMC_PFAPR_M6PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M6PFD) = (v)) |
Kojto | 90:cb3d968589d8 | 561 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 562 | |
Kojto | 90:cb3d968589d8 | 563 | /*! |
Kojto | 90:cb3d968589d8 | 564 | * @name Register FMC_PFAPR, field M7PFD[23] (RW) |
Kojto | 90:cb3d968589d8 | 565 | * |
Kojto | 90:cb3d968589d8 | 566 | * These bits control whether prefetching is enabled based on the logical number |
Kojto | 90:cb3d968589d8 | 567 | * of the requesting crossbar switch master. This field is further qualified by |
Kojto | 90:cb3d968589d8 | 568 | * the PFBnCR[BxDPE,BxIPE] bits. |
Kojto | 90:cb3d968589d8 | 569 | * |
Kojto | 90:cb3d968589d8 | 570 | * Values: |
Kojto | 90:cb3d968589d8 | 571 | * - 0 - Prefetching for this master is enabled. |
Kojto | 90:cb3d968589d8 | 572 | * - 1 - Prefetching for this master is disabled. |
Kojto | 90:cb3d968589d8 | 573 | */ |
Kojto | 90:cb3d968589d8 | 574 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 575 | #define BP_FMC_PFAPR_M7PFD (23U) /*!< Bit position for FMC_PFAPR_M7PFD. */ |
Kojto | 90:cb3d968589d8 | 576 | #define BM_FMC_PFAPR_M7PFD (0x00800000U) /*!< Bit mask for FMC_PFAPR_M7PFD. */ |
Kojto | 90:cb3d968589d8 | 577 | #define BS_FMC_PFAPR_M7PFD (1U) /*!< Bit field size in bits for FMC_PFAPR_M7PFD. */ |
Kojto | 90:cb3d968589d8 | 578 | |
Kojto | 90:cb3d968589d8 | 579 | /*! @brief Read current value of the FMC_PFAPR_M7PFD field. */ |
Kojto | 90:cb3d968589d8 | 580 | #define BR_FMC_PFAPR_M7PFD(x) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD)) |
Kojto | 90:cb3d968589d8 | 581 | |
Kojto | 90:cb3d968589d8 | 582 | /*! @brief Format value for bitfield FMC_PFAPR_M7PFD. */ |
Kojto | 90:cb3d968589d8 | 583 | #define BF_FMC_PFAPR_M7PFD(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFAPR_M7PFD) & BM_FMC_PFAPR_M7PFD) |
Kojto | 90:cb3d968589d8 | 584 | |
Kojto | 90:cb3d968589d8 | 585 | /*! @brief Set the M7PFD field to a new value. */ |
Kojto | 90:cb3d968589d8 | 586 | #define BW_FMC_PFAPR_M7PFD(x, v) (BITBAND_ACCESS32(HW_FMC_PFAPR_ADDR(x), BP_FMC_PFAPR_M7PFD) = (v)) |
Kojto | 90:cb3d968589d8 | 587 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 588 | |
Kojto | 90:cb3d968589d8 | 589 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 590 | * HW_FMC_PFB0CR - Flash Bank 0 Control Register |
Kojto | 90:cb3d968589d8 | 591 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 592 | |
Kojto | 90:cb3d968589d8 | 593 | /*! |
Kojto | 90:cb3d968589d8 | 594 | * @brief HW_FMC_PFB0CR - Flash Bank 0 Control Register (RW) |
Kojto | 90:cb3d968589d8 | 595 | * |
Kojto | 90:cb3d968589d8 | 596 | * Reset value: 0x3004001FU |
Kojto | 90:cb3d968589d8 | 597 | */ |
Kojto | 90:cb3d968589d8 | 598 | typedef union _hw_fmc_pfb0cr |
Kojto | 90:cb3d968589d8 | 599 | { |
Kojto | 90:cb3d968589d8 | 600 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 601 | struct _hw_fmc_pfb0cr_bitfields |
Kojto | 90:cb3d968589d8 | 602 | { |
Kojto | 90:cb3d968589d8 | 603 | uint32_t B0SEBE : 1; /*!< [0] Bank 0 Single Entry Buffer Enable */ |
Kojto | 90:cb3d968589d8 | 604 | uint32_t B0IPE : 1; /*!< [1] Bank 0 Instruction Prefetch Enable */ |
Kojto | 90:cb3d968589d8 | 605 | uint32_t B0DPE : 1; /*!< [2] Bank 0 Data Prefetch Enable */ |
Kojto | 90:cb3d968589d8 | 606 | uint32_t B0ICE : 1; /*!< [3] Bank 0 Instruction Cache Enable */ |
Kojto | 90:cb3d968589d8 | 607 | uint32_t B0DCE : 1; /*!< [4] Bank 0 Data Cache Enable */ |
Kojto | 90:cb3d968589d8 | 608 | uint32_t CRC : 3; /*!< [7:5] Cache Replacement Control */ |
Kojto | 90:cb3d968589d8 | 609 | uint32_t RESERVED0 : 9; /*!< [16:8] */ |
Kojto | 90:cb3d968589d8 | 610 | uint32_t B0MW : 2; /*!< [18:17] Bank 0 Memory Width */ |
Kojto | 90:cb3d968589d8 | 611 | uint32_t S_B_INV : 1; /*!< [19] Invalidate Prefetch Speculation |
Kojto | 90:cb3d968589d8 | 612 | * Buffer */ |
Kojto | 90:cb3d968589d8 | 613 | uint32_t CINV_WAY : 4; /*!< [23:20] Cache Invalidate Way x */ |
Kojto | 90:cb3d968589d8 | 614 | uint32_t CLCK_WAY : 4; /*!< [27:24] Cache Lock Way x */ |
Kojto | 90:cb3d968589d8 | 615 | uint32_t B0RWSC : 4; /*!< [31:28] Bank 0 Read Wait State Control */ |
Kojto | 90:cb3d968589d8 | 616 | } B; |
Kojto | 90:cb3d968589d8 | 617 | } hw_fmc_pfb0cr_t; |
Kojto | 90:cb3d968589d8 | 618 | |
Kojto | 90:cb3d968589d8 | 619 | /*! |
Kojto | 90:cb3d968589d8 | 620 | * @name Constants and macros for entire FMC_PFB0CR register |
Kojto | 90:cb3d968589d8 | 621 | */ |
Kojto | 90:cb3d968589d8 | 622 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 623 | #define HW_FMC_PFB0CR_ADDR(x) ((x) + 0x4U) |
Kojto | 90:cb3d968589d8 | 624 | |
Kojto | 90:cb3d968589d8 | 625 | #define HW_FMC_PFB0CR(x) (*(__IO hw_fmc_pfb0cr_t *) HW_FMC_PFB0CR_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 626 | #define HW_FMC_PFB0CR_RD(x) (HW_FMC_PFB0CR(x).U) |
Kojto | 90:cb3d968589d8 | 627 | #define HW_FMC_PFB0CR_WR(x, v) (HW_FMC_PFB0CR(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 628 | #define HW_FMC_PFB0CR_SET(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 629 | #define HW_FMC_PFB0CR_CLR(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 630 | #define HW_FMC_PFB0CR_TOG(x, v) (HW_FMC_PFB0CR_WR(x, HW_FMC_PFB0CR_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 631 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 632 | |
Kojto | 90:cb3d968589d8 | 633 | /* |
Kojto | 90:cb3d968589d8 | 634 | * Constants & macros for individual FMC_PFB0CR bitfields |
Kojto | 90:cb3d968589d8 | 635 | */ |
Kojto | 90:cb3d968589d8 | 636 | |
Kojto | 90:cb3d968589d8 | 637 | /*! |
Kojto | 90:cb3d968589d8 | 638 | * @name Register FMC_PFB0CR, field B0SEBE[0] (RW) |
Kojto | 90:cb3d968589d8 | 639 | * |
Kojto | 90:cb3d968589d8 | 640 | * This bit controls whether the single entry page buffer is enabled in response |
Kojto | 90:cb3d968589d8 | 641 | * to flash read accesses. Its operation is independent from bank 1's cache. A |
Kojto | 90:cb3d968589d8 | 642 | * high-to-low transition of this enable forces the page buffer to be invalidated. |
Kojto | 90:cb3d968589d8 | 643 | * |
Kojto | 90:cb3d968589d8 | 644 | * Values: |
Kojto | 90:cb3d968589d8 | 645 | * - 0 - Single entry buffer is disabled. |
Kojto | 90:cb3d968589d8 | 646 | * - 1 - Single entry buffer is enabled. |
Kojto | 90:cb3d968589d8 | 647 | */ |
Kojto | 90:cb3d968589d8 | 648 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 649 | #define BP_FMC_PFB0CR_B0SEBE (0U) /*!< Bit position for FMC_PFB0CR_B0SEBE. */ |
Kojto | 90:cb3d968589d8 | 650 | #define BM_FMC_PFB0CR_B0SEBE (0x00000001U) /*!< Bit mask for FMC_PFB0CR_B0SEBE. */ |
Kojto | 90:cb3d968589d8 | 651 | #define BS_FMC_PFB0CR_B0SEBE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0SEBE. */ |
Kojto | 90:cb3d968589d8 | 652 | |
Kojto | 90:cb3d968589d8 | 653 | /*! @brief Read current value of the FMC_PFB0CR_B0SEBE field. */ |
Kojto | 90:cb3d968589d8 | 654 | #define BR_FMC_PFB0CR_B0SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE)) |
Kojto | 90:cb3d968589d8 | 655 | |
Kojto | 90:cb3d968589d8 | 656 | /*! @brief Format value for bitfield FMC_PFB0CR_B0SEBE. */ |
Kojto | 90:cb3d968589d8 | 657 | #define BF_FMC_PFB0CR_B0SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0SEBE) & BM_FMC_PFB0CR_B0SEBE) |
Kojto | 90:cb3d968589d8 | 658 | |
Kojto | 90:cb3d968589d8 | 659 | /*! @brief Set the B0SEBE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 660 | #define BW_FMC_PFB0CR_B0SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0SEBE) = (v)) |
Kojto | 90:cb3d968589d8 | 661 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 662 | |
Kojto | 90:cb3d968589d8 | 663 | /*! |
Kojto | 90:cb3d968589d8 | 664 | * @name Register FMC_PFB0CR, field B0IPE[1] (RW) |
Kojto | 90:cb3d968589d8 | 665 | * |
Kojto | 90:cb3d968589d8 | 666 | * This bit controls whether prefetches (or speculative accesses) are initiated |
Kojto | 90:cb3d968589d8 | 667 | * in response to instruction fetches. |
Kojto | 90:cb3d968589d8 | 668 | * |
Kojto | 90:cb3d968589d8 | 669 | * Values: |
Kojto | 90:cb3d968589d8 | 670 | * - 0 - Do not prefetch in response to instruction fetches. |
Kojto | 90:cb3d968589d8 | 671 | * - 1 - Enable prefetches in response to instruction fetches. |
Kojto | 90:cb3d968589d8 | 672 | */ |
Kojto | 90:cb3d968589d8 | 673 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 674 | #define BP_FMC_PFB0CR_B0IPE (1U) /*!< Bit position for FMC_PFB0CR_B0IPE. */ |
Kojto | 90:cb3d968589d8 | 675 | #define BM_FMC_PFB0CR_B0IPE (0x00000002U) /*!< Bit mask for FMC_PFB0CR_B0IPE. */ |
Kojto | 90:cb3d968589d8 | 676 | #define BS_FMC_PFB0CR_B0IPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0IPE. */ |
Kojto | 90:cb3d968589d8 | 677 | |
Kojto | 90:cb3d968589d8 | 678 | /*! @brief Read current value of the FMC_PFB0CR_B0IPE field. */ |
Kojto | 90:cb3d968589d8 | 679 | #define BR_FMC_PFB0CR_B0IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE)) |
Kojto | 90:cb3d968589d8 | 680 | |
Kojto | 90:cb3d968589d8 | 681 | /*! @brief Format value for bitfield FMC_PFB0CR_B0IPE. */ |
Kojto | 90:cb3d968589d8 | 682 | #define BF_FMC_PFB0CR_B0IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0IPE) & BM_FMC_PFB0CR_B0IPE) |
Kojto | 90:cb3d968589d8 | 683 | |
Kojto | 90:cb3d968589d8 | 684 | /*! @brief Set the B0IPE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 685 | #define BW_FMC_PFB0CR_B0IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0IPE) = (v)) |
Kojto | 90:cb3d968589d8 | 686 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 687 | |
Kojto | 90:cb3d968589d8 | 688 | /*! |
Kojto | 90:cb3d968589d8 | 689 | * @name Register FMC_PFB0CR, field B0DPE[2] (RW) |
Kojto | 90:cb3d968589d8 | 690 | * |
Kojto | 90:cb3d968589d8 | 691 | * This bit controls whether prefetches (or speculative accesses) are initiated |
Kojto | 90:cb3d968589d8 | 692 | * in response to data references. |
Kojto | 90:cb3d968589d8 | 693 | * |
Kojto | 90:cb3d968589d8 | 694 | * Values: |
Kojto | 90:cb3d968589d8 | 695 | * - 0 - Do not prefetch in response to data references. |
Kojto | 90:cb3d968589d8 | 696 | * - 1 - Enable prefetches in response to data references. |
Kojto | 90:cb3d968589d8 | 697 | */ |
Kojto | 90:cb3d968589d8 | 698 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 699 | #define BP_FMC_PFB0CR_B0DPE (2U) /*!< Bit position for FMC_PFB0CR_B0DPE. */ |
Kojto | 90:cb3d968589d8 | 700 | #define BM_FMC_PFB0CR_B0DPE (0x00000004U) /*!< Bit mask for FMC_PFB0CR_B0DPE. */ |
Kojto | 90:cb3d968589d8 | 701 | #define BS_FMC_PFB0CR_B0DPE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DPE. */ |
Kojto | 90:cb3d968589d8 | 702 | |
Kojto | 90:cb3d968589d8 | 703 | /*! @brief Read current value of the FMC_PFB0CR_B0DPE field. */ |
Kojto | 90:cb3d968589d8 | 704 | #define BR_FMC_PFB0CR_B0DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE)) |
Kojto | 90:cb3d968589d8 | 705 | |
Kojto | 90:cb3d968589d8 | 706 | /*! @brief Format value for bitfield FMC_PFB0CR_B0DPE. */ |
Kojto | 90:cb3d968589d8 | 707 | #define BF_FMC_PFB0CR_B0DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DPE) & BM_FMC_PFB0CR_B0DPE) |
Kojto | 90:cb3d968589d8 | 708 | |
Kojto | 90:cb3d968589d8 | 709 | /*! @brief Set the B0DPE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 710 | #define BW_FMC_PFB0CR_B0DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DPE) = (v)) |
Kojto | 90:cb3d968589d8 | 711 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 712 | |
Kojto | 90:cb3d968589d8 | 713 | /*! |
Kojto | 90:cb3d968589d8 | 714 | * @name Register FMC_PFB0CR, field B0ICE[3] (RW) |
Kojto | 90:cb3d968589d8 | 715 | * |
Kojto | 90:cb3d968589d8 | 716 | * This bit controls whether instruction fetches are loaded into the cache. |
Kojto | 90:cb3d968589d8 | 717 | * |
Kojto | 90:cb3d968589d8 | 718 | * Values: |
Kojto | 90:cb3d968589d8 | 719 | * - 0 - Do not cache instruction fetches. |
Kojto | 90:cb3d968589d8 | 720 | * - 1 - Cache instruction fetches. |
Kojto | 90:cb3d968589d8 | 721 | */ |
Kojto | 90:cb3d968589d8 | 722 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 723 | #define BP_FMC_PFB0CR_B0ICE (3U) /*!< Bit position for FMC_PFB0CR_B0ICE. */ |
Kojto | 90:cb3d968589d8 | 724 | #define BM_FMC_PFB0CR_B0ICE (0x00000008U) /*!< Bit mask for FMC_PFB0CR_B0ICE. */ |
Kojto | 90:cb3d968589d8 | 725 | #define BS_FMC_PFB0CR_B0ICE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0ICE. */ |
Kojto | 90:cb3d968589d8 | 726 | |
Kojto | 90:cb3d968589d8 | 727 | /*! @brief Read current value of the FMC_PFB0CR_B0ICE field. */ |
Kojto | 90:cb3d968589d8 | 728 | #define BR_FMC_PFB0CR_B0ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE)) |
Kojto | 90:cb3d968589d8 | 729 | |
Kojto | 90:cb3d968589d8 | 730 | /*! @brief Format value for bitfield FMC_PFB0CR_B0ICE. */ |
Kojto | 90:cb3d968589d8 | 731 | #define BF_FMC_PFB0CR_B0ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0ICE) & BM_FMC_PFB0CR_B0ICE) |
Kojto | 90:cb3d968589d8 | 732 | |
Kojto | 90:cb3d968589d8 | 733 | /*! @brief Set the B0ICE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 734 | #define BW_FMC_PFB0CR_B0ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0ICE) = (v)) |
Kojto | 90:cb3d968589d8 | 735 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 736 | |
Kojto | 90:cb3d968589d8 | 737 | /*! |
Kojto | 90:cb3d968589d8 | 738 | * @name Register FMC_PFB0CR, field B0DCE[4] (RW) |
Kojto | 90:cb3d968589d8 | 739 | * |
Kojto | 90:cb3d968589d8 | 740 | * This bit controls whether data references are loaded into the cache. |
Kojto | 90:cb3d968589d8 | 741 | * |
Kojto | 90:cb3d968589d8 | 742 | * Values: |
Kojto | 90:cb3d968589d8 | 743 | * - 0 - Do not cache data references. |
Kojto | 90:cb3d968589d8 | 744 | * - 1 - Cache data references. |
Kojto | 90:cb3d968589d8 | 745 | */ |
Kojto | 90:cb3d968589d8 | 746 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 747 | #define BP_FMC_PFB0CR_B0DCE (4U) /*!< Bit position for FMC_PFB0CR_B0DCE. */ |
Kojto | 90:cb3d968589d8 | 748 | #define BM_FMC_PFB0CR_B0DCE (0x00000010U) /*!< Bit mask for FMC_PFB0CR_B0DCE. */ |
Kojto | 90:cb3d968589d8 | 749 | #define BS_FMC_PFB0CR_B0DCE (1U) /*!< Bit field size in bits for FMC_PFB0CR_B0DCE. */ |
Kojto | 90:cb3d968589d8 | 750 | |
Kojto | 90:cb3d968589d8 | 751 | /*! @brief Read current value of the FMC_PFB0CR_B0DCE field. */ |
Kojto | 90:cb3d968589d8 | 752 | #define BR_FMC_PFB0CR_B0DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE)) |
Kojto | 90:cb3d968589d8 | 753 | |
Kojto | 90:cb3d968589d8 | 754 | /*! @brief Format value for bitfield FMC_PFB0CR_B0DCE. */ |
Kojto | 90:cb3d968589d8 | 755 | #define BF_FMC_PFB0CR_B0DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_B0DCE) & BM_FMC_PFB0CR_B0DCE) |
Kojto | 90:cb3d968589d8 | 756 | |
Kojto | 90:cb3d968589d8 | 757 | /*! @brief Set the B0DCE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 758 | #define BW_FMC_PFB0CR_B0DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_B0DCE) = (v)) |
Kojto | 90:cb3d968589d8 | 759 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 760 | |
Kojto | 90:cb3d968589d8 | 761 | /*! |
Kojto | 90:cb3d968589d8 | 762 | * @name Register FMC_PFB0CR, field CRC[7:5] (RW) |
Kojto | 90:cb3d968589d8 | 763 | * |
Kojto | 90:cb3d968589d8 | 764 | * This 3-bit field defines the replacement algorithm for accesses that are |
Kojto | 90:cb3d968589d8 | 765 | * cached. |
Kojto | 90:cb3d968589d8 | 766 | * |
Kojto | 90:cb3d968589d8 | 767 | * Values: |
Kojto | 90:cb3d968589d8 | 768 | * - 000 - LRU replacement algorithm per set across all four ways |
Kojto | 90:cb3d968589d8 | 769 | * - 001 - Reserved |
Kojto | 90:cb3d968589d8 | 770 | * - 010 - Independent LRU with ways [0-1] for ifetches, [2-3] for data |
Kojto | 90:cb3d968589d8 | 771 | * - 011 - Independent LRU with ways [0-2] for ifetches, [3] for data |
Kojto | 90:cb3d968589d8 | 772 | * - 1xx - Reserved |
Kojto | 90:cb3d968589d8 | 773 | */ |
Kojto | 90:cb3d968589d8 | 774 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 775 | #define BP_FMC_PFB0CR_CRC (5U) /*!< Bit position for FMC_PFB0CR_CRC. */ |
Kojto | 90:cb3d968589d8 | 776 | #define BM_FMC_PFB0CR_CRC (0x000000E0U) /*!< Bit mask for FMC_PFB0CR_CRC. */ |
Kojto | 90:cb3d968589d8 | 777 | #define BS_FMC_PFB0CR_CRC (3U) /*!< Bit field size in bits for FMC_PFB0CR_CRC. */ |
Kojto | 90:cb3d968589d8 | 778 | |
Kojto | 90:cb3d968589d8 | 779 | /*! @brief Read current value of the FMC_PFB0CR_CRC field. */ |
Kojto | 90:cb3d968589d8 | 780 | #define BR_FMC_PFB0CR_CRC(x) (HW_FMC_PFB0CR(x).B.CRC) |
Kojto | 90:cb3d968589d8 | 781 | |
Kojto | 90:cb3d968589d8 | 782 | /*! @brief Format value for bitfield FMC_PFB0CR_CRC. */ |
Kojto | 90:cb3d968589d8 | 783 | #define BF_FMC_PFB0CR_CRC(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CRC) & BM_FMC_PFB0CR_CRC) |
Kojto | 90:cb3d968589d8 | 784 | |
Kojto | 90:cb3d968589d8 | 785 | /*! @brief Set the CRC field to a new value. */ |
Kojto | 90:cb3d968589d8 | 786 | #define BW_FMC_PFB0CR_CRC(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CRC) | BF_FMC_PFB0CR_CRC(v))) |
Kojto | 90:cb3d968589d8 | 787 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 788 | |
Kojto | 90:cb3d968589d8 | 789 | /*! |
Kojto | 90:cb3d968589d8 | 790 | * @name Register FMC_PFB0CR, field B0MW[18:17] (RO) |
Kojto | 90:cb3d968589d8 | 791 | * |
Kojto | 90:cb3d968589d8 | 792 | * This read-only field defines the width of the bank 0 memory. |
Kojto | 90:cb3d968589d8 | 793 | * |
Kojto | 90:cb3d968589d8 | 794 | * Values: |
Kojto | 90:cb3d968589d8 | 795 | * - 00 - 32 bits |
Kojto | 90:cb3d968589d8 | 796 | * - 01 - 64 bits |
Kojto | 90:cb3d968589d8 | 797 | * - 10 - 128 bits |
Kojto | 90:cb3d968589d8 | 798 | * - 11 - Reserved |
Kojto | 90:cb3d968589d8 | 799 | */ |
Kojto | 90:cb3d968589d8 | 800 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 801 | #define BP_FMC_PFB0CR_B0MW (17U) /*!< Bit position for FMC_PFB0CR_B0MW. */ |
Kojto | 90:cb3d968589d8 | 802 | #define BM_FMC_PFB0CR_B0MW (0x00060000U) /*!< Bit mask for FMC_PFB0CR_B0MW. */ |
Kojto | 90:cb3d968589d8 | 803 | #define BS_FMC_PFB0CR_B0MW (2U) /*!< Bit field size in bits for FMC_PFB0CR_B0MW. */ |
Kojto | 90:cb3d968589d8 | 804 | |
Kojto | 90:cb3d968589d8 | 805 | /*! @brief Read current value of the FMC_PFB0CR_B0MW field. */ |
Kojto | 90:cb3d968589d8 | 806 | #define BR_FMC_PFB0CR_B0MW(x) (HW_FMC_PFB0CR(x).B.B0MW) |
Kojto | 90:cb3d968589d8 | 807 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 808 | |
Kojto | 90:cb3d968589d8 | 809 | /*! |
Kojto | 90:cb3d968589d8 | 810 | * @name Register FMC_PFB0CR, field S_B_INV[19] (WORZ) |
Kojto | 90:cb3d968589d8 | 811 | * |
Kojto | 90:cb3d968589d8 | 812 | * This bit determines if the FMC's prefetch speculation buffer and the single |
Kojto | 90:cb3d968589d8 | 813 | * entry page buffer are to be invalidated (cleared). When this bit is written, |
Kojto | 90:cb3d968589d8 | 814 | * the speculation buffer and single entry buffer are immediately cleared. This bit |
Kojto | 90:cb3d968589d8 | 815 | * always reads as zero. |
Kojto | 90:cb3d968589d8 | 816 | * |
Kojto | 90:cb3d968589d8 | 817 | * Values: |
Kojto | 90:cb3d968589d8 | 818 | * - 0 - Speculation buffer and single entry buffer are not affected. |
Kojto | 90:cb3d968589d8 | 819 | * - 1 - Invalidate (clear) speculation buffer and single entry buffer. |
Kojto | 90:cb3d968589d8 | 820 | */ |
Kojto | 90:cb3d968589d8 | 821 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 822 | #define BP_FMC_PFB0CR_S_B_INV (19U) /*!< Bit position for FMC_PFB0CR_S_B_INV. */ |
Kojto | 90:cb3d968589d8 | 823 | #define BM_FMC_PFB0CR_S_B_INV (0x00080000U) /*!< Bit mask for FMC_PFB0CR_S_B_INV. */ |
Kojto | 90:cb3d968589d8 | 824 | #define BS_FMC_PFB0CR_S_B_INV (1U) /*!< Bit field size in bits for FMC_PFB0CR_S_B_INV. */ |
Kojto | 90:cb3d968589d8 | 825 | |
Kojto | 90:cb3d968589d8 | 826 | /*! @brief Format value for bitfield FMC_PFB0CR_S_B_INV. */ |
Kojto | 90:cb3d968589d8 | 827 | #define BF_FMC_PFB0CR_S_B_INV(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_S_B_INV) & BM_FMC_PFB0CR_S_B_INV) |
Kojto | 90:cb3d968589d8 | 828 | |
Kojto | 90:cb3d968589d8 | 829 | /*! @brief Set the S_B_INV field to a new value. */ |
Kojto | 90:cb3d968589d8 | 830 | #define BW_FMC_PFB0CR_S_B_INV(x, v) (BITBAND_ACCESS32(HW_FMC_PFB0CR_ADDR(x), BP_FMC_PFB0CR_S_B_INV) = (v)) |
Kojto | 90:cb3d968589d8 | 831 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 832 | |
Kojto | 90:cb3d968589d8 | 833 | /*! |
Kojto | 90:cb3d968589d8 | 834 | * @name Register FMC_PFB0CR, field CINV_WAY[23:20] (WORZ) |
Kojto | 90:cb3d968589d8 | 835 | * |
Kojto | 90:cb3d968589d8 | 836 | * These bits determine if the given cache way is to be invalidated (cleared). |
Kojto | 90:cb3d968589d8 | 837 | * When a bit within this field is written, the corresponding cache way is |
Kojto | 90:cb3d968589d8 | 838 | * immediately invalidated: the way's tag, data, and valid contents are cleared. This |
Kojto | 90:cb3d968589d8 | 839 | * field always reads as zero. Cache invalidation takes precedence over locking. |
Kojto | 90:cb3d968589d8 | 840 | * The cache is invalidated by system reset. System software is required to |
Kojto | 90:cb3d968589d8 | 841 | * maintain memory coherency when any segment of the flash memory is programmed or |
Kojto | 90:cb3d968589d8 | 842 | * erased. Accordingly, cache invalidations must occur after a programming or erase |
Kojto | 90:cb3d968589d8 | 843 | * event is completed and before the new memory image is accessed. The bit setting |
Kojto | 90:cb3d968589d8 | 844 | * definitions are for each bit in the field. |
Kojto | 90:cb3d968589d8 | 845 | * |
Kojto | 90:cb3d968589d8 | 846 | * Values: |
Kojto | 90:cb3d968589d8 | 847 | * - 0 - No cache way invalidation for the corresponding cache |
Kojto | 90:cb3d968589d8 | 848 | * - 1 - Invalidate cache way for the corresponding cache: clear the tag, data, |
Kojto | 90:cb3d968589d8 | 849 | * and vld bits of ways selected |
Kojto | 90:cb3d968589d8 | 850 | */ |
Kojto | 90:cb3d968589d8 | 851 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 852 | #define BP_FMC_PFB0CR_CINV_WAY (20U) /*!< Bit position for FMC_PFB0CR_CINV_WAY. */ |
Kojto | 90:cb3d968589d8 | 853 | #define BM_FMC_PFB0CR_CINV_WAY (0x00F00000U) /*!< Bit mask for FMC_PFB0CR_CINV_WAY. */ |
Kojto | 90:cb3d968589d8 | 854 | #define BS_FMC_PFB0CR_CINV_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CINV_WAY. */ |
Kojto | 90:cb3d968589d8 | 855 | |
Kojto | 90:cb3d968589d8 | 856 | /*! @brief Format value for bitfield FMC_PFB0CR_CINV_WAY. */ |
Kojto | 90:cb3d968589d8 | 857 | #define BF_FMC_PFB0CR_CINV_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CINV_WAY) & BM_FMC_PFB0CR_CINV_WAY) |
Kojto | 90:cb3d968589d8 | 858 | |
Kojto | 90:cb3d968589d8 | 859 | /*! @brief Set the CINV_WAY field to a new value. */ |
Kojto | 90:cb3d968589d8 | 860 | #define BW_FMC_PFB0CR_CINV_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CINV_WAY) | BF_FMC_PFB0CR_CINV_WAY(v))) |
Kojto | 90:cb3d968589d8 | 861 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 862 | |
Kojto | 90:cb3d968589d8 | 863 | /*! |
Kojto | 90:cb3d968589d8 | 864 | * @name Register FMC_PFB0CR, field CLCK_WAY[27:24] (RW) |
Kojto | 90:cb3d968589d8 | 865 | * |
Kojto | 90:cb3d968589d8 | 866 | * These bits determine if the given cache way is locked such that its contents |
Kojto | 90:cb3d968589d8 | 867 | * will not be displaced by future misses. The bit setting definitions are for |
Kojto | 90:cb3d968589d8 | 868 | * each bit in the field. |
Kojto | 90:cb3d968589d8 | 869 | * |
Kojto | 90:cb3d968589d8 | 870 | * Values: |
Kojto | 90:cb3d968589d8 | 871 | * - 0 - Cache way is unlocked and may be displaced |
Kojto | 90:cb3d968589d8 | 872 | * - 1 - Cache way is locked and its contents are not displaced |
Kojto | 90:cb3d968589d8 | 873 | */ |
Kojto | 90:cb3d968589d8 | 874 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 875 | #define BP_FMC_PFB0CR_CLCK_WAY (24U) /*!< Bit position for FMC_PFB0CR_CLCK_WAY. */ |
Kojto | 90:cb3d968589d8 | 876 | #define BM_FMC_PFB0CR_CLCK_WAY (0x0F000000U) /*!< Bit mask for FMC_PFB0CR_CLCK_WAY. */ |
Kojto | 90:cb3d968589d8 | 877 | #define BS_FMC_PFB0CR_CLCK_WAY (4U) /*!< Bit field size in bits for FMC_PFB0CR_CLCK_WAY. */ |
Kojto | 90:cb3d968589d8 | 878 | |
Kojto | 90:cb3d968589d8 | 879 | /*! @brief Read current value of the FMC_PFB0CR_CLCK_WAY field. */ |
Kojto | 90:cb3d968589d8 | 880 | #define BR_FMC_PFB0CR_CLCK_WAY(x) (HW_FMC_PFB0CR(x).B.CLCK_WAY) |
Kojto | 90:cb3d968589d8 | 881 | |
Kojto | 90:cb3d968589d8 | 882 | /*! @brief Format value for bitfield FMC_PFB0CR_CLCK_WAY. */ |
Kojto | 90:cb3d968589d8 | 883 | #define BF_FMC_PFB0CR_CLCK_WAY(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB0CR_CLCK_WAY) & BM_FMC_PFB0CR_CLCK_WAY) |
Kojto | 90:cb3d968589d8 | 884 | |
Kojto | 90:cb3d968589d8 | 885 | /*! @brief Set the CLCK_WAY field to a new value. */ |
Kojto | 90:cb3d968589d8 | 886 | #define BW_FMC_PFB0CR_CLCK_WAY(x, v) (HW_FMC_PFB0CR_WR(x, (HW_FMC_PFB0CR_RD(x) & ~BM_FMC_PFB0CR_CLCK_WAY) | BF_FMC_PFB0CR_CLCK_WAY(v))) |
Kojto | 90:cb3d968589d8 | 887 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 888 | |
Kojto | 90:cb3d968589d8 | 889 | /*! |
Kojto | 90:cb3d968589d8 | 890 | * @name Register FMC_PFB0CR, field B0RWSC[31:28] (RO) |
Kojto | 90:cb3d968589d8 | 891 | * |
Kojto | 90:cb3d968589d8 | 892 | * This read-only field defines the number of wait states required to access the |
Kojto | 90:cb3d968589d8 | 893 | * bank 0 flash memory. The relationship between the read access time of the |
Kojto | 90:cb3d968589d8 | 894 | * flash array (expressed in system clock cycles) and RWSC is defined as: Access |
Kojto | 90:cb3d968589d8 | 895 | * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates |
Kojto | 90:cb3d968589d8 | 896 | * this value based on the ratio of the system clock speed to the flash clock |
Kojto | 90:cb3d968589d8 | 897 | * speed. For example, when this ratio is 4:1, the field's value is 3h. |
Kojto | 90:cb3d968589d8 | 898 | */ |
Kojto | 90:cb3d968589d8 | 899 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 900 | #define BP_FMC_PFB0CR_B0RWSC (28U) /*!< Bit position for FMC_PFB0CR_B0RWSC. */ |
Kojto | 90:cb3d968589d8 | 901 | #define BM_FMC_PFB0CR_B0RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB0CR_B0RWSC. */ |
Kojto | 90:cb3d968589d8 | 902 | #define BS_FMC_PFB0CR_B0RWSC (4U) /*!< Bit field size in bits for FMC_PFB0CR_B0RWSC. */ |
Kojto | 90:cb3d968589d8 | 903 | |
Kojto | 90:cb3d968589d8 | 904 | /*! @brief Read current value of the FMC_PFB0CR_B0RWSC field. */ |
Kojto | 90:cb3d968589d8 | 905 | #define BR_FMC_PFB0CR_B0RWSC(x) (HW_FMC_PFB0CR(x).B.B0RWSC) |
Kojto | 90:cb3d968589d8 | 906 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 907 | |
Kojto | 90:cb3d968589d8 | 908 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 909 | * HW_FMC_PFB1CR - Flash Bank 1 Control Register |
Kojto | 90:cb3d968589d8 | 910 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 911 | |
Kojto | 90:cb3d968589d8 | 912 | /*! |
Kojto | 90:cb3d968589d8 | 913 | * @brief HW_FMC_PFB1CR - Flash Bank 1 Control Register (RW) |
Kojto | 90:cb3d968589d8 | 914 | * |
Kojto | 90:cb3d968589d8 | 915 | * Reset value: 0x3004001FU |
Kojto | 90:cb3d968589d8 | 916 | * |
Kojto | 90:cb3d968589d8 | 917 | * This register has a format similar to that for PFB0CR, except it controls the |
Kojto | 90:cb3d968589d8 | 918 | * operation of flash bank 1, and the "global" cache control fields are empty. |
Kojto | 90:cb3d968589d8 | 919 | */ |
Kojto | 90:cb3d968589d8 | 920 | typedef union _hw_fmc_pfb1cr |
Kojto | 90:cb3d968589d8 | 921 | { |
Kojto | 90:cb3d968589d8 | 922 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 923 | struct _hw_fmc_pfb1cr_bitfields |
Kojto | 90:cb3d968589d8 | 924 | { |
Kojto | 90:cb3d968589d8 | 925 | uint32_t B1SEBE : 1; /*!< [0] Bank 1 Single Entry Buffer Enable */ |
Kojto | 90:cb3d968589d8 | 926 | uint32_t B1IPE : 1; /*!< [1] Bank 1 Instruction Prefetch Enable */ |
Kojto | 90:cb3d968589d8 | 927 | uint32_t B1DPE : 1; /*!< [2] Bank 1 Data Prefetch Enable */ |
Kojto | 90:cb3d968589d8 | 928 | uint32_t B1ICE : 1; /*!< [3] Bank 1 Instruction Cache Enable */ |
Kojto | 90:cb3d968589d8 | 929 | uint32_t B1DCE : 1; /*!< [4] Bank 1 Data Cache Enable */ |
Kojto | 90:cb3d968589d8 | 930 | uint32_t RESERVED0 : 12; /*!< [16:5] */ |
Kojto | 90:cb3d968589d8 | 931 | uint32_t B1MW : 2; /*!< [18:17] Bank 1 Memory Width */ |
Kojto | 90:cb3d968589d8 | 932 | uint32_t RESERVED1 : 9; /*!< [27:19] */ |
Kojto | 90:cb3d968589d8 | 933 | uint32_t B1RWSC : 4; /*!< [31:28] Bank 1 Read Wait State Control */ |
Kojto | 90:cb3d968589d8 | 934 | } B; |
Kojto | 90:cb3d968589d8 | 935 | } hw_fmc_pfb1cr_t; |
Kojto | 90:cb3d968589d8 | 936 | |
Kojto | 90:cb3d968589d8 | 937 | /*! |
Kojto | 90:cb3d968589d8 | 938 | * @name Constants and macros for entire FMC_PFB1CR register |
Kojto | 90:cb3d968589d8 | 939 | */ |
Kojto | 90:cb3d968589d8 | 940 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 941 | #define HW_FMC_PFB1CR_ADDR(x) ((x) + 0x8U) |
Kojto | 90:cb3d968589d8 | 942 | |
Kojto | 90:cb3d968589d8 | 943 | #define HW_FMC_PFB1CR(x) (*(__IO hw_fmc_pfb1cr_t *) HW_FMC_PFB1CR_ADDR(x)) |
Kojto | 90:cb3d968589d8 | 944 | #define HW_FMC_PFB1CR_RD(x) (HW_FMC_PFB1CR(x).U) |
Kojto | 90:cb3d968589d8 | 945 | #define HW_FMC_PFB1CR_WR(x, v) (HW_FMC_PFB1CR(x).U = (v)) |
Kojto | 90:cb3d968589d8 | 946 | #define HW_FMC_PFB1CR_SET(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) | (v))) |
Kojto | 90:cb3d968589d8 | 947 | #define HW_FMC_PFB1CR_CLR(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) & ~(v))) |
Kojto | 90:cb3d968589d8 | 948 | #define HW_FMC_PFB1CR_TOG(x, v) (HW_FMC_PFB1CR_WR(x, HW_FMC_PFB1CR_RD(x) ^ (v))) |
Kojto | 90:cb3d968589d8 | 949 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 950 | |
Kojto | 90:cb3d968589d8 | 951 | /* |
Kojto | 90:cb3d968589d8 | 952 | * Constants & macros for individual FMC_PFB1CR bitfields |
Kojto | 90:cb3d968589d8 | 953 | */ |
Kojto | 90:cb3d968589d8 | 954 | |
Kojto | 90:cb3d968589d8 | 955 | /*! |
Kojto | 90:cb3d968589d8 | 956 | * @name Register FMC_PFB1CR, field B1SEBE[0] (RW) |
Kojto | 90:cb3d968589d8 | 957 | * |
Kojto | 90:cb3d968589d8 | 958 | * This bit controls whether the single entry buffer is enabled in response to |
Kojto | 90:cb3d968589d8 | 959 | * flash read accesses. Its operation is independent from bank 0's cache. A |
Kojto | 90:cb3d968589d8 | 960 | * high-to-low transition of this enable forces the page buffer to be invalidated. |
Kojto | 90:cb3d968589d8 | 961 | * |
Kojto | 90:cb3d968589d8 | 962 | * Values: |
Kojto | 90:cb3d968589d8 | 963 | * - 0 - Single entry buffer is disabled. |
Kojto | 90:cb3d968589d8 | 964 | * - 1 - Single entry buffer is enabled. |
Kojto | 90:cb3d968589d8 | 965 | */ |
Kojto | 90:cb3d968589d8 | 966 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 967 | #define BP_FMC_PFB1CR_B1SEBE (0U) /*!< Bit position for FMC_PFB1CR_B1SEBE. */ |
Kojto | 90:cb3d968589d8 | 968 | #define BM_FMC_PFB1CR_B1SEBE (0x00000001U) /*!< Bit mask for FMC_PFB1CR_B1SEBE. */ |
Kojto | 90:cb3d968589d8 | 969 | #define BS_FMC_PFB1CR_B1SEBE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1SEBE. */ |
Kojto | 90:cb3d968589d8 | 970 | |
Kojto | 90:cb3d968589d8 | 971 | /*! @brief Read current value of the FMC_PFB1CR_B1SEBE field. */ |
Kojto | 90:cb3d968589d8 | 972 | #define BR_FMC_PFB1CR_B1SEBE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE)) |
Kojto | 90:cb3d968589d8 | 973 | |
Kojto | 90:cb3d968589d8 | 974 | /*! @brief Format value for bitfield FMC_PFB1CR_B1SEBE. */ |
Kojto | 90:cb3d968589d8 | 975 | #define BF_FMC_PFB1CR_B1SEBE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1SEBE) & BM_FMC_PFB1CR_B1SEBE) |
Kojto | 90:cb3d968589d8 | 976 | |
Kojto | 90:cb3d968589d8 | 977 | /*! @brief Set the B1SEBE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 978 | #define BW_FMC_PFB1CR_B1SEBE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1SEBE) = (v)) |
Kojto | 90:cb3d968589d8 | 979 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 980 | |
Kojto | 90:cb3d968589d8 | 981 | /*! |
Kojto | 90:cb3d968589d8 | 982 | * @name Register FMC_PFB1CR, field B1IPE[1] (RW) |
Kojto | 90:cb3d968589d8 | 983 | * |
Kojto | 90:cb3d968589d8 | 984 | * This bit controls whether prefetches (or speculative accesses) are initiated |
Kojto | 90:cb3d968589d8 | 985 | * in response to instruction fetches. |
Kojto | 90:cb3d968589d8 | 986 | * |
Kojto | 90:cb3d968589d8 | 987 | * Values: |
Kojto | 90:cb3d968589d8 | 988 | * - 0 - Do not prefetch in response to instruction fetches. |
Kojto | 90:cb3d968589d8 | 989 | * - 1 - Enable prefetches in response to instruction fetches. |
Kojto | 90:cb3d968589d8 | 990 | */ |
Kojto | 90:cb3d968589d8 | 991 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 992 | #define BP_FMC_PFB1CR_B1IPE (1U) /*!< Bit position for FMC_PFB1CR_B1IPE. */ |
Kojto | 90:cb3d968589d8 | 993 | #define BM_FMC_PFB1CR_B1IPE (0x00000002U) /*!< Bit mask for FMC_PFB1CR_B1IPE. */ |
Kojto | 90:cb3d968589d8 | 994 | #define BS_FMC_PFB1CR_B1IPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1IPE. */ |
Kojto | 90:cb3d968589d8 | 995 | |
Kojto | 90:cb3d968589d8 | 996 | /*! @brief Read current value of the FMC_PFB1CR_B1IPE field. */ |
Kojto | 90:cb3d968589d8 | 997 | #define BR_FMC_PFB1CR_B1IPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE)) |
Kojto | 90:cb3d968589d8 | 998 | |
Kojto | 90:cb3d968589d8 | 999 | /*! @brief Format value for bitfield FMC_PFB1CR_B1IPE. */ |
Kojto | 90:cb3d968589d8 | 1000 | #define BF_FMC_PFB1CR_B1IPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1IPE) & BM_FMC_PFB1CR_B1IPE) |
Kojto | 90:cb3d968589d8 | 1001 | |
Kojto | 90:cb3d968589d8 | 1002 | /*! @brief Set the B1IPE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1003 | #define BW_FMC_PFB1CR_B1IPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1IPE) = (v)) |
Kojto | 90:cb3d968589d8 | 1004 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1005 | |
Kojto | 90:cb3d968589d8 | 1006 | /*! |
Kojto | 90:cb3d968589d8 | 1007 | * @name Register FMC_PFB1CR, field B1DPE[2] (RW) |
Kojto | 90:cb3d968589d8 | 1008 | * |
Kojto | 90:cb3d968589d8 | 1009 | * This bit controls whether prefetches (or speculative accesses) are initiated |
Kojto | 90:cb3d968589d8 | 1010 | * in response to data references. |
Kojto | 90:cb3d968589d8 | 1011 | * |
Kojto | 90:cb3d968589d8 | 1012 | * Values: |
Kojto | 90:cb3d968589d8 | 1013 | * - 0 - Do not prefetch in response to data references. |
Kojto | 90:cb3d968589d8 | 1014 | * - 1 - Enable prefetches in response to data references. |
Kojto | 90:cb3d968589d8 | 1015 | */ |
Kojto | 90:cb3d968589d8 | 1016 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1017 | #define BP_FMC_PFB1CR_B1DPE (2U) /*!< Bit position for FMC_PFB1CR_B1DPE. */ |
Kojto | 90:cb3d968589d8 | 1018 | #define BM_FMC_PFB1CR_B1DPE (0x00000004U) /*!< Bit mask for FMC_PFB1CR_B1DPE. */ |
Kojto | 90:cb3d968589d8 | 1019 | #define BS_FMC_PFB1CR_B1DPE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DPE. */ |
Kojto | 90:cb3d968589d8 | 1020 | |
Kojto | 90:cb3d968589d8 | 1021 | /*! @brief Read current value of the FMC_PFB1CR_B1DPE field. */ |
Kojto | 90:cb3d968589d8 | 1022 | #define BR_FMC_PFB1CR_B1DPE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE)) |
Kojto | 90:cb3d968589d8 | 1023 | |
Kojto | 90:cb3d968589d8 | 1024 | /*! @brief Format value for bitfield FMC_PFB1CR_B1DPE. */ |
Kojto | 90:cb3d968589d8 | 1025 | #define BF_FMC_PFB1CR_B1DPE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DPE) & BM_FMC_PFB1CR_B1DPE) |
Kojto | 90:cb3d968589d8 | 1026 | |
Kojto | 90:cb3d968589d8 | 1027 | /*! @brief Set the B1DPE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1028 | #define BW_FMC_PFB1CR_B1DPE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DPE) = (v)) |
Kojto | 90:cb3d968589d8 | 1029 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1030 | |
Kojto | 90:cb3d968589d8 | 1031 | /*! |
Kojto | 90:cb3d968589d8 | 1032 | * @name Register FMC_PFB1CR, field B1ICE[3] (RW) |
Kojto | 90:cb3d968589d8 | 1033 | * |
Kojto | 90:cb3d968589d8 | 1034 | * This bit controls whether instruction fetches are loaded into the cache. |
Kojto | 90:cb3d968589d8 | 1035 | * |
Kojto | 90:cb3d968589d8 | 1036 | * Values: |
Kojto | 90:cb3d968589d8 | 1037 | * - 0 - Do not cache instruction fetches. |
Kojto | 90:cb3d968589d8 | 1038 | * - 1 - Cache instruction fetches. |
Kojto | 90:cb3d968589d8 | 1039 | */ |
Kojto | 90:cb3d968589d8 | 1040 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1041 | #define BP_FMC_PFB1CR_B1ICE (3U) /*!< Bit position for FMC_PFB1CR_B1ICE. */ |
Kojto | 90:cb3d968589d8 | 1042 | #define BM_FMC_PFB1CR_B1ICE (0x00000008U) /*!< Bit mask for FMC_PFB1CR_B1ICE. */ |
Kojto | 90:cb3d968589d8 | 1043 | #define BS_FMC_PFB1CR_B1ICE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1ICE. */ |
Kojto | 90:cb3d968589d8 | 1044 | |
Kojto | 90:cb3d968589d8 | 1045 | /*! @brief Read current value of the FMC_PFB1CR_B1ICE field. */ |
Kojto | 90:cb3d968589d8 | 1046 | #define BR_FMC_PFB1CR_B1ICE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE)) |
Kojto | 90:cb3d968589d8 | 1047 | |
Kojto | 90:cb3d968589d8 | 1048 | /*! @brief Format value for bitfield FMC_PFB1CR_B1ICE. */ |
Kojto | 90:cb3d968589d8 | 1049 | #define BF_FMC_PFB1CR_B1ICE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1ICE) & BM_FMC_PFB1CR_B1ICE) |
Kojto | 90:cb3d968589d8 | 1050 | |
Kojto | 90:cb3d968589d8 | 1051 | /*! @brief Set the B1ICE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1052 | #define BW_FMC_PFB1CR_B1ICE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1ICE) = (v)) |
Kojto | 90:cb3d968589d8 | 1053 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1054 | |
Kojto | 90:cb3d968589d8 | 1055 | /*! |
Kojto | 90:cb3d968589d8 | 1056 | * @name Register FMC_PFB1CR, field B1DCE[4] (RW) |
Kojto | 90:cb3d968589d8 | 1057 | * |
Kojto | 90:cb3d968589d8 | 1058 | * This bit controls whether data references are loaded into the cache. |
Kojto | 90:cb3d968589d8 | 1059 | * |
Kojto | 90:cb3d968589d8 | 1060 | * Values: |
Kojto | 90:cb3d968589d8 | 1061 | * - 0 - Do not cache data references. |
Kojto | 90:cb3d968589d8 | 1062 | * - 1 - Cache data references. |
Kojto | 90:cb3d968589d8 | 1063 | */ |
Kojto | 90:cb3d968589d8 | 1064 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1065 | #define BP_FMC_PFB1CR_B1DCE (4U) /*!< Bit position for FMC_PFB1CR_B1DCE. */ |
Kojto | 90:cb3d968589d8 | 1066 | #define BM_FMC_PFB1CR_B1DCE (0x00000010U) /*!< Bit mask for FMC_PFB1CR_B1DCE. */ |
Kojto | 90:cb3d968589d8 | 1067 | #define BS_FMC_PFB1CR_B1DCE (1U) /*!< Bit field size in bits for FMC_PFB1CR_B1DCE. */ |
Kojto | 90:cb3d968589d8 | 1068 | |
Kojto | 90:cb3d968589d8 | 1069 | /*! @brief Read current value of the FMC_PFB1CR_B1DCE field. */ |
Kojto | 90:cb3d968589d8 | 1070 | #define BR_FMC_PFB1CR_B1DCE(x) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE)) |
Kojto | 90:cb3d968589d8 | 1071 | |
Kojto | 90:cb3d968589d8 | 1072 | /*! @brief Format value for bitfield FMC_PFB1CR_B1DCE. */ |
Kojto | 90:cb3d968589d8 | 1073 | #define BF_FMC_PFB1CR_B1DCE(v) ((uint32_t)((uint32_t)(v) << BP_FMC_PFB1CR_B1DCE) & BM_FMC_PFB1CR_B1DCE) |
Kojto | 90:cb3d968589d8 | 1074 | |
Kojto | 90:cb3d968589d8 | 1075 | /*! @brief Set the B1DCE field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1076 | #define BW_FMC_PFB1CR_B1DCE(x, v) (BITBAND_ACCESS32(HW_FMC_PFB1CR_ADDR(x), BP_FMC_PFB1CR_B1DCE) = (v)) |
Kojto | 90:cb3d968589d8 | 1077 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1078 | |
Kojto | 90:cb3d968589d8 | 1079 | /*! |
Kojto | 90:cb3d968589d8 | 1080 | * @name Register FMC_PFB1CR, field B1MW[18:17] (RO) |
Kojto | 90:cb3d968589d8 | 1081 | * |
Kojto | 90:cb3d968589d8 | 1082 | * This read-only field defines the width of the bank 1 memory. |
Kojto | 90:cb3d968589d8 | 1083 | * |
Kojto | 90:cb3d968589d8 | 1084 | * Values: |
Kojto | 90:cb3d968589d8 | 1085 | * - 00 - 32 bits |
Kojto | 90:cb3d968589d8 | 1086 | * - 01 - 64 bits |
Kojto | 90:cb3d968589d8 | 1087 | * - 10 - 128 bits |
Kojto | 90:cb3d968589d8 | 1088 | * - 11 - Reserved |
Kojto | 90:cb3d968589d8 | 1089 | */ |
Kojto | 90:cb3d968589d8 | 1090 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1091 | #define BP_FMC_PFB1CR_B1MW (17U) /*!< Bit position for FMC_PFB1CR_B1MW. */ |
Kojto | 90:cb3d968589d8 | 1092 | #define BM_FMC_PFB1CR_B1MW (0x00060000U) /*!< Bit mask for FMC_PFB1CR_B1MW. */ |
Kojto | 90:cb3d968589d8 | 1093 | #define BS_FMC_PFB1CR_B1MW (2U) /*!< Bit field size in bits for FMC_PFB1CR_B1MW. */ |
Kojto | 90:cb3d968589d8 | 1094 | |
Kojto | 90:cb3d968589d8 | 1095 | /*! @brief Read current value of the FMC_PFB1CR_B1MW field. */ |
Kojto | 90:cb3d968589d8 | 1096 | #define BR_FMC_PFB1CR_B1MW(x) (HW_FMC_PFB1CR(x).B.B1MW) |
Kojto | 90:cb3d968589d8 | 1097 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1098 | |
Kojto | 90:cb3d968589d8 | 1099 | /*! |
Kojto | 90:cb3d968589d8 | 1100 | * @name Register FMC_PFB1CR, field B1RWSC[31:28] (RO) |
Kojto | 90:cb3d968589d8 | 1101 | * |
Kojto | 90:cb3d968589d8 | 1102 | * This read-only field defines the number of wait states required to access the |
Kojto | 90:cb3d968589d8 | 1103 | * bank 1 flash memory. The relationship between the read access time of the |
Kojto | 90:cb3d968589d8 | 1104 | * flash array (expressed in system clock cycles) and RWSC is defined as: Access |
Kojto | 90:cb3d968589d8 | 1105 | * time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates |
Kojto | 90:cb3d968589d8 | 1106 | * this value based on the ratio of the system clock speed to the flash clock |
Kojto | 90:cb3d968589d8 | 1107 | * speed. For example, when this ratio is 4:1, the field's value is 3h. |
Kojto | 90:cb3d968589d8 | 1108 | */ |
Kojto | 90:cb3d968589d8 | 1109 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1110 | #define BP_FMC_PFB1CR_B1RWSC (28U) /*!< Bit position for FMC_PFB1CR_B1RWSC. */ |
Kojto | 90:cb3d968589d8 | 1111 | #define BM_FMC_PFB1CR_B1RWSC (0xF0000000U) /*!< Bit mask for FMC_PFB1CR_B1RWSC. */ |
Kojto | 90:cb3d968589d8 | 1112 | #define BS_FMC_PFB1CR_B1RWSC (4U) /*!< Bit field size in bits for FMC_PFB1CR_B1RWSC. */ |
Kojto | 90:cb3d968589d8 | 1113 | |
Kojto | 90:cb3d968589d8 | 1114 | /*! @brief Read current value of the FMC_PFB1CR_B1RWSC field. */ |
Kojto | 90:cb3d968589d8 | 1115 | #define BR_FMC_PFB1CR_B1RWSC(x) (HW_FMC_PFB1CR(x).B.B1RWSC) |
Kojto | 90:cb3d968589d8 | 1116 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1117 | |
Kojto | 90:cb3d968589d8 | 1118 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1119 | * HW_FMC_TAGVDW0Sn - Cache Tag Storage |
Kojto | 90:cb3d968589d8 | 1120 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1121 | |
Kojto | 90:cb3d968589d8 | 1122 | /*! |
Kojto | 90:cb3d968589d8 | 1123 | * @brief HW_FMC_TAGVDW0Sn - Cache Tag Storage (RW) |
Kojto | 90:cb3d968589d8 | 1124 | * |
Kojto | 90:cb3d968589d8 | 1125 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1126 | * |
Kojto | 90:cb3d968589d8 | 1127 | * The cache is a 4-way, set-associative cache with 4 sets. The ways are |
Kojto | 90:cb3d968589d8 | 1128 | * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y |
Kojto | 90:cb3d968589d8 | 1129 | * denotes the set. This section represents tag/vld information for all sets in the |
Kojto | 90:cb3d968589d8 | 1130 | * indicated way. |
Kojto | 90:cb3d968589d8 | 1131 | */ |
Kojto | 90:cb3d968589d8 | 1132 | typedef union _hw_fmc_tagvdw0sn |
Kojto | 90:cb3d968589d8 | 1133 | { |
Kojto | 90:cb3d968589d8 | 1134 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1135 | struct _hw_fmc_tagvdw0sn_bitfields |
Kojto | 90:cb3d968589d8 | 1136 | { |
Kojto | 90:cb3d968589d8 | 1137 | uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ |
Kojto | 90:cb3d968589d8 | 1138 | uint32_t RESERVED0 : 4; /*!< [4:1] */ |
Kojto | 90:cb3d968589d8 | 1139 | uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ |
Kojto | 90:cb3d968589d8 | 1140 | uint32_t RESERVED1 : 13; /*!< [31:19] */ |
Kojto | 90:cb3d968589d8 | 1141 | } B; |
Kojto | 90:cb3d968589d8 | 1142 | } hw_fmc_tagvdw0sn_t; |
Kojto | 90:cb3d968589d8 | 1143 | |
Kojto | 90:cb3d968589d8 | 1144 | /*! |
Kojto | 90:cb3d968589d8 | 1145 | * @name Constants and macros for entire FMC_TAGVDW0Sn register |
Kojto | 90:cb3d968589d8 | 1146 | */ |
Kojto | 90:cb3d968589d8 | 1147 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1148 | #define HW_FMC_TAGVDW0Sn_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1149 | |
Kojto | 90:cb3d968589d8 | 1150 | #define HW_FMC_TAGVDW0Sn_ADDR(x, n) ((x) + 0x100U + (0x4U * (n))) |
Kojto | 90:cb3d968589d8 | 1151 | |
Kojto | 90:cb3d968589d8 | 1152 | #define HW_FMC_TAGVDW0Sn(x, n) (*(__IO hw_fmc_tagvdw0sn_t *) HW_FMC_TAGVDW0Sn_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1153 | #define HW_FMC_TAGVDW0Sn_RD(x, n) (HW_FMC_TAGVDW0Sn(x, n).U) |
Kojto | 90:cb3d968589d8 | 1154 | #define HW_FMC_TAGVDW0Sn_WR(x, n, v) (HW_FMC_TAGVDW0Sn(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1155 | #define HW_FMC_TAGVDW0Sn_SET(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1156 | #define HW_FMC_TAGVDW0Sn_CLR(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1157 | #define HW_FMC_TAGVDW0Sn_TOG(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, HW_FMC_TAGVDW0Sn_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1158 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1159 | |
Kojto | 90:cb3d968589d8 | 1160 | /* |
Kojto | 90:cb3d968589d8 | 1161 | * Constants & macros for individual FMC_TAGVDW0Sn bitfields |
Kojto | 90:cb3d968589d8 | 1162 | */ |
Kojto | 90:cb3d968589d8 | 1163 | |
Kojto | 90:cb3d968589d8 | 1164 | /*! |
Kojto | 90:cb3d968589d8 | 1165 | * @name Register FMC_TAGVDW0Sn, field valid[0] (RW) |
Kojto | 90:cb3d968589d8 | 1166 | */ |
Kojto | 90:cb3d968589d8 | 1167 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1168 | #define BP_FMC_TAGVDW0Sn_valid (0U) /*!< Bit position for FMC_TAGVDW0Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1169 | #define BM_FMC_TAGVDW0Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW0Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1170 | #define BS_FMC_TAGVDW0Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1171 | |
Kojto | 90:cb3d968589d8 | 1172 | /*! @brief Read current value of the FMC_TAGVDW0Sn_valid field. */ |
Kojto | 90:cb3d968589d8 | 1173 | #define BR_FMC_TAGVDW0Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid)) |
Kojto | 90:cb3d968589d8 | 1174 | |
Kojto | 90:cb3d968589d8 | 1175 | /*! @brief Format value for bitfield FMC_TAGVDW0Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1176 | #define BF_FMC_TAGVDW0Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_valid) & BM_FMC_TAGVDW0Sn_valid) |
Kojto | 90:cb3d968589d8 | 1177 | |
Kojto | 90:cb3d968589d8 | 1178 | /*! @brief Set the valid field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1179 | #define BW_FMC_TAGVDW0Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW0Sn_ADDR(x, n), BP_FMC_TAGVDW0Sn_valid) = (v)) |
Kojto | 90:cb3d968589d8 | 1180 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1181 | |
Kojto | 90:cb3d968589d8 | 1182 | /*! |
Kojto | 90:cb3d968589d8 | 1183 | * @name Register FMC_TAGVDW0Sn, field tag[18:5] (RW) |
Kojto | 90:cb3d968589d8 | 1184 | */ |
Kojto | 90:cb3d968589d8 | 1185 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1186 | #define BP_FMC_TAGVDW0Sn_tag (5U) /*!< Bit position for FMC_TAGVDW0Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1187 | #define BM_FMC_TAGVDW0Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW0Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1188 | #define BS_FMC_TAGVDW0Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW0Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1189 | |
Kojto | 90:cb3d968589d8 | 1190 | /*! @brief Read current value of the FMC_TAGVDW0Sn_tag field. */ |
Kojto | 90:cb3d968589d8 | 1191 | #define BR_FMC_TAGVDW0Sn_tag(x, n) (HW_FMC_TAGVDW0Sn(x, n).B.tag) |
Kojto | 90:cb3d968589d8 | 1192 | |
Kojto | 90:cb3d968589d8 | 1193 | /*! @brief Format value for bitfield FMC_TAGVDW0Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1194 | #define BF_FMC_TAGVDW0Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW0Sn_tag) & BM_FMC_TAGVDW0Sn_tag) |
Kojto | 90:cb3d968589d8 | 1195 | |
Kojto | 90:cb3d968589d8 | 1196 | /*! @brief Set the tag field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1197 | #define BW_FMC_TAGVDW0Sn_tag(x, n, v) (HW_FMC_TAGVDW0Sn_WR(x, n, (HW_FMC_TAGVDW0Sn_RD(x, n) & ~BM_FMC_TAGVDW0Sn_tag) | BF_FMC_TAGVDW0Sn_tag(v))) |
Kojto | 90:cb3d968589d8 | 1198 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1199 | |
Kojto | 90:cb3d968589d8 | 1200 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1201 | * HW_FMC_TAGVDW1Sn - Cache Tag Storage |
Kojto | 90:cb3d968589d8 | 1202 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1203 | |
Kojto | 90:cb3d968589d8 | 1204 | /*! |
Kojto | 90:cb3d968589d8 | 1205 | * @brief HW_FMC_TAGVDW1Sn - Cache Tag Storage (RW) |
Kojto | 90:cb3d968589d8 | 1206 | * |
Kojto | 90:cb3d968589d8 | 1207 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1208 | * |
Kojto | 90:cb3d968589d8 | 1209 | * The cache is a 4-way, set-associative cache with 4 sets. The ways are |
Kojto | 90:cb3d968589d8 | 1210 | * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y |
Kojto | 90:cb3d968589d8 | 1211 | * denotes the set. This section represents tag/vld information for all sets in the |
Kojto | 90:cb3d968589d8 | 1212 | * indicated way. |
Kojto | 90:cb3d968589d8 | 1213 | */ |
Kojto | 90:cb3d968589d8 | 1214 | typedef union _hw_fmc_tagvdw1sn |
Kojto | 90:cb3d968589d8 | 1215 | { |
Kojto | 90:cb3d968589d8 | 1216 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1217 | struct _hw_fmc_tagvdw1sn_bitfields |
Kojto | 90:cb3d968589d8 | 1218 | { |
Kojto | 90:cb3d968589d8 | 1219 | uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ |
Kojto | 90:cb3d968589d8 | 1220 | uint32_t RESERVED0 : 4; /*!< [4:1] */ |
Kojto | 90:cb3d968589d8 | 1221 | uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ |
Kojto | 90:cb3d968589d8 | 1222 | uint32_t RESERVED1 : 13; /*!< [31:19] */ |
Kojto | 90:cb3d968589d8 | 1223 | } B; |
Kojto | 90:cb3d968589d8 | 1224 | } hw_fmc_tagvdw1sn_t; |
Kojto | 90:cb3d968589d8 | 1225 | |
Kojto | 90:cb3d968589d8 | 1226 | /*! |
Kojto | 90:cb3d968589d8 | 1227 | * @name Constants and macros for entire FMC_TAGVDW1Sn register |
Kojto | 90:cb3d968589d8 | 1228 | */ |
Kojto | 90:cb3d968589d8 | 1229 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1230 | #define HW_FMC_TAGVDW1Sn_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1231 | |
Kojto | 90:cb3d968589d8 | 1232 | #define HW_FMC_TAGVDW1Sn_ADDR(x, n) ((x) + 0x110U + (0x4U * (n))) |
Kojto | 90:cb3d968589d8 | 1233 | |
Kojto | 90:cb3d968589d8 | 1234 | #define HW_FMC_TAGVDW1Sn(x, n) (*(__IO hw_fmc_tagvdw1sn_t *) HW_FMC_TAGVDW1Sn_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1235 | #define HW_FMC_TAGVDW1Sn_RD(x, n) (HW_FMC_TAGVDW1Sn(x, n).U) |
Kojto | 90:cb3d968589d8 | 1236 | #define HW_FMC_TAGVDW1Sn_WR(x, n, v) (HW_FMC_TAGVDW1Sn(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1237 | #define HW_FMC_TAGVDW1Sn_SET(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1238 | #define HW_FMC_TAGVDW1Sn_CLR(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1239 | #define HW_FMC_TAGVDW1Sn_TOG(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, HW_FMC_TAGVDW1Sn_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1240 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1241 | |
Kojto | 90:cb3d968589d8 | 1242 | /* |
Kojto | 90:cb3d968589d8 | 1243 | * Constants & macros for individual FMC_TAGVDW1Sn bitfields |
Kojto | 90:cb3d968589d8 | 1244 | */ |
Kojto | 90:cb3d968589d8 | 1245 | |
Kojto | 90:cb3d968589d8 | 1246 | /*! |
Kojto | 90:cb3d968589d8 | 1247 | * @name Register FMC_TAGVDW1Sn, field valid[0] (RW) |
Kojto | 90:cb3d968589d8 | 1248 | */ |
Kojto | 90:cb3d968589d8 | 1249 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1250 | #define BP_FMC_TAGVDW1Sn_valid (0U) /*!< Bit position for FMC_TAGVDW1Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1251 | #define BM_FMC_TAGVDW1Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW1Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1252 | #define BS_FMC_TAGVDW1Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1253 | |
Kojto | 90:cb3d968589d8 | 1254 | /*! @brief Read current value of the FMC_TAGVDW1Sn_valid field. */ |
Kojto | 90:cb3d968589d8 | 1255 | #define BR_FMC_TAGVDW1Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid)) |
Kojto | 90:cb3d968589d8 | 1256 | |
Kojto | 90:cb3d968589d8 | 1257 | /*! @brief Format value for bitfield FMC_TAGVDW1Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1258 | #define BF_FMC_TAGVDW1Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_valid) & BM_FMC_TAGVDW1Sn_valid) |
Kojto | 90:cb3d968589d8 | 1259 | |
Kojto | 90:cb3d968589d8 | 1260 | /*! @brief Set the valid field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1261 | #define BW_FMC_TAGVDW1Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW1Sn_ADDR(x, n), BP_FMC_TAGVDW1Sn_valid) = (v)) |
Kojto | 90:cb3d968589d8 | 1262 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1263 | |
Kojto | 90:cb3d968589d8 | 1264 | /*! |
Kojto | 90:cb3d968589d8 | 1265 | * @name Register FMC_TAGVDW1Sn, field tag[18:5] (RW) |
Kojto | 90:cb3d968589d8 | 1266 | */ |
Kojto | 90:cb3d968589d8 | 1267 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1268 | #define BP_FMC_TAGVDW1Sn_tag (5U) /*!< Bit position for FMC_TAGVDW1Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1269 | #define BM_FMC_TAGVDW1Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW1Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1270 | #define BS_FMC_TAGVDW1Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW1Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1271 | |
Kojto | 90:cb3d968589d8 | 1272 | /*! @brief Read current value of the FMC_TAGVDW1Sn_tag field. */ |
Kojto | 90:cb3d968589d8 | 1273 | #define BR_FMC_TAGVDW1Sn_tag(x, n) (HW_FMC_TAGVDW1Sn(x, n).B.tag) |
Kojto | 90:cb3d968589d8 | 1274 | |
Kojto | 90:cb3d968589d8 | 1275 | /*! @brief Format value for bitfield FMC_TAGVDW1Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1276 | #define BF_FMC_TAGVDW1Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW1Sn_tag) & BM_FMC_TAGVDW1Sn_tag) |
Kojto | 90:cb3d968589d8 | 1277 | |
Kojto | 90:cb3d968589d8 | 1278 | /*! @brief Set the tag field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1279 | #define BW_FMC_TAGVDW1Sn_tag(x, n, v) (HW_FMC_TAGVDW1Sn_WR(x, n, (HW_FMC_TAGVDW1Sn_RD(x, n) & ~BM_FMC_TAGVDW1Sn_tag) | BF_FMC_TAGVDW1Sn_tag(v))) |
Kojto | 90:cb3d968589d8 | 1280 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1281 | |
Kojto | 90:cb3d968589d8 | 1282 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1283 | * HW_FMC_TAGVDW2Sn - Cache Tag Storage |
Kojto | 90:cb3d968589d8 | 1284 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1285 | |
Kojto | 90:cb3d968589d8 | 1286 | /*! |
Kojto | 90:cb3d968589d8 | 1287 | * @brief HW_FMC_TAGVDW2Sn - Cache Tag Storage (RW) |
Kojto | 90:cb3d968589d8 | 1288 | * |
Kojto | 90:cb3d968589d8 | 1289 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1290 | * |
Kojto | 90:cb3d968589d8 | 1291 | * The cache is a 4-way, set-associative cache with 4 sets. The ways are |
Kojto | 90:cb3d968589d8 | 1292 | * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y |
Kojto | 90:cb3d968589d8 | 1293 | * denotes the set. This section represents tag/vld information for all sets in the |
Kojto | 90:cb3d968589d8 | 1294 | * indicated way. |
Kojto | 90:cb3d968589d8 | 1295 | */ |
Kojto | 90:cb3d968589d8 | 1296 | typedef union _hw_fmc_tagvdw2sn |
Kojto | 90:cb3d968589d8 | 1297 | { |
Kojto | 90:cb3d968589d8 | 1298 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1299 | struct _hw_fmc_tagvdw2sn_bitfields |
Kojto | 90:cb3d968589d8 | 1300 | { |
Kojto | 90:cb3d968589d8 | 1301 | uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ |
Kojto | 90:cb3d968589d8 | 1302 | uint32_t RESERVED0 : 4; /*!< [4:1] */ |
Kojto | 90:cb3d968589d8 | 1303 | uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ |
Kojto | 90:cb3d968589d8 | 1304 | uint32_t RESERVED1 : 13; /*!< [31:19] */ |
Kojto | 90:cb3d968589d8 | 1305 | } B; |
Kojto | 90:cb3d968589d8 | 1306 | } hw_fmc_tagvdw2sn_t; |
Kojto | 90:cb3d968589d8 | 1307 | |
Kojto | 90:cb3d968589d8 | 1308 | /*! |
Kojto | 90:cb3d968589d8 | 1309 | * @name Constants and macros for entire FMC_TAGVDW2Sn register |
Kojto | 90:cb3d968589d8 | 1310 | */ |
Kojto | 90:cb3d968589d8 | 1311 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1312 | #define HW_FMC_TAGVDW2Sn_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1313 | |
Kojto | 90:cb3d968589d8 | 1314 | #define HW_FMC_TAGVDW2Sn_ADDR(x, n) ((x) + 0x120U + (0x4U * (n))) |
Kojto | 90:cb3d968589d8 | 1315 | |
Kojto | 90:cb3d968589d8 | 1316 | #define HW_FMC_TAGVDW2Sn(x, n) (*(__IO hw_fmc_tagvdw2sn_t *) HW_FMC_TAGVDW2Sn_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1317 | #define HW_FMC_TAGVDW2Sn_RD(x, n) (HW_FMC_TAGVDW2Sn(x, n).U) |
Kojto | 90:cb3d968589d8 | 1318 | #define HW_FMC_TAGVDW2Sn_WR(x, n, v) (HW_FMC_TAGVDW2Sn(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1319 | #define HW_FMC_TAGVDW2Sn_SET(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1320 | #define HW_FMC_TAGVDW2Sn_CLR(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1321 | #define HW_FMC_TAGVDW2Sn_TOG(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, HW_FMC_TAGVDW2Sn_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1322 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1323 | |
Kojto | 90:cb3d968589d8 | 1324 | /* |
Kojto | 90:cb3d968589d8 | 1325 | * Constants & macros for individual FMC_TAGVDW2Sn bitfields |
Kojto | 90:cb3d968589d8 | 1326 | */ |
Kojto | 90:cb3d968589d8 | 1327 | |
Kojto | 90:cb3d968589d8 | 1328 | /*! |
Kojto | 90:cb3d968589d8 | 1329 | * @name Register FMC_TAGVDW2Sn, field valid[0] (RW) |
Kojto | 90:cb3d968589d8 | 1330 | */ |
Kojto | 90:cb3d968589d8 | 1331 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1332 | #define BP_FMC_TAGVDW2Sn_valid (0U) /*!< Bit position for FMC_TAGVDW2Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1333 | #define BM_FMC_TAGVDW2Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW2Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1334 | #define BS_FMC_TAGVDW2Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1335 | |
Kojto | 90:cb3d968589d8 | 1336 | /*! @brief Read current value of the FMC_TAGVDW2Sn_valid field. */ |
Kojto | 90:cb3d968589d8 | 1337 | #define BR_FMC_TAGVDW2Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid)) |
Kojto | 90:cb3d968589d8 | 1338 | |
Kojto | 90:cb3d968589d8 | 1339 | /*! @brief Format value for bitfield FMC_TAGVDW2Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1340 | #define BF_FMC_TAGVDW2Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_valid) & BM_FMC_TAGVDW2Sn_valid) |
Kojto | 90:cb3d968589d8 | 1341 | |
Kojto | 90:cb3d968589d8 | 1342 | /*! @brief Set the valid field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1343 | #define BW_FMC_TAGVDW2Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW2Sn_ADDR(x, n), BP_FMC_TAGVDW2Sn_valid) = (v)) |
Kojto | 90:cb3d968589d8 | 1344 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1345 | |
Kojto | 90:cb3d968589d8 | 1346 | /*! |
Kojto | 90:cb3d968589d8 | 1347 | * @name Register FMC_TAGVDW2Sn, field tag[18:5] (RW) |
Kojto | 90:cb3d968589d8 | 1348 | */ |
Kojto | 90:cb3d968589d8 | 1349 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1350 | #define BP_FMC_TAGVDW2Sn_tag (5U) /*!< Bit position for FMC_TAGVDW2Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1351 | #define BM_FMC_TAGVDW2Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW2Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1352 | #define BS_FMC_TAGVDW2Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW2Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1353 | |
Kojto | 90:cb3d968589d8 | 1354 | /*! @brief Read current value of the FMC_TAGVDW2Sn_tag field. */ |
Kojto | 90:cb3d968589d8 | 1355 | #define BR_FMC_TAGVDW2Sn_tag(x, n) (HW_FMC_TAGVDW2Sn(x, n).B.tag) |
Kojto | 90:cb3d968589d8 | 1356 | |
Kojto | 90:cb3d968589d8 | 1357 | /*! @brief Format value for bitfield FMC_TAGVDW2Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1358 | #define BF_FMC_TAGVDW2Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW2Sn_tag) & BM_FMC_TAGVDW2Sn_tag) |
Kojto | 90:cb3d968589d8 | 1359 | |
Kojto | 90:cb3d968589d8 | 1360 | /*! @brief Set the tag field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1361 | #define BW_FMC_TAGVDW2Sn_tag(x, n, v) (HW_FMC_TAGVDW2Sn_WR(x, n, (HW_FMC_TAGVDW2Sn_RD(x, n) & ~BM_FMC_TAGVDW2Sn_tag) | BF_FMC_TAGVDW2Sn_tag(v))) |
Kojto | 90:cb3d968589d8 | 1362 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1363 | |
Kojto | 90:cb3d968589d8 | 1364 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1365 | * HW_FMC_TAGVDW3Sn - Cache Tag Storage |
Kojto | 90:cb3d968589d8 | 1366 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1367 | |
Kojto | 90:cb3d968589d8 | 1368 | /*! |
Kojto | 90:cb3d968589d8 | 1369 | * @brief HW_FMC_TAGVDW3Sn - Cache Tag Storage (RW) |
Kojto | 90:cb3d968589d8 | 1370 | * |
Kojto | 90:cb3d968589d8 | 1371 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1372 | * |
Kojto | 90:cb3d968589d8 | 1373 | * The cache is a 4-way, set-associative cache with 4 sets. The ways are |
Kojto | 90:cb3d968589d8 | 1374 | * numbered 0-3 and the sets are numbered 0-3. In TAGVDWxSy, x denotes the way, and y |
Kojto | 90:cb3d968589d8 | 1375 | * denotes the set. This section represents tag/vld information for all sets in the |
Kojto | 90:cb3d968589d8 | 1376 | * indicated way. |
Kojto | 90:cb3d968589d8 | 1377 | */ |
Kojto | 90:cb3d968589d8 | 1378 | typedef union _hw_fmc_tagvdw3sn |
Kojto | 90:cb3d968589d8 | 1379 | { |
Kojto | 90:cb3d968589d8 | 1380 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1381 | struct _hw_fmc_tagvdw3sn_bitfields |
Kojto | 90:cb3d968589d8 | 1382 | { |
Kojto | 90:cb3d968589d8 | 1383 | uint32_t valid : 1; /*!< [0] 1-bit valid for cache entry */ |
Kojto | 90:cb3d968589d8 | 1384 | uint32_t RESERVED0 : 4; /*!< [4:1] */ |
Kojto | 90:cb3d968589d8 | 1385 | uint32_t tag : 14; /*!< [18:5] 14-bit tag for cache entry */ |
Kojto | 90:cb3d968589d8 | 1386 | uint32_t RESERVED1 : 13; /*!< [31:19] */ |
Kojto | 90:cb3d968589d8 | 1387 | } B; |
Kojto | 90:cb3d968589d8 | 1388 | } hw_fmc_tagvdw3sn_t; |
Kojto | 90:cb3d968589d8 | 1389 | |
Kojto | 90:cb3d968589d8 | 1390 | /*! |
Kojto | 90:cb3d968589d8 | 1391 | * @name Constants and macros for entire FMC_TAGVDW3Sn register |
Kojto | 90:cb3d968589d8 | 1392 | */ |
Kojto | 90:cb3d968589d8 | 1393 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1394 | #define HW_FMC_TAGVDW3Sn_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1395 | |
Kojto | 90:cb3d968589d8 | 1396 | #define HW_FMC_TAGVDW3Sn_ADDR(x, n) ((x) + 0x130U + (0x4U * (n))) |
Kojto | 90:cb3d968589d8 | 1397 | |
Kojto | 90:cb3d968589d8 | 1398 | #define HW_FMC_TAGVDW3Sn(x, n) (*(__IO hw_fmc_tagvdw3sn_t *) HW_FMC_TAGVDW3Sn_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1399 | #define HW_FMC_TAGVDW3Sn_RD(x, n) (HW_FMC_TAGVDW3Sn(x, n).U) |
Kojto | 90:cb3d968589d8 | 1400 | #define HW_FMC_TAGVDW3Sn_WR(x, n, v) (HW_FMC_TAGVDW3Sn(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1401 | #define HW_FMC_TAGVDW3Sn_SET(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1402 | #define HW_FMC_TAGVDW3Sn_CLR(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1403 | #define HW_FMC_TAGVDW3Sn_TOG(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, HW_FMC_TAGVDW3Sn_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1404 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1405 | |
Kojto | 90:cb3d968589d8 | 1406 | /* |
Kojto | 90:cb3d968589d8 | 1407 | * Constants & macros for individual FMC_TAGVDW3Sn bitfields |
Kojto | 90:cb3d968589d8 | 1408 | */ |
Kojto | 90:cb3d968589d8 | 1409 | |
Kojto | 90:cb3d968589d8 | 1410 | /*! |
Kojto | 90:cb3d968589d8 | 1411 | * @name Register FMC_TAGVDW3Sn, field valid[0] (RW) |
Kojto | 90:cb3d968589d8 | 1412 | */ |
Kojto | 90:cb3d968589d8 | 1413 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1414 | #define BP_FMC_TAGVDW3Sn_valid (0U) /*!< Bit position for FMC_TAGVDW3Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1415 | #define BM_FMC_TAGVDW3Sn_valid (0x00000001U) /*!< Bit mask for FMC_TAGVDW3Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1416 | #define BS_FMC_TAGVDW3Sn_valid (1U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1417 | |
Kojto | 90:cb3d968589d8 | 1418 | /*! @brief Read current value of the FMC_TAGVDW3Sn_valid field. */ |
Kojto | 90:cb3d968589d8 | 1419 | #define BR_FMC_TAGVDW3Sn_valid(x, n) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid)) |
Kojto | 90:cb3d968589d8 | 1420 | |
Kojto | 90:cb3d968589d8 | 1421 | /*! @brief Format value for bitfield FMC_TAGVDW3Sn_valid. */ |
Kojto | 90:cb3d968589d8 | 1422 | #define BF_FMC_TAGVDW3Sn_valid(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_valid) & BM_FMC_TAGVDW3Sn_valid) |
Kojto | 90:cb3d968589d8 | 1423 | |
Kojto | 90:cb3d968589d8 | 1424 | /*! @brief Set the valid field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1425 | #define BW_FMC_TAGVDW3Sn_valid(x, n, v) (BITBAND_ACCESS32(HW_FMC_TAGVDW3Sn_ADDR(x, n), BP_FMC_TAGVDW3Sn_valid) = (v)) |
Kojto | 90:cb3d968589d8 | 1426 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1427 | |
Kojto | 90:cb3d968589d8 | 1428 | /*! |
Kojto | 90:cb3d968589d8 | 1429 | * @name Register FMC_TAGVDW3Sn, field tag[18:5] (RW) |
Kojto | 90:cb3d968589d8 | 1430 | */ |
Kojto | 90:cb3d968589d8 | 1431 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1432 | #define BP_FMC_TAGVDW3Sn_tag (5U) /*!< Bit position for FMC_TAGVDW3Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1433 | #define BM_FMC_TAGVDW3Sn_tag (0x0007FFE0U) /*!< Bit mask for FMC_TAGVDW3Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1434 | #define BS_FMC_TAGVDW3Sn_tag (14U) /*!< Bit field size in bits for FMC_TAGVDW3Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1435 | |
Kojto | 90:cb3d968589d8 | 1436 | /*! @brief Read current value of the FMC_TAGVDW3Sn_tag field. */ |
Kojto | 90:cb3d968589d8 | 1437 | #define BR_FMC_TAGVDW3Sn_tag(x, n) (HW_FMC_TAGVDW3Sn(x, n).B.tag) |
Kojto | 90:cb3d968589d8 | 1438 | |
Kojto | 90:cb3d968589d8 | 1439 | /*! @brief Format value for bitfield FMC_TAGVDW3Sn_tag. */ |
Kojto | 90:cb3d968589d8 | 1440 | #define BF_FMC_TAGVDW3Sn_tag(v) ((uint32_t)((uint32_t)(v) << BP_FMC_TAGVDW3Sn_tag) & BM_FMC_TAGVDW3Sn_tag) |
Kojto | 90:cb3d968589d8 | 1441 | |
Kojto | 90:cb3d968589d8 | 1442 | /*! @brief Set the tag field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1443 | #define BW_FMC_TAGVDW3Sn_tag(x, n, v) (HW_FMC_TAGVDW3Sn_WR(x, n, (HW_FMC_TAGVDW3Sn_RD(x, n) & ~BM_FMC_TAGVDW3Sn_tag) | BF_FMC_TAGVDW3Sn_tag(v))) |
Kojto | 90:cb3d968589d8 | 1444 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1445 | |
Kojto | 90:cb3d968589d8 | 1446 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1447 | * HW_FMC_DATAW0SnU - Cache Data Storage (upper word) |
Kojto | 90:cb3d968589d8 | 1448 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1449 | |
Kojto | 90:cb3d968589d8 | 1450 | /*! |
Kojto | 90:cb3d968589d8 | 1451 | * @brief HW_FMC_DATAW0SnU - Cache Data Storage (upper word) (RW) |
Kojto | 90:cb3d968589d8 | 1452 | * |
Kojto | 90:cb3d968589d8 | 1453 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1454 | * |
Kojto | 90:cb3d968589d8 | 1455 | * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. |
Kojto | 90:cb3d968589d8 | 1456 | * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and |
Kojto | 90:cb3d968589d8 | 1457 | * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and |
Kojto | 90:cb3d968589d8 | 1458 | * lower word, respectively. This section represents data for the upper word (bits |
Kojto | 90:cb3d968589d8 | 1459 | * [63:32]) of all sets in the indicated way. |
Kojto | 90:cb3d968589d8 | 1460 | */ |
Kojto | 90:cb3d968589d8 | 1461 | typedef union _hw_fmc_dataw0snu |
Kojto | 90:cb3d968589d8 | 1462 | { |
Kojto | 90:cb3d968589d8 | 1463 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1464 | struct _hw_fmc_dataw0snu_bitfields |
Kojto | 90:cb3d968589d8 | 1465 | { |
Kojto | 90:cb3d968589d8 | 1466 | uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ |
Kojto | 90:cb3d968589d8 | 1467 | } B; |
Kojto | 90:cb3d968589d8 | 1468 | } hw_fmc_dataw0snu_t; |
Kojto | 90:cb3d968589d8 | 1469 | |
Kojto | 90:cb3d968589d8 | 1470 | /*! |
Kojto | 90:cb3d968589d8 | 1471 | * @name Constants and macros for entire FMC_DATAW0SnU register |
Kojto | 90:cb3d968589d8 | 1472 | */ |
Kojto | 90:cb3d968589d8 | 1473 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1474 | #define HW_FMC_DATAW0SnU_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1475 | |
Kojto | 90:cb3d968589d8 | 1476 | #define HW_FMC_DATAW0SnU_ADDR(x, n) ((x) + 0x200U + (0x8U * (n))) |
Kojto | 90:cb3d968589d8 | 1477 | |
Kojto | 90:cb3d968589d8 | 1478 | #define HW_FMC_DATAW0SnU(x, n) (*(__IO hw_fmc_dataw0snu_t *) HW_FMC_DATAW0SnU_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1479 | #define HW_FMC_DATAW0SnU_RD(x, n) (HW_FMC_DATAW0SnU(x, n).U) |
Kojto | 90:cb3d968589d8 | 1480 | #define HW_FMC_DATAW0SnU_WR(x, n, v) (HW_FMC_DATAW0SnU(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1481 | #define HW_FMC_DATAW0SnU_SET(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1482 | #define HW_FMC_DATAW0SnU_CLR(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1483 | #define HW_FMC_DATAW0SnU_TOG(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, HW_FMC_DATAW0SnU_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1484 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1485 | |
Kojto | 90:cb3d968589d8 | 1486 | /* |
Kojto | 90:cb3d968589d8 | 1487 | * Constants & macros for individual FMC_DATAW0SnU bitfields |
Kojto | 90:cb3d968589d8 | 1488 | */ |
Kojto | 90:cb3d968589d8 | 1489 | |
Kojto | 90:cb3d968589d8 | 1490 | /*! |
Kojto | 90:cb3d968589d8 | 1491 | * @name Register FMC_DATAW0SnU, field data[31:0] (RW) |
Kojto | 90:cb3d968589d8 | 1492 | */ |
Kojto | 90:cb3d968589d8 | 1493 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1494 | #define BP_FMC_DATAW0SnU_data (0U) /*!< Bit position for FMC_DATAW0SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1495 | #define BM_FMC_DATAW0SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1496 | #define BS_FMC_DATAW0SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1497 | |
Kojto | 90:cb3d968589d8 | 1498 | /*! @brief Read current value of the FMC_DATAW0SnU_data field. */ |
Kojto | 90:cb3d968589d8 | 1499 | #define BR_FMC_DATAW0SnU_data(x, n) (HW_FMC_DATAW0SnU(x, n).U) |
Kojto | 90:cb3d968589d8 | 1500 | |
Kojto | 90:cb3d968589d8 | 1501 | /*! @brief Format value for bitfield FMC_DATAW0SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1502 | #define BF_FMC_DATAW0SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnU_data) & BM_FMC_DATAW0SnU_data) |
Kojto | 90:cb3d968589d8 | 1503 | |
Kojto | 90:cb3d968589d8 | 1504 | /*! @brief Set the data field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1505 | #define BW_FMC_DATAW0SnU_data(x, n, v) (HW_FMC_DATAW0SnU_WR(x, n, v)) |
Kojto | 90:cb3d968589d8 | 1506 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1507 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1508 | * HW_FMC_DATAW0SnL - Cache Data Storage (lower word) |
Kojto | 90:cb3d968589d8 | 1509 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1510 | |
Kojto | 90:cb3d968589d8 | 1511 | /*! |
Kojto | 90:cb3d968589d8 | 1512 | * @brief HW_FMC_DATAW0SnL - Cache Data Storage (lower word) (RW) |
Kojto | 90:cb3d968589d8 | 1513 | * |
Kojto | 90:cb3d968589d8 | 1514 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1515 | * |
Kojto | 90:cb3d968589d8 | 1516 | * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. |
Kojto | 90:cb3d968589d8 | 1517 | * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and |
Kojto | 90:cb3d968589d8 | 1518 | * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and |
Kojto | 90:cb3d968589d8 | 1519 | * lower word, respectively. This section represents data for the lower word (bits |
Kojto | 90:cb3d968589d8 | 1520 | * [31:0]) of all sets in the indicated way. |
Kojto | 90:cb3d968589d8 | 1521 | */ |
Kojto | 90:cb3d968589d8 | 1522 | typedef union _hw_fmc_dataw0snl |
Kojto | 90:cb3d968589d8 | 1523 | { |
Kojto | 90:cb3d968589d8 | 1524 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1525 | struct _hw_fmc_dataw0snl_bitfields |
Kojto | 90:cb3d968589d8 | 1526 | { |
Kojto | 90:cb3d968589d8 | 1527 | uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ |
Kojto | 90:cb3d968589d8 | 1528 | } B; |
Kojto | 90:cb3d968589d8 | 1529 | } hw_fmc_dataw0snl_t; |
Kojto | 90:cb3d968589d8 | 1530 | |
Kojto | 90:cb3d968589d8 | 1531 | /*! |
Kojto | 90:cb3d968589d8 | 1532 | * @name Constants and macros for entire FMC_DATAW0SnL register |
Kojto | 90:cb3d968589d8 | 1533 | */ |
Kojto | 90:cb3d968589d8 | 1534 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1535 | #define HW_FMC_DATAW0SnL_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1536 | |
Kojto | 90:cb3d968589d8 | 1537 | #define HW_FMC_DATAW0SnL_ADDR(x, n) ((x) + 0x204U + (0x8U * (n))) |
Kojto | 90:cb3d968589d8 | 1538 | |
Kojto | 90:cb3d968589d8 | 1539 | #define HW_FMC_DATAW0SnL(x, n) (*(__IO hw_fmc_dataw0snl_t *) HW_FMC_DATAW0SnL_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1540 | #define HW_FMC_DATAW0SnL_RD(x, n) (HW_FMC_DATAW0SnL(x, n).U) |
Kojto | 90:cb3d968589d8 | 1541 | #define HW_FMC_DATAW0SnL_WR(x, n, v) (HW_FMC_DATAW0SnL(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1542 | #define HW_FMC_DATAW0SnL_SET(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1543 | #define HW_FMC_DATAW0SnL_CLR(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1544 | #define HW_FMC_DATAW0SnL_TOG(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, HW_FMC_DATAW0SnL_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1545 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1546 | |
Kojto | 90:cb3d968589d8 | 1547 | /* |
Kojto | 90:cb3d968589d8 | 1548 | * Constants & macros for individual FMC_DATAW0SnL bitfields |
Kojto | 90:cb3d968589d8 | 1549 | */ |
Kojto | 90:cb3d968589d8 | 1550 | |
Kojto | 90:cb3d968589d8 | 1551 | /*! |
Kojto | 90:cb3d968589d8 | 1552 | * @name Register FMC_DATAW0SnL, field data[31:0] (RW) |
Kojto | 90:cb3d968589d8 | 1553 | */ |
Kojto | 90:cb3d968589d8 | 1554 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1555 | #define BP_FMC_DATAW0SnL_data (0U) /*!< Bit position for FMC_DATAW0SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1556 | #define BM_FMC_DATAW0SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW0SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1557 | #define BS_FMC_DATAW0SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW0SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1558 | |
Kojto | 90:cb3d968589d8 | 1559 | /*! @brief Read current value of the FMC_DATAW0SnL_data field. */ |
Kojto | 90:cb3d968589d8 | 1560 | #define BR_FMC_DATAW0SnL_data(x, n) (HW_FMC_DATAW0SnL(x, n).U) |
Kojto | 90:cb3d968589d8 | 1561 | |
Kojto | 90:cb3d968589d8 | 1562 | /*! @brief Format value for bitfield FMC_DATAW0SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1563 | #define BF_FMC_DATAW0SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW0SnL_data) & BM_FMC_DATAW0SnL_data) |
Kojto | 90:cb3d968589d8 | 1564 | |
Kojto | 90:cb3d968589d8 | 1565 | /*! @brief Set the data field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1566 | #define BW_FMC_DATAW0SnL_data(x, n, v) (HW_FMC_DATAW0SnL_WR(x, n, v)) |
Kojto | 90:cb3d968589d8 | 1567 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1568 | |
Kojto | 90:cb3d968589d8 | 1569 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1570 | * HW_FMC_DATAW1SnU - Cache Data Storage (upper word) |
Kojto | 90:cb3d968589d8 | 1571 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1572 | |
Kojto | 90:cb3d968589d8 | 1573 | /*! |
Kojto | 90:cb3d968589d8 | 1574 | * @brief HW_FMC_DATAW1SnU - Cache Data Storage (upper word) (RW) |
Kojto | 90:cb3d968589d8 | 1575 | * |
Kojto | 90:cb3d968589d8 | 1576 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1577 | * |
Kojto | 90:cb3d968589d8 | 1578 | * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. |
Kojto | 90:cb3d968589d8 | 1579 | * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and |
Kojto | 90:cb3d968589d8 | 1580 | * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and |
Kojto | 90:cb3d968589d8 | 1581 | * lower word, respectively. This section represents data for the upper word (bits |
Kojto | 90:cb3d968589d8 | 1582 | * [63:32]) of all sets in the indicated way. |
Kojto | 90:cb3d968589d8 | 1583 | */ |
Kojto | 90:cb3d968589d8 | 1584 | typedef union _hw_fmc_dataw1snu |
Kojto | 90:cb3d968589d8 | 1585 | { |
Kojto | 90:cb3d968589d8 | 1586 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1587 | struct _hw_fmc_dataw1snu_bitfields |
Kojto | 90:cb3d968589d8 | 1588 | { |
Kojto | 90:cb3d968589d8 | 1589 | uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ |
Kojto | 90:cb3d968589d8 | 1590 | } B; |
Kojto | 90:cb3d968589d8 | 1591 | } hw_fmc_dataw1snu_t; |
Kojto | 90:cb3d968589d8 | 1592 | |
Kojto | 90:cb3d968589d8 | 1593 | /*! |
Kojto | 90:cb3d968589d8 | 1594 | * @name Constants and macros for entire FMC_DATAW1SnU register |
Kojto | 90:cb3d968589d8 | 1595 | */ |
Kojto | 90:cb3d968589d8 | 1596 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1597 | #define HW_FMC_DATAW1SnU_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1598 | |
Kojto | 90:cb3d968589d8 | 1599 | #define HW_FMC_DATAW1SnU_ADDR(x, n) ((x) + 0x220U + (0x8U * (n))) |
Kojto | 90:cb3d968589d8 | 1600 | |
Kojto | 90:cb3d968589d8 | 1601 | #define HW_FMC_DATAW1SnU(x, n) (*(__IO hw_fmc_dataw1snu_t *) HW_FMC_DATAW1SnU_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1602 | #define HW_FMC_DATAW1SnU_RD(x, n) (HW_FMC_DATAW1SnU(x, n).U) |
Kojto | 90:cb3d968589d8 | 1603 | #define HW_FMC_DATAW1SnU_WR(x, n, v) (HW_FMC_DATAW1SnU(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1604 | #define HW_FMC_DATAW1SnU_SET(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1605 | #define HW_FMC_DATAW1SnU_CLR(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1606 | #define HW_FMC_DATAW1SnU_TOG(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, HW_FMC_DATAW1SnU_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1607 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1608 | |
Kojto | 90:cb3d968589d8 | 1609 | /* |
Kojto | 90:cb3d968589d8 | 1610 | * Constants & macros for individual FMC_DATAW1SnU bitfields |
Kojto | 90:cb3d968589d8 | 1611 | */ |
Kojto | 90:cb3d968589d8 | 1612 | |
Kojto | 90:cb3d968589d8 | 1613 | /*! |
Kojto | 90:cb3d968589d8 | 1614 | * @name Register FMC_DATAW1SnU, field data[31:0] (RW) |
Kojto | 90:cb3d968589d8 | 1615 | */ |
Kojto | 90:cb3d968589d8 | 1616 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1617 | #define BP_FMC_DATAW1SnU_data (0U) /*!< Bit position for FMC_DATAW1SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1618 | #define BM_FMC_DATAW1SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1619 | #define BS_FMC_DATAW1SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1620 | |
Kojto | 90:cb3d968589d8 | 1621 | /*! @brief Read current value of the FMC_DATAW1SnU_data field. */ |
Kojto | 90:cb3d968589d8 | 1622 | #define BR_FMC_DATAW1SnU_data(x, n) (HW_FMC_DATAW1SnU(x, n).U) |
Kojto | 90:cb3d968589d8 | 1623 | |
Kojto | 90:cb3d968589d8 | 1624 | /*! @brief Format value for bitfield FMC_DATAW1SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1625 | #define BF_FMC_DATAW1SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnU_data) & BM_FMC_DATAW1SnU_data) |
Kojto | 90:cb3d968589d8 | 1626 | |
Kojto | 90:cb3d968589d8 | 1627 | /*! @brief Set the data field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1628 | #define BW_FMC_DATAW1SnU_data(x, n, v) (HW_FMC_DATAW1SnU_WR(x, n, v)) |
Kojto | 90:cb3d968589d8 | 1629 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1630 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1631 | * HW_FMC_DATAW1SnL - Cache Data Storage (lower word) |
Kojto | 90:cb3d968589d8 | 1632 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1633 | |
Kojto | 90:cb3d968589d8 | 1634 | /*! |
Kojto | 90:cb3d968589d8 | 1635 | * @brief HW_FMC_DATAW1SnL - Cache Data Storage (lower word) (RW) |
Kojto | 90:cb3d968589d8 | 1636 | * |
Kojto | 90:cb3d968589d8 | 1637 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1638 | * |
Kojto | 90:cb3d968589d8 | 1639 | * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. |
Kojto | 90:cb3d968589d8 | 1640 | * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and |
Kojto | 90:cb3d968589d8 | 1641 | * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and |
Kojto | 90:cb3d968589d8 | 1642 | * lower word, respectively. This section represents data for the lower word (bits |
Kojto | 90:cb3d968589d8 | 1643 | * [31:0]) of all sets in the indicated way. |
Kojto | 90:cb3d968589d8 | 1644 | */ |
Kojto | 90:cb3d968589d8 | 1645 | typedef union _hw_fmc_dataw1snl |
Kojto | 90:cb3d968589d8 | 1646 | { |
Kojto | 90:cb3d968589d8 | 1647 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1648 | struct _hw_fmc_dataw1snl_bitfields |
Kojto | 90:cb3d968589d8 | 1649 | { |
Kojto | 90:cb3d968589d8 | 1650 | uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ |
Kojto | 90:cb3d968589d8 | 1651 | } B; |
Kojto | 90:cb3d968589d8 | 1652 | } hw_fmc_dataw1snl_t; |
Kojto | 90:cb3d968589d8 | 1653 | |
Kojto | 90:cb3d968589d8 | 1654 | /*! |
Kojto | 90:cb3d968589d8 | 1655 | * @name Constants and macros for entire FMC_DATAW1SnL register |
Kojto | 90:cb3d968589d8 | 1656 | */ |
Kojto | 90:cb3d968589d8 | 1657 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1658 | #define HW_FMC_DATAW1SnL_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1659 | |
Kojto | 90:cb3d968589d8 | 1660 | #define HW_FMC_DATAW1SnL_ADDR(x, n) ((x) + 0x224U + (0x8U * (n))) |
Kojto | 90:cb3d968589d8 | 1661 | |
Kojto | 90:cb3d968589d8 | 1662 | #define HW_FMC_DATAW1SnL(x, n) (*(__IO hw_fmc_dataw1snl_t *) HW_FMC_DATAW1SnL_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1663 | #define HW_FMC_DATAW1SnL_RD(x, n) (HW_FMC_DATAW1SnL(x, n).U) |
Kojto | 90:cb3d968589d8 | 1664 | #define HW_FMC_DATAW1SnL_WR(x, n, v) (HW_FMC_DATAW1SnL(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1665 | #define HW_FMC_DATAW1SnL_SET(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1666 | #define HW_FMC_DATAW1SnL_CLR(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1667 | #define HW_FMC_DATAW1SnL_TOG(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, HW_FMC_DATAW1SnL_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1668 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1669 | |
Kojto | 90:cb3d968589d8 | 1670 | /* |
Kojto | 90:cb3d968589d8 | 1671 | * Constants & macros for individual FMC_DATAW1SnL bitfields |
Kojto | 90:cb3d968589d8 | 1672 | */ |
Kojto | 90:cb3d968589d8 | 1673 | |
Kojto | 90:cb3d968589d8 | 1674 | /*! |
Kojto | 90:cb3d968589d8 | 1675 | * @name Register FMC_DATAW1SnL, field data[31:0] (RW) |
Kojto | 90:cb3d968589d8 | 1676 | */ |
Kojto | 90:cb3d968589d8 | 1677 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1678 | #define BP_FMC_DATAW1SnL_data (0U) /*!< Bit position for FMC_DATAW1SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1679 | #define BM_FMC_DATAW1SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW1SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1680 | #define BS_FMC_DATAW1SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW1SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1681 | |
Kojto | 90:cb3d968589d8 | 1682 | /*! @brief Read current value of the FMC_DATAW1SnL_data field. */ |
Kojto | 90:cb3d968589d8 | 1683 | #define BR_FMC_DATAW1SnL_data(x, n) (HW_FMC_DATAW1SnL(x, n).U) |
Kojto | 90:cb3d968589d8 | 1684 | |
Kojto | 90:cb3d968589d8 | 1685 | /*! @brief Format value for bitfield FMC_DATAW1SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1686 | #define BF_FMC_DATAW1SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW1SnL_data) & BM_FMC_DATAW1SnL_data) |
Kojto | 90:cb3d968589d8 | 1687 | |
Kojto | 90:cb3d968589d8 | 1688 | /*! @brief Set the data field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1689 | #define BW_FMC_DATAW1SnL_data(x, n, v) (HW_FMC_DATAW1SnL_WR(x, n, v)) |
Kojto | 90:cb3d968589d8 | 1690 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1691 | |
Kojto | 90:cb3d968589d8 | 1692 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1693 | * HW_FMC_DATAW2SnU - Cache Data Storage (upper word) |
Kojto | 90:cb3d968589d8 | 1694 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1695 | |
Kojto | 90:cb3d968589d8 | 1696 | /*! |
Kojto | 90:cb3d968589d8 | 1697 | * @brief HW_FMC_DATAW2SnU - Cache Data Storage (upper word) (RW) |
Kojto | 90:cb3d968589d8 | 1698 | * |
Kojto | 90:cb3d968589d8 | 1699 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1700 | * |
Kojto | 90:cb3d968589d8 | 1701 | * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. |
Kojto | 90:cb3d968589d8 | 1702 | * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and |
Kojto | 90:cb3d968589d8 | 1703 | * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and |
Kojto | 90:cb3d968589d8 | 1704 | * lower word, respectively. This section represents data for the upper word (bits |
Kojto | 90:cb3d968589d8 | 1705 | * [63:32]) of all sets in the indicated way. |
Kojto | 90:cb3d968589d8 | 1706 | */ |
Kojto | 90:cb3d968589d8 | 1707 | typedef union _hw_fmc_dataw2snu |
Kojto | 90:cb3d968589d8 | 1708 | { |
Kojto | 90:cb3d968589d8 | 1709 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1710 | struct _hw_fmc_dataw2snu_bitfields |
Kojto | 90:cb3d968589d8 | 1711 | { |
Kojto | 90:cb3d968589d8 | 1712 | uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ |
Kojto | 90:cb3d968589d8 | 1713 | } B; |
Kojto | 90:cb3d968589d8 | 1714 | } hw_fmc_dataw2snu_t; |
Kojto | 90:cb3d968589d8 | 1715 | |
Kojto | 90:cb3d968589d8 | 1716 | /*! |
Kojto | 90:cb3d968589d8 | 1717 | * @name Constants and macros for entire FMC_DATAW2SnU register |
Kojto | 90:cb3d968589d8 | 1718 | */ |
Kojto | 90:cb3d968589d8 | 1719 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1720 | #define HW_FMC_DATAW2SnU_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1721 | |
Kojto | 90:cb3d968589d8 | 1722 | #define HW_FMC_DATAW2SnU_ADDR(x, n) ((x) + 0x240U + (0x8U * (n))) |
Kojto | 90:cb3d968589d8 | 1723 | |
Kojto | 90:cb3d968589d8 | 1724 | #define HW_FMC_DATAW2SnU(x, n) (*(__IO hw_fmc_dataw2snu_t *) HW_FMC_DATAW2SnU_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1725 | #define HW_FMC_DATAW2SnU_RD(x, n) (HW_FMC_DATAW2SnU(x, n).U) |
Kojto | 90:cb3d968589d8 | 1726 | #define HW_FMC_DATAW2SnU_WR(x, n, v) (HW_FMC_DATAW2SnU(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1727 | #define HW_FMC_DATAW2SnU_SET(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1728 | #define HW_FMC_DATAW2SnU_CLR(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1729 | #define HW_FMC_DATAW2SnU_TOG(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, HW_FMC_DATAW2SnU_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1730 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1731 | |
Kojto | 90:cb3d968589d8 | 1732 | /* |
Kojto | 90:cb3d968589d8 | 1733 | * Constants & macros for individual FMC_DATAW2SnU bitfields |
Kojto | 90:cb3d968589d8 | 1734 | */ |
Kojto | 90:cb3d968589d8 | 1735 | |
Kojto | 90:cb3d968589d8 | 1736 | /*! |
Kojto | 90:cb3d968589d8 | 1737 | * @name Register FMC_DATAW2SnU, field data[31:0] (RW) |
Kojto | 90:cb3d968589d8 | 1738 | */ |
Kojto | 90:cb3d968589d8 | 1739 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1740 | #define BP_FMC_DATAW2SnU_data (0U) /*!< Bit position for FMC_DATAW2SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1741 | #define BM_FMC_DATAW2SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1742 | #define BS_FMC_DATAW2SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1743 | |
Kojto | 90:cb3d968589d8 | 1744 | /*! @brief Read current value of the FMC_DATAW2SnU_data field. */ |
Kojto | 90:cb3d968589d8 | 1745 | #define BR_FMC_DATAW2SnU_data(x, n) (HW_FMC_DATAW2SnU(x, n).U) |
Kojto | 90:cb3d968589d8 | 1746 | |
Kojto | 90:cb3d968589d8 | 1747 | /*! @brief Format value for bitfield FMC_DATAW2SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1748 | #define BF_FMC_DATAW2SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnU_data) & BM_FMC_DATAW2SnU_data) |
Kojto | 90:cb3d968589d8 | 1749 | |
Kojto | 90:cb3d968589d8 | 1750 | /*! @brief Set the data field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1751 | #define BW_FMC_DATAW2SnU_data(x, n, v) (HW_FMC_DATAW2SnU_WR(x, n, v)) |
Kojto | 90:cb3d968589d8 | 1752 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1753 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1754 | * HW_FMC_DATAW2SnL - Cache Data Storage (lower word) |
Kojto | 90:cb3d968589d8 | 1755 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1756 | |
Kojto | 90:cb3d968589d8 | 1757 | /*! |
Kojto | 90:cb3d968589d8 | 1758 | * @brief HW_FMC_DATAW2SnL - Cache Data Storage (lower word) (RW) |
Kojto | 90:cb3d968589d8 | 1759 | * |
Kojto | 90:cb3d968589d8 | 1760 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1761 | * |
Kojto | 90:cb3d968589d8 | 1762 | * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. |
Kojto | 90:cb3d968589d8 | 1763 | * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and |
Kojto | 90:cb3d968589d8 | 1764 | * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and |
Kojto | 90:cb3d968589d8 | 1765 | * lower word, respectively. This section represents data for the lower word (bits |
Kojto | 90:cb3d968589d8 | 1766 | * [31:0]) of all sets in the indicated way. |
Kojto | 90:cb3d968589d8 | 1767 | */ |
Kojto | 90:cb3d968589d8 | 1768 | typedef union _hw_fmc_dataw2snl |
Kojto | 90:cb3d968589d8 | 1769 | { |
Kojto | 90:cb3d968589d8 | 1770 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1771 | struct _hw_fmc_dataw2snl_bitfields |
Kojto | 90:cb3d968589d8 | 1772 | { |
Kojto | 90:cb3d968589d8 | 1773 | uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ |
Kojto | 90:cb3d968589d8 | 1774 | } B; |
Kojto | 90:cb3d968589d8 | 1775 | } hw_fmc_dataw2snl_t; |
Kojto | 90:cb3d968589d8 | 1776 | |
Kojto | 90:cb3d968589d8 | 1777 | /*! |
Kojto | 90:cb3d968589d8 | 1778 | * @name Constants and macros for entire FMC_DATAW2SnL register |
Kojto | 90:cb3d968589d8 | 1779 | */ |
Kojto | 90:cb3d968589d8 | 1780 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1781 | #define HW_FMC_DATAW2SnL_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1782 | |
Kojto | 90:cb3d968589d8 | 1783 | #define HW_FMC_DATAW2SnL_ADDR(x, n) ((x) + 0x244U + (0x8U * (n))) |
Kojto | 90:cb3d968589d8 | 1784 | |
Kojto | 90:cb3d968589d8 | 1785 | #define HW_FMC_DATAW2SnL(x, n) (*(__IO hw_fmc_dataw2snl_t *) HW_FMC_DATAW2SnL_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1786 | #define HW_FMC_DATAW2SnL_RD(x, n) (HW_FMC_DATAW2SnL(x, n).U) |
Kojto | 90:cb3d968589d8 | 1787 | #define HW_FMC_DATAW2SnL_WR(x, n, v) (HW_FMC_DATAW2SnL(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1788 | #define HW_FMC_DATAW2SnL_SET(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1789 | #define HW_FMC_DATAW2SnL_CLR(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1790 | #define HW_FMC_DATAW2SnL_TOG(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, HW_FMC_DATAW2SnL_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1791 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1792 | |
Kojto | 90:cb3d968589d8 | 1793 | /* |
Kojto | 90:cb3d968589d8 | 1794 | * Constants & macros for individual FMC_DATAW2SnL bitfields |
Kojto | 90:cb3d968589d8 | 1795 | */ |
Kojto | 90:cb3d968589d8 | 1796 | |
Kojto | 90:cb3d968589d8 | 1797 | /*! |
Kojto | 90:cb3d968589d8 | 1798 | * @name Register FMC_DATAW2SnL, field data[31:0] (RW) |
Kojto | 90:cb3d968589d8 | 1799 | */ |
Kojto | 90:cb3d968589d8 | 1800 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1801 | #define BP_FMC_DATAW2SnL_data (0U) /*!< Bit position for FMC_DATAW2SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1802 | #define BM_FMC_DATAW2SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW2SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1803 | #define BS_FMC_DATAW2SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW2SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1804 | |
Kojto | 90:cb3d968589d8 | 1805 | /*! @brief Read current value of the FMC_DATAW2SnL_data field. */ |
Kojto | 90:cb3d968589d8 | 1806 | #define BR_FMC_DATAW2SnL_data(x, n) (HW_FMC_DATAW2SnL(x, n).U) |
Kojto | 90:cb3d968589d8 | 1807 | |
Kojto | 90:cb3d968589d8 | 1808 | /*! @brief Format value for bitfield FMC_DATAW2SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1809 | #define BF_FMC_DATAW2SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW2SnL_data) & BM_FMC_DATAW2SnL_data) |
Kojto | 90:cb3d968589d8 | 1810 | |
Kojto | 90:cb3d968589d8 | 1811 | /*! @brief Set the data field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1812 | #define BW_FMC_DATAW2SnL_data(x, n, v) (HW_FMC_DATAW2SnL_WR(x, n, v)) |
Kojto | 90:cb3d968589d8 | 1813 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1814 | |
Kojto | 90:cb3d968589d8 | 1815 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1816 | * HW_FMC_DATAW3SnU - Cache Data Storage (upper word) |
Kojto | 90:cb3d968589d8 | 1817 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1818 | |
Kojto | 90:cb3d968589d8 | 1819 | /*! |
Kojto | 90:cb3d968589d8 | 1820 | * @brief HW_FMC_DATAW3SnU - Cache Data Storage (upper word) (RW) |
Kojto | 90:cb3d968589d8 | 1821 | * |
Kojto | 90:cb3d968589d8 | 1822 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1823 | * |
Kojto | 90:cb3d968589d8 | 1824 | * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. |
Kojto | 90:cb3d968589d8 | 1825 | * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and |
Kojto | 90:cb3d968589d8 | 1826 | * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and |
Kojto | 90:cb3d968589d8 | 1827 | * lower word, respectively. This section represents data for the upper word (bits |
Kojto | 90:cb3d968589d8 | 1828 | * [63:32]) of all sets in the indicated way. |
Kojto | 90:cb3d968589d8 | 1829 | */ |
Kojto | 90:cb3d968589d8 | 1830 | typedef union _hw_fmc_dataw3snu |
Kojto | 90:cb3d968589d8 | 1831 | { |
Kojto | 90:cb3d968589d8 | 1832 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1833 | struct _hw_fmc_dataw3snu_bitfields |
Kojto | 90:cb3d968589d8 | 1834 | { |
Kojto | 90:cb3d968589d8 | 1835 | uint32_t data : 32; /*!< [31:0] Bits [63:32] of data entry */ |
Kojto | 90:cb3d968589d8 | 1836 | } B; |
Kojto | 90:cb3d968589d8 | 1837 | } hw_fmc_dataw3snu_t; |
Kojto | 90:cb3d968589d8 | 1838 | |
Kojto | 90:cb3d968589d8 | 1839 | /*! |
Kojto | 90:cb3d968589d8 | 1840 | * @name Constants and macros for entire FMC_DATAW3SnU register |
Kojto | 90:cb3d968589d8 | 1841 | */ |
Kojto | 90:cb3d968589d8 | 1842 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1843 | #define HW_FMC_DATAW3SnU_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1844 | |
Kojto | 90:cb3d968589d8 | 1845 | #define HW_FMC_DATAW3SnU_ADDR(x, n) ((x) + 0x260U + (0x8U * (n))) |
Kojto | 90:cb3d968589d8 | 1846 | |
Kojto | 90:cb3d968589d8 | 1847 | #define HW_FMC_DATAW3SnU(x, n) (*(__IO hw_fmc_dataw3snu_t *) HW_FMC_DATAW3SnU_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1848 | #define HW_FMC_DATAW3SnU_RD(x, n) (HW_FMC_DATAW3SnU(x, n).U) |
Kojto | 90:cb3d968589d8 | 1849 | #define HW_FMC_DATAW3SnU_WR(x, n, v) (HW_FMC_DATAW3SnU(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1850 | #define HW_FMC_DATAW3SnU_SET(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1851 | #define HW_FMC_DATAW3SnU_CLR(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1852 | #define HW_FMC_DATAW3SnU_TOG(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, HW_FMC_DATAW3SnU_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1853 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1854 | |
Kojto | 90:cb3d968589d8 | 1855 | /* |
Kojto | 90:cb3d968589d8 | 1856 | * Constants & macros for individual FMC_DATAW3SnU bitfields |
Kojto | 90:cb3d968589d8 | 1857 | */ |
Kojto | 90:cb3d968589d8 | 1858 | |
Kojto | 90:cb3d968589d8 | 1859 | /*! |
Kojto | 90:cb3d968589d8 | 1860 | * @name Register FMC_DATAW3SnU, field data[31:0] (RW) |
Kojto | 90:cb3d968589d8 | 1861 | */ |
Kojto | 90:cb3d968589d8 | 1862 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1863 | #define BP_FMC_DATAW3SnU_data (0U) /*!< Bit position for FMC_DATAW3SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1864 | #define BM_FMC_DATAW3SnU_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1865 | #define BS_FMC_DATAW3SnU_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1866 | |
Kojto | 90:cb3d968589d8 | 1867 | /*! @brief Read current value of the FMC_DATAW3SnU_data field. */ |
Kojto | 90:cb3d968589d8 | 1868 | #define BR_FMC_DATAW3SnU_data(x, n) (HW_FMC_DATAW3SnU(x, n).U) |
Kojto | 90:cb3d968589d8 | 1869 | |
Kojto | 90:cb3d968589d8 | 1870 | /*! @brief Format value for bitfield FMC_DATAW3SnU_data. */ |
Kojto | 90:cb3d968589d8 | 1871 | #define BF_FMC_DATAW3SnU_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnU_data) & BM_FMC_DATAW3SnU_data) |
Kojto | 90:cb3d968589d8 | 1872 | |
Kojto | 90:cb3d968589d8 | 1873 | /*! @brief Set the data field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1874 | #define BW_FMC_DATAW3SnU_data(x, n, v) (HW_FMC_DATAW3SnU_WR(x, n, v)) |
Kojto | 90:cb3d968589d8 | 1875 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1876 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1877 | * HW_FMC_DATAW3SnL - Cache Data Storage (lower word) |
Kojto | 90:cb3d968589d8 | 1878 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1879 | |
Kojto | 90:cb3d968589d8 | 1880 | /*! |
Kojto | 90:cb3d968589d8 | 1881 | * @brief HW_FMC_DATAW3SnL - Cache Data Storage (lower word) (RW) |
Kojto | 90:cb3d968589d8 | 1882 | * |
Kojto | 90:cb3d968589d8 | 1883 | * Reset value: 0x00000000U |
Kojto | 90:cb3d968589d8 | 1884 | * |
Kojto | 90:cb3d968589d8 | 1885 | * The cache of 64-bit entries is a 4-way, set-associative cache with 4 sets. |
Kojto | 90:cb3d968589d8 | 1886 | * The ways are numbered 0-3 and the sets are numbered 0-3. In DATAWxSyU and |
Kojto | 90:cb3d968589d8 | 1887 | * DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and |
Kojto | 90:cb3d968589d8 | 1888 | * lower word, respectively. This section represents data for the lower word (bits |
Kojto | 90:cb3d968589d8 | 1889 | * [31:0]) of all sets in the indicated way. |
Kojto | 90:cb3d968589d8 | 1890 | */ |
Kojto | 90:cb3d968589d8 | 1891 | typedef union _hw_fmc_dataw3snl |
Kojto | 90:cb3d968589d8 | 1892 | { |
Kojto | 90:cb3d968589d8 | 1893 | uint32_t U; |
Kojto | 90:cb3d968589d8 | 1894 | struct _hw_fmc_dataw3snl_bitfields |
Kojto | 90:cb3d968589d8 | 1895 | { |
Kojto | 90:cb3d968589d8 | 1896 | uint32_t data : 32; /*!< [31:0] Bits [31:0] of data entry */ |
Kojto | 90:cb3d968589d8 | 1897 | } B; |
Kojto | 90:cb3d968589d8 | 1898 | } hw_fmc_dataw3snl_t; |
Kojto | 90:cb3d968589d8 | 1899 | |
Kojto | 90:cb3d968589d8 | 1900 | /*! |
Kojto | 90:cb3d968589d8 | 1901 | * @name Constants and macros for entire FMC_DATAW3SnL register |
Kojto | 90:cb3d968589d8 | 1902 | */ |
Kojto | 90:cb3d968589d8 | 1903 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1904 | #define HW_FMC_DATAW3SnL_COUNT (4U) |
Kojto | 90:cb3d968589d8 | 1905 | |
Kojto | 90:cb3d968589d8 | 1906 | #define HW_FMC_DATAW3SnL_ADDR(x, n) ((x) + 0x264U + (0x8U * (n))) |
Kojto | 90:cb3d968589d8 | 1907 | |
Kojto | 90:cb3d968589d8 | 1908 | #define HW_FMC_DATAW3SnL(x, n) (*(__IO hw_fmc_dataw3snl_t *) HW_FMC_DATAW3SnL_ADDR(x, n)) |
Kojto | 90:cb3d968589d8 | 1909 | #define HW_FMC_DATAW3SnL_RD(x, n) (HW_FMC_DATAW3SnL(x, n).U) |
Kojto | 90:cb3d968589d8 | 1910 | #define HW_FMC_DATAW3SnL_WR(x, n, v) (HW_FMC_DATAW3SnL(x, n).U = (v)) |
Kojto | 90:cb3d968589d8 | 1911 | #define HW_FMC_DATAW3SnL_SET(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) | (v))) |
Kojto | 90:cb3d968589d8 | 1912 | #define HW_FMC_DATAW3SnL_CLR(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) & ~(v))) |
Kojto | 90:cb3d968589d8 | 1913 | #define HW_FMC_DATAW3SnL_TOG(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, HW_FMC_DATAW3SnL_RD(x, n) ^ (v))) |
Kojto | 90:cb3d968589d8 | 1914 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1915 | |
Kojto | 90:cb3d968589d8 | 1916 | /* |
Kojto | 90:cb3d968589d8 | 1917 | * Constants & macros for individual FMC_DATAW3SnL bitfields |
Kojto | 90:cb3d968589d8 | 1918 | */ |
Kojto | 90:cb3d968589d8 | 1919 | |
Kojto | 90:cb3d968589d8 | 1920 | /*! |
Kojto | 90:cb3d968589d8 | 1921 | * @name Register FMC_DATAW3SnL, field data[31:0] (RW) |
Kojto | 90:cb3d968589d8 | 1922 | */ |
Kojto | 90:cb3d968589d8 | 1923 | /*@{*/ |
Kojto | 90:cb3d968589d8 | 1924 | #define BP_FMC_DATAW3SnL_data (0U) /*!< Bit position for FMC_DATAW3SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1925 | #define BM_FMC_DATAW3SnL_data (0xFFFFFFFFU) /*!< Bit mask for FMC_DATAW3SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1926 | #define BS_FMC_DATAW3SnL_data (32U) /*!< Bit field size in bits for FMC_DATAW3SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1927 | |
Kojto | 90:cb3d968589d8 | 1928 | /*! @brief Read current value of the FMC_DATAW3SnL_data field. */ |
Kojto | 90:cb3d968589d8 | 1929 | #define BR_FMC_DATAW3SnL_data(x, n) (HW_FMC_DATAW3SnL(x, n).U) |
Kojto | 90:cb3d968589d8 | 1930 | |
Kojto | 90:cb3d968589d8 | 1931 | /*! @brief Format value for bitfield FMC_DATAW3SnL_data. */ |
Kojto | 90:cb3d968589d8 | 1932 | #define BF_FMC_DATAW3SnL_data(v) ((uint32_t)((uint32_t)(v) << BP_FMC_DATAW3SnL_data) & BM_FMC_DATAW3SnL_data) |
Kojto | 90:cb3d968589d8 | 1933 | |
Kojto | 90:cb3d968589d8 | 1934 | /*! @brief Set the data field to a new value. */ |
Kojto | 90:cb3d968589d8 | 1935 | #define BW_FMC_DATAW3SnL_data(x, n, v) (HW_FMC_DATAW3SnL_WR(x, n, v)) |
Kojto | 90:cb3d968589d8 | 1936 | /*@}*/ |
Kojto | 90:cb3d968589d8 | 1937 | |
Kojto | 90:cb3d968589d8 | 1938 | /******************************************************************************* |
Kojto | 90:cb3d968589d8 | 1939 | * hw_fmc_t - module struct |
Kojto | 90:cb3d968589d8 | 1940 | ******************************************************************************/ |
Kojto | 90:cb3d968589d8 | 1941 | /*! |
Kojto | 90:cb3d968589d8 | 1942 | * @brief All FMC module registers. |
Kojto | 90:cb3d968589d8 | 1943 | */ |
Kojto | 90:cb3d968589d8 | 1944 | #pragma pack(1) |
Kojto | 90:cb3d968589d8 | 1945 | typedef struct _hw_fmc |
Kojto | 90:cb3d968589d8 | 1946 | { |
Kojto | 90:cb3d968589d8 | 1947 | __IO hw_fmc_pfapr_t PFAPR; /*!< [0x0] Flash Access Protection Register */ |
Kojto | 90:cb3d968589d8 | 1948 | __IO hw_fmc_pfb0cr_t PFB0CR; /*!< [0x4] Flash Bank 0 Control Register */ |
Kojto | 90:cb3d968589d8 | 1949 | __IO hw_fmc_pfb1cr_t PFB1CR; /*!< [0x8] Flash Bank 1 Control Register */ |
Kojto | 90:cb3d968589d8 | 1950 | uint8_t _reserved0[244]; |
Kojto | 90:cb3d968589d8 | 1951 | __IO hw_fmc_tagvdw0sn_t TAGVDW0Sn[4]; /*!< [0x100] Cache Tag Storage */ |
Kojto | 90:cb3d968589d8 | 1952 | __IO hw_fmc_tagvdw1sn_t TAGVDW1Sn[4]; /*!< [0x110] Cache Tag Storage */ |
Kojto | 90:cb3d968589d8 | 1953 | __IO hw_fmc_tagvdw2sn_t TAGVDW2Sn[4]; /*!< [0x120] Cache Tag Storage */ |
Kojto | 90:cb3d968589d8 | 1954 | __IO hw_fmc_tagvdw3sn_t TAGVDW3Sn[4]; /*!< [0x130] Cache Tag Storage */ |
Kojto | 90:cb3d968589d8 | 1955 | uint8_t _reserved1[192]; |
Kojto | 90:cb3d968589d8 | 1956 | struct { |
Kojto | 90:cb3d968589d8 | 1957 | __IO hw_fmc_dataw0snu_t DATAW0SnU; /*!< [0x200] Cache Data Storage (upper word) */ |
Kojto | 90:cb3d968589d8 | 1958 | __IO hw_fmc_dataw0snl_t DATAW0SnL; /*!< [0x204] Cache Data Storage (lower word) */ |
Kojto | 90:cb3d968589d8 | 1959 | } DATAW0Sn[4]; |
Kojto | 90:cb3d968589d8 | 1960 | struct { |
Kojto | 90:cb3d968589d8 | 1961 | __IO hw_fmc_dataw1snu_t DATAW1SnU; /*!< [0x220] Cache Data Storage (upper word) */ |
Kojto | 90:cb3d968589d8 | 1962 | __IO hw_fmc_dataw1snl_t DATAW1SnL; /*!< [0x224] Cache Data Storage (lower word) */ |
Kojto | 90:cb3d968589d8 | 1963 | } DATAW1Sn[4]; |
Kojto | 90:cb3d968589d8 | 1964 | struct { |
Kojto | 90:cb3d968589d8 | 1965 | __IO hw_fmc_dataw2snu_t DATAW2SnU; /*!< [0x240] Cache Data Storage (upper word) */ |
Kojto | 90:cb3d968589d8 | 1966 | __IO hw_fmc_dataw2snl_t DATAW2SnL; /*!< [0x244] Cache Data Storage (lower word) */ |
Kojto | 90:cb3d968589d8 | 1967 | } DATAW2Sn[4]; |
Kojto | 90:cb3d968589d8 | 1968 | struct { |
Kojto | 90:cb3d968589d8 | 1969 | __IO hw_fmc_dataw3snu_t DATAW3SnU; /*!< [0x260] Cache Data Storage (upper word) */ |
Kojto | 90:cb3d968589d8 | 1970 | __IO hw_fmc_dataw3snl_t DATAW3SnL; /*!< [0x264] Cache Data Storage (lower word) */ |
Kojto | 90:cb3d968589d8 | 1971 | } DATAW3Sn[4]; |
Kojto | 90:cb3d968589d8 | 1972 | } hw_fmc_t; |
Kojto | 90:cb3d968589d8 | 1973 | #pragma pack() |
Kojto | 90:cb3d968589d8 | 1974 | |
Kojto | 90:cb3d968589d8 | 1975 | /*! @brief Macro to access all FMC registers. */ |
Kojto | 90:cb3d968589d8 | 1976 | /*! @param x FMC module instance base address. */ |
Kojto | 90:cb3d968589d8 | 1977 | /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
Kojto | 90:cb3d968589d8 | 1978 | * use the '&' operator, like <code>&HW_FMC(FMC_BASE)</code>. */ |
Kojto | 90:cb3d968589d8 | 1979 | #define HW_FMC(x) (*(hw_fmc_t *)(x)) |
Kojto | 90:cb3d968589d8 | 1980 | |
Kojto | 90:cb3d968589d8 | 1981 | #endif /* __HW_FMC_REGISTERS_H__ */ |
Kojto | 90:cb3d968589d8 | 1982 | /* EOF */ |