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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_dmamux.h@104:b9ad9a133dc7, 2015-08-05 (annotated)

Committer:
Kojto
Date:
Wed Aug 05 13:16:35 2015 +0100
Revision:
104:b9ad9a133dc7
Parent:
90:cb3d968589d8 
Release 104 of the mbed library:



Changes:

- new platforms: nrf51 microbit

- MAXxxx - fix pwm array search

- LPC8xx - usart enable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 4 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 5 ** GNU C Compiler
Kojto 90:cb3d968589d8 6 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 7 **
Kojto 90:cb3d968589d8 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Kojto 90:cb3d968589d8 9 ** Version: rev. 2.5, 2014-02-10
Kojto 90:cb3d968589d8 10 ** Build: b140604
Kojto 90:cb3d968589d8 11 **
Kojto 90:cb3d968589d8 12 ** Abstract:
Kojto 90:cb3d968589d8 13 ** Extension to the CMSIS register access layer header.
Kojto 90:cb3d968589d8 14 **
Kojto 90:cb3d968589d8 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 16 ** All rights reserved.
Kojto 90:cb3d968589d8 17 **
Kojto 90:cb3d968589d8 18 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 19 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 20 **
Kojto 90:cb3d968589d8 21 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 22 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 23 **
Kojto 90:cb3d968589d8 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 25 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 26 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 27 **
Kojto 90:cb3d968589d8 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 29 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 30 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 **
Kojto 90:cb3d968589d8 43 ** http: www.freescale.com
Kojto 90:cb3d968589d8 44 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 45 **
Kojto 90:cb3d968589d8 46 ** Revisions:
Kojto 90:cb3d968589d8 47 ** - rev. 1.0 (2013-08-12)
Kojto 90:cb3d968589d8 48 ** Initial version.
Kojto 90:cb3d968589d8 49 ** - rev. 2.0 (2013-10-29)
Kojto 90:cb3d968589d8 50 ** Register accessor macros added to the memory map.
Kojto 90:cb3d968589d8 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Kojto 90:cb3d968589d8 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
Kojto 90:cb3d968589d8 53 ** System initialization updated.
Kojto 90:cb3d968589d8 54 ** MCG - registers updated.
Kojto 90:cb3d968589d8 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Kojto 90:cb3d968589d8 56 ** - rev. 2.1 (2013-10-30)
Kojto 90:cb3d968589d8 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Kojto 90:cb3d968589d8 58 ** - rev. 2.2 (2013-12-09)
Kojto 90:cb3d968589d8 59 ** DMA - EARS register removed.
Kojto 90:cb3d968589d8 60 ** AIPS0, AIPS1 - MPRA register updated.
Kojto 90:cb3d968589d8 61 ** - rev. 2.3 (2014-01-24)
Kojto 90:cb3d968589d8 62 ** Update according to reference manual rev. 2
Kojto 90:cb3d968589d8 63 ** ENET, MCG, MCM, SIM, USB - registers updated
Kojto 90:cb3d968589d8 64 ** - rev. 2.4 (2014-02-10)
Kojto 90:cb3d968589d8 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 67 ** - rev. 2.5 (2014-02-10)
Kojto 90:cb3d968589d8 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Kojto 90:cb3d968589d8 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Kojto 90:cb3d968589d8 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Kojto 90:cb3d968589d8 71 **
Kojto 90:cb3d968589d8 72 ** ###################################################################
Kojto 90:cb3d968589d8 73 */
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /*
Kojto 90:cb3d968589d8 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
Kojto 90:cb3d968589d8 77 *
Kojto 90:cb3d968589d8 78 * This file was generated automatically and any changes may be lost.
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80 #ifndef __HW_DMAMUX_REGISTERS_H__
Kojto 90:cb3d968589d8 81 #define __HW_DMAMUX_REGISTERS_H__
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 #include "MK64F12.h"
Kojto 90:cb3d968589d8 84 #include "fsl_bitaccess.h"
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*
Kojto 90:cb3d968589d8 87 * MK64F12 DMAMUX
Kojto 90:cb3d968589d8 88 *
Kojto 90:cb3d968589d8 89 * DMA channel multiplexor
Kojto 90:cb3d968589d8 90 *
Kojto 90:cb3d968589d8 91 * Registers defined in this header file:
Kojto 90:cb3d968589d8 92 * - HW_DMAMUX_CHCFGn - Channel Configuration register
Kojto 90:cb3d968589d8 93 *
Kojto 90:cb3d968589d8 94 * - hw_dmamux_t - Struct containing all module registers.
Kojto 90:cb3d968589d8 95 */
Kojto 90:cb3d968589d8 96
Kojto 90:cb3d968589d8 97 #define HW_DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
Kojto 90:cb3d968589d8 98
Kojto 90:cb3d968589d8 99 /*******************************************************************************
Kojto 90:cb3d968589d8 100 * HW_DMAMUX_CHCFGn - Channel Configuration register
Kojto 90:cb3d968589d8 101 ******************************************************************************/
Kojto 90:cb3d968589d8 102
Kojto 90:cb3d968589d8 103 /*!
Kojto 90:cb3d968589d8 104 * @brief HW_DMAMUX_CHCFGn - Channel Configuration register (RW)
Kojto 90:cb3d968589d8 105 *
Kojto 90:cb3d968589d8 106 * Reset value: 0x00U
Kojto 90:cb3d968589d8 107 *
Kojto 90:cb3d968589d8 108 * Each of the DMA channels can be independently enabled/disabled and associated
Kojto 90:cb3d968589d8 109 * with one of the DMA slots (peripheral slots or always-on slots) in the
Kojto 90:cb3d968589d8 110 * system. Setting multiple CHCFG registers with the same source value will result in
Kojto 90:cb3d968589d8 111 * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
Kojto 90:cb3d968589d8 112 * Before changing the trigger or source settings, a DMA channel must be disabled
Kojto 90:cb3d968589d8 113 * via CHCFGn[ENBL].
Kojto 90:cb3d968589d8 114 */
Kojto 90:cb3d968589d8 115 typedef union _hw_dmamux_chcfgn
Kojto 90:cb3d968589d8 116 {
Kojto 90:cb3d968589d8 117 uint8_t U;
Kojto 90:cb3d968589d8 118 struct _hw_dmamux_chcfgn_bitfields
Kojto 90:cb3d968589d8 119 {
Kojto 90:cb3d968589d8 120 uint8_t SOURCE : 6; /*!< [5:0] DMA Channel Source (Slot) */
Kojto 90:cb3d968589d8 121 uint8_t TRIG : 1; /*!< [6] DMA Channel Trigger Enable */
Kojto 90:cb3d968589d8 122 uint8_t ENBL : 1; /*!< [7] DMA Channel Enable */
Kojto 90:cb3d968589d8 123 } B;
Kojto 90:cb3d968589d8 124 } hw_dmamux_chcfgn_t;
Kojto 90:cb3d968589d8 125
Kojto 90:cb3d968589d8 126 /*!
Kojto 90:cb3d968589d8 127 * @name Constants and macros for entire DMAMUX_CHCFGn register
Kojto 90:cb3d968589d8 128 */
Kojto 90:cb3d968589d8 129 /*@{*/
Kojto 90:cb3d968589d8 130 #define HW_DMAMUX_CHCFGn_COUNT (16U)
Kojto 90:cb3d968589d8 131
Kojto 90:cb3d968589d8 132 #define HW_DMAMUX_CHCFGn_ADDR(x, n) ((x) + 0x0U + (0x1U * (n)))
Kojto 90:cb3d968589d8 133
Kojto 90:cb3d968589d8 134 #define HW_DMAMUX_CHCFGn(x, n) (*(__IO hw_dmamux_chcfgn_t *) HW_DMAMUX_CHCFGn_ADDR(x, n))
Kojto 90:cb3d968589d8 135 #define HW_DMAMUX_CHCFGn_RD(x, n) (HW_DMAMUX_CHCFGn(x, n).U)
Kojto 90:cb3d968589d8 136 #define HW_DMAMUX_CHCFGn_WR(x, n, v) (HW_DMAMUX_CHCFGn(x, n).U = (v))
Kojto 90:cb3d968589d8 137 #define HW_DMAMUX_CHCFGn_SET(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) | (v)))
Kojto 90:cb3d968589d8 138 #define HW_DMAMUX_CHCFGn_CLR(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) & ~(v)))
Kojto 90:cb3d968589d8 139 #define HW_DMAMUX_CHCFGn_TOG(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, HW_DMAMUX_CHCFGn_RD(x, n) ^ (v)))
Kojto 90:cb3d968589d8 140 /*@}*/
Kojto 90:cb3d968589d8 141
Kojto 90:cb3d968589d8 142 /*
Kojto 90:cb3d968589d8 143 * Constants & macros for individual DMAMUX_CHCFGn bitfields
Kojto 90:cb3d968589d8 144 */
Kojto 90:cb3d968589d8 145
Kojto 90:cb3d968589d8 146 /*!
Kojto 90:cb3d968589d8 147 * @name Register DMAMUX_CHCFGn, field SOURCE[5:0] (RW)
Kojto 90:cb3d968589d8 148 *
Kojto 90:cb3d968589d8 149 * Specifies which DMA source, if any, is routed to a particular DMA channel.
Kojto 90:cb3d968589d8 150 * See your device's chip configuration details for information about the
Kojto 90:cb3d968589d8 151 * peripherals and their slot numbers.
Kojto 90:cb3d968589d8 152 */
Kojto 90:cb3d968589d8 153 /*@{*/
Kojto 90:cb3d968589d8 154 #define BP_DMAMUX_CHCFGn_SOURCE (0U) /*!< Bit position for DMAMUX_CHCFGn_SOURCE. */
Kojto 90:cb3d968589d8 155 #define BM_DMAMUX_CHCFGn_SOURCE (0x3FU) /*!< Bit mask for DMAMUX_CHCFGn_SOURCE. */
Kojto 90:cb3d968589d8 156 #define BS_DMAMUX_CHCFGn_SOURCE (6U) /*!< Bit field size in bits for DMAMUX_CHCFGn_SOURCE. */
Kojto 90:cb3d968589d8 157
Kojto 90:cb3d968589d8 158 /*! @brief Read current value of the DMAMUX_CHCFGn_SOURCE field. */
Kojto 90:cb3d968589d8 159 #define BR_DMAMUX_CHCFGn_SOURCE(x, n) (HW_DMAMUX_CHCFGn(x, n).B.SOURCE)
Kojto 90:cb3d968589d8 160
Kojto 90:cb3d968589d8 161 /*! @brief Format value for bitfield DMAMUX_CHCFGn_SOURCE. */
Kojto 90:cb3d968589d8 162 #define BF_DMAMUX_CHCFGn_SOURCE(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_SOURCE) & BM_DMAMUX_CHCFGn_SOURCE)
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 /*! @brief Set the SOURCE field to a new value. */
Kojto 90:cb3d968589d8 165 #define BW_DMAMUX_CHCFGn_SOURCE(x, n, v) (HW_DMAMUX_CHCFGn_WR(x, n, (HW_DMAMUX_CHCFGn_RD(x, n) & ~BM_DMAMUX_CHCFGn_SOURCE) | BF_DMAMUX_CHCFGn_SOURCE(v)))
Kojto 90:cb3d968589d8 166 /*@}*/
Kojto 90:cb3d968589d8 167
Kojto 90:cb3d968589d8 168 /*!
Kojto 90:cb3d968589d8 169 * @name Register DMAMUX_CHCFGn, field TRIG[6] (RW)
Kojto 90:cb3d968589d8 170 *
Kojto 90:cb3d968589d8 171 * Enables the periodic trigger capability for the triggered DMA channel.
Kojto 90:cb3d968589d8 172 *
Kojto 90:cb3d968589d8 173 * Values:
Kojto 90:cb3d968589d8 174 * - 0 - Triggering is disabled. If triggering is disabled and ENBL is set, the
Kojto 90:cb3d968589d8 175 * DMA Channel will simply route the specified source to the DMA channel.
Kojto 90:cb3d968589d8 176 * (Normal mode)
Kojto 90:cb3d968589d8 177 * - 1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
Kojto 90:cb3d968589d8 178 * DMAMUX is in Periodic Trigger mode.
Kojto 90:cb3d968589d8 179 */
Kojto 90:cb3d968589d8 180 /*@{*/
Kojto 90:cb3d968589d8 181 #define BP_DMAMUX_CHCFGn_TRIG (6U) /*!< Bit position for DMAMUX_CHCFGn_TRIG. */
Kojto 90:cb3d968589d8 182 #define BM_DMAMUX_CHCFGn_TRIG (0x40U) /*!< Bit mask for DMAMUX_CHCFGn_TRIG. */
Kojto 90:cb3d968589d8 183 #define BS_DMAMUX_CHCFGn_TRIG (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_TRIG. */
Kojto 90:cb3d968589d8 184
Kojto 90:cb3d968589d8 185 /*! @brief Read current value of the DMAMUX_CHCFGn_TRIG field. */
Kojto 90:cb3d968589d8 186 #define BR_DMAMUX_CHCFGn_TRIG(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG))
Kojto 90:cb3d968589d8 187
Kojto 90:cb3d968589d8 188 /*! @brief Format value for bitfield DMAMUX_CHCFGn_TRIG. */
Kojto 90:cb3d968589d8 189 #define BF_DMAMUX_CHCFGn_TRIG(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_TRIG) & BM_DMAMUX_CHCFGn_TRIG)
Kojto 90:cb3d968589d8 190
Kojto 90:cb3d968589d8 191 /*! @brief Set the TRIG field to a new value. */
Kojto 90:cb3d968589d8 192 #define BW_DMAMUX_CHCFGn_TRIG(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_TRIG) = (v))
Kojto 90:cb3d968589d8 193 /*@}*/
Kojto 90:cb3d968589d8 194
Kojto 90:cb3d968589d8 195 /*!
Kojto 90:cb3d968589d8 196 * @name Register DMAMUX_CHCFGn, field ENBL[7] (RW)
Kojto 90:cb3d968589d8 197 *
Kojto 90:cb3d968589d8 198 * Enables the DMA channel.
Kojto 90:cb3d968589d8 199 *
Kojto 90:cb3d968589d8 200 * Values:
Kojto 90:cb3d968589d8 201 * - 0 - DMA channel is disabled. This mode is primarily used during
Kojto 90:cb3d968589d8 202 * configuration of the DMAMux. The DMA has separate channel enables/disables, which
Kojto 90:cb3d968589d8 203 * should be used to disable or reconfigure a DMA channel.
Kojto 90:cb3d968589d8 204 * - 1 - DMA channel is enabled
Kojto 90:cb3d968589d8 205 */
Kojto 90:cb3d968589d8 206 /*@{*/
Kojto 90:cb3d968589d8 207 #define BP_DMAMUX_CHCFGn_ENBL (7U) /*!< Bit position for DMAMUX_CHCFGn_ENBL. */
Kojto 90:cb3d968589d8 208 #define BM_DMAMUX_CHCFGn_ENBL (0x80U) /*!< Bit mask for DMAMUX_CHCFGn_ENBL. */
Kojto 90:cb3d968589d8 209 #define BS_DMAMUX_CHCFGn_ENBL (1U) /*!< Bit field size in bits for DMAMUX_CHCFGn_ENBL. */
Kojto 90:cb3d968589d8 210
Kojto 90:cb3d968589d8 211 /*! @brief Read current value of the DMAMUX_CHCFGn_ENBL field. */
Kojto 90:cb3d968589d8 212 #define BR_DMAMUX_CHCFGn_ENBL(x, n) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL))
Kojto 90:cb3d968589d8 213
Kojto 90:cb3d968589d8 214 /*! @brief Format value for bitfield DMAMUX_CHCFGn_ENBL. */
Kojto 90:cb3d968589d8 215 #define BF_DMAMUX_CHCFGn_ENBL(v) ((uint8_t)((uint8_t)(v) << BP_DMAMUX_CHCFGn_ENBL) & BM_DMAMUX_CHCFGn_ENBL)
Kojto 90:cb3d968589d8 216
Kojto 90:cb3d968589d8 217 /*! @brief Set the ENBL field to a new value. */
Kojto 90:cb3d968589d8 218 #define BW_DMAMUX_CHCFGn_ENBL(x, n, v) (BITBAND_ACCESS8(HW_DMAMUX_CHCFGn_ADDR(x, n), BP_DMAMUX_CHCFGn_ENBL) = (v))
Kojto 90:cb3d968589d8 219 /*@}*/
Kojto 90:cb3d968589d8 220
Kojto 90:cb3d968589d8 221 /*******************************************************************************
Kojto 90:cb3d968589d8 222 * hw_dmamux_t - module struct
Kojto 90:cb3d968589d8 223 ******************************************************************************/
Kojto 90:cb3d968589d8 224 /*!
Kojto 90:cb3d968589d8 225 * @brief All DMAMUX module registers.
Kojto 90:cb3d968589d8 226 */
Kojto 90:cb3d968589d8 227 #pragma pack(1)
Kojto 90:cb3d968589d8 228 typedef struct _hw_dmamux
Kojto 90:cb3d968589d8 229 {
Kojto 90:cb3d968589d8 230 __IO hw_dmamux_chcfgn_t CHCFGn[16]; /*!< [0x0] Channel Configuration register */
Kojto 90:cb3d968589d8 231 } hw_dmamux_t;
Kojto 90:cb3d968589d8 232 #pragma pack()
Kojto 90:cb3d968589d8 233
Kojto 90:cb3d968589d8 234 /*! @brief Macro to access all DMAMUX registers. */
Kojto 90:cb3d968589d8 235 /*! @param x DMAMUX module instance base address. */
Kojto 90:cb3d968589d8 236 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
Kojto 90:cb3d968589d8 237 * use the '&' operator, like <code>&HW_DMAMUX(DMAMUX_BASE)</code>. */
Kojto 90:cb3d968589d8 238 #define HW_DMAMUX(x) (*(hw_dmamux_t *)(x))
Kojto 90:cb3d968589d8 239
Kojto 90:cb3d968589d8 240 #endif /* __HW_DMAMUX_REGISTERS_H__ */
Kojto 90:cb3d968589d8 241 /* EOF */